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   1 /*
   2  * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
   3  *
   4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
   5  *
   6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
   7  *  the following copyright notices:
   8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
   9  *     Portions Copyright (C) 2002 Embedix, Inc
  10  *     Copyright 2002 Hewlett-Packard Company
  11
  12  *  2.6 version of this driver inspired by:
  13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  14  *     All Rights Reserved.
  15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  16  *     All Rights Reserved.
  17  *
  18
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  */
  23
  24 /* Why is a timer used to detect insert events?
  25  *
  26  * From the AU1100 MMC application guide:
  27  * If the Au1100-based design is intended to support both MultiMediaCards
  28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
  29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  30  * In doing so, a MMC card never enters SPI-mode communications,
  31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  32  * (the low to high transition will not occur).
  33  *
  34  * So we use the timer to check the status manually.
  35  */
  36
  37 #include <linux/module.h>
  38 #include <linux/init.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/mm.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/dma-mapping.h>
  43
  44 #include <linux/mmc/host.h>
  45 #include <asm/io.h>
  46 #include <asm/mach-au1x00/au1000.h>
  47 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  48 #include <asm/mach-au1x00/au1100_mmc.h>
  49 #include <asm/scatterlist.h>
  50
  51 #include <au1xxx.h>
  52 #include "au1xmmc.h"
  53
  54 #define DRIVER_NAME "au1xxx-mmc"
  55
  56 /* Set this to enable special debugging macros */
  57
  58 #ifdef DEBUG
  59 #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
  60 #else
  61 #define DBG(fmt, idx, args...)
  62 #endif
  63
  64 const struct {
  65         u32 iobase;
  66         u32 tx_devid, rx_devid;
  67         u16 bcsrpwr;
  68         u16 bcsrstatus;
  69         u16 wpstatus;
  70 } au1xmmc_card_table[] = {
  71         { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,
  72           BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },
  73 #ifndef CONFIG_MIPS_DB1200
  74         { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,
  75           BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }
  76 #endif
  77 };
  78
  79 #define AU1XMMC_CONTROLLER_COUNT \
  80         (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
  81
  82 /* This array stores pointers for the hosts (used by the IRQ handler) */
  83 struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];
  84 static int dma = 1;
  85
  86 #ifdef MODULE
  87 module_param(dma, bool, 0);
  88 MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");
  89 #endif
  90
  91 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
  92 {
  93         u32 val = au_readl(HOST_CONFIG(host));
  94         val |= mask;
  95         au_writel(val, HOST_CONFIG(host));
  96         au_sync();
  97 }
  98
  99 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
 100 {
 101         u32 val = au_readl(HOST_CONFIG2(host));
 102
 103         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
 104         au_sync_delay(1);
 105
 106         /* SEND_STOP will turn off clock control - this re-enables it */
 107         val &= ~SD_CONFIG2_DF;
 108
 109         au_writel(val, HOST_CONFIG2(host));
 110         au_sync();
 111 }
 112
 113 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
 114 {
 115         u32 val = au_readl(HOST_CONFIG(host));
 116         val &= ~mask;
 117         au_writel(val, HOST_CONFIG(host));
 118         au_sync();
 119 }
 120
 121 static inline void SEND_STOP(struct au1xmmc_host *host)
 122 {
 123
 124         /* We know the value of CONFIG2, so avoid a read we don't need */
 125         u32 mask = SD_CONFIG2_EN;
 126
 127         WARN_ON(host->status != HOST_S_DATA);
 128         host->status = HOST_S_STOP;
 129
 130         au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
 131         au_sync();
 132
 133         /* Send the stop commmand */
 134         au_writel(STOP_CMD, HOST_CMD(host));
 135 }
 136
 137 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
 138 {
 139
 140         u32 val = au1xmmc_card_table[host->id].bcsrpwr;
 141
 142         bcsr->board &= ~val;
 143         if (state) bcsr->board |= val;
 144
 145         au_sync_delay(1);
 146 }
 147
 148 static inline int au1xmmc_card_inserted(struct au1xmmc_host *host)
 149 {
 150         return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)
 151                 ? 1 : 0;
 152 }
 153
 154 static int au1xmmc_card_readonly(struct mmc_host *mmc)
 155 {
 156         struct au1xmmc_host *host = mmc_priv(mmc);
 157         return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)
 158                 ? 1 : 0;
 159 }
 160
 161 static void au1xmmc_finish_request(struct au1xmmc_host *host)
 162 {
 163
 164         struct mmc_request *mrq = host->mrq;
 165
 166         host->mrq = NULL;
 167         host->flags &= HOST_F_ACTIVE;
 168
 169         host->dma.len = 0;
 170         host->dma.dir = 0;
 171
 172         host->pio.index  = 0;
 173         host->pio.offset = 0;
 174         host->pio.len = 0;
 175
 176         host->status = HOST_S_IDLE;
 177
 178         bcsr->disk_leds |= (1 << 8);
 179
 180         mmc_request_done(host->mmc, mrq);
 181 }
 182
 183 static void au1xmmc_tasklet_finish(unsigned long param)
 184 {
 185         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 186         au1xmmc_finish_request(host);
 187 }
 188
 189 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
 190                                 struct mmc_command *cmd)
 191 {
 192
 193         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
 194
 195         switch (mmc_resp_type(cmd)) {
 196         case MMC_RSP_NONE:
 197                 break;
 198         case MMC_RSP_R1:
 199                 mmccmd |= SD_CMD_RT_1;
 200                 break;
 201         case MMC_RSP_R1B:
 202                 mmccmd |= SD_CMD_RT_1B;
 203                 break;
 204         case MMC_RSP_R2:
 205                 mmccmd |= SD_CMD_RT_2;
 206                 break;
 207         case MMC_RSP_R3:
 208                 mmccmd |= SD_CMD_RT_3;
 209                 break;
 210         default:
 211                 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
 212                         mmc_resp_type(cmd));
 213                 return MMC_ERR_INVALID;
 214         }
 215
 216         switch(cmd->opcode) {
 217         case MMC_READ_SINGLE_BLOCK:
 218         case SD_APP_SEND_SCR:
 219                 mmccmd |= SD_CMD_CT_2;
 220                 break;
 221         case MMC_READ_MULTIPLE_BLOCK:
 222                 mmccmd |= SD_CMD_CT_4;
 223                 break;
 224         case MMC_WRITE_BLOCK:
 225                 mmccmd |= SD_CMD_CT_1;
 226                 break;
 227
 228         case MMC_WRITE_MULTIPLE_BLOCK:
 229                 mmccmd |= SD_CMD_CT_3;
 230                 break;
 231         case MMC_STOP_TRANSMISSION:
 232                 mmccmd |= SD_CMD_CT_7;
 233                 break;
 234         }
 235
 236         au_writel(cmd->arg, HOST_CMDARG(host));
 237         au_sync();
 238
 239         if (wait)
 240                 IRQ_OFF(host, SD_CONFIG_CR);
 241
 242         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
 243         au_sync();
 244
 245         /* Wait for the command to go on the line */
 246
 247         while(1) {
 248                 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
 249                         break;
 250         }
 251
 252         /* Wait for the command to come back */
 253
 254         if (wait) {
 255                 u32 status = au_readl(HOST_STATUS(host));
 256
 257                 while(!(status & SD_STATUS_CR))
 258                         status = au_readl(HOST_STATUS(host));
 259
 260                 /* Clear the CR status */
 261                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
 262
 263                 IRQ_ON(host, SD_CONFIG_CR);
 264         }
 265
 266         return MMC_ERR_NONE;
 267 }
 268
 269 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
 270 {
 271
 272         struct mmc_request *mrq = host->mrq;
 273         struct mmc_data *data;
 274         u32 crc;
 275
 276         WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
 277
 278         if (host->mrq == NULL)
 279                 return;
 280
 281         data = mrq->cmd->data;
 282
 283         if (status == 0)
 284                 status = au_readl(HOST_STATUS(host));
 285
 286         /* The transaction is really over when the SD_STATUS_DB bit is clear */
 287
 288         while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
 289                 status = au_readl(HOST_STATUS(host));
 290
 291         data->error = MMC_ERR_NONE;
 292         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
 293
 294         /* Process any errors */
 295
 296         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
 297         if (host->flags & HOST_F_XMIT)
 298                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
 299
 300         if (crc)
 301                 data->error = MMC_ERR_BADCRC;
 302
 303         /* Clear the CRC bits */
 304         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
 305
 306         data->bytes_xfered = 0;
 307
 308         if (data->error == MMC_ERR_NONE) {
 309                 if (host->flags & HOST_F_DMA) {
 310                         u32 chan = DMA_CHANNEL(host);
 311
 312                         chan_tab_t *c = *((chan_tab_t **) chan);
 313                         au1x_dma_chan_t *cp = c->chan_ptr;
 314                         data->bytes_xfered = cp->ddma_bytecnt;
 315                 }
 316                 else
 317                         data->bytes_xfered =
 318                                 (data->blocks * data->blksz) -
 319                                 host->pio.len;
 320         }
 321
 322         au1xmmc_finish_request(host);
 323 }
 324
 325 static void au1xmmc_tasklet_data(unsigned long param)
 326 {
 327         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 328
 329         u32 status = au_readl(HOST_STATUS(host));
 330         au1xmmc_data_complete(host, status);
 331 }
 332
 333 #define AU1XMMC_MAX_TRANSFER 8
 334
 335 static void au1xmmc_send_pio(struct au1xmmc_host *host)
 336 {
 337
 338         struct mmc_data *data = 0;
 339         int sg_len, max, count = 0;
 340         unsigned char *sg_ptr;
 341         u32 status = 0;
 342         struct scatterlist *sg;
 343
 344         data = host->mrq->data;
 345
 346         if (!(host->flags & HOST_F_XMIT))
 347                 return;
 348
 349         /* This is the pointer to the data buffer */
 350         sg = &data->sg[host->pio.index];
 351         sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
 352
 353         /* This is the space left inside the buffer */
 354         sg_len = data->sg[host->pio.index].length - host->pio.offset;
 355
 356         /* Check to if we need less then the size of the sg_buffer */
 357
 358         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
 359         if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
 360
 361         for(count = 0; count < max; count++ ) {
 362                 unsigned char val;
 363
 364                 status = au_readl(HOST_STATUS(host));
 365
 366                 if (!(status & SD_STATUS_TH))
 367                         break;
 368
 369                 val = *sg_ptr++;
 370
 371                 au_writel((unsigned long) val, HOST_TXPORT(host));
 372                 au_sync();
 373         }
 374
 375         host->pio.len -= count;
 376         host->pio.offset += count;
 377
 378         if (count == sg_len) {
 379                 host->pio.index++;
 380                 host->pio.offset = 0;
 381         }
 382
 383         if (host->pio.len == 0) {
 384                 IRQ_OFF(host, SD_CONFIG_TH);
 385
 386                 if (host->flags & HOST_F_STOP)
 387                         SEND_STOP(host);
 388
 389                 tasklet_schedule(&host->data_task);
 390         }
 391 }
 392
 393 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
 394 {
 395
 396         struct mmc_data *data = 0;
 397         int sg_len = 0, max = 0, count = 0;
 398         unsigned char *sg_ptr = 0;
 399         u32 status = 0;
 400         struct scatterlist *sg;
 401
 402         data = host->mrq->data;
 403
 404         if (!(host->flags & HOST_F_RECV))
 405                 return;
 406
 407         max = host->pio.len;
 408
 409         if (host->pio.index < host->dma.len) {
 410                 sg = &data->sg[host->pio.index];
 411                 sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
 412
 413                 /* This is the space left inside the buffer */
 414                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
 415
 416                 /* Check to if we need less then the size of the sg_buffer */
 417                 if (sg_len < max) max = sg_len;
 418         }
 419
 420         if (max > AU1XMMC_MAX_TRANSFER)
 421                 max = AU1XMMC_MAX_TRANSFER;
 422
 423         for(count = 0; count < max; count++ ) {
 424                 u32 val;
 425                 status = au_readl(HOST_STATUS(host));
 426
 427                 if (!(status & SD_STATUS_NE))
 428                         break;
 429
 430                 if (status & SD_STATUS_RC) {
 431                         DBG("RX CRC Error [%d + %d].\n", host->id,
 432                                         host->pio.len, count);
 433                         break;
 434                 }
 435
 436                 if (status & SD_STATUS_RO) {
 437                         DBG("RX Overrun [%d + %d]\n", host->id,
 438                                         host->pio.len, count);
 439                         break;
 440                 }
 441                 else if (status & SD_STATUS_RU) {
 442                         DBG("RX Underrun [%d + %d]\n", host->id,
 443                                         host->pio.len,  count);
 444                         break;
 445                 }
 446
 447                 val = au_readl(HOST_RXPORT(host));
 448
 449                 if (sg_ptr)
 450                         *sg_ptr++ = (unsigned char) (val & 0xFF);
 451         }
 452
 453         host->pio.len -= count;
 454         host->pio.offset += count;
 455
 456         if (sg_len && count == sg_len) {
 457                 host->pio.index++;
 458                 host->pio.offset = 0;
 459         }
 460
 461         if (host->pio.len == 0) {
 462                 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
 463                 IRQ_OFF(host, SD_CONFIG_NE);
 464
 465                 if (host->flags & HOST_F_STOP)
 466                         SEND_STOP(host);
 467
 468                 tasklet_schedule(&host->data_task);
 469         }
 470 }
 471
 472 /* static void au1xmmc_cmd_complete
 473    This is called when a command has been completed - grab the response
 474    and check for errors.  Then start the data transfer if it is indicated.
 475 */
 476
 477 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
 478 {
 479
 480         struct mmc_request *mrq = host->mrq;
 481         struct mmc_command *cmd;
 482         int trans;
 483
 484         if (!host->mrq)
 485                 return;
 486
 487         cmd = mrq->cmd;
 488         cmd->error = MMC_ERR_NONE;
 489
 490         if (cmd->flags & MMC_RSP_PRESENT) {
 491                 if (cmd->flags & MMC_RSP_136) {
 492                         u32 r[4];
 493                         int i;
 494
 495                         r[0] = au_readl(host->iobase + SD_RESP3);
 496                         r[1] = au_readl(host->iobase + SD_RESP2);
 497                         r[2] = au_readl(host->iobase + SD_RESP1);
 498                         r[3] = au_readl(host->iobase + SD_RESP0);
 499
 500                         /* The CRC is omitted from the response, so really
 501                          * we only got 120 bytes, but the engine expects
 502                          * 128 bits, so we have to shift things up
 503                          */
 504
 505                         for(i = 0; i < 4; i++) {
 506                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
 507                                 if (i != 3)
 508                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
 509                         }
 510                 } else {
 511                         /* Techincally, we should be getting all 48 bits of
 512                          * the response (SD_RESP1 + SD_RESP2), but because
 513                          * our response omits the CRC, our data ends up
 514                          * being shifted 8 bits to the right.  In this case,
 515                          * that means that the OSR data starts at bit 31,
 516                          * so we can just read RESP0 and return that
 517                          */
 518                         cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
 519                 }
 520         }
 521
 522         /* Figure out errors */
 523
 524         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
 525                 cmd->error = MMC_ERR_BADCRC;
 526
 527         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
 528
 529         if (!trans || cmd->error != MMC_ERR_NONE) {
 530
 531                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
 532                 tasklet_schedule(&host->finish_task);
 533                 return;
 534         }
 535
 536         host->status = HOST_S_DATA;
 537
 538         if (host->flags & HOST_F_DMA) {
 539                 u32 channel = DMA_CHANNEL(host);
 540
 541                 /* Start the DMA as soon as the buffer gets something in it */
 542
 543                 if (host->flags & HOST_F_RECV) {
 544                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
 545
 546                         while((status & mask) != mask)
 547                                 status = au_readl(HOST_STATUS(host));
 548                 }
 549
 550                 au1xxx_dbdma_start(channel);
 551         }
 552 }
 553
 554 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
 555 {
 556
 557         unsigned int pbus = get_au1x00_speed();
 558         unsigned int divisor;
 559         u32 config;
 560
 561         /* From databook:
 562            divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
 563         */
 564
 565         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
 566         pbus /= 2;
 567
 568         divisor = ((pbus / rate) / 2) - 1;
 569
 570         config = au_readl(HOST_CONFIG(host));
 571
 572         config &= ~(SD_CONFIG_DIV);
 573         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
 574
 575         au_writel(config, HOST_CONFIG(host));
 576         au_sync();
 577 }
 578
 579 static int
 580 au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
 581 {
 582
 583         int datalen = data->blocks * data->blksz;
 584
 585         if (dma != 0)
 586                 host->flags |= HOST_F_DMA;
 587
 588         if (data->flags & MMC_DATA_READ)
 589                 host->flags |= HOST_F_RECV;
 590         else
 591                 host->flags |= HOST_F_XMIT;
 592
 593         if (host->mrq->stop)
 594                 host->flags |= HOST_F_STOP;
 595
 596         host->dma.dir = DMA_BIDIRECTIONAL;
 597
 598         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 599                                    data->sg_len, host->dma.dir);
 600
 601         if (host->dma.len == 0)
 602                 return MMC_ERR_TIMEOUT;
 603
 604         au_writel(data->blksz - 1, HOST_BLKSIZE(host));
 605
 606         if (host->flags & HOST_F_DMA) {
 607                 int i;
 608                 u32 channel = DMA_CHANNEL(host);
 609
 610                 au1xxx_dbdma_stop(channel);
 611
 612                 for(i = 0; i < host->dma.len; i++) {
 613                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
 614                         struct scatterlist *sg = &data->sg[i];
 615                         int sg_len = sg->length;
 616
 617                         int len = (datalen > sg_len) ? sg_len : datalen;
 618
 619                         if (i == host->dma.len - 1)
 620                                 flags = DDMA_FLAGS_IE;
 621
 622                         if (host->flags & HOST_F_XMIT){
 623                                 ret = au1xxx_dbdma_put_source_flags(channel,
 624                                         (void *) (page_address(sg->page) +
 625                                                   sg->offset),
 626                                         len, flags);
 627                         }
 628                         else {
 629                                 ret = au1xxx_dbdma_put_dest_flags(channel,
 630                                         (void *) (page_address(sg->page) +
 631                                                   sg->offset),
 632                                         len, flags);
 633                         }
 634
 635                         if (!ret)
 636                                 goto dataerr;
 637
 638                         datalen -= len;
 639                 }
 640         }
 641         else {
 642                 host->pio.index = 0;
 643                 host->pio.offset = 0;
 644                 host->pio.len = datalen;
 645
 646                 if (host->flags & HOST_F_XMIT)
 647                         IRQ_ON(host, SD_CONFIG_TH);
 648                 else
 649                         IRQ_ON(host, SD_CONFIG_NE);
 650                         //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
 651         }
 652
 653         return MMC_ERR_NONE;
 654
 655  dataerr:
 656         dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir);
 657         return MMC_ERR_TIMEOUT;
 658 }
 659
 660 /* static void au1xmmc_request
 661    This actually starts a command or data transaction
 662 */
 663
 664 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
 665 {
 666
 667         struct au1xmmc_host *host = mmc_priv(mmc);
 668         int ret = MMC_ERR_NONE;
 669
 670         WARN_ON(irqs_disabled());
 671         WARN_ON(host->status != HOST_S_IDLE);
 672
 673         host->mrq = mrq;
 674         host->status = HOST_S_CMD;
 675
 676         bcsr->disk_leds &= ~(1 << 8);
 677
 678         if (mrq->data) {
 679                 FLUSH_FIFO(host);
 680                 ret = au1xmmc_prepare_data(host, mrq->data);
 681         }
 682
 683         if (ret == MMC_ERR_NONE)
 684                 ret = au1xmmc_send_command(host, 0, mrq->cmd);
 685
 686         if (ret != MMC_ERR_NONE) {
 687                 mrq->cmd->error = ret;
 688                 au1xmmc_finish_request(host);
 689         }
 690 }
 691
 692 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
 693 {
 694
 695         /* Apply the clock */
 696         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
 697         au_sync_delay(1);
 698
 699         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
 700         au_sync_delay(5);
 701
 702         au_writel(~0, HOST_STATUS(host));
 703         au_sync();
 704
 705         au_writel(0, HOST_BLKSIZE(host));
 706         au_writel(0x001fffff, HOST_TIMEOUT(host));
 707         au_sync();
 708
 709         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 710         au_sync();
 711
 712         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
 713         au_sync_delay(1);
 714
 715         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 716         au_sync();
 717
 718         /* Configure interrupts */
 719         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
 720         au_sync();
 721 }
 722
 723
 724 static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
 725 {
 726         struct au1xmmc_host *host = mmc_priv(mmc);
 727
 728         if (ios->power_mode == MMC_POWER_OFF)
 729                 au1xmmc_set_power(host, 0);
 730         else if (ios->power_mode == MMC_POWER_ON) {
 731                 au1xmmc_set_power(host, 1);
 732         }
 733
 734         if (ios->clock && ios->clock != host->clock) {
 735                 au1xmmc_set_clock(host, ios->clock);
 736                 host->clock = ios->clock;
 737         }
 738 }
 739
 740 static void au1xmmc_dma_callback(int irq, void *dev_id)
 741 {
 742         struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
 743
 744         /* Avoid spurious interrupts */
 745
 746         if (!host->mrq)
 747                 return;
 748
 749         if (host->flags & HOST_F_STOP)
 750                 SEND_STOP(host);
 751
 752         tasklet_schedule(&host->data_task);
 753 }
 754
 755 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
 756 #define STATUS_DATA_IN  (SD_STATUS_NE)
 757 #define STATUS_DATA_OUT (SD_STATUS_TH)
 758
 759 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
 760 {
 761
 762         u32 status;
 763         int i, ret = 0;
 764
 765         disable_irq(AU1100_SD_IRQ);
 766
 767         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
 768                 struct au1xmmc_host * host = au1xmmc_hosts[i];
 769                 u32 handled = 1;
 770
 771                 status = au_readl(HOST_STATUS(host));
 772
 773                 if (host->mrq && (status & STATUS_TIMEOUT)) {
 774                         if (status & SD_STATUS_RAT)
 775                                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
 776
 777                         else if (status & SD_STATUS_DT)
 778                                 host->mrq->data->error = MMC_ERR_TIMEOUT;
 779
 780                         /* In PIO mode, interrupts might still be enabled */
 781                         IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
 782
 783                         //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
 784                         tasklet_schedule(&host->finish_task);
 785                 }
 786 #if 0
 787                 else if (status & SD_STATUS_DD) {
 788
 789                         /* Sometimes we get a DD before a NE in PIO mode */
 790
 791                         if (!(host->flags & HOST_F_DMA) &&
 792                                         (status & SD_STATUS_NE))
 793                                 au1xmmc_receive_pio(host);
 794                         else {
 795                                 au1xmmc_data_complete(host, status);
 796                                 //tasklet_schedule(&host->data_task);
 797                         }
 798                 }
 799 #endif
 800                 else if (status & (SD_STATUS_CR)) {
 801                         if (host->status == HOST_S_CMD)
 802                                 au1xmmc_cmd_complete(host,status);
 803                 }
 804                 else if (!(host->flags & HOST_F_DMA)) {
 805                         if ((host->flags & HOST_F_XMIT) &&
 806                             (status & STATUS_DATA_OUT))
 807                                 au1xmmc_send_pio(host);
 808                         else if ((host->flags & HOST_F_RECV) &&
 809                             (status & STATUS_DATA_IN))
 810                                 au1xmmc_receive_pio(host);
 811                 }
 812                 else if (status & 0x203FBC70) {
 813                         DBG("Unhandled status %8.8x\n", host->id, status);
 814                         handled = 0;
 815                 }
 816
 817                 au_writel(status, HOST_STATUS(host));
 818                 au_sync();
 819
 820                 ret |= handled;
 821         }
 822
 823         enable_irq(AU1100_SD_IRQ);
 824         return ret;
 825 }
 826
 827 static void au1xmmc_poll_event(unsigned long arg)
 828 {
 829         struct au1xmmc_host *host = (struct au1xmmc_host *) arg;
 830
 831         int card = au1xmmc_card_inserted(host);
 832         int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
 833
 834         if (card != controller) {
 835                 host->flags &= ~HOST_F_ACTIVE;
 836                 if (card) host->flags |= HOST_F_ACTIVE;
 837                 mmc_detect_change(host->mmc, 0);
 838         }
 839
 840         if (host->mrq != NULL) {
 841                 u32 status = au_readl(HOST_STATUS(host));
 842                 DBG("PENDING - %8.8x\n", host->id, status);
 843         }
 844
 845         mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
 846 }
 847
 848 static dbdev_tab_t au1xmmc_mem_dbdev =
 849 {
 850         DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0
 851 };
 852
 853 static void au1xmmc_init_dma(struct au1xmmc_host *host)
 854 {
 855
 856         u32 rxchan, txchan;
 857
 858         int txid = au1xmmc_card_table[host->id].tx_devid;
 859         int rxid = au1xmmc_card_table[host->id].rx_devid;
 860
 861         /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
 862            of 8 bits.  And since devices are shared, we need to create
 863            our own to avoid freaking out other devices
 864         */
 865
 866         int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
 867
 868         txchan = au1xxx_dbdma_chan_alloc(memid, txid,
 869                                          au1xmmc_dma_callback, (void *) host);
 870
 871         rxchan = au1xxx_dbdma_chan_alloc(rxid, memid,
 872                                          au1xmmc_dma_callback, (void *) host);
 873
 874         au1xxx_dbdma_set_devwidth(txchan, 8);
 875         au1xxx_dbdma_set_devwidth(rxchan, 8);
 876
 877         au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);
 878         au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);
 879
 880         host->tx_chan = txchan;
 881         host->rx_chan = rxchan;
 882 }
 883
 884 static const struct mmc_host_ops au1xmmc_ops = {
 885         .request        = au1xmmc_request,
 886         .set_ios        = au1xmmc_set_ios,
 887         .get_ro         = au1xmmc_card_readonly,
 888 };
 889
 890 static int __devinit au1xmmc_probe(struct platform_device *pdev)
 891 {
 892
 893         int i, ret = 0;
 894
 895         /* THe interrupt is shared among all controllers */
 896         ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, IRQF_DISABLED, "MMC", 0);
 897
 898         if (ret) {
 899                 printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n",
 900                                 AU1100_SD_IRQ, ret);
 901                 return -ENXIO;
 902         }
 903
 904         disable_irq(AU1100_SD_IRQ);
 905
 906         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
 907                 struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
 908                 struct au1xmmc_host *host = 0;
 909
 910                 if (!mmc) {
 911                         printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);
 912                         au1xmmc_hosts[i] = 0;
 913                         continue;
 914                 }
 915
 916                 mmc->ops = &au1xmmc_ops;
 917
 918                 mmc->f_min =   450000;
 919                 mmc->f_max = 24000000;
 920
 921                 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
 922                 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
 923
 924                 mmc->max_blk_size = 2048;
 925                 mmc->max_blk_count = 512;
 926
 927                 mmc->ocr_avail = AU1XMMC_OCR;
 928
 929                 host = mmc_priv(mmc);
 930                 host->mmc = mmc;
 931
 932                 host->id = i;
 933                 host->iobase = au1xmmc_card_table[host->id].iobase;
 934                 host->clock = 0;
 935                 host->power_mode = MMC_POWER_OFF;
 936
 937                 host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;
 938                 host->status = HOST_S_IDLE;
 939
 940                 init_timer(&host->timer);
 941
 942                 host->timer.function = au1xmmc_poll_event;
 943                 host->timer.data = (unsigned long) host;
 944                 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
 945
 946                 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
 947                                 (unsigned long) host);
 948
 949                 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
 950                                 (unsigned long) host);
 951
 952                 spin_lock_init(&host->lock);
 953
 954                 if (dma != 0)
 955                         au1xmmc_init_dma(host);
 956
 957                 au1xmmc_reset_controller(host);
 958
 959                 mmc_add_host(mmc);
 960                 au1xmmc_hosts[i] = host;
 961
 962                 add_timer(&host->timer);
 963
 964                 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",
 965                        host->id, host->iobase, dma ? "dma" : "pio");
 966         }
 967
 968         enable_irq(AU1100_SD_IRQ);
 969
 970         return 0;
 971 }
 972
 973 static int __devexit au1xmmc_remove(struct platform_device *pdev)
 974 {
 975
 976         int i;
 977
 978         disable_irq(AU1100_SD_IRQ);
 979
 980         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
 981                 struct au1xmmc_host *host = au1xmmc_hosts[i];
 982                 if (!host) continue;
 983
 984                 tasklet_kill(&host->data_task);
 985                 tasklet_kill(&host->finish_task);
 986
 987                 del_timer_sync(&host->timer);
 988                 au1xmmc_set_power(host, 0);
 989
 990                 mmc_remove_host(host->mmc);
 991
 992                 au1xxx_dbdma_chan_free(host->tx_chan);
 993                 au1xxx_dbdma_chan_free(host->rx_chan);
 994
 995                 au_writel(0x0, HOST_ENABLE(host));
 996                 au_sync();
 997         }
 998
 999         free_irq(AU1100_SD_IRQ, 0);
1000         return 0;
1001 }
1002
1003 static struct platform_driver au1xmmc_driver = {
1004         .probe         = au1xmmc_probe,
1005         .remove        = au1xmmc_remove,
1006         .suspend       = NULL,
1007         .resume        = NULL,
1008         .driver        = {
1009                 .name  = DRIVER_NAME,
1010         },
1011 };
1012
1013 static int __init au1xmmc_init(void)
1014 {
1015         return platform_driver_register(&au1xmmc_driver);
1016 }
1017
1018 static void __exit au1xmmc_exit(void)
1019 {
1020         platform_driver_unregister(&au1xmmc_driver);
1021 }
1022
1023 module_init(au1xmmc_init);
1024 module_exit(au1xmmc_exit);
1025
1026 #ifdef MODULE
1027 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1028 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1029 MODULE_LICENSE("GPL");
1030 #endif
1031