2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
35 #include <linux/videodev2.h>
38 #include <mach/camera.h>
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
43 /* Camera Interface */
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
166 * YUV422P picture size should be a multiple of 16, so the heuristic aligns
167 * height, width on 4 byte boundaries to reach the 16 multiple for the size.
169 #define YUV422P_X_Y_ALIGN 4
170 #define YUV422P_SIZE_ALIGN YUV422P_X_Y_ALIGN * YUV422P_X_Y_ALIGN
175 enum pxa_camera_active_dma {
181 /* descriptor needed for the PXA DMA engine */
184 struct pxa_dma_desc *sg_cpu;
189 /* buffer for one video frame */
191 /* common v4l buffer stuff -- must be first */
192 struct videobuf_buffer vb;
194 const struct soc_camera_data_format *fmt;
196 /* our descriptor lists for Y, U and V channels */
197 struct pxa_cam_dma dmas[3];
201 enum pxa_camera_active_dma active_dma;
204 struct pxa_camera_dev {
206 /* PXA27x is only supposed to handle one camera on its Quick Capture
207 * interface. If anyone ever builds hardware to enable more than
208 * one camera, they will have to modify this driver too */
209 struct soc_camera_device *icd;
216 unsigned int dma_chans[3];
218 struct pxacamera_platform_data *pdata;
219 struct resource *res;
220 unsigned long platform_flags;
225 struct list_head capture;
229 struct pxa_buffer *active;
230 struct pxa_dma_desc *sg_tail[3];
235 static const char *pxa_cam_driver_description = "PXA_Camera";
237 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
240 * Videobuf operations
242 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
245 struct soc_camera_device *icd = vq->priv_data;
247 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
249 *size = roundup(icd->width * icd->height *
250 ((icd->current_fmt->depth + 7) >> 3), 8);
254 while (*size * *count > vid_limit * 1024 * 1024)
260 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
262 struct soc_camera_device *icd = vq->priv_data;
263 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
264 struct pxa_camera_dev *pcdev = ici->priv;
265 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
268 BUG_ON(in_interrupt());
270 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
271 &buf->vb, buf->vb.baddr, buf->vb.bsize);
273 /* This waits until this buffer is out of danger, i.e., until it is no
274 * longer in STATE_QUEUED or STATE_ACTIVE */
275 videobuf_waiton(&buf->vb, 0, 0);
276 videobuf_dma_unmap(vq, dma);
277 videobuf_dma_free(dma);
279 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
280 if (buf->dmas[i].sg_cpu)
281 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
283 buf->dmas[i].sg_dma);
284 buf->dmas[i].sg_cpu = NULL;
287 buf->vb.state = VIDEOBUF_NEEDS_INIT;
290 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
291 int sg_first_ofs, int size)
293 int i, offset, dma_len, xfer_len;
294 struct scatterlist *sg;
296 offset = sg_first_ofs;
297 for_each_sg(sglist, sg, sglen, i) {
298 dma_len = sg_dma_len(sg);
300 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
301 xfer_len = roundup(min(dma_len - offset, size), 8);
303 size = max(0, size - xfer_len);
314 * pxa_init_dma_channel - init dma descriptors
315 * @pcdev: pxa camera device
316 * @buf: pxa buffer to find pxa dma channel
317 * @dma: dma video buffer
318 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
319 * @cibr: camera Receive Buffer Register
320 * @size: bytes to transfer
321 * @sg_first: first element of sg_list
322 * @sg_first_ofs: offset in first element of sg_list
324 * Prepares the pxa dma descriptors to transfer one camera channel.
325 * Beware sg_first and sg_first_ofs are both input and output parameters.
327 * Returns 0 or -ENOMEM if no coherent memory is available
329 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
330 struct pxa_buffer *buf,
331 struct videobuf_dmabuf *dma, int channel,
333 struct scatterlist **sg_first, int *sg_first_ofs)
335 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
336 struct scatterlist *sg;
337 int i, offset, sglen;
338 int dma_len = 0, xfer_len = 0;
341 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
342 pxa_dma->sg_cpu, pxa_dma->sg_dma);
344 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
345 *sg_first_ofs, size);
347 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
348 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
349 &pxa_dma->sg_dma, GFP_KERNEL);
350 if (!pxa_dma->sg_cpu)
353 pxa_dma->sglen = sglen;
354 offset = *sg_first_ofs;
356 dev_dbg(pcdev->dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
357 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
360 for_each_sg(*sg_first, sg, sglen, i) {
361 dma_len = sg_dma_len(sg);
363 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
364 xfer_len = roundup(min(dma_len - offset, size), 8);
366 size = max(0, size - xfer_len);
368 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
369 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
370 pxa_dma->sg_cpu[i].dcmd =
371 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
374 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
376 pxa_dma->sg_cpu[i].ddadr =
377 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
379 dev_vdbg(pcdev->dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
380 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
381 sg_dma_address(sg) + offset, xfer_len);
388 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
389 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
392 * Handle 1 special case :
393 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
394 * to dma_len (end on PAGE boundary). In this case, the sg element
395 * for next plane should be the next after the last used to store the
396 * last scatter gather RAM page
398 if (xfer_len >= dma_len) {
399 *sg_first_ofs = xfer_len - dma_len;
400 *sg_first = sg_next(sg);
402 *sg_first_ofs = xfer_len;
409 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
410 struct pxa_buffer *buf)
412 buf->active_dma = DMA_Y;
413 if (pcdev->channels == 3)
414 buf->active_dma |= DMA_U | DMA_V;
418 * Please check the DMA prepared buffer structure in :
419 * Documentation/video4linux/pxa_camera.txt
420 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
421 * modification while DMA chain is running will work anyway.
423 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
424 struct videobuf_buffer *vb, enum v4l2_field field)
426 struct soc_camera_device *icd = vq->priv_data;
427 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
428 struct pxa_camera_dev *pcdev = ici->priv;
429 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
431 int size_y, size_u = 0, size_v = 0;
433 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
434 vb, vb->baddr, vb->bsize);
436 /* Added list head initialization on alloc */
437 WARN_ON(!list_empty(&vb->queue));
440 /* This can be useful if you want to see if we actually fill
441 * the buffer with something */
442 memset((void *)vb->baddr, 0xaa, vb->bsize);
445 BUG_ON(NULL == icd->current_fmt);
447 /* I think, in buf_prepare you only have to protect global data,
448 * the actual buffer is yours */
451 if (buf->fmt != icd->current_fmt ||
452 vb->width != icd->width ||
453 vb->height != icd->height ||
454 vb->field != field) {
455 buf->fmt = icd->current_fmt;
456 vb->width = icd->width;
457 vb->height = icd->height;
459 vb->state = VIDEOBUF_NEEDS_INIT;
462 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
463 if (0 != vb->baddr && vb->bsize < vb->size) {
468 if (vb->state == VIDEOBUF_NEEDS_INIT) {
471 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
472 struct scatterlist *sg;
474 ret = videobuf_iolock(vq, vb, NULL);
478 if (pcdev->channels == 3) {
480 size_u = size_v = size / 4;
487 /* init DMA for Y channel */
488 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
492 "DMA initialization for Y/RGB failed\n");
496 /* init DMA for U channel */
498 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
499 size_u, &sg, &next_ofs);
502 "DMA initialization for U failed\n");
506 /* init DMA for V channel */
508 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
509 size_v, &sg, &next_ofs);
512 "DMA initialization for V failed\n");
516 vb->state = VIDEOBUF_PREPARED;
520 pxa_videobuf_set_actdma(pcdev, buf);
525 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
526 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
528 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
529 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
531 free_buffer(vq, buf);
538 * pxa_dma_start_channels - start DMA channel for active buffer
539 * @pcdev: pxa camera device
541 * Initialize DMA channels to the beginning of the active video buffer, and
542 * start these channels.
544 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
547 struct pxa_buffer *active;
549 active = pcdev->active;
551 for (i = 0; i < pcdev->channels; i++) {
552 dev_dbg(pcdev->dev, "%s (channel=%d) ddadr=%08x\n", __func__,
553 i, active->dmas[i].sg_dma);
554 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
555 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
559 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
563 for (i = 0; i < pcdev->channels; i++) {
564 dev_dbg(pcdev->dev, "%s (channel=%d)\n", __func__, i);
565 DCSR(pcdev->dma_chans[i]) = 0;
569 static void pxa_dma_update_sg_tail(struct pxa_camera_dev *pcdev,
570 struct pxa_buffer *buf)
574 for (i = 0; i < pcdev->channels; i++)
575 pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
578 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
579 struct pxa_buffer *buf)
582 struct pxa_dma_desc *buf_last_desc;
584 for (i = 0; i < pcdev->channels; i++) {
585 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
586 buf_last_desc->ddadr = DDADR_STOP;
588 if (!pcdev->sg_tail[i])
590 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
593 pxa_dma_update_sg_tail(pcdev, buf);
597 * pxa_camera_start_capture - start video capturing
598 * @pcdev: camera device
600 * Launch capturing. DMA channels should not be active yet. They should get
601 * activated at the end of frame interrupt, to capture only whole frames, and
602 * never begin the capture of a partial frame.
604 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
606 unsigned long cicr0, cifr;
608 dev_dbg(pcdev->dev, "%s\n", __func__);
609 /* Reset the FIFOs */
610 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
611 __raw_writel(cifr, pcdev->base + CIFR);
612 /* Enable End-Of-Frame Interrupt */
613 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
614 cicr0 &= ~CICR0_EOFM;
615 __raw_writel(cicr0, pcdev->base + CICR0);
618 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
622 pxa_dma_stop_channels(pcdev);
624 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
625 __raw_writel(cicr0, pcdev->base + CICR0);
627 pcdev->active = NULL;
628 dev_dbg(pcdev->dev, "%s\n", __func__);
631 static void pxa_videobuf_queue(struct videobuf_queue *vq,
632 struct videobuf_buffer *vb)
634 struct soc_camera_device *icd = vq->priv_data;
635 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
636 struct pxa_camera_dev *pcdev = ici->priv;
637 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
640 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d active=%p\n", __func__,
641 vb, vb->baddr, vb->bsize, pcdev->active);
643 spin_lock_irqsave(&pcdev->lock, flags);
645 list_add_tail(&vb->queue, &pcdev->capture);
647 vb->state = VIDEOBUF_ACTIVE;
648 pxa_dma_add_tail_buf(pcdev, buf);
651 pxa_camera_start_capture(pcdev);
653 spin_unlock_irqrestore(&pcdev->lock, flags);
656 static void pxa_videobuf_release(struct videobuf_queue *vq,
657 struct videobuf_buffer *vb)
659 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
661 struct soc_camera_device *icd = vq->priv_data;
663 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
664 vb, vb->baddr, vb->bsize);
667 case VIDEOBUF_ACTIVE:
668 dev_dbg(&icd->dev, "%s (active)\n", __func__);
670 case VIDEOBUF_QUEUED:
671 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
673 case VIDEOBUF_PREPARED:
674 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
677 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
682 free_buffer(vq, buf);
685 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
686 struct videobuf_buffer *vb,
687 struct pxa_buffer *buf)
691 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
692 list_del_init(&vb->queue);
693 vb->state = VIDEOBUF_DONE;
694 do_gettimeofday(&vb->ts);
697 dev_dbg(pcdev->dev, "%s dequeud buffer (vb=0x%p)\n", __func__, vb);
699 if (list_empty(&pcdev->capture)) {
700 pxa_camera_stop_capture(pcdev);
701 for (i = 0; i < pcdev->channels; i++)
702 pcdev->sg_tail[i] = NULL;
706 pcdev->active = list_entry(pcdev->capture.next,
707 struct pxa_buffer, vb.queue);
711 * pxa_camera_check_link_miss - check missed DMA linking
712 * @pcdev: camera device
714 * The DMA chaining is done with DMA running. This means a tiny temporal window
715 * remains, where a buffer is queued on the chain, while the chain is already
716 * stopped. This means the tailed buffer would never be transfered by DMA.
717 * This function restarts the capture for this corner case, where :
718 * - DADR() == DADDR_STOP
719 * - a videobuffer is queued on the pcdev->capture list
721 * Please check the "DMA hot chaining timeslice issue" in
722 * Documentation/video4linux/pxa_camera.txt
724 * Context: should only be called within the dma irq handler
726 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
728 int i, is_dma_stopped = 1;
730 for (i = 0; i < pcdev->channels; i++)
731 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
733 dev_dbg(pcdev->dev, "%s : top queued buffer=%p, dma_stopped=%d\n",
734 __func__, pcdev->active, is_dma_stopped);
735 if (pcdev->active && is_dma_stopped)
736 pxa_camera_start_capture(pcdev);
739 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
740 enum pxa_camera_active_dma act_dma)
742 struct pxa_buffer *buf;
744 u32 status, camera_status, overrun;
745 struct videobuf_buffer *vb;
747 spin_lock_irqsave(&pcdev->lock, flags);
749 status = DCSR(channel);
750 DCSR(channel) = status;
752 camera_status = __raw_readl(pcdev->base + CISR);
753 overrun = CISR_IFO_0;
754 if (pcdev->channels == 3)
755 overrun |= CISR_IFO_1 | CISR_IFO_2;
757 if (status & DCSR_BUSERR) {
758 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
762 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
763 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
764 "status: 0x%08x\n", status);
769 * pcdev->active should not be NULL in DMA irq handler.
771 * But there is one corner case : if capture was stopped due to an
772 * overrun of channel 1, and at that same channel 2 was completed.
774 * When handling the overrun in DMA irq for channel 1, we'll stop the
775 * capture and restart it (and thus set pcdev->active to NULL). But the
776 * DMA irq handler will already be pending for channel 2. So on entering
777 * the DMA irq handler for channel 2 there will be no active buffer, yet
783 vb = &pcdev->active->vb;
784 buf = container_of(vb, struct pxa_buffer, vb);
785 WARN_ON(buf->inwork || list_empty(&vb->queue));
787 dev_dbg(pcdev->dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
788 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
789 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
791 if (status & DCSR_ENDINTR) {
793 * It's normal if the last frame creates an overrun, as there
794 * are no more DMA descriptors to fetch from QCI fifos
796 if (camera_status & overrun &&
797 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
798 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n",
800 pxa_camera_stop_capture(pcdev);
801 pxa_camera_start_capture(pcdev);
804 buf->active_dma &= ~act_dma;
805 if (!buf->active_dma) {
806 pxa_camera_wakeup(pcdev, vb, buf);
807 pxa_camera_check_link_miss(pcdev);
812 spin_unlock_irqrestore(&pcdev->lock, flags);
815 static void pxa_camera_dma_irq_y(int channel, void *data)
817 struct pxa_camera_dev *pcdev = data;
818 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
821 static void pxa_camera_dma_irq_u(int channel, void *data)
823 struct pxa_camera_dev *pcdev = data;
824 pxa_camera_dma_irq(channel, pcdev, DMA_U);
827 static void pxa_camera_dma_irq_v(int channel, void *data)
829 struct pxa_camera_dev *pcdev = data;
830 pxa_camera_dma_irq(channel, pcdev, DMA_V);
833 static struct videobuf_queue_ops pxa_videobuf_ops = {
834 .buf_setup = pxa_videobuf_setup,
835 .buf_prepare = pxa_videobuf_prepare,
836 .buf_queue = pxa_videobuf_queue,
837 .buf_release = pxa_videobuf_release,
840 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
841 struct soc_camera_device *icd)
843 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
844 struct pxa_camera_dev *pcdev = ici->priv;
846 /* We must pass NULL as dev pointer, then all pci_* dma operations
847 * transform to normal dma_* ones. */
848 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
849 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
850 sizeof(struct pxa_buffer), icd);
853 static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
855 unsigned long mclk = pcdev->mclk;
857 unsigned long lcdclk;
859 lcdclk = clk_get_rate(pcdev->clk);
860 pcdev->ciclk = lcdclk;
862 /* mclk <= ciclk / 4 (27.4.2) */
863 if (mclk > lcdclk / 4) {
865 dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk);
868 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
869 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
871 /* If we're not supplying MCLK, leave it at 0 */
872 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
873 pcdev->mclk = lcdclk / (2 * (div + 1));
875 dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, "
876 "divisor %u\n", lcdclk, mclk, div);
881 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
884 /* We want a timeout > 1 pixel time, not ">=" */
885 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
887 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
890 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
892 struct pxacamera_platform_data *pdata = pcdev->pdata;
895 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
898 if (pdata && pdata->init) {
899 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
900 pdata->init(pcdev->dev);
903 /* disable all interrupts */
904 __raw_writel(0x3ff, pcdev->base + CICR0);
906 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
907 cicr4 |= CICR4_PCLK_EN;
908 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
909 cicr4 |= CICR4_MCLK_EN;
910 if (pcdev->platform_flags & PXA_CAMERA_PCP)
912 if (pcdev->platform_flags & PXA_CAMERA_HSP)
914 if (pcdev->platform_flags & PXA_CAMERA_VSP)
917 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
919 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
920 /* Initialise the timeout under the assumption pclk = mclk */
921 recalculate_fifo_timeout(pcdev, pcdev->mclk);
923 /* "Safe default" - 13MHz */
924 recalculate_fifo_timeout(pcdev, 13000000);
926 clk_enable(pcdev->clk);
929 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
931 clk_disable(pcdev->clk);
934 static irqreturn_t pxa_camera_irq(int irq, void *data)
936 struct pxa_camera_dev *pcdev = data;
937 unsigned long status, cicr0;
938 struct pxa_buffer *buf;
939 struct videobuf_buffer *vb;
941 status = __raw_readl(pcdev->base + CISR);
942 dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status);
947 __raw_writel(status, pcdev->base + CISR);
949 if (status & CISR_EOF) {
950 pcdev->active = list_first_entry(&pcdev->capture,
951 struct pxa_buffer, vb.queue);
952 vb = &pcdev->active->vb;
953 buf = container_of(vb, struct pxa_buffer, vb);
954 pxa_videobuf_set_actdma(pcdev, buf);
956 pxa_dma_start_channels(pcdev);
958 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
959 __raw_writel(cicr0, pcdev->base + CICR0);
966 * The following two functions absolutely depend on the fact, that
967 * there can be only one camera on PXA quick capture interface
968 * Called with .video_lock held
970 static int pxa_camera_add_device(struct soc_camera_device *icd)
972 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
973 struct pxa_camera_dev *pcdev = ici->priv;
981 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
984 pxa_camera_activate(pcdev);
985 ret = icd->ops->init(icd);
994 /* Called with .video_lock held */
995 static void pxa_camera_remove_device(struct soc_camera_device *icd)
997 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
998 struct pxa_camera_dev *pcdev = ici->priv;
1000 BUG_ON(icd != pcdev->icd);
1002 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
1005 /* disable capture, disable interrupts */
1006 __raw_writel(0x3ff, pcdev->base + CICR0);
1008 /* Stop DMA engine */
1009 DCSR(pcdev->dma_chans[0]) = 0;
1010 DCSR(pcdev->dma_chans[1]) = 0;
1011 DCSR(pcdev->dma_chans[2]) = 0;
1013 icd->ops->release(icd);
1015 pxa_camera_deactivate(pcdev);
1020 static int test_platform_param(struct pxa_camera_dev *pcdev,
1021 unsigned char buswidth, unsigned long *flags)
1024 * Platform specified synchronization and pixel clock polarities are
1025 * only a recommendation and are only used during probing. The PXA270
1026 * quick capture interface supports both.
1028 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1029 SOCAM_MASTER : SOCAM_SLAVE) |
1030 SOCAM_HSYNC_ACTIVE_HIGH |
1031 SOCAM_HSYNC_ACTIVE_LOW |
1032 SOCAM_VSYNC_ACTIVE_HIGH |
1033 SOCAM_VSYNC_ACTIVE_LOW |
1034 SOCAM_DATA_ACTIVE_HIGH |
1035 SOCAM_PCLK_SAMPLE_RISING |
1036 SOCAM_PCLK_SAMPLE_FALLING;
1038 /* If requested data width is supported by the platform, use it */
1041 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1043 *flags |= SOCAM_DATAWIDTH_10;
1046 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1048 *flags |= SOCAM_DATAWIDTH_9;
1051 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1053 *flags |= SOCAM_DATAWIDTH_8;
1062 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1064 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1065 struct pxa_camera_dev *pcdev = ici->priv;
1066 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
1067 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
1068 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
1073 camera_flags = icd->ops->query_bus_param(icd);
1075 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1079 pcdev->channels = 1;
1081 /* Make choises, based on platform preferences */
1082 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1083 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1084 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1085 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1087 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1090 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1091 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1092 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1093 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1095 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1098 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1099 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1100 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1101 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1103 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1106 ret = icd->ops->set_bus_param(icd, common_flags);
1110 /* Datawidth is now guaranteed to be equal to one of the three values.
1111 * We fix bit-per-pixel equal to data-width... */
1112 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
1113 case SOCAM_DATAWIDTH_10:
1117 case SOCAM_DATAWIDTH_9:
1122 /* Actually it can only be 8 now,
1123 * default is just to silence compiler warnings */
1124 case SOCAM_DATAWIDTH_8:
1129 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1130 cicr4 |= CICR4_PCLK_EN;
1131 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1132 cicr4 |= CICR4_MCLK_EN;
1133 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
1135 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
1137 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
1140 cicr0 = __raw_readl(pcdev->base + CICR0);
1141 if (cicr0 & CICR0_ENB)
1142 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1144 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
1147 case V4L2_PIX_FMT_YUV422P:
1148 pcdev->channels = 3;
1149 cicr1 |= CICR1_YCBCR_F;
1151 * Normally, pxa bus wants as input UYVY format. We allow all
1152 * reorderings of the YUV422 format, as no processing is done,
1153 * and the YUV stream is just passed through without any
1154 * transformation. Note that UYVY is the only format that
1155 * should be used if pxa framebuffer Overlay2 is used.
1157 case V4L2_PIX_FMT_UYVY:
1158 case V4L2_PIX_FMT_VYUY:
1159 case V4L2_PIX_FMT_YUYV:
1160 case V4L2_PIX_FMT_YVYU:
1161 cicr1 |= CICR1_COLOR_SP_VAL(2);
1163 case V4L2_PIX_FMT_RGB555:
1164 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1165 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1167 case V4L2_PIX_FMT_RGB565:
1168 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1173 cicr3 = CICR3_LPF_VAL(icd->height - 1) |
1174 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1175 cicr4 |= pcdev->mclk_divisor;
1177 __raw_writel(cicr1, pcdev->base + CICR1);
1178 __raw_writel(cicr2, pcdev->base + CICR2);
1179 __raw_writel(cicr3, pcdev->base + CICR3);
1180 __raw_writel(cicr4, pcdev->base + CICR4);
1182 /* CIF interrupts are not used, only DMA */
1183 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1184 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1185 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1186 __raw_writel(cicr0, pcdev->base + CICR0);
1191 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1192 unsigned char buswidth)
1194 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1195 struct pxa_camera_dev *pcdev = ici->priv;
1196 unsigned long bus_flags, camera_flags;
1197 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1202 camera_flags = icd->ops->query_bus_param(icd);
1204 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1207 static const struct soc_camera_data_format pxa_camera_formats[] = {
1209 .name = "Planar YUV422 16 bit",
1211 .fourcc = V4L2_PIX_FMT_YUV422P,
1212 .colorspace = V4L2_COLORSPACE_JPEG,
1216 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1218 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1219 struct pxa_camera_dev *pcdev = ici->priv;
1223 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1225 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1227 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1232 static int required_buswidth(const struct soc_camera_data_format *fmt)
1234 switch (fmt->fourcc) {
1235 case V4L2_PIX_FMT_UYVY:
1236 case V4L2_PIX_FMT_VYUY:
1237 case V4L2_PIX_FMT_YUYV:
1238 case V4L2_PIX_FMT_YVYU:
1239 case V4L2_PIX_FMT_RGB565:
1240 case V4L2_PIX_FMT_RGB555:
1247 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1248 struct soc_camera_format_xlate *xlate)
1250 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1251 int formats = 0, buswidth, ret;
1253 buswidth = required_buswidth(icd->formats + idx);
1255 if (!buswidth_supported(icd, buswidth))
1258 ret = pxa_camera_try_bus_param(icd, buswidth);
1262 switch (icd->formats[idx].fourcc) {
1263 case V4L2_PIX_FMT_UYVY:
1266 xlate->host_fmt = &pxa_camera_formats[0];
1267 xlate->cam_fmt = icd->formats + idx;
1268 xlate->buswidth = buswidth;
1270 dev_dbg(&ici->dev, "Providing format %s using %s\n",
1271 pxa_camera_formats[0].name,
1272 icd->formats[idx].name);
1274 case V4L2_PIX_FMT_VYUY:
1275 case V4L2_PIX_FMT_YUYV:
1276 case V4L2_PIX_FMT_YVYU:
1277 case V4L2_PIX_FMT_RGB565:
1278 case V4L2_PIX_FMT_RGB555:
1281 xlate->host_fmt = icd->formats + idx;
1282 xlate->cam_fmt = icd->formats + idx;
1283 xlate->buswidth = buswidth;
1285 dev_dbg(&ici->dev, "Providing format %s packed\n",
1286 icd->formats[idx].name);
1290 /* Generic pass-through */
1293 xlate->host_fmt = icd->formats + idx;
1294 xlate->cam_fmt = icd->formats + idx;
1295 xlate->buswidth = icd->formats[idx].depth;
1298 "Providing format %s in pass-through mode\n",
1299 icd->formats[idx].name);
1306 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1307 struct v4l2_rect *rect)
1309 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1310 struct pxa_camera_dev *pcdev = ici->priv;
1311 struct soc_camera_sense sense = {
1312 .master_clock = pcdev->mclk,
1313 .pixel_clock_max = pcdev->ciclk / 4,
1317 /* If PCLK is used to latch data from the sensor, check sense */
1318 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1319 icd->sense = &sense;
1321 ret = icd->ops->set_crop(icd, rect);
1326 dev_warn(&ici->dev, "Failed to crop to %ux%u@%u:%u\n",
1327 rect->width, rect->height, rect->left, rect->top);
1328 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1329 if (sense.pixel_clock > sense.pixel_clock_max) {
1331 "pixel clock %lu set by the camera too high!",
1335 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1341 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1342 struct v4l2_format *f)
1344 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1345 struct pxa_camera_dev *pcdev = ici->priv;
1346 const struct soc_camera_data_format *cam_fmt = NULL;
1347 const struct soc_camera_format_xlate *xlate = NULL;
1348 struct soc_camera_sense sense = {
1349 .master_clock = pcdev->mclk,
1350 .pixel_clock_max = pcdev->ciclk / 4,
1352 struct v4l2_pix_format *pix = &f->fmt.pix;
1353 struct v4l2_format cam_f = *f;
1356 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1358 dev_warn(&ici->dev, "Format %x not found\n", pix->pixelformat);
1362 cam_fmt = xlate->cam_fmt;
1364 /* If PCLK is used to latch data from the sensor, check sense */
1365 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1366 icd->sense = &sense;
1368 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1369 ret = icd->ops->set_fmt(icd, &cam_f);
1374 dev_warn(&ici->dev, "Failed to configure for format %x\n",
1376 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1377 if (sense.pixel_clock > sense.pixel_clock_max) {
1379 "pixel clock %lu set by the camera too high!",
1383 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1387 icd->buswidth = xlate->buswidth;
1388 icd->current_fmt = xlate->host_fmt;
1394 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1395 struct v4l2_format *f)
1397 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1398 const struct soc_camera_format_xlate *xlate;
1399 struct v4l2_pix_format *pix = &f->fmt.pix;
1400 __u32 pixfmt = pix->pixelformat;
1401 enum v4l2_field field;
1404 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1406 dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
1410 /* limit to pxa hardware capabilities */
1411 if (pix->height < 32)
1413 if (pix->height > 2048)
1415 if (pix->width < 48)
1417 if (pix->width > 2048)
1419 pix->width &= ~0x01;
1422 * YUV422P planar format requires images size to be a 16 bytes
1423 * multiple. If not, zeros will be inserted between Y and U planes, and
1424 * U and V planes, and YUV422P standard would be violated.
1426 if (xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
1427 if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN))
1428 pix->height = ALIGN(pix->height, YUV422P_X_Y_ALIGN);
1429 if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN))
1430 pix->width = ALIGN(pix->width, YUV422P_X_Y_ALIGN);
1433 pix->bytesperline = pix->width *
1434 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1435 pix->sizeimage = pix->height * pix->bytesperline;
1437 /* camera has to see its format, but the user the original one */
1438 pix->pixelformat = xlate->cam_fmt->fourcc;
1439 /* limit to sensor capabilities */
1440 ret = icd->ops->try_fmt(icd, f);
1441 pix->pixelformat = xlate->host_fmt->fourcc;
1445 if (field == V4L2_FIELD_ANY) {
1446 pix->field = V4L2_FIELD_NONE;
1447 } else if (field != V4L2_FIELD_NONE) {
1448 dev_err(&icd->dev, "Field type %d unsupported.\n", field);
1455 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1456 struct v4l2_requestbuffers *p)
1460 /* This is for locking debugging only. I removed spinlocks and now I
1461 * check whether .prepare is ever called on a linked buffer, or whether
1462 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1463 * it hadn't triggered */
1464 for (i = 0; i < p->count; i++) {
1465 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1466 struct pxa_buffer, vb);
1468 INIT_LIST_HEAD(&buf->vb.queue);
1474 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1476 struct soc_camera_file *icf = file->private_data;
1477 struct pxa_buffer *buf;
1479 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1482 poll_wait(file, &buf->vb.done, pt);
1484 if (buf->vb.state == VIDEOBUF_DONE ||
1485 buf->vb.state == VIDEOBUF_ERROR)
1486 return POLLIN|POLLRDNORM;
1491 static int pxa_camera_querycap(struct soc_camera_host *ici,
1492 struct v4l2_capability *cap)
1494 /* cap->name is set by the firendly caller:-> */
1495 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1496 cap->version = PXA_CAM_VERSION_CODE;
1497 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1502 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1504 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1505 struct pxa_camera_dev *pcdev = ici->priv;
1508 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1509 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1510 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1511 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1512 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1514 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1515 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1520 static int pxa_camera_resume(struct soc_camera_device *icd)
1522 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1523 struct pxa_camera_dev *pcdev = ici->priv;
1526 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1527 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1528 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1530 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1531 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1532 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1533 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1534 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1536 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1537 ret = pcdev->icd->ops->resume(pcdev->icd);
1539 /* Restart frame capture if active buffer exists */
1540 if (!ret && pcdev->active)
1541 pxa_camera_start_capture(pcdev);
1546 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1547 .owner = THIS_MODULE,
1548 .add = pxa_camera_add_device,
1549 .remove = pxa_camera_remove_device,
1550 .suspend = pxa_camera_suspend,
1551 .resume = pxa_camera_resume,
1552 .set_crop = pxa_camera_set_crop,
1553 .get_formats = pxa_camera_get_formats,
1554 .set_fmt = pxa_camera_set_fmt,
1555 .try_fmt = pxa_camera_try_fmt,
1556 .init_videobuf = pxa_camera_init_videobuf,
1557 .reqbufs = pxa_camera_reqbufs,
1558 .poll = pxa_camera_poll,
1559 .querycap = pxa_camera_querycap,
1560 .set_bus_param = pxa_camera_set_bus_param,
1563 /* Should be allocated dynamically too, but we have only one. */
1564 static struct soc_camera_host pxa_soc_camera_host = {
1565 .drv_name = PXA_CAM_DRV_NAME,
1566 .ops = &pxa_soc_camera_host_ops,
1569 static int pxa_camera_probe(struct platform_device *pdev)
1571 struct pxa_camera_dev *pcdev;
1572 struct resource *res;
1577 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1578 irq = platform_get_irq(pdev, 0);
1579 if (!res || irq < 0) {
1584 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1586 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1591 pcdev->clk = clk_get(&pdev->dev, NULL);
1592 if (IS_ERR(pcdev->clk)) {
1593 err = PTR_ERR(pcdev->clk);
1597 dev_set_drvdata(&pdev->dev, pcdev);
1600 pcdev->pdata = pdev->dev.platform_data;
1601 pcdev->platform_flags = pcdev->pdata->flags;
1602 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1603 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1604 /* Platform hasn't set available data widths. This is bad.
1605 * Warn and use a default. */
1606 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1607 "data widths, using default 10 bit\n");
1608 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1610 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1612 dev_warn(&pdev->dev,
1613 "mclk == 0! Please, fix your platform data. "
1614 "Using default 20MHz\n");
1615 pcdev->mclk = 20000000;
1618 pcdev->dev = &pdev->dev;
1619 pcdev->mclk_divisor = mclk_get_divisor(pcdev);
1621 INIT_LIST_HEAD(&pcdev->capture);
1622 spin_lock_init(&pcdev->lock);
1625 * Request the regions.
1627 if (!request_mem_region(res->start, res->end - res->start + 1,
1628 PXA_CAM_DRV_NAME)) {
1633 base = ioremap(res->start, res->end - res->start + 1);
1642 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1643 pxa_camera_dma_irq_y, pcdev);
1645 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1648 pcdev->dma_chans[0] = err;
1649 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1651 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1652 pxa_camera_dma_irq_u, pcdev);
1654 dev_err(pcdev->dev, "Can't request DMA for U\n");
1655 goto exit_free_dma_y;
1657 pcdev->dma_chans[1] = err;
1658 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1660 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1661 pxa_camera_dma_irq_v, pcdev);
1663 dev_err(pcdev->dev, "Can't request DMA for V\n");
1664 goto exit_free_dma_u;
1666 pcdev->dma_chans[2] = err;
1667 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1669 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1670 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1671 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1674 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1677 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1681 pxa_soc_camera_host.priv = pcdev;
1682 pxa_soc_camera_host.dev.parent = &pdev->dev;
1683 pxa_soc_camera_host.nr = pdev->id;
1684 err = soc_camera_host_register(&pxa_soc_camera_host);
1691 free_irq(pcdev->irq, pcdev);
1693 pxa_free_dma(pcdev->dma_chans[2]);
1695 pxa_free_dma(pcdev->dma_chans[1]);
1697 pxa_free_dma(pcdev->dma_chans[0]);
1701 release_mem_region(res->start, res->end - res->start + 1);
1703 clk_put(pcdev->clk);
1710 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1712 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1713 struct resource *res;
1715 clk_put(pcdev->clk);
1717 pxa_free_dma(pcdev->dma_chans[0]);
1718 pxa_free_dma(pcdev->dma_chans[1]);
1719 pxa_free_dma(pcdev->dma_chans[2]);
1720 free_irq(pcdev->irq, pcdev);
1722 soc_camera_host_unregister(&pxa_soc_camera_host);
1724 iounmap(pcdev->base);
1727 release_mem_region(res->start, res->end - res->start + 1);
1731 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1736 static struct platform_driver pxa_camera_driver = {
1738 .name = PXA_CAM_DRV_NAME,
1740 .probe = pxa_camera_probe,
1741 .remove = __exit_p(pxa_camera_remove),
1745 static int __devinit pxa_camera_init(void)
1747 return platform_driver_register(&pxa_camera_driver);
1750 static void __exit pxa_camera_exit(void)
1752 platform_driver_unregister(&pxa_camera_driver);
1755 module_init(pxa_camera_init);
1756 module_exit(pxa_camera_exit);
1758 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1759 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1760 MODULE_LICENSE("GPL");