SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include <media/tuner.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-eeprom.h"
  34 #include "pvrusb2-hdw-internal.h"
  35 #include "pvrusb2-encoder.h"
  36 #include "pvrusb2-debug.h"
  37 #include "pvrusb2-fx2-cmd.h"
  38 #include "pvrusb2-wm8775.h"
  39 #include "pvrusb2-video-v4l.h"
  40 #include "pvrusb2-cx2584x-v4l.h"
  41 #include "pvrusb2-cs53l32a.h"
  42 #include "pvrusb2-audio.h"
  43
  44 #define TV_MIN_FREQ     55250000L
  45 #define TV_MAX_FREQ    850000000L
  46
  47 /* This defines a minimum interval that the decoder must remain quiet
  48    before we are allowed to start it running. */
  49 #define TIME_MSEC_DECODER_WAIT 50
  50
  51 /* This defines a minimum interval that the decoder must be allowed to run
  52    before we can safely begin using its streaming output. */
  53 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  54
  55 /* This defines a minimum interval that the encoder must remain quiet
  56    before we are allowed to configure it. */
  57 #define TIME_MSEC_ENCODER_WAIT 50
  58
  59 /* This defines the minimum interval that the encoder must successfully run
  60    before we consider that the encoder has run at least once since its
  61    firmware has been loaded.  This measurement is in important for cases
  62    where we can't do something until we know that the encoder has been run
  63    at least once. */
  64 #define TIME_MSEC_ENCODER_OK 250
  65
  66 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  67 static DEFINE_MUTEX(pvr2_unit_mtx);
  68
  69 static int ctlchg;
  70 static int procreload;
  71 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  72 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  73 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  74 static int init_pause_msec;
  75
  76 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  77 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  78 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  79 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  80 module_param(procreload, int, S_IRUGO|S_IWUSR);
  81 MODULE_PARM_DESC(procreload,
  82                  "Attempt init failure recovery with firmware reload");
  83 module_param_array(tuner,    int, NULL, 0444);
  84 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  85 module_param_array(video_std,    int, NULL, 0444);
  86 MODULE_PARM_DESC(video_std,"specify initial video standard");
  87 module_param_array(tolerance,    int, NULL, 0444);
  88 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  89
  90 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
  91 static int default_tv_freq    = 61250000L;
  92 /* 104.3 MHz, a usable FM station for my area */
  93 static int default_radio_freq = 104300000L;
  94
  95 module_param_named(tv_freq, default_tv_freq, int, 0444);
  96 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  97 module_param_named(radio_freq, default_radio_freq, int, 0444);
  98 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  99
 100 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 101 #define PVR2_CTL_READ_ENDPOINT   0x81
 102
 103 #define PVR2_GPIO_IN 0x9008
 104 #define PVR2_GPIO_OUT 0x900c
 105 #define PVR2_GPIO_DIR 0x9020
 106
 107 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 108
 109 #define PVR2_FIRMWARE_ENDPOINT   0x02
 110
 111 /* size of a firmware chunk */
 112 #define FIRMWARE_CHUNK_SIZE 0x2000
 113
 114 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 115                                         struct v4l2_subdev *);
 116
 117 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 118         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 119         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 120         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 121         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 122         [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 123 };
 124
 125 static const char *module_names[] = {
 126         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 127         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 128         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 129         [PVR2_CLIENT_ID_TUNER] = "tuner",
 130         [PVR2_CLIENT_ID_DEMOD] = "tuner",
 131         [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 132         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 133 };
 134
 135
 136 static const unsigned char *module_i2c_addresses[] = {
 137         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 138         [PVR2_CLIENT_ID_DEMOD] = "\x43",
 139         [PVR2_CLIENT_ID_MSP3400] = "\x40",
 140         [PVR2_CLIENT_ID_SAA7115] = "\x21",
 141         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 142         [PVR2_CLIENT_ID_CX25840] = "\x44",
 143         [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 144 };
 145
 146
 147 static const char *ir_scheme_names[] = {
 148         [PVR2_IR_SCHEME_NONE] = "none",
 149         [PVR2_IR_SCHEME_29XXX] = "29xxx",
 150         [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 151         [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 152         [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 153 };
 154
 155
 156 /* Define the list of additional controls we'll dynamically construct based
 157    on query of the cx2341x module. */
 158 struct pvr2_mpeg_ids {
 159         const char *strid;
 160         int id;
 161 };
 162 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 163         {
 164                 .strid = "audio_layer",
 165                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 166         },{
 167                 .strid = "audio_bitrate",
 168                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 169         },{
 170                 /* Already using audio_mode elsewhere :-( */
 171                 .strid = "mpeg_audio_mode",
 172                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 173         },{
 174                 .strid = "mpeg_audio_mode_extension",
 175                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 176         },{
 177                 .strid = "audio_emphasis",
 178                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 179         },{
 180                 .strid = "audio_crc",
 181                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 182         },{
 183                 .strid = "video_aspect",
 184                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 185         },{
 186                 .strid = "video_b_frames",
 187                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 188         },{
 189                 .strid = "video_gop_size",
 190                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 191         },{
 192                 .strid = "video_gop_closure",
 193                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 194         },{
 195                 .strid = "video_bitrate_mode",
 196                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 197         },{
 198                 .strid = "video_bitrate",
 199                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 200         },{
 201                 .strid = "video_bitrate_peak",
 202                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 203         },{
 204                 .strid = "video_temporal_decimation",
 205                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 206         },{
 207                 .strid = "stream_type",
 208                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 209         },{
 210                 .strid = "video_spatial_filter_mode",
 211                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 212         },{
 213                 .strid = "video_spatial_filter",
 214                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 215         },{
 216                 .strid = "video_luma_spatial_filter_type",
 217                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 218         },{
 219                 .strid = "video_chroma_spatial_filter_type",
 220                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 221         },{
 222                 .strid = "video_temporal_filter_mode",
 223                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 224         },{
 225                 .strid = "video_temporal_filter",
 226                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 227         },{
 228                 .strid = "video_median_filter_type",
 229                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 230         },{
 231                 .strid = "video_luma_median_filter_top",
 232                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 233         },{
 234                 .strid = "video_luma_median_filter_bottom",
 235                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 236         },{
 237                 .strid = "video_chroma_median_filter_top",
 238                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 239         },{
 240                 .strid = "video_chroma_median_filter_bottom",
 241                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 242         }
 243 };
 244 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 245
 246
 247 static const char *control_values_srate[] = {
 248         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 249         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 250         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 251 };
 252
 253
 254
 255 static const char *control_values_input[] = {
 256         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 257         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 258         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 259         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 260         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 261 };
 262
 263
 264 static const char *control_values_audiomode[] = {
 265         [V4L2_TUNER_MODE_MONO]   = "Mono",
 266         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 267         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 268         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 269         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 270 };
 271
 272
 273 static const char *control_values_hsm[] = {
 274         [PVR2_CVAL_HSM_FAIL] = "Fail",
 275         [PVR2_CVAL_HSM_HIGH] = "High",
 276         [PVR2_CVAL_HSM_FULL] = "Full",
 277 };
 278
 279
 280 static const char *pvr2_state_names[] = {
 281         [PVR2_STATE_NONE] =    "none",
 282         [PVR2_STATE_DEAD] =    "dead",
 283         [PVR2_STATE_COLD] =    "cold",
 284         [PVR2_STATE_WARM] =    "warm",
 285         [PVR2_STATE_ERROR] =   "error",
 286         [PVR2_STATE_READY] =   "ready",
 287         [PVR2_STATE_RUN] =     "run",
 288 };
 289
 290
 291 struct pvr2_fx2cmd_descdef {
 292         unsigned char id;
 293         unsigned char *desc;
 294 };
 295
 296 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 297         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 298         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 299         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 300         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 301         {FX2CMD_REG_WRITE, "write encoder register"},
 302         {FX2CMD_REG_READ, "read encoder register"},
 303         {FX2CMD_MEMSEL, "encoder memsel"},
 304         {FX2CMD_I2C_WRITE, "i2c write"},
 305         {FX2CMD_I2C_READ, "i2c read"},
 306         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 307         {FX2CMD_STREAMING_ON, "stream on"},
 308         {FX2CMD_STREAMING_OFF, "stream off"},
 309         {FX2CMD_FWPOST1, "fwpost1"},
 310         {FX2CMD_POWER_OFF, "power off"},
 311         {FX2CMD_POWER_ON, "power on"},
 312         {FX2CMD_DEEP_RESET, "deep reset"},
 313         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 314         {FX2CMD_GET_IR_CODE, "get IR code"},
 315         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 316         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 317         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 318         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 319         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 320         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 321         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 322 };
 323
 324
 325 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 326 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 327 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 328 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 329 static void pvr2_hdw_worker_poll(struct work_struct *work);
 330 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 331 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 332 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 333 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 334 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 335 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 336 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 337 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 338 static void pvr2_hdw_quiescent_timeout(unsigned long);
 339 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
 340 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 341 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 342 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 343 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 344                                 unsigned int timeout,int probe_fl,
 345                                 void *write_data,unsigned int write_len,
 346                                 void *read_data,unsigned int read_len);
 347 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 348
 349
 350 static void trace_stbit(const char *name,int val)
 351 {
 352         pvr2_trace(PVR2_TRACE_STBITS,
 353                    "State bit %s <-- %s",
 354                    name,(val ? "true" : "false"));
 355 }
 356
 357 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 358 {
 359         struct pvr2_hdw *hdw = cptr->hdw;
 360         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 361                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 362         } else {
 363                 *vp = 0;
 364         }
 365         return 0;
 366 }
 367
 368 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 369 {
 370         struct pvr2_hdw *hdw = cptr->hdw;
 371         unsigned int slotId = hdw->freqProgSlot;
 372         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 373                 hdw->freqTable[slotId-1] = v;
 374                 /* Handle side effects correctly - if we're tuned to this
 375                    slot, then forgot the slot id relation since the stored
 376                    frequency has been changed. */
 377                 if (hdw->freqSelector) {
 378                         if (hdw->freqSlotRadio == slotId) {
 379                                 hdw->freqSlotRadio = 0;
 380                         }
 381                 } else {
 382                         if (hdw->freqSlotTelevision == slotId) {
 383                                 hdw->freqSlotTelevision = 0;
 384                         }
 385                 }
 386         }
 387         return 0;
 388 }
 389
 390 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 391 {
 392         *vp = cptr->hdw->freqProgSlot;
 393         return 0;
 394 }
 395
 396 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 397 {
 398         struct pvr2_hdw *hdw = cptr->hdw;
 399         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 400                 hdw->freqProgSlot = v;
 401         }
 402         return 0;
 403 }
 404
 405 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 406 {
 407         struct pvr2_hdw *hdw = cptr->hdw;
 408         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 409         return 0;
 410 }
 411
 412 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 413 {
 414         unsigned freq = 0;
 415         struct pvr2_hdw *hdw = cptr->hdw;
 416         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 417         if (slotId > 0) {
 418                 freq = hdw->freqTable[slotId-1];
 419                 if (!freq) return 0;
 420                 pvr2_hdw_set_cur_freq(hdw,freq);
 421         }
 422         if (hdw->freqSelector) {
 423                 hdw->freqSlotRadio = slotId;
 424         } else {
 425                 hdw->freqSlotTelevision = slotId;
 426         }
 427         return 0;
 428 }
 429
 430 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 431 {
 432         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 433         return 0;
 434 }
 435
 436 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 437 {
 438         return cptr->hdw->freqDirty != 0;
 439 }
 440
 441 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 442 {
 443         cptr->hdw->freqDirty = 0;
 444 }
 445
 446 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 447 {
 448         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 449         return 0;
 450 }
 451
 452 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 453 {
 454         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 455         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 456         if (stat != 0) {
 457                 return stat;
 458         }
 459         *left = cap->bounds.left;
 460         return 0;
 461 }
 462
 463 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 464 {
 465         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 466         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 467         if (stat != 0) {
 468                 return stat;
 469         }
 470         *left = cap->bounds.left;
 471         if (cap->bounds.width > cptr->hdw->cropw_val) {
 472                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 473         }
 474         return 0;
 475 }
 476
 477 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 478 {
 479         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 480         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 481         if (stat != 0) {
 482                 return stat;
 483         }
 484         *top = cap->bounds.top;
 485         return 0;
 486 }
 487
 488 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 489 {
 490         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 491         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 492         if (stat != 0) {
 493                 return stat;
 494         }
 495         *top = cap->bounds.top;
 496         if (cap->bounds.height > cptr->hdw->croph_val) {
 497                 *top += cap->bounds.height - cptr->hdw->croph_val;
 498         }
 499         return 0;
 500 }
 501
 502 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 503 {
 504         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 505         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 506         if (stat != 0) {
 507                 return stat;
 508         }
 509         *val = 0;
 510         if (cap->bounds.width > cptr->hdw->cropl_val) {
 511                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 512         }
 513         return 0;
 514 }
 515
 516 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 517 {
 518         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 519         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 520         if (stat != 0) {
 521                 return stat;
 522         }
 523         *val = 0;
 524         if (cap->bounds.height > cptr->hdw->cropt_val) {
 525                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 526         }
 527         return 0;
 528 }
 529
 530 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 531 {
 532         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 533         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 534         if (stat != 0) {
 535                 return stat;
 536         }
 537         *val = cap->bounds.left;
 538         return 0;
 539 }
 540
 541 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 542 {
 543         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 544         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 545         if (stat != 0) {
 546                 return stat;
 547         }
 548         *val = cap->bounds.top;
 549         return 0;
 550 }
 551
 552 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 553 {
 554         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 555         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 556         if (stat != 0) {
 557                 return stat;
 558         }
 559         *val = cap->bounds.width;
 560         return 0;
 561 }
 562
 563 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 564 {
 565         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 566         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 567         if (stat != 0) {
 568                 return stat;
 569         }
 570         *val = cap->bounds.height;
 571         return 0;
 572 }
 573
 574 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 575 {
 576         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 577         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 578         if (stat != 0) {
 579                 return stat;
 580         }
 581         *val = cap->defrect.left;
 582         return 0;
 583 }
 584
 585 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 586 {
 587         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 588         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 589         if (stat != 0) {
 590                 return stat;
 591         }
 592         *val = cap->defrect.top;
 593         return 0;
 594 }
 595
 596 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 597 {
 598         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 599         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 600         if (stat != 0) {
 601                 return stat;
 602         }
 603         *val = cap->defrect.width;
 604         return 0;
 605 }
 606
 607 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 608 {
 609         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 610         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 611         if (stat != 0) {
 612                 return stat;
 613         }
 614         *val = cap->defrect.height;
 615         return 0;
 616 }
 617
 618 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 619 {
 620         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 621         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 622         if (stat != 0) {
 623                 return stat;
 624         }
 625         *val = cap->pixelaspect.numerator;
 626         return 0;
 627 }
 628
 629 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 630 {
 631         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 632         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 633         if (stat != 0) {
 634                 return stat;
 635         }
 636         *val = cap->pixelaspect.denominator;
 637         return 0;
 638 }
 639
 640 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 641 {
 642         /* Actual maximum depends on the video standard in effect. */
 643         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 644                 *vp = 480;
 645         } else {
 646                 *vp = 576;
 647         }
 648         return 0;
 649 }
 650
 651 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 652 {
 653         /* Actual minimum depends on device digitizer type. */
 654         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 655                 *vp = 75;
 656         } else {
 657                 *vp = 17;
 658         }
 659         return 0;
 660 }
 661
 662 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 663 {
 664         *vp = cptr->hdw->input_val;
 665         return 0;
 666 }
 667
 668 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 669 {
 670         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 671 }
 672
 673 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 674 {
 675         return pvr2_hdw_set_input(cptr->hdw,v);
 676 }
 677
 678 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 679 {
 680         return cptr->hdw->input_dirty != 0;
 681 }
 682
 683 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 684 {
 685         cptr->hdw->input_dirty = 0;
 686 }
 687
 688
 689 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 690 {
 691         unsigned long fv;
 692         struct pvr2_hdw *hdw = cptr->hdw;
 693         if (hdw->tuner_signal_stale) {
 694                 pvr2_hdw_status_poll(hdw);
 695         }
 696         fv = hdw->tuner_signal_info.rangehigh;
 697         if (!fv) {
 698                 /* Safety fallback */
 699                 *vp = TV_MAX_FREQ;
 700                 return 0;
 701         }
 702         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 703                 fv = (fv * 125) / 2;
 704         } else {
 705                 fv = fv * 62500;
 706         }
 707         *vp = fv;
 708         return 0;
 709 }
 710
 711 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 712 {
 713         unsigned long fv;
 714         struct pvr2_hdw *hdw = cptr->hdw;
 715         if (hdw->tuner_signal_stale) {
 716                 pvr2_hdw_status_poll(hdw);
 717         }
 718         fv = hdw->tuner_signal_info.rangelow;
 719         if (!fv) {
 720                 /* Safety fallback */
 721                 *vp = TV_MIN_FREQ;
 722                 return 0;
 723         }
 724         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 725                 fv = (fv * 125) / 2;
 726         } else {
 727                 fv = fv * 62500;
 728         }
 729         *vp = fv;
 730         return 0;
 731 }
 732
 733 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 734 {
 735         return cptr->hdw->enc_stale != 0;
 736 }
 737
 738 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 739 {
 740         cptr->hdw->enc_stale = 0;
 741         cptr->hdw->enc_unsafe_stale = 0;
 742 }
 743
 744 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 745 {
 746         int ret;
 747         struct v4l2_ext_controls cs;
 748         struct v4l2_ext_control c1;
 749         memset(&cs,0,sizeof(cs));
 750         memset(&c1,0,sizeof(c1));
 751         cs.controls = &c1;
 752         cs.count = 1;
 753         c1.id = cptr->info->v4l_id;
 754         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 755                                 VIDIOC_G_EXT_CTRLS);
 756         if (ret) return ret;
 757         *vp = c1.value;
 758         return 0;
 759 }
 760
 761 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 762 {
 763         int ret;
 764         struct pvr2_hdw *hdw = cptr->hdw;
 765         struct v4l2_ext_controls cs;
 766         struct v4l2_ext_control c1;
 767         memset(&cs,0,sizeof(cs));
 768         memset(&c1,0,sizeof(c1));
 769         cs.controls = &c1;
 770         cs.count = 1;
 771         c1.id = cptr->info->v4l_id;
 772         c1.value = v;
 773         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 774                                 hdw->state_encoder_run, &cs,
 775                                 VIDIOC_S_EXT_CTRLS);
 776         if (ret == -EBUSY) {
 777                 /* Oops.  cx2341x is telling us it's not safe to change
 778                    this control while we're capturing.  Make a note of this
 779                    fact so that the pipeline will be stopped the next time
 780                    controls are committed.  Then go on ahead and store this
 781                    change anyway. */
 782                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 783                                         0, &cs,
 784                                         VIDIOC_S_EXT_CTRLS);
 785                 if (!ret) hdw->enc_unsafe_stale = !0;
 786         }
 787         if (ret) return ret;
 788         hdw->enc_stale = !0;
 789         return 0;
 790 }
 791
 792 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 793 {
 794         struct v4l2_queryctrl qctrl;
 795         struct pvr2_ctl_info *info;
 796         qctrl.id = cptr->info->v4l_id;
 797         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 798         /* Strip out the const so we can adjust a function pointer.  It's
 799            OK to do this here because we know this is a dynamically created
 800            control, so the underlying storage for the info pointer is (a)
 801            private to us, and (b) not in read-only storage.  Either we do
 802            this or we significantly complicate the underlying control
 803            implementation. */
 804         info = (struct pvr2_ctl_info *)(cptr->info);
 805         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 806                 if (info->set_value) {
 807                         info->set_value = NULL;
 808                 }
 809         } else {
 810                 if (!(info->set_value)) {
 811                         info->set_value = ctrl_cx2341x_set;
 812                 }
 813         }
 814         return qctrl.flags;
 815 }
 816
 817 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 818 {
 819         *vp = cptr->hdw->state_pipeline_req;
 820         return 0;
 821 }
 822
 823 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 824 {
 825         *vp = cptr->hdw->master_state;
 826         return 0;
 827 }
 828
 829 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 830 {
 831         int result = pvr2_hdw_is_hsm(cptr->hdw);
 832         *vp = PVR2_CVAL_HSM_FULL;
 833         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 834         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 835         return 0;
 836 }
 837
 838 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 839 {
 840         *vp = cptr->hdw->std_mask_avail;
 841         return 0;
 842 }
 843
 844 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 845 {
 846         struct pvr2_hdw *hdw = cptr->hdw;
 847         v4l2_std_id ns;
 848         ns = hdw->std_mask_avail;
 849         ns = (ns & ~m) | (v & m);
 850         if (ns == hdw->std_mask_avail) return 0;
 851         hdw->std_mask_avail = ns;
 852         pvr2_hdw_internal_set_std_avail(hdw);
 853         pvr2_hdw_internal_find_stdenum(hdw);
 854         return 0;
 855 }
 856
 857 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 858                                char *bufPtr,unsigned int bufSize,
 859                                unsigned int *len)
 860 {
 861         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 862         return 0;
 863 }
 864
 865 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 866                                const char *bufPtr,unsigned int bufSize,
 867                                int *mskp,int *valp)
 868 {
 869         int ret;
 870         v4l2_std_id id;
 871         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 872         if (ret < 0) return ret;
 873         if (mskp) *mskp = id;
 874         if (valp) *valp = id;
 875         return 0;
 876 }
 877
 878 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 879 {
 880         *vp = cptr->hdw->std_mask_cur;
 881         return 0;
 882 }
 883
 884 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 885 {
 886         struct pvr2_hdw *hdw = cptr->hdw;
 887         v4l2_std_id ns;
 888         ns = hdw->std_mask_cur;
 889         ns = (ns & ~m) | (v & m);
 890         if (ns == hdw->std_mask_cur) return 0;
 891         hdw->std_mask_cur = ns;
 892         hdw->std_dirty = !0;
 893         pvr2_hdw_internal_find_stdenum(hdw);
 894         return 0;
 895 }
 896
 897 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 898 {
 899         return cptr->hdw->std_dirty != 0;
 900 }
 901
 902 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 903 {
 904         cptr->hdw->std_dirty = 0;
 905 }
 906
 907 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 908 {
 909         struct pvr2_hdw *hdw = cptr->hdw;
 910         pvr2_hdw_status_poll(hdw);
 911         *vp = hdw->tuner_signal_info.signal;
 912         return 0;
 913 }
 914
 915 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 916 {
 917         int val = 0;
 918         unsigned int subchan;
 919         struct pvr2_hdw *hdw = cptr->hdw;
 920         pvr2_hdw_status_poll(hdw);
 921         subchan = hdw->tuner_signal_info.rxsubchans;
 922         if (subchan & V4L2_TUNER_SUB_MONO) {
 923                 val |= (1 << V4L2_TUNER_MODE_MONO);
 924         }
 925         if (subchan & V4L2_TUNER_SUB_STEREO) {
 926                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 927         }
 928         if (subchan & V4L2_TUNER_SUB_LANG1) {
 929                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 930         }
 931         if (subchan & V4L2_TUNER_SUB_LANG2) {
 932                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 933         }
 934         *vp = val;
 935         return 0;
 936 }
 937
 938
 939 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 940 {
 941         struct pvr2_hdw *hdw = cptr->hdw;
 942         if (v < 0) return -EINVAL;
 943         if (v > hdw->std_enum_cnt) return -EINVAL;
 944         hdw->std_enum_cur = v;
 945         if (!v) return 0;
 946         v--;
 947         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 948         hdw->std_mask_cur = hdw->std_defs[v].id;
 949         hdw->std_dirty = !0;
 950         return 0;
 951 }
 952
 953
 954 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 955 {
 956         *vp = cptr->hdw->std_enum_cur;
 957         return 0;
 958 }
 959
 960
 961 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 962 {
 963         return cptr->hdw->std_dirty != 0;
 964 }
 965
 966
 967 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 968 {
 969         cptr->hdw->std_dirty = 0;
 970 }
 971
 972
 973 #define DEFINT(vmin,vmax) \
 974         .type = pvr2_ctl_int, \
 975         .def.type_int.min_value = vmin, \
 976         .def.type_int.max_value = vmax
 977
 978 #define DEFENUM(tab) \
 979         .type = pvr2_ctl_enum, \
 980         .def.type_enum.count = ARRAY_SIZE(tab), \
 981         .def.type_enum.value_names = tab
 982
 983 #define DEFBOOL \
 984         .type = pvr2_ctl_bool
 985
 986 #define DEFMASK(msk,tab) \
 987         .type = pvr2_ctl_bitmask, \
 988         .def.type_bitmask.valid_bits = msk, \
 989         .def.type_bitmask.bit_names = tab
 990
 991 #define DEFREF(vname) \
 992         .set_value = ctrl_set_##vname, \
 993         .get_value = ctrl_get_##vname, \
 994         .is_dirty = ctrl_isdirty_##vname, \
 995         .clear_dirty = ctrl_cleardirty_##vname
 996
 997
 998 #define VCREATE_FUNCS(vname) \
 999 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1000 {*vp = cptr->hdw->vname##_val; return 0;} \
1001 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1002 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1003 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1004 {return cptr->hdw->vname##_dirty != 0;} \
1005 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1006 {cptr->hdw->vname##_dirty = 0;}
1007
1008 VCREATE_FUNCS(brightness)
1009 VCREATE_FUNCS(contrast)
1010 VCREATE_FUNCS(saturation)
1011 VCREATE_FUNCS(hue)
1012 VCREATE_FUNCS(volume)
1013 VCREATE_FUNCS(balance)
1014 VCREATE_FUNCS(bass)
1015 VCREATE_FUNCS(treble)
1016 VCREATE_FUNCS(mute)
1017 VCREATE_FUNCS(cropl)
1018 VCREATE_FUNCS(cropt)
1019 VCREATE_FUNCS(cropw)
1020 VCREATE_FUNCS(croph)
1021 VCREATE_FUNCS(audiomode)
1022 VCREATE_FUNCS(res_hor)
1023 VCREATE_FUNCS(res_ver)
1024 VCREATE_FUNCS(srate)
1025
1026 /* Table definition of all controls which can be manipulated */
1027 static const struct pvr2_ctl_info control_defs[] = {
1028         {
1029                 .v4l_id = V4L2_CID_BRIGHTNESS,
1030                 .desc = "Brightness",
1031                 .name = "brightness",
1032                 .default_value = 128,
1033                 DEFREF(brightness),
1034                 DEFINT(0,255),
1035         },{
1036                 .v4l_id = V4L2_CID_CONTRAST,
1037                 .desc = "Contrast",
1038                 .name = "contrast",
1039                 .default_value = 68,
1040                 DEFREF(contrast),
1041                 DEFINT(0,127),
1042         },{
1043                 .v4l_id = V4L2_CID_SATURATION,
1044                 .desc = "Saturation",
1045                 .name = "saturation",
1046                 .default_value = 64,
1047                 DEFREF(saturation),
1048                 DEFINT(0,127),
1049         },{
1050                 .v4l_id = V4L2_CID_HUE,
1051                 .desc = "Hue",
1052                 .name = "hue",
1053                 .default_value = 0,
1054                 DEFREF(hue),
1055                 DEFINT(-128,127),
1056         },{
1057                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1058                 .desc = "Volume",
1059                 .name = "volume",
1060                 .default_value = 62000,
1061                 DEFREF(volume),
1062                 DEFINT(0,65535),
1063         },{
1064                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1065                 .desc = "Balance",
1066                 .name = "balance",
1067                 .default_value = 0,
1068                 DEFREF(balance),
1069                 DEFINT(-32768,32767),
1070         },{
1071                 .v4l_id = V4L2_CID_AUDIO_BASS,
1072                 .desc = "Bass",
1073                 .name = "bass",
1074                 .default_value = 0,
1075                 DEFREF(bass),
1076                 DEFINT(-32768,32767),
1077         },{
1078                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1079                 .desc = "Treble",
1080                 .name = "treble",
1081                 .default_value = 0,
1082                 DEFREF(treble),
1083                 DEFINT(-32768,32767),
1084         },{
1085                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1086                 .desc = "Mute",
1087                 .name = "mute",
1088                 .default_value = 0,
1089                 DEFREF(mute),
1090                 DEFBOOL,
1091         }, {
1092                 .desc = "Capture crop left margin",
1093                 .name = "crop_left",
1094                 .internal_id = PVR2_CID_CROPL,
1095                 .default_value = 0,
1096                 DEFREF(cropl),
1097                 DEFINT(-129, 340),
1098                 .get_min_value = ctrl_cropl_min_get,
1099                 .get_max_value = ctrl_cropl_max_get,
1100                 .get_def_value = ctrl_get_cropcapdl,
1101         }, {
1102                 .desc = "Capture crop top margin",
1103                 .name = "crop_top",
1104                 .internal_id = PVR2_CID_CROPT,
1105                 .default_value = 0,
1106                 DEFREF(cropt),
1107                 DEFINT(-35, 544),
1108                 .get_min_value = ctrl_cropt_min_get,
1109                 .get_max_value = ctrl_cropt_max_get,
1110                 .get_def_value = ctrl_get_cropcapdt,
1111         }, {
1112                 .desc = "Capture crop width",
1113                 .name = "crop_width",
1114                 .internal_id = PVR2_CID_CROPW,
1115                 .default_value = 720,
1116                 DEFREF(cropw),
1117                 .get_max_value = ctrl_cropw_max_get,
1118                 .get_def_value = ctrl_get_cropcapdw,
1119         }, {
1120                 .desc = "Capture crop height",
1121                 .name = "crop_height",
1122                 .internal_id = PVR2_CID_CROPH,
1123                 .default_value = 480,
1124                 DEFREF(croph),
1125                 .get_max_value = ctrl_croph_max_get,
1126                 .get_def_value = ctrl_get_cropcapdh,
1127         }, {
1128                 .desc = "Capture capability pixel aspect numerator",
1129                 .name = "cropcap_pixel_numerator",
1130                 .internal_id = PVR2_CID_CROPCAPPAN,
1131                 .get_value = ctrl_get_cropcappan,
1132         }, {
1133                 .desc = "Capture capability pixel aspect denominator",
1134                 .name = "cropcap_pixel_denominator",
1135                 .internal_id = PVR2_CID_CROPCAPPAD,
1136                 .get_value = ctrl_get_cropcappad,
1137         }, {
1138                 .desc = "Capture capability bounds top",
1139                 .name = "cropcap_bounds_top",
1140                 .internal_id = PVR2_CID_CROPCAPBT,
1141                 .get_value = ctrl_get_cropcapbt,
1142         }, {
1143                 .desc = "Capture capability bounds left",
1144                 .name = "cropcap_bounds_left",
1145                 .internal_id = PVR2_CID_CROPCAPBL,
1146                 .get_value = ctrl_get_cropcapbl,
1147         }, {
1148                 .desc = "Capture capability bounds width",
1149                 .name = "cropcap_bounds_width",
1150                 .internal_id = PVR2_CID_CROPCAPBW,
1151                 .get_value = ctrl_get_cropcapbw,
1152         }, {
1153                 .desc = "Capture capability bounds height",
1154                 .name = "cropcap_bounds_height",
1155                 .internal_id = PVR2_CID_CROPCAPBH,
1156                 .get_value = ctrl_get_cropcapbh,
1157         },{
1158                 .desc = "Video Source",
1159                 .name = "input",
1160                 .internal_id = PVR2_CID_INPUT,
1161                 .default_value = PVR2_CVAL_INPUT_TV,
1162                 .check_value = ctrl_check_input,
1163                 DEFREF(input),
1164                 DEFENUM(control_values_input),
1165         },{
1166                 .desc = "Audio Mode",
1167                 .name = "audio_mode",
1168                 .internal_id = PVR2_CID_AUDIOMODE,
1169                 .default_value = V4L2_TUNER_MODE_STEREO,
1170                 DEFREF(audiomode),
1171                 DEFENUM(control_values_audiomode),
1172         },{
1173                 .desc = "Horizontal capture resolution",
1174                 .name = "resolution_hor",
1175                 .internal_id = PVR2_CID_HRES,
1176                 .default_value = 720,
1177                 DEFREF(res_hor),
1178                 DEFINT(19,720),
1179         },{
1180                 .desc = "Vertical capture resolution",
1181                 .name = "resolution_ver",
1182                 .internal_id = PVR2_CID_VRES,
1183                 .default_value = 480,
1184                 DEFREF(res_ver),
1185                 DEFINT(17,576),
1186                 /* Hook in check for video standard and adjust maximum
1187                    depending on the standard. */
1188                 .get_max_value = ctrl_vres_max_get,
1189                 .get_min_value = ctrl_vres_min_get,
1190         },{
1191                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1192                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1193                 .desc = "Audio Sampling Frequency",
1194                 .name = "srate",
1195                 DEFREF(srate),
1196                 DEFENUM(control_values_srate),
1197         },{
1198                 .desc = "Tuner Frequency (Hz)",
1199                 .name = "frequency",
1200                 .internal_id = PVR2_CID_FREQUENCY,
1201                 .default_value = 0,
1202                 .set_value = ctrl_freq_set,
1203                 .get_value = ctrl_freq_get,
1204                 .is_dirty = ctrl_freq_is_dirty,
1205                 .clear_dirty = ctrl_freq_clear_dirty,
1206                 DEFINT(0,0),
1207                 /* Hook in check for input value (tv/radio) and adjust
1208                    max/min values accordingly */
1209                 .get_max_value = ctrl_freq_max_get,
1210                 .get_min_value = ctrl_freq_min_get,
1211         },{
1212                 .desc = "Channel",
1213                 .name = "channel",
1214                 .set_value = ctrl_channel_set,
1215                 .get_value = ctrl_channel_get,
1216                 DEFINT(0,FREQTABLE_SIZE),
1217         },{
1218                 .desc = "Channel Program Frequency",
1219                 .name = "freq_table_value",
1220                 .set_value = ctrl_channelfreq_set,
1221                 .get_value = ctrl_channelfreq_get,
1222                 DEFINT(0,0),
1223                 /* Hook in check for input value (tv/radio) and adjust
1224                    max/min values accordingly */
1225                 .get_max_value = ctrl_freq_max_get,
1226                 .get_min_value = ctrl_freq_min_get,
1227         },{
1228                 .desc = "Channel Program ID",
1229                 .name = "freq_table_channel",
1230                 .set_value = ctrl_channelprog_set,
1231                 .get_value = ctrl_channelprog_get,
1232                 DEFINT(0,FREQTABLE_SIZE),
1233         },{
1234                 .desc = "Streaming Enabled",
1235                 .name = "streaming_enabled",
1236                 .get_value = ctrl_streamingenabled_get,
1237                 DEFBOOL,
1238         },{
1239                 .desc = "USB Speed",
1240                 .name = "usb_speed",
1241                 .get_value = ctrl_hsm_get,
1242                 DEFENUM(control_values_hsm),
1243         },{
1244                 .desc = "Master State",
1245                 .name = "master_state",
1246                 .get_value = ctrl_masterstate_get,
1247                 DEFENUM(pvr2_state_names),
1248         },{
1249                 .desc = "Signal Present",
1250                 .name = "signal_present",
1251                 .get_value = ctrl_signal_get,
1252                 DEFINT(0,65535),
1253         },{
1254                 .desc = "Audio Modes Present",
1255                 .name = "audio_modes_present",
1256                 .get_value = ctrl_audio_modes_present_get,
1257                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1258                    v4l.  Nothing outside of this module cares about this,
1259                    but I reuse it in order to also reuse the
1260                    control_values_audiomode string table. */
1261                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1262                          (1 << V4L2_TUNER_MODE_STEREO)|
1263                          (1 << V4L2_TUNER_MODE_LANG1)|
1264                          (1 << V4L2_TUNER_MODE_LANG2)),
1265                         control_values_audiomode),
1266         },{
1267                 .desc = "Video Standards Available Mask",
1268                 .name = "video_standard_mask_available",
1269                 .internal_id = PVR2_CID_STDAVAIL,
1270                 .skip_init = !0,
1271                 .get_value = ctrl_stdavail_get,
1272                 .set_value = ctrl_stdavail_set,
1273                 .val_to_sym = ctrl_std_val_to_sym,
1274                 .sym_to_val = ctrl_std_sym_to_val,
1275                 .type = pvr2_ctl_bitmask,
1276         },{
1277                 .desc = "Video Standards In Use Mask",
1278                 .name = "video_standard_mask_active",
1279                 .internal_id = PVR2_CID_STDCUR,
1280                 .skip_init = !0,
1281                 .get_value = ctrl_stdcur_get,
1282                 .set_value = ctrl_stdcur_set,
1283                 .is_dirty = ctrl_stdcur_is_dirty,
1284                 .clear_dirty = ctrl_stdcur_clear_dirty,
1285                 .val_to_sym = ctrl_std_val_to_sym,
1286                 .sym_to_val = ctrl_std_sym_to_val,
1287                 .type = pvr2_ctl_bitmask,
1288         },{
1289                 .desc = "Video Standard Name",
1290                 .name = "video_standard",
1291                 .internal_id = PVR2_CID_STDENUM,
1292                 .skip_init = !0,
1293                 .get_value = ctrl_stdenumcur_get,
1294                 .set_value = ctrl_stdenumcur_set,
1295                 .is_dirty = ctrl_stdenumcur_is_dirty,
1296                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1297                 .type = pvr2_ctl_enum,
1298         }
1299 };
1300
1301 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1302
1303
1304 const char *pvr2_config_get_name(enum pvr2_config cfg)
1305 {
1306         switch (cfg) {
1307         case pvr2_config_empty: return "empty";
1308         case pvr2_config_mpeg: return "mpeg";
1309         case pvr2_config_vbi: return "vbi";
1310         case pvr2_config_pcm: return "pcm";
1311         case pvr2_config_rawvideo: return "raw video";
1312         }
1313         return "<unknown>";
1314 }
1315
1316
1317 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1318 {
1319         return hdw->usb_dev;
1320 }
1321
1322
1323 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1324 {
1325         return hdw->serial_number;
1326 }
1327
1328
1329 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1330 {
1331         return hdw->bus_info;
1332 }
1333
1334
1335 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1336 {
1337         return hdw->identifier;
1338 }
1339
1340
1341 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1342 {
1343         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1344 }
1345
1346 /* Set the currently tuned frequency and account for all possible
1347    driver-core side effects of this action. */
1348 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1349 {
1350         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1351                 if (hdw->freqSelector) {
1352                         /* Swing over to radio frequency selection */
1353                         hdw->freqSelector = 0;
1354                         hdw->freqDirty = !0;
1355                 }
1356                 if (hdw->freqValRadio != val) {
1357                         hdw->freqValRadio = val;
1358                         hdw->freqSlotRadio = 0;
1359                         hdw->freqDirty = !0;
1360                 }
1361         } else {
1362                 if (!(hdw->freqSelector)) {
1363                         /* Swing over to television frequency selection */
1364                         hdw->freqSelector = 1;
1365                         hdw->freqDirty = !0;
1366                 }
1367                 if (hdw->freqValTelevision != val) {
1368                         hdw->freqValTelevision = val;
1369                         hdw->freqSlotTelevision = 0;
1370                         hdw->freqDirty = !0;
1371                 }
1372         }
1373 }
1374
1375 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1376 {
1377         return hdw->unit_number;
1378 }
1379
1380
1381 /* Attempt to locate one of the given set of files.  Messages are logged
1382    appropriate to what has been found.  The return value will be 0 or
1383    greater on success (it will be the index of the file name found) and
1384    fw_entry will be filled in.  Otherwise a negative error is returned on
1385    failure.  If the return value is -ENOENT then no viable firmware file
1386    could be located. */
1387 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1388                                 const struct firmware **fw_entry,
1389                                 const char *fwtypename,
1390                                 unsigned int fwcount,
1391                                 const char *fwnames[])
1392 {
1393         unsigned int idx;
1394         int ret = -EINVAL;
1395         for (idx = 0; idx < fwcount; idx++) {
1396                 ret = request_firmware(fw_entry,
1397                                        fwnames[idx],
1398                                        &hdw->usb_dev->dev);
1399                 if (!ret) {
1400                         trace_firmware("Located %s firmware: %s;"
1401                                        " uploading...",
1402                                        fwtypename,
1403                                        fwnames[idx]);
1404                         return idx;
1405                 }
1406                 if (ret == -ENOENT) continue;
1407                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1408                            "request_firmware fatal error with code=%d",ret);
1409                 return ret;
1410         }
1411         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1412                    "***WARNING***"
1413                    " Device %s firmware"
1414                    " seems to be missing.",
1415                    fwtypename);
1416         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1417                    "Did you install the pvrusb2 firmware files"
1418                    " in their proper location?");
1419         if (fwcount == 1) {
1420                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1421                            "request_firmware unable to locate %s file %s",
1422                            fwtypename,fwnames[0]);
1423         } else {
1424                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425                            "request_firmware unable to locate"
1426                            " one of the following %s files:",
1427                            fwtypename);
1428                 for (idx = 0; idx < fwcount; idx++) {
1429                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1430                                    "request_firmware: Failed to find %s",
1431                                    fwnames[idx]);
1432                 }
1433         }
1434         return ret;
1435 }
1436
1437
1438 /*
1439  * pvr2_upload_firmware1().
1440  *
1441  * Send the 8051 firmware to the device.  After the upload, arrange for
1442  * device to re-enumerate.
1443  *
1444  * NOTE : the pointer to the firmware data given by request_firmware()
1445  * is not suitable for an usb transaction.
1446  *
1447  */
1448 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1449 {
1450         const struct firmware *fw_entry = NULL;
1451         void  *fw_ptr;
1452         unsigned int pipe;
1453         unsigned int fwsize;
1454         int ret;
1455         u16 address;
1456
1457         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1458                 hdw->fw1_state = FW1_STATE_OK;
1459                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1460                            "Connected device type defines"
1461                            " no firmware to upload; ignoring firmware");
1462                 return -ENOTTY;
1463         }
1464
1465         hdw->fw1_state = FW1_STATE_FAILED; // default result
1466
1467         trace_firmware("pvr2_upload_firmware1");
1468
1469         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1470                                    hdw->hdw_desc->fx2_firmware.cnt,
1471                                    hdw->hdw_desc->fx2_firmware.lst);
1472         if (ret < 0) {
1473                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1474                 return ret;
1475         }
1476
1477         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1478
1479         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1480         fwsize = fw_entry->size;
1481
1482         if ((fwsize != 0x2000) &&
1483             (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1484                 if (hdw->hdw_desc->flag_fx2_16kb) {
1485                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1486                                    "Wrong fx2 firmware size"
1487                                    " (expected 8192 or 16384, got %u)",
1488                                    fwsize);
1489                 } else {
1490                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1491                                    "Wrong fx2 firmware size"
1492                                    " (expected 8192, got %u)",
1493                                    fwsize);
1494                 }
1495                 release_firmware(fw_entry);
1496                 return -ENOMEM;
1497         }
1498
1499         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1500         if (fw_ptr == NULL){
1501                 release_firmware(fw_entry);
1502                 return -ENOMEM;
1503         }
1504
1505         /* We have to hold the CPU during firmware upload. */
1506         pvr2_hdw_cpureset_assert(hdw,1);
1507
1508         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1509            chunk. */
1510
1511         ret = 0;
1512         for (address = 0; address < fwsize; address += 0x800) {
1513                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1514                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1515                                        0, fw_ptr, 0x800, HZ);
1516         }
1517
1518         trace_firmware("Upload done, releasing device's CPU");
1519
1520         /* Now release the CPU.  It will disconnect and reconnect later. */
1521         pvr2_hdw_cpureset_assert(hdw,0);
1522
1523         kfree(fw_ptr);
1524         release_firmware(fw_entry);
1525
1526         trace_firmware("Upload done (%d bytes sent)",ret);
1527
1528         /* We should have written fwsize bytes */
1529         if (ret == fwsize) {
1530                 hdw->fw1_state = FW1_STATE_RELOAD;
1531                 return 0;
1532         }
1533
1534         return -EIO;
1535 }
1536
1537
1538 /*
1539  * pvr2_upload_firmware2()
1540  *
1541  * This uploads encoder firmware on endpoint 2.
1542  *
1543  */
1544
1545 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1546 {
1547         const struct firmware *fw_entry = NULL;
1548         void  *fw_ptr;
1549         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1550         int actual_length;
1551         int ret = 0;
1552         int fwidx;
1553         static const char *fw_files[] = {
1554                 CX2341X_FIRM_ENC_FILENAME,
1555         };
1556
1557         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1558                 return 0;
1559         }
1560
1561         trace_firmware("pvr2_upload_firmware2");
1562
1563         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1564                                    ARRAY_SIZE(fw_files), fw_files);
1565         if (ret < 0) return ret;
1566         fwidx = ret;
1567         ret = 0;
1568         /* Since we're about to completely reinitialize the encoder,
1569            invalidate our cached copy of its configuration state.  Next
1570            time we configure the encoder, then we'll fully configure it. */
1571         hdw->enc_cur_valid = 0;
1572
1573         /* Encoder is about to be reset so note that as far as we're
1574            concerned now, the encoder has never been run. */
1575         del_timer_sync(&hdw->encoder_run_timer);
1576         if (hdw->state_encoder_runok) {
1577                 hdw->state_encoder_runok = 0;
1578                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1579         }
1580
1581         /* First prepare firmware loading */
1582         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1583         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1584         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1585         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1586         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1587         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1588         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1589         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1590         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1591         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1592         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1593         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1594         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1595         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1596         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1597         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1598         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1599         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1600
1601         if (ret) {
1602                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1603                            "firmware2 upload prep failed, ret=%d",ret);
1604                 release_firmware(fw_entry);
1605                 goto done;
1606         }
1607
1608         /* Now send firmware */
1609
1610         fw_len = fw_entry->size;
1611
1612         if (fw_len % sizeof(u32)) {
1613                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1614                            "size of %s firmware"
1615                            " must be a multiple of %zu bytes",
1616                            fw_files[fwidx],sizeof(u32));
1617                 release_firmware(fw_entry);
1618                 ret = -EINVAL;
1619                 goto done;
1620         }
1621
1622         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1623         if (fw_ptr == NULL){
1624                 release_firmware(fw_entry);
1625                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1626                            "failed to allocate memory for firmware2 upload");
1627                 ret = -ENOMEM;
1628                 goto done;
1629         }
1630
1631         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1632
1633         fw_done = 0;
1634         for (fw_done = 0; fw_done < fw_len;) {
1635                 bcnt = fw_len - fw_done;
1636                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1637                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1638                 /* Usbsnoop log shows that we must swap bytes... */
1639                 /* Some background info: The data being swapped here is a
1640                    firmware image destined for the mpeg encoder chip that
1641                    lives at the other end of a USB endpoint.  The encoder
1642                    chip always talks in 32 bit chunks and its storage is
1643                    organized into 32 bit words.  However from the file
1644                    system to the encoder chip everything is purely a byte
1645                    stream.  The firmware file's contents are always 32 bit
1646                    swapped from what the encoder expects.  Thus the need
1647                    always exists to swap the bytes regardless of the endian
1648                    type of the host processor and therefore swab32() makes
1649                    the most sense. */
1650                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1651                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1652
1653                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1654                                     &actual_length, HZ);
1655                 ret |= (actual_length != bcnt);
1656                 if (ret) break;
1657                 fw_done += bcnt;
1658         }
1659
1660         trace_firmware("upload of %s : %i / %i ",
1661                        fw_files[fwidx],fw_done,fw_len);
1662
1663         kfree(fw_ptr);
1664         release_firmware(fw_entry);
1665
1666         if (ret) {
1667                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1668                            "firmware2 upload transfer failure");
1669                 goto done;
1670         }
1671
1672         /* Finish upload */
1673
1674         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1675         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1676         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1677
1678         if (ret) {
1679                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1680                            "firmware2 upload post-proc failure");
1681         }
1682
1683  done:
1684         if (hdw->hdw_desc->signal_routing_scheme ==
1685             PVR2_ROUTING_SCHEME_GOTVIEW) {
1686                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1687                    hardware. */
1688                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1689         }
1690         return ret;
1691 }
1692
1693
1694 static const char *pvr2_get_state_name(unsigned int st)
1695 {
1696         if (st < ARRAY_SIZE(pvr2_state_names)) {
1697                 return pvr2_state_names[st];
1698         }
1699         return "???";
1700 }
1701
1702 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1703 {
1704         /* Even though we really only care about the video decoder chip at
1705            this point, we'll broadcast stream on/off to all sub-devices
1706            anyway, just in case somebody else wants to hear the
1707            command... */
1708         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1709                    (enablefl ? "on" : "off"));
1710         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1711         v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1712         if (hdw->decoder_client_id) {
1713                 /* We get here if the encoder has been noticed.  Otherwise
1714                    we'll issue a warning to the user (which should
1715                    normally never happen). */
1716                 return 0;
1717         }
1718         if (!hdw->flag_decoder_missed) {
1719                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1720                            "WARNING: No decoder present");
1721                 hdw->flag_decoder_missed = !0;
1722                 trace_stbit("flag_decoder_missed",
1723                             hdw->flag_decoder_missed);
1724         }
1725         return -EIO;
1726 }
1727
1728
1729 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1730 {
1731         return hdw->master_state;
1732 }
1733
1734
1735 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1736 {
1737         if (!hdw->flag_tripped) return 0;
1738         hdw->flag_tripped = 0;
1739         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1740                    "Clearing driver error statuss");
1741         return !0;
1742 }
1743
1744
1745 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1746 {
1747         int fl;
1748         LOCK_TAKE(hdw->big_lock); do {
1749                 fl = pvr2_hdw_untrip_unlocked(hdw);
1750         } while (0); LOCK_GIVE(hdw->big_lock);
1751         if (fl) pvr2_hdw_state_sched(hdw);
1752         return 0;
1753 }
1754
1755
1756
1757
1758 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1759 {
1760         return hdw->state_pipeline_req != 0;
1761 }
1762
1763
1764 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1765 {
1766         int ret,st;
1767         LOCK_TAKE(hdw->big_lock); do {
1768                 pvr2_hdw_untrip_unlocked(hdw);
1769                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1770                         hdw->state_pipeline_req = enable_flag != 0;
1771                         pvr2_trace(PVR2_TRACE_START_STOP,
1772                                    "/*--TRACE_STREAM--*/ %s",
1773                                    enable_flag ? "enable" : "disable");
1774                 }
1775                 pvr2_hdw_state_sched(hdw);
1776         } while (0); LOCK_GIVE(hdw->big_lock);
1777         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1778         if (enable_flag) {
1779                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1780                         if (st != PVR2_STATE_READY) return -EIO;
1781                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1782                 }
1783         }
1784         return 0;
1785 }
1786
1787
1788 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1789 {
1790         int fl;
1791         LOCK_TAKE(hdw->big_lock);
1792         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1793                 hdw->desired_stream_type = config;
1794                 hdw->state_pipeline_config = 0;
1795                 trace_stbit("state_pipeline_config",
1796                             hdw->state_pipeline_config);
1797                 pvr2_hdw_state_sched(hdw);
1798         }
1799         LOCK_GIVE(hdw->big_lock);
1800         if (fl) return 0;
1801         return pvr2_hdw_wait(hdw,0);
1802 }
1803
1804
1805 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1806 {
1807         int unit_number = hdw->unit_number;
1808         int tp = -1;
1809         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1810                 tp = tuner[unit_number];
1811         }
1812         if (tp < 0) return -EINVAL;
1813         hdw->tuner_type = tp;
1814         hdw->tuner_updated = !0;
1815         return 0;
1816 }
1817
1818
1819 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1820 {
1821         int unit_number = hdw->unit_number;
1822         int tp = 0;
1823         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1824                 tp = video_std[unit_number];
1825                 if (tp) return tp;
1826         }
1827         return 0;
1828 }
1829
1830
1831 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1832 {
1833         int unit_number = hdw->unit_number;
1834         int tp = 0;
1835         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1836                 tp = tolerance[unit_number];
1837         }
1838         return tp;
1839 }
1840
1841
1842 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1843 {
1844         /* Try a harmless request to fetch the eeprom's address over
1845            endpoint 1.  See what happens.  Only the full FX2 image can
1846            respond to this.  If this probe fails then likely the FX2
1847            firmware needs be loaded. */
1848         int result;
1849         LOCK_TAKE(hdw->ctl_lock); do {
1850                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1851                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1852                                            hdw->cmd_buffer,1,
1853                                            hdw->cmd_buffer,1);
1854                 if (result < 0) break;
1855         } while(0); LOCK_GIVE(hdw->ctl_lock);
1856         if (result) {
1857                 pvr2_trace(PVR2_TRACE_INIT,
1858                            "Probe of device endpoint 1 result status %d",
1859                            result);
1860         } else {
1861                 pvr2_trace(PVR2_TRACE_INIT,
1862                            "Probe of device endpoint 1 succeeded");
1863         }
1864         return result == 0;
1865 }
1866
1867 struct pvr2_std_hack {
1868         v4l2_std_id pat;  /* Pattern to match */
1869         v4l2_std_id msk;  /* Which bits we care about */
1870         v4l2_std_id std;  /* What additional standards or default to set */
1871 };
1872
1873 /* This data structure labels specific combinations of standards from
1874    tveeprom that we'll try to recognize.  If we recognize one, then assume
1875    a specified default standard to use.  This is here because tveeprom only
1876    tells us about available standards not the intended default standard (if
1877    any) for the device in question.  We guess the default based on what has
1878    been reported as available.  Note that this is only for guessing a
1879    default - which can always be overridden explicitly - and if the user
1880    has otherwise named a default then that default will always be used in
1881    place of this table. */
1882 static const struct pvr2_std_hack std_eeprom_maps[] = {
1883         {       /* PAL(B/G) */
1884                 .pat = V4L2_STD_B|V4L2_STD_GH,
1885                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1886         },
1887         {       /* NTSC(M) */
1888                 .pat = V4L2_STD_MN,
1889                 .std = V4L2_STD_NTSC_M,
1890         },
1891         {       /* PAL(I) */
1892                 .pat = V4L2_STD_PAL_I,
1893                 .std = V4L2_STD_PAL_I,
1894         },
1895         {       /* SECAM(L/L') */
1896                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1897                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1898         },
1899         {       /* PAL(D/D1/K) */
1900                 .pat = V4L2_STD_DK,
1901                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1902         },
1903 };
1904
1905 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1906 {
1907         char buf[40];
1908         unsigned int bcnt;
1909         v4l2_std_id std1,std2,std3;
1910
1911         std1 = get_default_standard(hdw);
1912         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1913
1914         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1915         pvr2_trace(PVR2_TRACE_STD,
1916                    "Supported video standard(s) reported available"
1917                    " in hardware: %.*s",
1918                    bcnt,buf);
1919
1920         hdw->std_mask_avail = hdw->std_mask_eeprom;
1921
1922         std2 = (std1|std3) & ~hdw->std_mask_avail;
1923         if (std2) {
1924                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1925                 pvr2_trace(PVR2_TRACE_STD,
1926                            "Expanding supported video standards"
1927                            " to include: %.*s",
1928                            bcnt,buf);
1929                 hdw->std_mask_avail |= std2;
1930         }
1931
1932         pvr2_hdw_internal_set_std_avail(hdw);
1933
1934         if (std1) {
1935                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1936                 pvr2_trace(PVR2_TRACE_STD,
1937                            "Initial video standard forced to %.*s",
1938                            bcnt,buf);
1939                 hdw->std_mask_cur = std1;
1940                 hdw->std_dirty = !0;
1941                 pvr2_hdw_internal_find_stdenum(hdw);
1942                 return;
1943         }
1944         if (std3) {
1945                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1946                 pvr2_trace(PVR2_TRACE_STD,
1947                            "Initial video standard"
1948                            " (determined by device type): %.*s",bcnt,buf);
1949                 hdw->std_mask_cur = std3;
1950                 hdw->std_dirty = !0;
1951                 pvr2_hdw_internal_find_stdenum(hdw);
1952                 return;
1953         }
1954
1955         {
1956                 unsigned int idx;
1957                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1958                         if (std_eeprom_maps[idx].msk ?
1959                             ((std_eeprom_maps[idx].pat ^
1960                              hdw->std_mask_eeprom) &
1961                              std_eeprom_maps[idx].msk) :
1962                             (std_eeprom_maps[idx].pat !=
1963                              hdw->std_mask_eeprom)) continue;
1964                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1965                                                   std_eeprom_maps[idx].std);
1966                         pvr2_trace(PVR2_TRACE_STD,
1967                                    "Initial video standard guessed as %.*s",
1968                                    bcnt,buf);
1969                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1970                         hdw->std_dirty = !0;
1971                         pvr2_hdw_internal_find_stdenum(hdw);
1972                         return;
1973                 }
1974         }
1975
1976         if (hdw->std_enum_cnt > 1) {
1977                 // Autoselect the first listed standard
1978                 hdw->std_enum_cur = 1;
1979                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1980                 hdw->std_dirty = !0;
1981                 pvr2_trace(PVR2_TRACE_STD,
1982                            "Initial video standard auto-selected to %s",
1983                            hdw->std_defs[hdw->std_enum_cur-1].name);
1984                 return;
1985         }
1986
1987         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1988                    "Unable to select a viable initial video standard");
1989 }
1990
1991
1992 static unsigned int pvr2_copy_i2c_addr_list(
1993         unsigned short *dst, const unsigned char *src,
1994         unsigned int dst_max)
1995 {
1996         unsigned int cnt = 0;
1997         if (!src) return 0;
1998         while (src[cnt] && (cnt + 1) < dst_max) {
1999                 dst[cnt] = src[cnt];
2000                 cnt++;
2001         }
2002         dst[cnt] = I2C_CLIENT_END;
2003         return cnt;
2004 }
2005
2006
2007 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2008 {
2009         /*
2010           Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2011           for cx25840 causes that module to correctly set up its video
2012           scaling.  This is really a problem in the cx25840 module itself,
2013           but we work around it here.  The problem has not been seen in
2014           ivtv because there VBI is supported and set up.  We don't do VBI
2015           here (at least not yet) and thus we never attempted to even set
2016           it up.
2017         */
2018         struct v4l2_format fmt;
2019         if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2020                 /* We're not using a cx25840 so don't enable the hack */
2021                 return;
2022         }
2023
2024         pvr2_trace(PVR2_TRACE_INIT,
2025                    "Module ID %u:"
2026                    " Executing cx25840 VBI hack",
2027                    hdw->decoder_client_id);
2028         memset(&fmt, 0, sizeof(fmt));
2029         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2030         v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
2031                              vbi, s_sliced_fmt, &fmt.fmt.sliced);
2032 }
2033
2034
2035 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2036                                 const struct pvr2_device_client_desc *cd)
2037 {
2038         const char *fname;
2039         unsigned char mid;
2040         struct v4l2_subdev *sd;
2041         unsigned int i2ccnt;
2042         const unsigned char *p;
2043         /* Arbitrary count - max # i2c addresses we will probe */
2044         unsigned short i2caddr[25];
2045
2046         mid = cd->module_id;
2047         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2048         if (!fname) {
2049                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2050                            "Module ID %u for device %s has no name?"
2051                            "  The driver might have a configuration problem.",
2052                            mid,
2053                            hdw->hdw_desc->description);
2054                 return -EINVAL;
2055         }
2056         pvr2_trace(PVR2_TRACE_INIT,
2057                    "Module ID %u (%s) for device %s being loaded...",
2058                    mid, fname,
2059                    hdw->hdw_desc->description);
2060
2061         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2062                                          ARRAY_SIZE(i2caddr));
2063         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2064                          module_i2c_addresses[mid] : NULL) != NULL)) {
2065                 /* Second chance: Try default i2c address list */
2066                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2067                                                  ARRAY_SIZE(i2caddr));
2068                 if (i2ccnt) {
2069                         pvr2_trace(PVR2_TRACE_INIT,
2070                                    "Module ID %u:"
2071                                    " Using default i2c address list",
2072                                    mid);
2073                 }
2074         }
2075
2076         if (!i2ccnt) {
2077                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2078                            "Module ID %u (%s) for device %s:"
2079                            " No i2c addresses."
2080                            "  The driver might have a configuration problem.",
2081                            mid, fname, hdw->hdw_desc->description);
2082                 return -EINVAL;
2083         }
2084
2085         /* Note how the 2nd and 3rd arguments are the same for
2086          * v4l2_i2c_new_subdev().  Why?
2087          * Well the 2nd argument is the module name to load, while the 3rd
2088          * argument is documented in the framework as being the "chipid" -
2089          * and every other place where I can find examples of this, the
2090          * "chipid" appears to just be the module name again.  So here we
2091          * just do the same thing. */
2092         if (i2ccnt == 1) {
2093                 pvr2_trace(PVR2_TRACE_INIT,
2094                            "Module ID %u:"
2095                            " Setting up with specified i2c address 0x%x",
2096                            mid, i2caddr[0]);
2097                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2098                                          fname, fname,
2099                                          i2caddr[0], NULL);
2100         } else {
2101                 pvr2_trace(PVR2_TRACE_INIT,
2102                            "Module ID %u:"
2103                            " Setting up with address probe list",
2104                            mid);
2105                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2106                                                 fname, fname,
2107                                                 0, i2caddr);
2108         }
2109
2110         if (!sd) {
2111                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2112                            "Module ID %u (%s) for device %s failed to load."
2113                            "  Possible missing sub-device kernel module or"
2114                            " initialization failure within module.",
2115                            mid, fname, hdw->hdw_desc->description);
2116                 return -EIO;
2117         }
2118
2119         /* Tag this sub-device instance with the module ID we know about.
2120            In other places we'll use that tag to determine if the instance
2121            requires special handling. */
2122         sd->grp_id = mid;
2123
2124         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2125
2126
2127         /* client-specific setup... */
2128         switch (mid) {
2129         case PVR2_CLIENT_ID_CX25840:
2130         case PVR2_CLIENT_ID_SAA7115:
2131                 hdw->decoder_client_id = mid;
2132                 break;
2133         default: break;
2134         }
2135
2136         return 0;
2137 }
2138
2139
2140 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2141 {
2142         unsigned int idx;
2143         const struct pvr2_string_table *cm;
2144         const struct pvr2_device_client_table *ct;
2145         int okFl = !0;
2146
2147         cm = &hdw->hdw_desc->client_modules;
2148         for (idx = 0; idx < cm->cnt; idx++) {
2149                 request_module(cm->lst[idx]);
2150         }
2151
2152         ct = &hdw->hdw_desc->client_table;
2153         for (idx = 0; idx < ct->cnt; idx++) {
2154                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2155         }
2156         if (!okFl) {
2157                 hdw->flag_modulefail = !0;
2158                 pvr2_hdw_render_useless(hdw);
2159         }
2160 }
2161
2162
2163 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2164 {
2165         int ret;
2166         unsigned int idx;
2167         struct pvr2_ctrl *cptr;
2168         int reloadFl = 0;
2169         if (hdw->hdw_desc->fx2_firmware.cnt) {
2170                 if (!reloadFl) {
2171                         reloadFl =
2172                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2173                                  == 0);
2174                         if (reloadFl) {
2175                                 pvr2_trace(PVR2_TRACE_INIT,
2176                                            "USB endpoint config looks strange"
2177                                            "; possibly firmware needs to be"
2178                                            " loaded");
2179                         }
2180                 }
2181                 if (!reloadFl) {
2182                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2183                         if (reloadFl) {
2184                                 pvr2_trace(PVR2_TRACE_INIT,
2185                                            "Check for FX2 firmware failed"
2186                                            "; possibly firmware needs to be"
2187                                            " loaded");
2188                         }
2189                 }
2190                 if (reloadFl) {
2191                         if (pvr2_upload_firmware1(hdw) != 0) {
2192                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2193                                            "Failure uploading firmware1");
2194                         }
2195                         return;
2196                 }
2197         }
2198         hdw->fw1_state = FW1_STATE_OK;
2199
2200         if (!pvr2_hdw_dev_ok(hdw)) return;
2201
2202         hdw->force_dirty = !0;
2203
2204         if (!hdw->hdw_desc->flag_no_powerup) {
2205                 pvr2_hdw_cmd_powerup(hdw);
2206                 if (!pvr2_hdw_dev_ok(hdw)) return;
2207         }
2208
2209         /* Take the IR chip out of reset, if appropriate */
2210         if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2211                 pvr2_issue_simple_cmd(hdw,
2212                                       FX2CMD_HCW_ZILOG_RESET |
2213                                       (1 << 8) |
2214                                       ((0) << 16));
2215         }
2216
2217         // This step MUST happen after the earlier powerup step.
2218         pvr2_i2c_core_init(hdw);
2219         if (!pvr2_hdw_dev_ok(hdw)) return;
2220
2221         pvr2_hdw_load_modules(hdw);
2222         if (!pvr2_hdw_dev_ok(hdw)) return;
2223
2224         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2225
2226         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2227                 cptr = hdw->controls + idx;
2228                 if (cptr->info->skip_init) continue;
2229                 if (!cptr->info->set_value) continue;
2230                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2231         }
2232
2233         pvr2_hdw_cx25840_vbi_hack(hdw);
2234
2235         /* Set up special default values for the television and radio
2236            frequencies here.  It's not really important what these defaults
2237            are, but I set them to something usable in the Chicago area just
2238            to make driver testing a little easier. */
2239
2240         hdw->freqValTelevision = default_tv_freq;
2241         hdw->freqValRadio = default_radio_freq;
2242
2243         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2244         // thread-safe against the normal pvr2_send_request() mechanism.
2245         // (We should make it thread safe).
2246
2247         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2248                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2249                 if (!pvr2_hdw_dev_ok(hdw)) return;
2250                 if (ret < 0) {
2251                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2252                                    "Unable to determine location of eeprom,"
2253                                    " skipping");
2254                 } else {
2255                         hdw->eeprom_addr = ret;
2256                         pvr2_eeprom_analyze(hdw);
2257                         if (!pvr2_hdw_dev_ok(hdw)) return;
2258                 }
2259         } else {
2260                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2261                 hdw->tuner_updated = !0;
2262                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2263         }
2264
2265         if (hdw->serial_number) {
2266                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2267                                 "sn-%lu", hdw->serial_number);
2268         } else if (hdw->unit_number >= 0) {
2269                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2270                                 "unit-%c",
2271                                 hdw->unit_number + 'a');
2272         } else {
2273                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2274                                 "unit-??");
2275         }
2276         hdw->identifier[idx] = 0;
2277
2278         pvr2_hdw_setup_std(hdw);
2279
2280         if (!get_default_tuner_type(hdw)) {
2281                 pvr2_trace(PVR2_TRACE_INIT,
2282                            "pvr2_hdw_setup: Tuner type overridden to %d",
2283                            hdw->tuner_type);
2284         }
2285
2286
2287         if (!pvr2_hdw_dev_ok(hdw)) return;
2288
2289         if (hdw->hdw_desc->signal_routing_scheme ==
2290             PVR2_ROUTING_SCHEME_GOTVIEW) {
2291                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2292                    hardware. */
2293                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2294         }
2295
2296         pvr2_hdw_commit_setup(hdw);
2297
2298         hdw->vid_stream = pvr2_stream_create();
2299         if (!pvr2_hdw_dev_ok(hdw)) return;
2300         pvr2_trace(PVR2_TRACE_INIT,
2301                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2302         if (hdw->vid_stream) {
2303                 idx = get_default_error_tolerance(hdw);
2304                 if (idx) {
2305                         pvr2_trace(PVR2_TRACE_INIT,
2306                                    "pvr2_hdw_setup: video stream %p"
2307                                    " setting tolerance %u",
2308                                    hdw->vid_stream,idx);
2309                 }
2310                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2311                                   PVR2_VID_ENDPOINT,idx);
2312         }
2313
2314         if (!pvr2_hdw_dev_ok(hdw)) return;
2315
2316         hdw->flag_init_ok = !0;
2317
2318         pvr2_hdw_state_sched(hdw);
2319 }
2320
2321
2322 /* Set up the structure and attempt to put the device into a usable state.
2323    This can be a time-consuming operation, which is why it is not done
2324    internally as part of the create() step. */
2325 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2326 {
2327         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2328         do {
2329                 pvr2_hdw_setup_low(hdw);
2330                 pvr2_trace(PVR2_TRACE_INIT,
2331                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2332                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2333                 if (pvr2_hdw_dev_ok(hdw)) {
2334                         if (hdw->flag_init_ok) {
2335                                 pvr2_trace(
2336                                         PVR2_TRACE_INFO,
2337                                         "Device initialization"
2338                                         " completed successfully.");
2339                                 break;
2340                         }
2341                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2342                                 pvr2_trace(
2343                                         PVR2_TRACE_INFO,
2344                                         "Device microcontroller firmware"
2345                                         " (re)loaded; it should now reset"
2346                                         " and reconnect.");
2347                                 break;
2348                         }
2349                         pvr2_trace(
2350                                 PVR2_TRACE_ERROR_LEGS,
2351                                 "Device initialization was not successful.");
2352                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2353                                 pvr2_trace(
2354                                         PVR2_TRACE_ERROR_LEGS,
2355                                         "Giving up since device"
2356                                         " microcontroller firmware"
2357                                         " appears to be missing.");
2358                                 break;
2359                         }
2360                 }
2361                 if (hdw->flag_modulefail) {
2362                         pvr2_trace(
2363                                 PVR2_TRACE_ERROR_LEGS,
2364                                 "***WARNING*** pvrusb2 driver initialization"
2365                                 " failed due to the failure of one or more"
2366                                 " sub-device kernel modules.");
2367                         pvr2_trace(
2368                                 PVR2_TRACE_ERROR_LEGS,
2369                                 "You need to resolve the failing condition"
2370                                 " before this driver can function.  There"
2371                                 " should be some earlier messages giving more"
2372                                 " information about the problem.");
2373                         break;
2374                 }
2375                 if (procreload) {
2376                         pvr2_trace(
2377                                 PVR2_TRACE_ERROR_LEGS,
2378                                 "Attempting pvrusb2 recovery by reloading"
2379                                 " primary firmware.");
2380                         pvr2_trace(
2381                                 PVR2_TRACE_ERROR_LEGS,
2382                                 "If this works, device should disconnect"
2383                                 " and reconnect in a sane state.");
2384                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2385                         pvr2_upload_firmware1(hdw);
2386                 } else {
2387                         pvr2_trace(
2388                                 PVR2_TRACE_ERROR_LEGS,
2389                                 "***WARNING*** pvrusb2 device hardware"
2390                                 " appears to be jammed"
2391                                 " and I can't clear it.");
2392                         pvr2_trace(
2393                                 PVR2_TRACE_ERROR_LEGS,
2394                                 "You might need to power cycle"
2395                                 " the pvrusb2 device"
2396                                 " in order to recover.");
2397                 }
2398         } while (0);
2399         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2400 }
2401
2402
2403 /* Perform second stage initialization.  Set callback pointer first so that
2404    we can avoid a possible initialization race (if the kernel thread runs
2405    before the callback has been set). */
2406 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2407                         void (*callback_func)(void *),
2408                         void *callback_data)
2409 {
2410         LOCK_TAKE(hdw->big_lock); do {
2411                 if (hdw->flag_disconnected) {
2412                         /* Handle a race here: If we're already
2413                            disconnected by this point, then give up.  If we
2414                            get past this then we'll remain connected for
2415                            the duration of initialization since the entire
2416                            initialization sequence is now protected by the
2417                            big_lock. */
2418                         break;
2419                 }
2420                 hdw->state_data = callback_data;
2421                 hdw->state_func = callback_func;
2422                 pvr2_hdw_setup(hdw);
2423         } while (0); LOCK_GIVE(hdw->big_lock);
2424         return hdw->flag_init_ok;
2425 }
2426
2427
2428 /* Create, set up, and return a structure for interacting with the
2429    underlying hardware.  */
2430 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2431                                  const struct usb_device_id *devid)
2432 {
2433         unsigned int idx,cnt1,cnt2,m;
2434         struct pvr2_hdw *hdw = NULL;
2435         int valid_std_mask;
2436         struct pvr2_ctrl *cptr;
2437         struct usb_device *usb_dev;
2438         const struct pvr2_device_desc *hdw_desc;
2439         __u8 ifnum;
2440         struct v4l2_queryctrl qctrl;
2441         struct pvr2_ctl_info *ciptr;
2442
2443         usb_dev = interface_to_usbdev(intf);
2444
2445         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2446
2447         if (hdw_desc == NULL) {
2448                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2449                            " No device description pointer,"
2450                            " unable to continue.");
2451                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2452                            " please contact Mike Isely <isely@pobox.com>"
2453                            " to get it included in the driver\n");
2454                 goto fail;
2455         }
2456
2457         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2458         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2459                    hdw,hdw_desc->description);
2460         pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2461                 hdw_desc->description);
2462         if (!hdw) goto fail;
2463
2464         init_timer(&hdw->quiescent_timer);
2465         hdw->quiescent_timer.data = (unsigned long)hdw;
2466         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2467
2468         init_timer(&hdw->decoder_stabilization_timer);
2469         hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2470         hdw->decoder_stabilization_timer.function =
2471                 pvr2_hdw_decoder_stabilization_timeout;
2472
2473         init_timer(&hdw->encoder_wait_timer);
2474         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2475         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2476
2477         init_timer(&hdw->encoder_run_timer);
2478         hdw->encoder_run_timer.data = (unsigned long)hdw;
2479         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2480
2481         hdw->master_state = PVR2_STATE_DEAD;
2482
2483         init_waitqueue_head(&hdw->state_wait_data);
2484
2485         hdw->tuner_signal_stale = !0;
2486         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2487
2488         /* Calculate which inputs are OK */
2489         m = 0;
2490         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2491         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2492                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2493         }
2494         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2495         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2496         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2497         hdw->input_avail_mask = m;
2498         hdw->input_allowed_mask = hdw->input_avail_mask;
2499
2500         /* If not a hybrid device, pathway_state never changes.  So
2501            initialize it here to what it should forever be. */
2502         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2503                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2504         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2505                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2506         }
2507
2508         hdw->control_cnt = CTRLDEF_COUNT;
2509         hdw->control_cnt += MPEGDEF_COUNT;
2510         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2511                                 GFP_KERNEL);
2512         if (!hdw->controls) goto fail;
2513         hdw->hdw_desc = hdw_desc;
2514         hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2515         for (idx = 0; idx < hdw->control_cnt; idx++) {
2516                 cptr = hdw->controls + idx;
2517                 cptr->hdw = hdw;
2518         }
2519         for (idx = 0; idx < 32; idx++) {
2520                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2521         }
2522         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2523                 cptr = hdw->controls + idx;
2524                 cptr->info = control_defs+idx;
2525         }
2526
2527         /* Ensure that default input choice is a valid one. */
2528         m = hdw->input_avail_mask;
2529         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2530                 if (!((1 << idx) & m)) continue;
2531                 hdw->input_val = idx;
2532                 break;
2533         }
2534
2535         /* Define and configure additional controls from cx2341x module. */
2536         hdw->mpeg_ctrl_info = kzalloc(
2537                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2538         if (!hdw->mpeg_ctrl_info) goto fail;
2539         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2540                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2541                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2542                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2543                 ciptr->name = mpeg_ids[idx].strid;
2544                 ciptr->v4l_id = mpeg_ids[idx].id;
2545                 ciptr->skip_init = !0;
2546                 ciptr->get_value = ctrl_cx2341x_get;
2547                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2548                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2549                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2550                 qctrl.id = ciptr->v4l_id;
2551                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2552                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2553                         ciptr->set_value = ctrl_cx2341x_set;
2554                 }
2555                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2556                         PVR2_CTLD_INFO_DESC_SIZE);
2557                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2558                 ciptr->default_value = qctrl.default_value;
2559                 switch (qctrl.type) {
2560                 default:
2561                 case V4L2_CTRL_TYPE_INTEGER:
2562                         ciptr->type = pvr2_ctl_int;
2563                         ciptr->def.type_int.min_value = qctrl.minimum;
2564                         ciptr->def.type_int.max_value = qctrl.maximum;
2565                         break;
2566                 case V4L2_CTRL_TYPE_BOOLEAN:
2567                         ciptr->type = pvr2_ctl_bool;
2568                         break;
2569                 case V4L2_CTRL_TYPE_MENU:
2570                         ciptr->type = pvr2_ctl_enum;
2571                         ciptr->def.type_enum.value_names =
2572                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2573                                                                 ciptr->v4l_id);
2574                         for (cnt1 = 0;
2575                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2576                              cnt1++) { }
2577                         ciptr->def.type_enum.count = cnt1;
2578                         break;
2579                 }
2580                 cptr->info = ciptr;
2581         }
2582
2583         // Initialize video standard enum dynamic control
2584         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2585         if (cptr) {
2586                 memcpy(&hdw->std_info_enum,cptr->info,
2587                        sizeof(hdw->std_info_enum));
2588                 cptr->info = &hdw->std_info_enum;
2589
2590         }
2591         // Initialize control data regarding video standard masks
2592         valid_std_mask = pvr2_std_get_usable();
2593         for (idx = 0; idx < 32; idx++) {
2594                 if (!(valid_std_mask & (1 << idx))) continue;
2595                 cnt1 = pvr2_std_id_to_str(
2596                         hdw->std_mask_names[idx],
2597                         sizeof(hdw->std_mask_names[idx])-1,
2598                         1 << idx);
2599                 hdw->std_mask_names[idx][cnt1] = 0;
2600         }
2601         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2602         if (cptr) {
2603                 memcpy(&hdw->std_info_avail,cptr->info,
2604                        sizeof(hdw->std_info_avail));
2605                 cptr->info = &hdw->std_info_avail;
2606                 hdw->std_info_avail.def.type_bitmask.bit_names =
2607                         hdw->std_mask_ptrs;
2608                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2609                         valid_std_mask;
2610         }
2611         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2612         if (cptr) {
2613                 memcpy(&hdw->std_info_cur,cptr->info,
2614                        sizeof(hdw->std_info_cur));
2615                 cptr->info = &hdw->std_info_cur;
2616                 hdw->std_info_cur.def.type_bitmask.bit_names =
2617                         hdw->std_mask_ptrs;
2618                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2619                         valid_std_mask;
2620         }
2621
2622         hdw->cropcap_stale = !0;
2623         hdw->eeprom_addr = -1;
2624         hdw->unit_number = -1;
2625         hdw->v4l_minor_number_video = -1;
2626         hdw->v4l_minor_number_vbi = -1;
2627         hdw->v4l_minor_number_radio = -1;
2628         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2629         if (!hdw->ctl_write_buffer) goto fail;
2630         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2631         if (!hdw->ctl_read_buffer) goto fail;
2632         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2633         if (!hdw->ctl_write_urb) goto fail;
2634         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2635         if (!hdw->ctl_read_urb) goto fail;
2636
2637         if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2638                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2639                            "Error registering with v4l core, giving up");
2640                 goto fail;
2641         }
2642         mutex_lock(&pvr2_unit_mtx); do {
2643                 for (idx = 0; idx < PVR_NUM; idx++) {
2644                         if (unit_pointers[idx]) continue;
2645                         hdw->unit_number = idx;
2646                         unit_pointers[idx] = hdw;
2647                         break;
2648                 }
2649         } while (0); mutex_unlock(&pvr2_unit_mtx);
2650
2651         cnt1 = 0;
2652         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2653         cnt1 += cnt2;
2654         if (hdw->unit_number >= 0) {
2655                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2656                                  ('a' + hdw->unit_number));
2657                 cnt1 += cnt2;
2658         }
2659         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2660         hdw->name[cnt1] = 0;
2661
2662         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2663         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2664
2665         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2666                    hdw->unit_number,hdw->name);
2667
2668         hdw->tuner_type = -1;
2669         hdw->flag_ok = !0;
2670
2671         hdw->usb_intf = intf;
2672         hdw->usb_dev = usb_dev;
2673
2674         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2675
2676         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2677         usb_set_interface(hdw->usb_dev,ifnum,0);
2678
2679         mutex_init(&hdw->ctl_lock_mutex);
2680         mutex_init(&hdw->big_lock_mutex);
2681
2682         return hdw;
2683  fail:
2684         if (hdw) {
2685                 del_timer_sync(&hdw->quiescent_timer);
2686                 del_timer_sync(&hdw->decoder_stabilization_timer);
2687                 del_timer_sync(&hdw->encoder_run_timer);
2688                 del_timer_sync(&hdw->encoder_wait_timer);
2689                 if (hdw->workqueue) {
2690                         flush_workqueue(hdw->workqueue);
2691                         destroy_workqueue(hdw->workqueue);
2692                         hdw->workqueue = NULL;
2693                 }
2694                 usb_free_urb(hdw->ctl_read_urb);
2695                 usb_free_urb(hdw->ctl_write_urb);
2696                 kfree(hdw->ctl_read_buffer);
2697                 kfree(hdw->ctl_write_buffer);
2698                 kfree(hdw->controls);
2699                 kfree(hdw->mpeg_ctrl_info);
2700                 kfree(hdw->std_defs);
2701                 kfree(hdw->std_enum_names);
2702                 kfree(hdw);
2703         }
2704         return NULL;
2705 }
2706
2707
2708 /* Remove _all_ associations between this driver and the underlying USB
2709    layer. */
2710 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2711 {
2712         if (hdw->flag_disconnected) return;
2713         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2714         if (hdw->ctl_read_urb) {
2715                 usb_kill_urb(hdw->ctl_read_urb);
2716                 usb_free_urb(hdw->ctl_read_urb);
2717                 hdw->ctl_read_urb = NULL;
2718         }
2719         if (hdw->ctl_write_urb) {
2720                 usb_kill_urb(hdw->ctl_write_urb);
2721                 usb_free_urb(hdw->ctl_write_urb);
2722                 hdw->ctl_write_urb = NULL;
2723         }
2724         if (hdw->ctl_read_buffer) {
2725                 kfree(hdw->ctl_read_buffer);
2726                 hdw->ctl_read_buffer = NULL;
2727         }
2728         if (hdw->ctl_write_buffer) {
2729                 kfree(hdw->ctl_write_buffer);
2730                 hdw->ctl_write_buffer = NULL;
2731         }
2732         hdw->flag_disconnected = !0;
2733         /* If we don't do this, then there will be a dangling struct device
2734            reference to our disappearing device persisting inside the V4L
2735            core... */
2736         v4l2_device_disconnect(&hdw->v4l2_dev);
2737         hdw->usb_dev = NULL;
2738         hdw->usb_intf = NULL;
2739         pvr2_hdw_render_useless(hdw);
2740 }
2741
2742
2743 /* Destroy hardware interaction structure */
2744 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2745 {
2746         if (!hdw) return;
2747         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2748         if (hdw->workqueue) {
2749                 flush_workqueue(hdw->workqueue);
2750                 destroy_workqueue(hdw->workqueue);
2751                 hdw->workqueue = NULL;
2752         }
2753         del_timer_sync(&hdw->quiescent_timer);
2754         del_timer_sync(&hdw->decoder_stabilization_timer);
2755         del_timer_sync(&hdw->encoder_run_timer);
2756         del_timer_sync(&hdw->encoder_wait_timer);
2757         if (hdw->fw_buffer) {
2758                 kfree(hdw->fw_buffer);
2759                 hdw->fw_buffer = NULL;
2760         }
2761         if (hdw->vid_stream) {
2762                 pvr2_stream_destroy(hdw->vid_stream);
2763                 hdw->vid_stream = NULL;
2764         }
2765         pvr2_i2c_core_done(hdw);
2766         v4l2_device_unregister(&hdw->v4l2_dev);
2767         pvr2_hdw_remove_usb_stuff(hdw);
2768         mutex_lock(&pvr2_unit_mtx); do {
2769                 if ((hdw->unit_number >= 0) &&
2770                     (hdw->unit_number < PVR_NUM) &&
2771                     (unit_pointers[hdw->unit_number] == hdw)) {
2772                         unit_pointers[hdw->unit_number] = NULL;
2773                 }
2774         } while (0); mutex_unlock(&pvr2_unit_mtx);
2775         kfree(hdw->controls);
2776         kfree(hdw->mpeg_ctrl_info);
2777         kfree(hdw->std_defs);
2778         kfree(hdw->std_enum_names);
2779         kfree(hdw);
2780 }
2781
2782
2783 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2784 {
2785         return (hdw && hdw->flag_ok);
2786 }
2787
2788
2789 /* Called when hardware has been unplugged */
2790 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2791 {
2792         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2793         LOCK_TAKE(hdw->big_lock);
2794         LOCK_TAKE(hdw->ctl_lock);
2795         pvr2_hdw_remove_usb_stuff(hdw);
2796         LOCK_GIVE(hdw->ctl_lock);
2797         LOCK_GIVE(hdw->big_lock);
2798 }
2799
2800
2801 // Attempt to autoselect an appropriate value for std_enum_cur given
2802 // whatever is currently in std_mask_cur
2803 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2804 {
2805         unsigned int idx;
2806         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2807                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2808                         hdw->std_enum_cur = idx;
2809                         return;
2810                 }
2811         }
2812         hdw->std_enum_cur = 0;
2813 }
2814
2815
2816 // Calculate correct set of enumerated standards based on currently known
2817 // set of available standards bits.
2818 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2819 {
2820         struct v4l2_standard *newstd;
2821         unsigned int std_cnt;
2822         unsigned int idx;
2823
2824         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2825
2826         if (hdw->std_defs) {
2827                 kfree(hdw->std_defs);
2828                 hdw->std_defs = NULL;
2829         }
2830         hdw->std_enum_cnt = 0;
2831         if (hdw->std_enum_names) {
2832                 kfree(hdw->std_enum_names);
2833                 hdw->std_enum_names = NULL;
2834         }
2835
2836         if (!std_cnt) {
2837                 pvr2_trace(
2838                         PVR2_TRACE_ERROR_LEGS,
2839                         "WARNING: Failed to identify any viable standards");
2840         }
2841         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2842         hdw->std_enum_names[0] = "none";
2843         for (idx = 0; idx < std_cnt; idx++) {
2844                 hdw->std_enum_names[idx+1] =
2845                         newstd[idx].name;
2846         }
2847         // Set up the dynamic control for this standard
2848         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2849         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2850         hdw->std_defs = newstd;
2851         hdw->std_enum_cnt = std_cnt+1;
2852         hdw->std_enum_cur = 0;
2853         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2854 }
2855
2856
2857 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2858                                struct v4l2_standard *std,
2859                                unsigned int idx)
2860 {
2861         int ret = -EINVAL;
2862         if (!idx) return ret;
2863         LOCK_TAKE(hdw->big_lock); do {
2864                 if (idx >= hdw->std_enum_cnt) break;
2865                 idx--;
2866                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2867                 ret = 0;
2868         } while (0); LOCK_GIVE(hdw->big_lock);
2869         return ret;
2870 }
2871
2872
2873 /* Get the number of defined controls */
2874 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2875 {
2876         return hdw->control_cnt;
2877 }
2878
2879
2880 /* Retrieve a control handle given its index (0..count-1) */
2881 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2882                                              unsigned int idx)
2883 {
2884         if (idx >= hdw->control_cnt) return NULL;
2885         return hdw->controls + idx;
2886 }
2887
2888
2889 /* Retrieve a control handle given its index (0..count-1) */
2890 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2891                                           unsigned int ctl_id)
2892 {
2893         struct pvr2_ctrl *cptr;
2894         unsigned int idx;
2895         int i;
2896
2897         /* This could be made a lot more efficient, but for now... */
2898         for (idx = 0; idx < hdw->control_cnt; idx++) {
2899                 cptr = hdw->controls + idx;
2900                 i = cptr->info->internal_id;
2901                 if (i && (i == ctl_id)) return cptr;
2902         }
2903         return NULL;
2904 }
2905
2906
2907 /* Given a V4L ID, retrieve the control structure associated with it. */
2908 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2909 {
2910         struct pvr2_ctrl *cptr;
2911         unsigned int idx;
2912         int i;
2913
2914         /* This could be made a lot more efficient, but for now... */
2915         for (idx = 0; idx < hdw->control_cnt; idx++) {
2916                 cptr = hdw->controls + idx;
2917                 i = cptr->info->v4l_id;
2918                 if (i && (i == ctl_id)) return cptr;
2919         }
2920         return NULL;
2921 }
2922
2923
2924 /* Given a V4L ID for its immediate predecessor, retrieve the control
2925    structure associated with it. */
2926 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2927                                             unsigned int ctl_id)
2928 {
2929         struct pvr2_ctrl *cptr,*cp2;
2930         unsigned int idx;
2931         int i;
2932
2933         /* This could be made a lot more efficient, but for now... */
2934         cp2 = NULL;
2935         for (idx = 0; idx < hdw->control_cnt; idx++) {
2936                 cptr = hdw->controls + idx;
2937                 i = cptr->info->v4l_id;
2938                 if (!i) continue;
2939                 if (i <= ctl_id) continue;
2940                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2941                 cp2 = cptr;
2942         }
2943         return cp2;
2944         return NULL;
2945 }
2946
2947
2948 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2949 {
2950         switch (tp) {
2951         case pvr2_ctl_int: return "integer";
2952         case pvr2_ctl_enum: return "enum";
2953         case pvr2_ctl_bool: return "boolean";
2954         case pvr2_ctl_bitmask: return "bitmask";
2955         }
2956         return "";
2957 }
2958
2959
2960 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2961                                     const char *name, int val)
2962 {
2963         struct v4l2_control ctrl;
2964         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2965         memset(&ctrl, 0, sizeof(ctrl));
2966         ctrl.id = id;
2967         ctrl.value = val;
2968         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2969 }
2970
2971 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2972         if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2973                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2974         }
2975
2976 /* Execute whatever commands are required to update the state of all the
2977    sub-devices so that they match our current control values. */
2978 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2979 {
2980         struct v4l2_subdev *sd;
2981         unsigned int id;
2982         pvr2_subdev_update_func fp;
2983
2984         pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2985
2986         if (hdw->tuner_updated || hdw->force_dirty) {
2987                 struct tuner_setup setup;
2988                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2989                            hdw->tuner_type);
2990                 if (((int)(hdw->tuner_type)) >= 0) {
2991                         memset(&setup, 0, sizeof(setup));
2992                         setup.addr = ADDR_UNSET;
2993                         setup.type = hdw->tuner_type;
2994                         setup.mode_mask = T_RADIO | T_ANALOG_TV;
2995                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2996                                              tuner, s_type_addr, &setup);
2997                 }
2998         }
2999
3000         if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
3001                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
3002                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3003                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
3004                                              tuner, s_radio);
3005                 } else {
3006                         v4l2_std_id vs;
3007                         vs = hdw->std_mask_cur;
3008                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
3009                                              core, s_std, vs);
3010                         pvr2_hdw_cx25840_vbi_hack(hdw);
3011                 }
3012                 hdw->tuner_signal_stale = !0;
3013                 hdw->cropcap_stale = !0;
3014         }
3015
3016         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3017         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3018         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3019         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3020         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3021         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3022         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3023         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3024         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3025
3026         if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
3027                 struct v4l2_tuner vt;
3028                 memset(&vt, 0, sizeof(vt));
3029                 vt.audmode = hdw->audiomode_val;
3030                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3031         }
3032
3033         if (hdw->freqDirty || hdw->force_dirty) {
3034                 unsigned long fv;
3035                 struct v4l2_frequency freq;
3036                 fv = pvr2_hdw_get_cur_freq(hdw);
3037                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3038                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3039                 memset(&freq, 0, sizeof(freq));
3040                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3041                         /* ((fv * 1000) / 62500) */
3042                         freq.frequency = (fv * 2) / 125;
3043                 } else {
3044                         freq.frequency = fv / 62500;
3045                 }
3046                 /* tuner-core currently doesn't seem to care about this, but
3047                    let's set it anyway for completeness. */
3048                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3049                         freq.type = V4L2_TUNER_RADIO;
3050                 } else {
3051                         freq.type = V4L2_TUNER_ANALOG_TV;
3052                 }
3053                 freq.tuner = 0;
3054                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3055                                      s_frequency, &freq);
3056         }
3057
3058         if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
3059                 struct v4l2_format fmt;
3060                 memset(&fmt, 0, sizeof(fmt));
3061                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3062                 fmt.fmt.pix.width = hdw->res_hor_val;
3063                 fmt.fmt.pix.height = hdw->res_ver_val;
3064                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
3065                            fmt.fmt.pix.width, fmt.fmt.pix.height);
3066                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3067         }
3068
3069         if (hdw->srate_dirty || hdw->force_dirty) {
3070                 u32 val;
3071                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3072                            hdw->srate_val);
3073                 switch (hdw->srate_val) {
3074                 default:
3075                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3076                         val = 48000;
3077                         break;
3078                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3079                         val = 44100;
3080                         break;
3081                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3082                         val = 32000;
3083                         break;
3084                 }
3085                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3086                                      audio, s_clock_freq, val);
3087         }
3088
3089         /* Unable to set crop parameters; there is apparently no equivalent
3090            for VIDIOC_S_CROP */
3091
3092         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3093                 id = sd->grp_id;
3094                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3095                 fp = pvr2_module_update_functions[id];
3096                 if (!fp) continue;
3097                 (*fp)(hdw, sd);
3098         }
3099
3100         if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3101                 pvr2_hdw_status_poll(hdw);
3102         }
3103 }
3104
3105
3106 /* Figure out if we need to commit control changes.  If so, mark internal
3107    state flags to indicate this fact and return true.  Otherwise do nothing
3108    else and return false. */
3109 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3110 {
3111         unsigned int idx;
3112         struct pvr2_ctrl *cptr;
3113         int value;
3114         int commit_flag = hdw->force_dirty;
3115         char buf[100];
3116         unsigned int bcnt,ccnt;
3117
3118         for (idx = 0; idx < hdw->control_cnt; idx++) {
3119                 cptr = hdw->controls + idx;
3120                 if (!cptr->info->is_dirty) continue;
3121                 if (!cptr->info->is_dirty(cptr)) continue;
3122                 commit_flag = !0;
3123
3124                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3125                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3126                                  cptr->info->name);
3127                 value = 0;
3128                 cptr->info->get_value(cptr,&value);
3129                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3130                                                 buf+bcnt,
3131                                                 sizeof(buf)-bcnt,&ccnt);
3132                 bcnt += ccnt;
3133                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3134                                   get_ctrl_typename(cptr->info->type));
3135                 pvr2_trace(PVR2_TRACE_CTL,
3136                            "/*--TRACE_COMMIT--*/ %.*s",
3137                            bcnt,buf);
3138         }
3139
3140         if (!commit_flag) {
3141                 /* Nothing has changed */
3142                 return 0;
3143         }
3144
3145         hdw->state_pipeline_config = 0;
3146         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3147         pvr2_hdw_state_sched(hdw);
3148
3149         return !0;
3150 }
3151
3152
3153 /* Perform all operations needed to commit all control changes.  This must
3154    be performed in synchronization with the pipeline state and is thus
3155    expected to be called as part of the driver's worker thread.  Return
3156    true if commit successful, otherwise return false to indicate that
3157    commit isn't possible at this time. */
3158 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3159 {
3160         unsigned int idx;
3161         struct pvr2_ctrl *cptr;
3162         int disruptive_change;
3163
3164         /* Handle some required side effects when the video standard is
3165            changed.... */
3166         if (hdw->std_dirty) {
3167                 int nvres;
3168                 int gop_size;
3169                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3170                         nvres = 480;
3171                         gop_size = 15;
3172                 } else {
3173                         nvres = 576;
3174                         gop_size = 12;
3175                 }
3176                 /* Rewrite the vertical resolution to be appropriate to the
3177                    video standard that has been selected. */
3178                 if (nvres != hdw->res_ver_val) {
3179                         hdw->res_ver_val = nvres;
3180                         hdw->res_ver_dirty = !0;
3181                 }
3182                 /* Rewrite the GOP size to be appropriate to the video
3183                    standard that has been selected. */
3184                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3185                         struct v4l2_ext_controls cs;
3186                         struct v4l2_ext_control c1;
3187                         memset(&cs, 0, sizeof(cs));
3188                         memset(&c1, 0, sizeof(c1));
3189                         cs.controls = &c1;
3190                         cs.count = 1;
3191                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3192                         c1.value = gop_size;
3193                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3194                                           VIDIOC_S_EXT_CTRLS);
3195                 }
3196         }
3197
3198         if (hdw->input_dirty && hdw->state_pathway_ok &&
3199             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3200               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3201              hdw->pathway_state)) {
3202                 /* Change of mode being asked for... */
3203                 hdw->state_pathway_ok = 0;
3204                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3205         }
3206         if (!hdw->state_pathway_ok) {
3207                 /* Can't commit anything until pathway is ok. */
3208                 return 0;
3209         }
3210         /* The broadcast decoder can only scale down, so if
3211          * res_*_dirty && crop window < output format ==> enlarge crop.
3212          *
3213          * The mpeg encoder receives fields of res_hor_val dots and
3214          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3215          */
3216         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3217                 hdw->cropw_val = hdw->res_hor_val;
3218                 hdw->cropw_dirty = !0;
3219         } else if (hdw->cropw_dirty) {
3220                 hdw->res_hor_dirty = !0;           /* must rescale */
3221                 hdw->res_hor_val = min(720, hdw->cropw_val);
3222         }
3223         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3224                 hdw->croph_val = hdw->res_ver_val;
3225                 hdw->croph_dirty = !0;
3226         } else if (hdw->croph_dirty) {
3227                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3228                 hdw->res_ver_dirty = !0;
3229                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3230         }
3231
3232         /* If any of the below has changed, then we can't do the update
3233            while the pipeline is running.  Pipeline must be paused first
3234            and decoder -> encoder connection be made quiescent before we
3235            can proceed. */
3236         disruptive_change =
3237                 (hdw->std_dirty ||
3238                  hdw->enc_unsafe_stale ||
3239                  hdw->srate_dirty ||
3240                  hdw->res_ver_dirty ||
3241                  hdw->res_hor_dirty ||
3242                  hdw->cropw_dirty ||
3243                  hdw->croph_dirty ||
3244                  hdw->input_dirty ||
3245                  (hdw->active_stream_type != hdw->desired_stream_type));
3246         if (disruptive_change && !hdw->state_pipeline_idle) {
3247                 /* Pipeline is not idle; we can't proceed.  Arrange to
3248                    cause pipeline to stop so that we can try this again
3249                    later.... */
3250                 hdw->state_pipeline_pause = !0;
3251                 return 0;
3252         }
3253
3254         if (hdw->srate_dirty) {
3255                 /* Write new sample rate into control structure since
3256                  * the master copy is stale.  We must track srate
3257                  * separate from the mpeg control structure because
3258                  * other logic also uses this value. */
3259                 struct v4l2_ext_controls cs;
3260                 struct v4l2_ext_control c1;
3261                 memset(&cs,0,sizeof(cs));
3262                 memset(&c1,0,sizeof(c1));
3263                 cs.controls = &c1;
3264                 cs.count = 1;
3265                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3266                 c1.value = hdw->srate_val;
3267                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3268         }
3269
3270         if (hdw->active_stream_type != hdw->desired_stream_type) {
3271                 /* Handle any side effects of stream config here */
3272                 hdw->active_stream_type = hdw->desired_stream_type;
3273         }
3274
3275         if (hdw->hdw_desc->signal_routing_scheme ==
3276             PVR2_ROUTING_SCHEME_GOTVIEW) {
3277                 u32 b;
3278                 /* Handle GOTVIEW audio switching */
3279                 pvr2_hdw_gpio_get_out(hdw,&b);
3280                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3281                         /* Set GPIO 11 */
3282                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3283                 } else {
3284                         /* Clear GPIO 11 */
3285                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3286                 }
3287         }
3288
3289         /* Check and update state for all sub-devices. */
3290         pvr2_subdev_update(hdw);
3291
3292         hdw->tuner_updated = 0;
3293         hdw->force_dirty = 0;
3294         for (idx = 0; idx < hdw->control_cnt; idx++) {
3295                 cptr = hdw->controls + idx;
3296                 if (!cptr->info->clear_dirty) continue;
3297                 cptr->info->clear_dirty(cptr);
3298         }
3299
3300         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3301             hdw->state_encoder_run) {
3302                 /* If encoder isn't running or it can't be touched, then
3303                    this will get worked out later when we start the
3304                    encoder. */
3305                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3306         }
3307
3308         hdw->state_pipeline_config = !0;
3309         /* Hardware state may have changed in a way to cause the cropping
3310            capabilities to have changed.  So mark it stale, which will
3311            cause a later re-fetch. */
3312         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3313         return !0;
3314 }
3315
3316
3317 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3318 {
3319         int fl;
3320         LOCK_TAKE(hdw->big_lock);
3321         fl = pvr2_hdw_commit_setup(hdw);
3322         LOCK_GIVE(hdw->big_lock);
3323         if (!fl) return 0;
3324         return pvr2_hdw_wait(hdw,0);
3325 }
3326
3327
3328 static void pvr2_hdw_worker_poll(struct work_struct *work)
3329 {
3330         int fl = 0;
3331         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3332         LOCK_TAKE(hdw->big_lock); do {
3333                 fl = pvr2_hdw_state_eval(hdw);
3334         } while (0); LOCK_GIVE(hdw->big_lock);
3335         if (fl && hdw->state_func) {
3336                 hdw->state_func(hdw->state_data);
3337         }
3338 }
3339
3340
3341 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3342 {
3343         return wait_event_interruptible(
3344                 hdw->state_wait_data,
3345                 (hdw->state_stale == 0) &&
3346                 (!state || (hdw->master_state != state)));
3347 }
3348
3349
3350 /* Return name for this driver instance */
3351 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3352 {
3353         return hdw->name;
3354 }
3355
3356
3357 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3358 {
3359         return hdw->hdw_desc->description;
3360 }
3361
3362
3363 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3364 {
3365         return hdw->hdw_desc->shortname;
3366 }
3367
3368
3369 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3370 {
3371         int result;
3372         LOCK_TAKE(hdw->ctl_lock); do {
3373                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3374                 result = pvr2_send_request(hdw,
3375                                            hdw->cmd_buffer,1,
3376                                            hdw->cmd_buffer,1);
3377                 if (result < 0) break;
3378                 result = (hdw->cmd_buffer[0] != 0);
3379         } while(0); LOCK_GIVE(hdw->ctl_lock);
3380         return result;
3381 }
3382
3383
3384 /* Execute poll of tuner status */
3385 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3386 {
3387         LOCK_TAKE(hdw->big_lock); do {
3388                 pvr2_hdw_status_poll(hdw);
3389         } while (0); LOCK_GIVE(hdw->big_lock);
3390 }
3391
3392
3393 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3394 {
3395         if (!hdw->cropcap_stale) {
3396                 return 0;
3397         }
3398         pvr2_hdw_status_poll(hdw);
3399         if (hdw->cropcap_stale) {
3400                 return -EIO;
3401         }
3402         return 0;
3403 }
3404
3405
3406 /* Return information about cropping capabilities */
3407 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3408 {
3409         int stat = 0;
3410         LOCK_TAKE(hdw->big_lock);
3411         stat = pvr2_hdw_check_cropcap(hdw);
3412         if (!stat) {
3413                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3414         }
3415         LOCK_GIVE(hdw->big_lock);
3416         return stat;
3417 }
3418
3419
3420 /* Return information about the tuner */
3421 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3422 {
3423         LOCK_TAKE(hdw->big_lock); do {
3424                 if (hdw->tuner_signal_stale) {
3425                         pvr2_hdw_status_poll(hdw);
3426                 }
3427                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3428         } while (0); LOCK_GIVE(hdw->big_lock);
3429         return 0;
3430 }
3431
3432
3433 /* Get handle to video output stream */
3434 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3435 {
3436         return hp->vid_stream;
3437 }
3438
3439
3440 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3441 {
3442         int nr = pvr2_hdw_get_unit_number(hdw);
3443         LOCK_TAKE(hdw->big_lock); do {
3444                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3445                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3446                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3447                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3448                 pvr2_hdw_state_log_state(hdw);
3449                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3450         } while (0); LOCK_GIVE(hdw->big_lock);
3451 }
3452
3453
3454 /* Grab EEPROM contents, needed for direct method. */
3455 #define EEPROM_SIZE 8192
3456 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3457 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3458 {
3459         struct i2c_msg msg[2];
3460         u8 *eeprom;
3461         u8 iadd[2];
3462         u8 addr;
3463         u16 eepromSize;
3464         unsigned int offs;
3465         int ret;
3466         int mode16 = 0;
3467         unsigned pcnt,tcnt;
3468         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3469         if (!eeprom) {
3470                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3471                            "Failed to allocate memory"
3472                            " required to read eeprom");
3473                 return NULL;
3474         }
3475
3476         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3477                      hdw->eeprom_addr);
3478         addr = hdw->eeprom_addr;
3479         /* Seems that if the high bit is set, then the *real* eeprom
3480            address is shifted right now bit position (noticed this in
3481            newer PVR USB2 hardware) */
3482         if (addr & 0x80) addr >>= 1;
3483
3484         /* FX2 documentation states that a 16bit-addressed eeprom is
3485            expected if the I2C address is an odd number (yeah, this is
3486            strange but it's what they do) */
3487         mode16 = (addr & 1);
3488         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3489         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3490                      " using %d bit addressing",eepromSize,addr,
3491                      mode16 ? 16 : 8);
3492
3493         msg[0].addr = addr;
3494         msg[0].flags = 0;
3495         msg[0].len = mode16 ? 2 : 1;
3496         msg[0].buf = iadd;
3497         msg[1].addr = addr;
3498         msg[1].flags = I2C_M_RD;
3499
3500         /* We have to do the actual eeprom data fetch ourselves, because
3501            (1) we're only fetching part of the eeprom, and (2) if we were
3502            getting the whole thing our I2C driver can't grab it in one
3503            pass - which is what tveeprom is otherwise going to attempt */
3504         memset(eeprom,0,EEPROM_SIZE);
3505         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3506                 pcnt = 16;
3507                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3508                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3509                 if (mode16) {
3510                         iadd[0] = offs >> 8;
3511                         iadd[1] = offs;
3512                 } else {
3513                         iadd[0] = offs;
3514                 }
3515                 msg[1].len = pcnt;
3516                 msg[1].buf = eeprom+tcnt;
3517                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3518                                         msg,ARRAY_SIZE(msg))) != 2) {
3519                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3520                                    "eeprom fetch set offs err=%d",ret);
3521                         kfree(eeprom);
3522                         return NULL;
3523                 }
3524         }
3525         return eeprom;
3526 }
3527
3528
3529 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3530                                 int mode,
3531                                 int enable_flag)
3532 {
3533         int ret;
3534         u16 address;
3535         unsigned int pipe;
3536         LOCK_TAKE(hdw->big_lock); do {
3537                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3538
3539                 if (!enable_flag) {
3540                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3541                                    "Cleaning up after CPU firmware fetch");
3542                         kfree(hdw->fw_buffer);
3543                         hdw->fw_buffer = NULL;
3544                         hdw->fw_size = 0;
3545                         if (hdw->fw_cpu_flag) {
3546                                 /* Now release the CPU.  It will disconnect
3547                                    and reconnect later. */
3548                                 pvr2_hdw_cpureset_assert(hdw,0);
3549                         }
3550                         break;
3551                 }
3552
3553                 hdw->fw_cpu_flag = (mode != 2);
3554                 if (hdw->fw_cpu_flag) {
3555                         hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3556                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3557                                    "Preparing to suck out CPU firmware"
3558                                    " (size=%u)", hdw->fw_size);
3559                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3560                         if (!hdw->fw_buffer) {
3561                                 hdw->fw_size = 0;
3562                                 break;
3563                         }
3564
3565                         /* We have to hold the CPU during firmware upload. */
3566                         pvr2_hdw_cpureset_assert(hdw,1);
3567
3568                         /* download the firmware from address 0000-1fff in 2048
3569                            (=0x800) bytes chunk. */
3570
3571                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3572                                    "Grabbing CPU firmware");
3573                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3574                         for(address = 0; address < hdw->fw_size;
3575                             address += 0x800) {
3576                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3577                                                       0xa0,0xc0,
3578                                                       address,0,
3579                                                       hdw->fw_buffer+address,
3580                                                       0x800,HZ);
3581                                 if (ret < 0) break;
3582                         }
3583
3584                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3585                                    "Done grabbing CPU firmware");
3586                 } else {
3587                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3588                                    "Sucking down EEPROM contents");
3589                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3590                         if (!hdw->fw_buffer) {
3591                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3592                                            "EEPROM content suck failed.");
3593                                 break;
3594                         }
3595                         hdw->fw_size = EEPROM_SIZE;
3596                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3597                                    "Done sucking down EEPROM contents");
3598                 }
3599
3600         } while (0); LOCK_GIVE(hdw->big_lock);
3601 }
3602
3603
3604 /* Return true if we're in a mode for retrieval CPU firmware */
3605 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3606 {
3607         return hdw->fw_buffer != NULL;
3608 }
3609
3610
3611 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3612                        char *buf,unsigned int cnt)
3613 {
3614         int ret = -EINVAL;
3615         LOCK_TAKE(hdw->big_lock); do {
3616                 if (!buf) break;
3617                 if (!cnt) break;
3618
3619                 if (!hdw->fw_buffer) {
3620                         ret = -EIO;
3621                         break;
3622                 }
3623
3624                 if (offs >= hdw->fw_size) {
3625                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3626                                    "Read firmware data offs=%d EOF",
3627                                    offs);
3628                         ret = 0;
3629                         break;
3630                 }
3631
3632                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3633
3634                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3635
3636                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3637                            "Read firmware data offs=%d cnt=%d",
3638                            offs,cnt);
3639                 ret = cnt;
3640         } while (0); LOCK_GIVE(hdw->big_lock);
3641
3642         return ret;
3643 }
3644
3645
3646 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3647                                   enum pvr2_v4l_type index)
3648 {
3649         switch (index) {
3650         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3651         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3652         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3653         default: return -1;
3654         }
3655 }
3656
3657
3658 /* Store a v4l minor device number */
3659 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3660                                      enum pvr2_v4l_type index,int v)
3661 {
3662         switch (index) {
3663         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3664         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3665         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3666         default: break;
3667         }
3668 }
3669
3670
3671 static void pvr2_ctl_write_complete(struct urb *urb)
3672 {
3673         struct pvr2_hdw *hdw = urb->context;
3674         hdw->ctl_write_pend_flag = 0;
3675         if (hdw->ctl_read_pend_flag) return;
3676         complete(&hdw->ctl_done);
3677 }
3678
3679
3680 static void pvr2_ctl_read_complete(struct urb *urb)
3681 {
3682         struct pvr2_hdw *hdw = urb->context;
3683         hdw->ctl_read_pend_flag = 0;
3684         if (hdw->ctl_write_pend_flag) return;
3685         complete(&hdw->ctl_done);
3686 }
3687
3688
3689 static void pvr2_ctl_timeout(unsigned long data)
3690 {
3691         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3692         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3693                 hdw->ctl_timeout_flag = !0;
3694                 if (hdw->ctl_write_pend_flag)
3695                         usb_unlink_urb(hdw->ctl_write_urb);
3696                 if (hdw->ctl_read_pend_flag)
3697                         usb_unlink_urb(hdw->ctl_read_urb);
3698         }
3699 }
3700
3701
3702 /* Issue a command and get a response from the device.  This extended
3703    version includes a probe flag (which if set means that device errors
3704    should not be logged or treated as fatal) and a timeout in jiffies.
3705    This can be used to non-lethally probe the health of endpoint 1. */
3706 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3707                                 unsigned int timeout,int probe_fl,
3708                                 void *write_data,unsigned int write_len,
3709                                 void *read_data,unsigned int read_len)
3710 {
3711         unsigned int idx;
3712         int status = 0;
3713         struct timer_list timer;
3714         if (!hdw->ctl_lock_held) {
3715                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3716                            "Attempted to execute control transfer"
3717                            " without lock!!");
3718                 return -EDEADLK;
3719         }
3720         if (!hdw->flag_ok && !probe_fl) {
3721                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3722                            "Attempted to execute control transfer"
3723                            " when device not ok");
3724                 return -EIO;
3725         }
3726         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3727                 if (!probe_fl) {
3728                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3729                                    "Attempted to execute control transfer"
3730                                    " when USB is disconnected");
3731                 }
3732                 return -ENOTTY;
3733         }
3734
3735         /* Ensure that we have sane parameters */
3736         if (!write_data) write_len = 0;
3737         if (!read_data) read_len = 0;
3738         if (write_len > PVR2_CTL_BUFFSIZE) {
3739                 pvr2_trace(
3740                         PVR2_TRACE_ERROR_LEGS,
3741                         "Attempted to execute %d byte"
3742                         " control-write transfer (limit=%d)",
3743                         write_len,PVR2_CTL_BUFFSIZE);
3744                 return -EINVAL;
3745         }
3746         if (read_len > PVR2_CTL_BUFFSIZE) {
3747                 pvr2_trace(
3748                         PVR2_TRACE_ERROR_LEGS,
3749                         "Attempted to execute %d byte"
3750                         " control-read transfer (limit=%d)",
3751                         write_len,PVR2_CTL_BUFFSIZE);
3752                 return -EINVAL;
3753         }
3754         if ((!write_len) && (!read_len)) {
3755                 pvr2_trace(
3756                         PVR2_TRACE_ERROR_LEGS,
3757                         "Attempted to execute null control transfer?");
3758                 return -EINVAL;
3759         }
3760
3761
3762         hdw->cmd_debug_state = 1;
3763         if (write_len) {
3764                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3765         } else {
3766                 hdw->cmd_debug_code = 0;
3767         }
3768         hdw->cmd_debug_write_len = write_len;
3769         hdw->cmd_debug_read_len = read_len;
3770
3771         /* Initialize common stuff */
3772         init_completion(&hdw->ctl_done);
3773         hdw->ctl_timeout_flag = 0;
3774         hdw->ctl_write_pend_flag = 0;
3775         hdw->ctl_read_pend_flag = 0;
3776         init_timer(&timer);
3777         timer.expires = jiffies + timeout;
3778         timer.data = (unsigned long)hdw;
3779         timer.function = pvr2_ctl_timeout;
3780
3781         if (write_len) {
3782                 hdw->cmd_debug_state = 2;
3783                 /* Transfer write data to internal buffer */
3784                 for (idx = 0; idx < write_len; idx++) {
3785                         hdw->ctl_write_buffer[idx] =
3786                                 ((unsigned char *)write_data)[idx];
3787                 }
3788                 /* Initiate a write request */
3789                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3790                                   hdw->usb_dev,
3791                                   usb_sndbulkpipe(hdw->usb_dev,
3792                                                   PVR2_CTL_WRITE_ENDPOINT),
3793                                   hdw->ctl_write_buffer,
3794                                   write_len,
3795                                   pvr2_ctl_write_complete,
3796                                   hdw);
3797                 hdw->ctl_write_urb->actual_length = 0;
3798                 hdw->ctl_write_pend_flag = !0;
3799                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3800                 if (status < 0) {
3801                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3802                                    "Failed to submit write-control"
3803                                    " URB status=%d",status);
3804                         hdw->ctl_write_pend_flag = 0;
3805                         goto done;
3806                 }
3807         }
3808
3809         if (read_len) {
3810                 hdw->cmd_debug_state = 3;
3811                 memset(hdw->ctl_read_buffer,0x43,read_len);
3812                 /* Initiate a read request */
3813                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3814                                   hdw->usb_dev,
3815                                   usb_rcvbulkpipe(hdw->usb_dev,
3816                                                   PVR2_CTL_READ_ENDPOINT),
3817                                   hdw->ctl_read_buffer,
3818                                   read_len,
3819                                   pvr2_ctl_read_complete,
3820                                   hdw);
3821                 hdw->ctl_read_urb->actual_length = 0;
3822                 hdw->ctl_read_pend_flag = !0;
3823                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3824                 if (status < 0) {
3825                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3826                                    "Failed to submit read-control"
3827                                    " URB status=%d",status);
3828                         hdw->ctl_read_pend_flag = 0;
3829                         goto done;
3830                 }
3831         }
3832
3833         /* Start timer */
3834         add_timer(&timer);
3835
3836         /* Now wait for all I/O to complete */
3837         hdw->cmd_debug_state = 4;
3838         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3839                 wait_for_completion(&hdw->ctl_done);
3840         }
3841         hdw->cmd_debug_state = 5;
3842
3843         /* Stop timer */
3844         del_timer_sync(&timer);
3845
3846         hdw->cmd_debug_state = 6;
3847         status = 0;
3848
3849         if (hdw->ctl_timeout_flag) {
3850                 status = -ETIMEDOUT;
3851                 if (!probe_fl) {
3852                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3853                                    "Timed out control-write");
3854                 }
3855                 goto done;
3856         }
3857
3858         if (write_len) {
3859                 /* Validate results of write request */
3860                 if ((hdw->ctl_write_urb->status != 0) &&
3861                     (hdw->ctl_write_urb->status != -ENOENT) &&
3862                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3863                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3864                         /* USB subsystem is reporting some kind of failure
3865                            on the write */
3866                         status = hdw->ctl_write_urb->status;
3867                         if (!probe_fl) {
3868                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3869                                            "control-write URB failure,"
3870                                            " status=%d",
3871                                            status);
3872                         }
3873                         goto done;
3874                 }
3875                 if (hdw->ctl_write_urb->actual_length < write_len) {
3876                         /* Failed to write enough data */
3877                         status = -EIO;
3878                         if (!probe_fl) {
3879                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3880                                            "control-write URB short,"
3881                                            " expected=%d got=%d",
3882                                            write_len,
3883                                            hdw->ctl_write_urb->actual_length);
3884                         }
3885                         goto done;
3886                 }
3887         }
3888         if (read_len) {
3889                 /* Validate results of read request */
3890                 if ((hdw->ctl_read_urb->status != 0) &&
3891                     (hdw->ctl_read_urb->status != -ENOENT) &&
3892                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3893                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3894                         /* USB subsystem is reporting some kind of failure
3895                            on the read */
3896                         status = hdw->ctl_read_urb->status;
3897                         if (!probe_fl) {
3898                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3899                                            "control-read URB failure,"
3900                                            " status=%d",
3901                                            status);
3902                         }
3903                         goto done;
3904                 }
3905                 if (hdw->ctl_read_urb->actual_length < read_len) {
3906                         /* Failed to read enough data */
3907                         status = -EIO;
3908                         if (!probe_fl) {
3909                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3910                                            "control-read URB short,"
3911                                            " expected=%d got=%d",
3912                                            read_len,
3913                                            hdw->ctl_read_urb->actual_length);
3914                         }
3915                         goto done;
3916                 }
3917                 /* Transfer retrieved data out from internal buffer */
3918                 for (idx = 0; idx < read_len; idx++) {
3919                         ((unsigned char *)read_data)[idx] =
3920                                 hdw->ctl_read_buffer[idx];
3921                 }
3922         }
3923
3924  done:
3925
3926         hdw->cmd_debug_state = 0;
3927         if ((status < 0) && (!probe_fl)) {
3928                 pvr2_hdw_render_useless(hdw);
3929         }
3930         return status;
3931 }
3932
3933
3934 int pvr2_send_request(struct pvr2_hdw *hdw,
3935                       void *write_data,unsigned int write_len,
3936                       void *read_data,unsigned int read_len)
3937 {
3938         return pvr2_send_request_ex(hdw,HZ*4,0,
3939                                     write_data,write_len,
3940                                     read_data,read_len);
3941 }
3942
3943
3944 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3945 {
3946         int ret;
3947         unsigned int cnt = 1;
3948         unsigned int args = 0;
3949         LOCK_TAKE(hdw->ctl_lock);
3950         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3951         args = (cmdcode >> 8) & 0xffu;
3952         args = (args > 2) ? 2 : args;
3953         if (args) {
3954                 cnt += args;
3955                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3956                 if (args > 1) {
3957                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3958                 }
3959         }
3960         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3961                 unsigned int idx;
3962                 unsigned int ccnt,bcnt;
3963                 char tbuf[50];
3964                 cmdcode &= 0xffu;
3965                 bcnt = 0;
3966                 ccnt = scnprintf(tbuf+bcnt,
3967                                  sizeof(tbuf)-bcnt,
3968                                  "Sending FX2 command 0x%x",cmdcode);
3969                 bcnt += ccnt;
3970                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3971                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3972                                 ccnt = scnprintf(tbuf+bcnt,
3973                                                  sizeof(tbuf)-bcnt,
3974                                                  " \"%s\"",
3975                                                  pvr2_fx2cmd_desc[idx].desc);
3976                                 bcnt += ccnt;
3977                                 break;
3978                         }
3979                 }
3980                 if (args) {
3981                         ccnt = scnprintf(tbuf+bcnt,
3982                                          sizeof(tbuf)-bcnt,
3983                                          " (%u",hdw->cmd_buffer[1]);
3984                         bcnt += ccnt;
3985                         if (args > 1) {
3986                                 ccnt = scnprintf(tbuf+bcnt,
3987                                                  sizeof(tbuf)-bcnt,
3988                                                  ",%u",hdw->cmd_buffer[2]);
3989                                 bcnt += ccnt;
3990                         }
3991                         ccnt = scnprintf(tbuf+bcnt,
3992                                          sizeof(tbuf)-bcnt,
3993                                          ")");
3994                         bcnt += ccnt;
3995                 }
3996                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3997         }
3998         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3999         LOCK_GIVE(hdw->ctl_lock);
4000         return ret;
4001 }
4002
4003
4004 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
4005 {
4006         int ret;
4007
4008         LOCK_TAKE(hdw->ctl_lock);
4009
4010         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
4011         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4012         hdw->cmd_buffer[5] = 0;
4013         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4014         hdw->cmd_buffer[7] = reg & 0xff;
4015
4016
4017         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4018
4019         LOCK_GIVE(hdw->ctl_lock);
4020
4021         return ret;
4022 }
4023
4024
4025 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
4026 {
4027         int ret = 0;
4028
4029         LOCK_TAKE(hdw->ctl_lock);
4030
4031         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
4032         hdw->cmd_buffer[1] = 0;
4033         hdw->cmd_buffer[2] = 0;
4034         hdw->cmd_buffer[3] = 0;
4035         hdw->cmd_buffer[4] = 0;
4036         hdw->cmd_buffer[5] = 0;
4037         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4038         hdw->cmd_buffer[7] = reg & 0xff;
4039
4040         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4041         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4042
4043         LOCK_GIVE(hdw->ctl_lock);
4044
4045         return ret;
4046 }
4047
4048
4049 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
4050 {
4051         if (!hdw->flag_ok) return;
4052         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4053                    "Device being rendered inoperable");
4054         if (hdw->vid_stream) {
4055                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
4056         }
4057         hdw->flag_ok = 0;
4058         trace_stbit("flag_ok",hdw->flag_ok);
4059         pvr2_hdw_state_sched(hdw);
4060 }
4061
4062
4063 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4064 {
4065         int ret;
4066         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4067         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4068         if (ret == 0) {
4069                 ret = usb_reset_device(hdw->usb_dev);
4070                 usb_unlock_device(hdw->usb_dev);
4071         } else {
4072                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4073                            "Failed to lock USB device ret=%d",ret);
4074         }
4075         if (init_pause_msec) {
4076                 pvr2_trace(PVR2_TRACE_INFO,
4077                            "Waiting %u msec for hardware to settle",
4078                            init_pause_msec);
4079                 msleep(init_pause_msec);
4080         }
4081
4082 }
4083
4084
4085 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4086 {
4087         char da[1];
4088         unsigned int pipe;
4089         int ret;
4090
4091         if (!hdw->usb_dev) return;
4092
4093         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4094
4095         da[0] = val ? 0x01 : 0x00;
4096
4097         /* Write the CPUCS register on the 8051.  The lsb of the register
4098            is the reset bit; a 1 asserts reset while a 0 clears it. */
4099         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4100         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4101         if (ret < 0) {
4102                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4103                            "cpureset_assert(%d) error=%d",val,ret);
4104                 pvr2_hdw_render_useless(hdw);
4105         }
4106 }
4107
4108
4109 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4110 {
4111         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4112 }
4113
4114
4115 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4116 {
4117         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4118 }
4119
4120
4121 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4122 {
4123         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4124 }
4125
4126
4127 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4128 {
4129         pvr2_trace(PVR2_TRACE_INIT,
4130                    "Requesting decoder reset");
4131         if (hdw->decoder_client_id) {
4132                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4133                                      core, reset, 0);
4134                 pvr2_hdw_cx25840_vbi_hack(hdw);
4135                 return 0;
4136         }
4137         pvr2_trace(PVR2_TRACE_INIT,
4138                    "Unable to reset decoder: nothing attached");
4139         return -ENOTTY;
4140 }
4141
4142
4143 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4144 {
4145         hdw->flag_ok = !0;
4146         return pvr2_issue_simple_cmd(hdw,
4147                                      FX2CMD_HCW_DEMOD_RESETIN |
4148                                      (1 << 8) |
4149                                      ((onoff ? 1 : 0) << 16));
4150 }
4151
4152
4153 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4154 {
4155         hdw->flag_ok = !0;
4156         return pvr2_issue_simple_cmd(hdw,(onoff ?
4157                                           FX2CMD_ONAIR_DTV_POWER_ON :
4158                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4159 }
4160
4161
4162 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4163                                                 int onoff)
4164 {
4165         return pvr2_issue_simple_cmd(hdw,(onoff ?
4166                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4167                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4168 }
4169
4170
4171 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4172 {
4173         int cmode;
4174         /* Compare digital/analog desired setting with current setting.  If
4175            they don't match, fix it... */
4176         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4177         if (cmode == hdw->pathway_state) {
4178                 /* They match; nothing to do */
4179                 return;
4180         }
4181
4182         switch (hdw->hdw_desc->digital_control_scheme) {
4183         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4184                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4185                 if (cmode == PVR2_PATHWAY_ANALOG) {
4186                         /* If moving to analog mode, also force the decoder
4187                            to reset.  If no decoder is attached, then it's
4188                            ok to ignore this because if/when the decoder
4189                            attaches, it will reset itself at that time. */
4190                         pvr2_hdw_cmd_decoder_reset(hdw);
4191                 }
4192                 break;
4193         case PVR2_DIGITAL_SCHEME_ONAIR:
4194                 /* Supposedly we should always have the power on whether in
4195                    digital or analog mode.  But for now do what appears to
4196                    work... */
4197                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4198                 break;
4199         default: break;
4200         }
4201
4202         pvr2_hdw_untrip_unlocked(hdw);
4203         hdw->pathway_state = cmode;
4204 }
4205
4206
4207 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4208 {
4209         /* change some GPIO data
4210          *
4211          * note: bit d7 of dir appears to control the LED,
4212          * so we shut it off here.
4213          *
4214          */
4215         if (onoff) {
4216                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4217         } else {
4218                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4219         }
4220         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4221 }
4222
4223
4224 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4225
4226 static led_method_func led_methods[] = {
4227         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4228 };
4229
4230
4231 /* Toggle LED */
4232 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4233 {
4234         unsigned int scheme_id;
4235         led_method_func fp;
4236
4237         if ((!onoff) == (!hdw->led_on)) return;
4238
4239         hdw->led_on = onoff != 0;
4240
4241         scheme_id = hdw->hdw_desc->led_scheme;
4242         if (scheme_id < ARRAY_SIZE(led_methods)) {
4243                 fp = led_methods[scheme_id];
4244         } else {
4245                 fp = NULL;
4246         }
4247
4248         if (fp) (*fp)(hdw,onoff);
4249 }
4250
4251
4252 /* Stop / start video stream transport */
4253 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4254 {
4255         int ret;
4256
4257         /* If we're in analog mode, then just issue the usual analog
4258            command. */
4259         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4260                 return pvr2_issue_simple_cmd(hdw,
4261                                              (runFl ?
4262                                               FX2CMD_STREAMING_ON :
4263                                               FX2CMD_STREAMING_OFF));
4264                 /*Note: Not reached */
4265         }
4266
4267         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4268                 /* Whoops, we don't know what mode we're in... */
4269                 return -EINVAL;
4270         }
4271
4272         /* To get here we have to be in digital mode.  The mechanism here
4273            is unfortunately different for different vendors.  So we switch
4274            on the device's digital scheme attribute in order to figure out
4275            what to do. */
4276         switch (hdw->hdw_desc->digital_control_scheme) {
4277         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4278                 return pvr2_issue_simple_cmd(hdw,
4279                                              (runFl ?
4280                                               FX2CMD_HCW_DTV_STREAMING_ON :
4281                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4282         case PVR2_DIGITAL_SCHEME_ONAIR:
4283                 ret = pvr2_issue_simple_cmd(hdw,
4284                                             (runFl ?
4285                                              FX2CMD_STREAMING_ON :
4286                                              FX2CMD_STREAMING_OFF));
4287                 if (ret) return ret;
4288                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4289         default:
4290                 return -EINVAL;
4291         }
4292 }
4293
4294
4295 /* Evaluate whether or not state_pathway_ok can change */
4296 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4297 {
4298         if (hdw->state_pathway_ok) {
4299                 /* Nothing to do if pathway is already ok */
4300                 return 0;
4301         }
4302         if (!hdw->state_pipeline_idle) {
4303                 /* Not allowed to change anything if pipeline is not idle */
4304                 return 0;
4305         }
4306         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4307         hdw->state_pathway_ok = !0;
4308         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4309         return !0;
4310 }
4311
4312
4313 /* Evaluate whether or not state_encoder_ok can change */
4314 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4315 {
4316         if (hdw->state_encoder_ok) return 0;
4317         if (hdw->flag_tripped) return 0;
4318         if (hdw->state_encoder_run) return 0;
4319         if (hdw->state_encoder_config) return 0;
4320         if (hdw->state_decoder_run) return 0;
4321         if (hdw->state_usbstream_run) return 0;
4322         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4323                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4324         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4325                 return 0;
4326         }
4327
4328         if (pvr2_upload_firmware2(hdw) < 0) {
4329                 hdw->flag_tripped = !0;
4330                 trace_stbit("flag_tripped",hdw->flag_tripped);
4331                 return !0;
4332         }
4333         hdw->state_encoder_ok = !0;
4334         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4335         return !0;
4336 }
4337
4338
4339 /* Evaluate whether or not state_encoder_config can change */
4340 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4341 {
4342         if (hdw->state_encoder_config) {
4343                 if (hdw->state_encoder_ok) {
4344                         if (hdw->state_pipeline_req &&
4345                             !hdw->state_pipeline_pause) return 0;
4346                 }
4347                 hdw->state_encoder_config = 0;
4348                 hdw->state_encoder_waitok = 0;
4349                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4350                 /* paranoia - solve race if timer just completed */
4351                 del_timer_sync(&hdw->encoder_wait_timer);
4352         } else {
4353                 if (!hdw->state_pathway_ok ||
4354                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4355                     !hdw->state_encoder_ok ||
4356                     !hdw->state_pipeline_idle ||
4357                     hdw->state_pipeline_pause ||
4358                     !hdw->state_pipeline_req ||
4359                     !hdw->state_pipeline_config) {
4360                         /* We must reset the enforced wait interval if
4361                            anything has happened that might have disturbed
4362                            the encoder.  This should be a rare case. */
4363                         if (timer_pending(&hdw->encoder_wait_timer)) {
4364                                 del_timer_sync(&hdw->encoder_wait_timer);
4365                         }
4366                         if (hdw->state_encoder_waitok) {
4367                                 /* Must clear the state - therefore we did
4368                                    something to a state bit and must also
4369                                    return true. */
4370                                 hdw->state_encoder_waitok = 0;
4371                                 trace_stbit("state_encoder_waitok",
4372                                             hdw->state_encoder_waitok);
4373                                 return !0;
4374                         }
4375                         return 0;
4376                 }
4377                 if (!hdw->state_encoder_waitok) {
4378                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4379                                 /* waitok flag wasn't set and timer isn't
4380                                    running.  Check flag once more to avoid
4381                                    a race then start the timer.  This is
4382                                    the point when we measure out a minimal
4383                                    quiet interval before doing something to
4384                                    the encoder. */
4385                                 if (!hdw->state_encoder_waitok) {
4386                                         hdw->encoder_wait_timer.expires =
4387                                                 jiffies +
4388                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4389                                                  / 1000);
4390                                         add_timer(&hdw->encoder_wait_timer);
4391                                 }
4392                         }
4393                         /* We can't continue until we know we have been
4394                            quiet for the interval measured by this
4395                            timer. */
4396                         return 0;
4397                 }
4398                 pvr2_encoder_configure(hdw);
4399                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4400         }
4401         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4402         return !0;
4403 }
4404
4405
4406 /* Return true if the encoder should not be running. */
4407 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4408 {
4409         if (!hdw->state_encoder_ok) {
4410                 /* Encoder isn't healthy at the moment, so stop it. */
4411                 return !0;
4412         }
4413         if (!hdw->state_pathway_ok) {
4414                 /* Mode is not understood at the moment (i.e. it wants to
4415                    change), so encoder must be stopped. */
4416                 return !0;
4417         }
4418
4419         switch (hdw->pathway_state) {
4420         case PVR2_PATHWAY_ANALOG:
4421                 if (!hdw->state_decoder_run) {
4422                         /* We're in analog mode and the decoder is not
4423                            running; thus the encoder should be stopped as
4424                            well. */
4425                         return !0;
4426                 }
4427                 break;
4428         case PVR2_PATHWAY_DIGITAL:
4429                 if (hdw->state_encoder_runok) {
4430                         /* This is a funny case.  We're in digital mode so
4431                            really the encoder should be stopped.  However
4432                            if it really is running, only kill it after
4433                            runok has been set.  This gives a chance for the
4434                            onair quirk to function (encoder must run
4435                            briefly first, at least once, before onair
4436                            digital streaming can work). */
4437                         return !0;
4438                 }
4439                 break;
4440         default:
4441                 /* Unknown mode; so encoder should be stopped. */
4442                 return !0;
4443         }
4444
4445         /* If we get here, we haven't found a reason to stop the
4446            encoder. */
4447         return 0;
4448 }
4449
4450
4451 /* Return true if the encoder should be running. */
4452 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4453 {
4454         if (!hdw->state_encoder_ok) {
4455                 /* Don't run the encoder if it isn't healthy... */
4456                 return 0;
4457         }
4458         if (!hdw->state_pathway_ok) {
4459                 /* Don't run the encoder if we don't (yet) know what mode
4460                    we need to be in... */
4461                 return 0;
4462         }
4463
4464         switch (hdw->pathway_state) {
4465         case PVR2_PATHWAY_ANALOG:
4466                 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4467                         /* In analog mode, if the decoder is running, then
4468                            run the encoder. */
4469                         return !0;
4470                 }
4471                 break;
4472         case PVR2_PATHWAY_DIGITAL:
4473                 if ((hdw->hdw_desc->digital_control_scheme ==
4474                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4475                     !hdw->state_encoder_runok) {
4476                         /* This is a quirk.  OnAir hardware won't stream
4477                            digital until the encoder has been run at least
4478                            once, for a minimal period of time (empiricially
4479                            measured to be 1/4 second).  So if we're on
4480                            OnAir hardware and the encoder has never been
4481                            run at all, then start the encoder.  Normal
4482                            state machine logic in the driver will
4483                            automatically handle the remaining bits. */
4484                         return !0;
4485                 }
4486                 break;
4487         default:
4488                 /* For completeness (unknown mode; encoder won't run ever) */
4489                 break;
4490         }
4491         /* If we get here, then we haven't found any reason to run the
4492            encoder, so don't run it. */
4493         return 0;
4494 }
4495
4496
4497 /* Evaluate whether or not state_encoder_run can change */
4498 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4499 {
4500         if (hdw->state_encoder_run) {
4501                 if (!state_check_disable_encoder_run(hdw)) return 0;
4502                 if (hdw->state_encoder_ok) {
4503                         del_timer_sync(&hdw->encoder_run_timer);
4504                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4505                 }
4506                 hdw->state_encoder_run = 0;
4507         } else {
4508                 if (!state_check_enable_encoder_run(hdw)) return 0;
4509                 if (pvr2_encoder_start(hdw) < 0) return !0;
4510                 hdw->state_encoder_run = !0;
4511                 if (!hdw->state_encoder_runok) {
4512                         hdw->encoder_run_timer.expires =
4513                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4514                         add_timer(&hdw->encoder_run_timer);
4515                 }
4516         }
4517         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4518         return !0;
4519 }
4520
4521
4522 /* Timeout function for quiescent timer. */
4523 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4524 {
4525         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4526         hdw->state_decoder_quiescent = !0;
4527         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4528         hdw->state_stale = !0;
4529         queue_work(hdw->workqueue,&hdw->workpoll);
4530 }
4531
4532
4533 /* Timeout function for decoder stabilization timer. */
4534 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4535 {
4536         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4537         hdw->state_decoder_ready = !0;
4538         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4539         hdw->state_stale = !0;
4540         queue_work(hdw->workqueue, &hdw->workpoll);
4541 }
4542
4543
4544 /* Timeout function for encoder wait timer. */
4545 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4546 {
4547         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4548         hdw->state_encoder_waitok = !0;
4549         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4550         hdw->state_stale = !0;
4551         queue_work(hdw->workqueue,&hdw->workpoll);
4552 }
4553
4554
4555 /* Timeout function for encoder run timer. */
4556 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4557 {
4558         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4559         if (!hdw->state_encoder_runok) {
4560                 hdw->state_encoder_runok = !0;
4561                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4562                 hdw->state_stale = !0;
4563                 queue_work(hdw->workqueue,&hdw->workpoll);
4564         }
4565 }
4566
4567
4568 /* Evaluate whether or not state_decoder_run can change */
4569 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4570 {
4571         if (hdw->state_decoder_run) {
4572                 if (hdw->state_encoder_ok) {
4573                         if (hdw->state_pipeline_req &&
4574                             !hdw->state_pipeline_pause &&
4575                             hdw->state_pathway_ok) return 0;
4576                 }
4577                 if (!hdw->flag_decoder_missed) {
4578                         pvr2_decoder_enable(hdw,0);
4579                 }
4580                 hdw->state_decoder_quiescent = 0;
4581                 hdw->state_decoder_run = 0;
4582                 /* paranoia - solve race if timer(s) just completed */
4583                 del_timer_sync(&hdw->quiescent_timer);
4584                 /* Kill the stabilization timer, in case we're killing the
4585                    encoder before the previous stabilization interval has
4586                    been properly timed. */
4587                 del_timer_sync(&hdw->decoder_stabilization_timer);
4588                 hdw->state_decoder_ready = 0;
4589         } else {
4590                 if (!hdw->state_decoder_quiescent) {
4591                         if (!timer_pending(&hdw->quiescent_timer)) {
4592                                 /* We don't do something about the
4593                                    quiescent timer until right here because
4594                                    we also want to catch cases where the
4595                                    decoder was already not running (like
4596                                    after initialization) as opposed to
4597                                    knowing that we had just stopped it.
4598                                    The second flag check is here to cover a
4599                                    race - the timer could have run and set
4600                                    this flag just after the previous check
4601                                    but before we did the pending check. */
4602                                 if (!hdw->state_decoder_quiescent) {
4603                                         hdw->quiescent_timer.expires =
4604                                                 jiffies +
4605                                                 (HZ * TIME_MSEC_DECODER_WAIT
4606                                                  / 1000);
4607                                         add_timer(&hdw->quiescent_timer);
4608                                 }
4609                         }
4610                         /* Don't allow decoder to start again until it has
4611                            been quiesced first.  This little detail should
4612                            hopefully further stabilize the encoder. */
4613                         return 0;
4614                 }
4615                 if (!hdw->state_pathway_ok ||
4616                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4617                     !hdw->state_pipeline_req ||
4618                     hdw->state_pipeline_pause ||
4619                     !hdw->state_pipeline_config ||
4620                     !hdw->state_encoder_config ||
4621                     !hdw->state_encoder_ok) return 0;
4622                 del_timer_sync(&hdw->quiescent_timer);
4623                 if (hdw->flag_decoder_missed) return 0;
4624                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4625                 hdw->state_decoder_quiescent = 0;
4626                 hdw->state_decoder_ready = 0;
4627                 hdw->state_decoder_run = !0;
4628                 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4629                         hdw->decoder_stabilization_timer.expires =
4630                                 jiffies +
4631                                 (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
4632                                  1000);
4633                         add_timer(&hdw->decoder_stabilization_timer);
4634                 } else {
4635                         hdw->state_decoder_ready = !0;
4636                 }
4637         }
4638         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4639         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4640         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4641         return !0;
4642 }
4643
4644
4645 /* Evaluate whether or not state_usbstream_run can change */
4646 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4647 {
4648         if (hdw->state_usbstream_run) {
4649                 int fl = !0;
4650                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4651                         fl = (hdw->state_encoder_ok &&
4652                               hdw->state_encoder_run);
4653                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4654                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4655                         fl = hdw->state_encoder_ok;
4656                 }
4657                 if (fl &&
4658                     hdw->state_pipeline_req &&
4659                     !hdw->state_pipeline_pause &&
4660                     hdw->state_pathway_ok) {
4661                         return 0;
4662                 }
4663                 pvr2_hdw_cmd_usbstream(hdw,0);
4664                 hdw->state_usbstream_run = 0;
4665         } else {
4666                 if (!hdw->state_pipeline_req ||
4667                     hdw->state_pipeline_pause ||
4668                     !hdw->state_pathway_ok) return 0;
4669                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4670                         if (!hdw->state_encoder_ok ||
4671                             !hdw->state_encoder_run) return 0;
4672                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4673                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4674                         if (!hdw->state_encoder_ok) return 0;
4675                         if (hdw->state_encoder_run) return 0;
4676                         if (hdw->hdw_desc->digital_control_scheme ==
4677                             PVR2_DIGITAL_SCHEME_ONAIR) {
4678                                 /* OnAir digital receivers won't stream
4679                                    unless the analog encoder has run first.
4680                                    Why?  I have no idea.  But don't even
4681                                    try until we know the analog side is
4682                                    known to have run. */
4683                                 if (!hdw->state_encoder_runok) return 0;
4684                         }
4685                 }
4686                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4687                 hdw->state_usbstream_run = !0;
4688         }
4689         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4690         return !0;
4691 }
4692
4693
4694 /* Attempt to configure pipeline, if needed */
4695 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4696 {
4697         if (hdw->state_pipeline_config ||
4698             hdw->state_pipeline_pause) return 0;
4699         pvr2_hdw_commit_execute(hdw);
4700         return !0;
4701 }
4702
4703
4704 /* Update pipeline idle and pipeline pause tracking states based on other
4705    inputs.  This must be called whenever the other relevant inputs have
4706    changed. */
4707 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4708 {
4709         unsigned int st;
4710         int updatedFl = 0;
4711         /* Update pipeline state */
4712         st = !(hdw->state_encoder_run ||
4713                hdw->state_decoder_run ||
4714                hdw->state_usbstream_run ||
4715                (!hdw->state_decoder_quiescent));
4716         if (!st != !hdw->state_pipeline_idle) {
4717                 hdw->state_pipeline_idle = st;
4718                 updatedFl = !0;
4719         }
4720         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4721                 hdw->state_pipeline_pause = 0;
4722                 updatedFl = !0;
4723         }
4724         return updatedFl;
4725 }
4726
4727
4728 typedef int (*state_eval_func)(struct pvr2_hdw *);
4729
4730 /* Set of functions to be run to evaluate various states in the driver. */
4731 static const state_eval_func eval_funcs[] = {
4732         state_eval_pathway_ok,
4733         state_eval_pipeline_config,
4734         state_eval_encoder_ok,
4735         state_eval_encoder_config,
4736         state_eval_decoder_run,
4737         state_eval_encoder_run,
4738         state_eval_usbstream_run,
4739 };
4740
4741
4742 /* Process various states and return true if we did anything interesting. */
4743 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4744 {
4745         unsigned int i;
4746         int state_updated = 0;
4747         int check_flag;
4748
4749         if (!hdw->state_stale) return 0;
4750         if ((hdw->fw1_state != FW1_STATE_OK) ||
4751             !hdw->flag_ok) {
4752                 hdw->state_stale = 0;
4753                 return !0;
4754         }
4755         /* This loop is the heart of the entire driver.  It keeps trying to
4756            evaluate various bits of driver state until nothing changes for
4757            one full iteration.  Each "bit of state" tracks some global
4758            aspect of the driver, e.g. whether decoder should run, if
4759            pipeline is configured, usb streaming is on, etc.  We separately
4760            evaluate each of those questions based on other driver state to
4761            arrive at the correct running configuration. */
4762         do {
4763                 check_flag = 0;
4764                 state_update_pipeline_state(hdw);
4765                 /* Iterate over each bit of state */
4766                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4767                         if ((*eval_funcs[i])(hdw)) {
4768                                 check_flag = !0;
4769                                 state_updated = !0;
4770                                 state_update_pipeline_state(hdw);
4771                         }
4772                 }
4773         } while (check_flag && hdw->flag_ok);
4774         hdw->state_stale = 0;
4775         trace_stbit("state_stale",hdw->state_stale);
4776         return state_updated;
4777 }
4778
4779
4780 static unsigned int print_input_mask(unsigned int msk,
4781                                      char *buf,unsigned int acnt)
4782 {
4783         unsigned int idx,ccnt;
4784         unsigned int tcnt = 0;
4785         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4786                 if (!((1 << idx) & msk)) continue;
4787                 ccnt = scnprintf(buf+tcnt,
4788                                  acnt-tcnt,
4789                                  "%s%s",
4790                                  (tcnt ? ", " : ""),
4791                                  control_values_input[idx]);
4792                 tcnt += ccnt;
4793         }
4794         return tcnt;
4795 }
4796
4797
4798 static const char *pvr2_pathway_state_name(int id)
4799 {
4800         switch (id) {
4801         case PVR2_PATHWAY_ANALOG: return "analog";
4802         case PVR2_PATHWAY_DIGITAL: return "digital";
4803         default: return "unknown";
4804         }
4805 }
4806
4807
4808 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4809                                              char *buf,unsigned int acnt)
4810 {
4811         switch (which) {
4812         case 0:
4813                 return scnprintf(
4814                         buf,acnt,
4815                         "driver:%s%s%s%s%s <mode=%s>",
4816                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4817                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4818                         (hdw->flag_disconnected ? " <disconnected>" :
4819                          " <connected>"),
4820                         (hdw->flag_tripped ? " <tripped>" : ""),
4821                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4822                         pvr2_pathway_state_name(hdw->pathway_state));
4823
4824         case 1:
4825                 return scnprintf(
4826                         buf,acnt,
4827                         "pipeline:%s%s%s%s",
4828                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4829                         (hdw->state_pipeline_config ?
4830                          " <configok>" : " <stale>"),
4831                         (hdw->state_pipeline_req ? " <req>" : ""),
4832                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4833         case 2:
4834                 return scnprintf(
4835                         buf,acnt,
4836                         "worker:%s%s%s%s%s%s%s",
4837                         (hdw->state_decoder_run ?
4838                          (hdw->state_decoder_ready ?
4839                           "<decode:run>" : " <decode:start>") :
4840                          (hdw->state_decoder_quiescent ?
4841                           "" : " <decode:stop>")),
4842                         (hdw->state_decoder_quiescent ?
4843                          " <decode:quiescent>" : ""),
4844                         (hdw->state_encoder_ok ?
4845                          "" : " <encode:init>"),
4846                         (hdw->state_encoder_run ?
4847                          (hdw->state_encoder_runok ?
4848                           " <encode:run>" :
4849                           " <encode:firstrun>") :
4850                          (hdw->state_encoder_runok ?
4851                           " <encode:stop>" :
4852                           " <encode:virgin>")),
4853                         (hdw->state_encoder_config ?
4854                          " <encode:configok>" :
4855                          (hdw->state_encoder_waitok ?
4856                           "" : " <encode:waitok>")),
4857                         (hdw->state_usbstream_run ?
4858                          " <usb:run>" : " <usb:stop>"),
4859                         (hdw->state_pathway_ok ?
4860                          " <pathway:ok>" : ""));
4861         case 3:
4862                 return scnprintf(
4863                         buf,acnt,
4864                         "state: %s",
4865                         pvr2_get_state_name(hdw->master_state));
4866         case 4: {
4867                 unsigned int tcnt = 0;
4868                 unsigned int ccnt;
4869
4870                 ccnt = scnprintf(buf,
4871                                  acnt,
4872                                  "Hardware supported inputs: ");
4873                 tcnt += ccnt;
4874                 tcnt += print_input_mask(hdw->input_avail_mask,
4875                                          buf+tcnt,
4876                                          acnt-tcnt);
4877                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4878                         ccnt = scnprintf(buf+tcnt,
4879                                          acnt-tcnt,
4880                                          "; allowed inputs: ");
4881                         tcnt += ccnt;
4882                         tcnt += print_input_mask(hdw->input_allowed_mask,
4883                                                  buf+tcnt,
4884                                                  acnt-tcnt);
4885                 }
4886                 return tcnt;
4887         }
4888         case 5: {
4889                 struct pvr2_stream_stats stats;
4890                 if (!hdw->vid_stream) break;
4891                 pvr2_stream_get_stats(hdw->vid_stream,
4892                                       &stats,
4893                                       0);
4894                 return scnprintf(
4895                         buf,acnt,
4896                         "Bytes streamed=%u"
4897                         " URBs: queued=%u idle=%u ready=%u"
4898                         " processed=%u failed=%u",
4899                         stats.bytes_processed,
4900                         stats.buffers_in_queue,
4901                         stats.buffers_in_idle,
4902                         stats.buffers_in_ready,
4903                         stats.buffers_processed,
4904                         stats.buffers_failed);
4905         }
4906         case 6: {
4907                 unsigned int id = hdw->ir_scheme_active;
4908                 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4909                                  (id >= ARRAY_SIZE(ir_scheme_names) ?
4910                                   "?" : ir_scheme_names[id]));
4911         }
4912         default: break;
4913         }
4914         return 0;
4915 }
4916
4917
4918 /* Generate report containing info about attached sub-devices and attached
4919    i2c clients, including an indication of which attached i2c clients are
4920    actually sub-devices. */
4921 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4922                                             char *buf, unsigned int acnt)
4923 {
4924         struct v4l2_subdev *sd;
4925         unsigned int tcnt = 0;
4926         unsigned int ccnt;
4927         struct i2c_client *client;
4928         const char *p;
4929         unsigned int id;
4930
4931         ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4932         tcnt += ccnt;
4933         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4934                 id = sd->grp_id;
4935                 p = NULL;
4936                 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4937                 if (p) {
4938                         ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4939                         tcnt += ccnt;
4940                 } else {
4941                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4942                                          "  (unknown id=%u):", id);
4943                         tcnt += ccnt;
4944                 }
4945                 client = v4l2_get_subdevdata(sd);
4946                 if (client) {
4947                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4948                                          " %s @ %02x\n", client->name,
4949                                          client->addr);
4950                         tcnt += ccnt;
4951                 } else {
4952                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4953                                          " no i2c client\n");
4954                         tcnt += ccnt;
4955                 }
4956         }
4957         return tcnt;
4958 }
4959
4960
4961 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4962                                    char *buf,unsigned int acnt)
4963 {
4964         unsigned int bcnt,ccnt,idx;
4965         bcnt = 0;
4966         LOCK_TAKE(hdw->big_lock);
4967         for (idx = 0; ; idx++) {
4968                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4969                 if (!ccnt) break;
4970                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4971                 if (!acnt) break;
4972                 buf[0] = '\n'; ccnt = 1;
4973                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4974         }
4975         ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4976         bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4977         LOCK_GIVE(hdw->big_lock);
4978         return bcnt;
4979 }
4980
4981
4982 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4983 {
4984         char buf[256];
4985         unsigned int idx, ccnt;
4986         unsigned int lcnt, ucnt;
4987
4988         for (idx = 0; ; idx++) {
4989                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4990                 if (!ccnt) break;
4991                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4992         }
4993         ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4994         ucnt = 0;
4995         while (ucnt < ccnt) {
4996                 lcnt = 0;
4997                 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4998                         lcnt++;
4999                 }
5000                 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
5001                 ucnt += lcnt + 1;
5002         }
5003 }
5004
5005
5006 /* Evaluate and update the driver's current state, taking various actions
5007    as appropriate for the update. */
5008 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
5009 {
5010         unsigned int st;
5011         int state_updated = 0;
5012         int callback_flag = 0;
5013         int analog_mode;
5014
5015         pvr2_trace(PVR2_TRACE_STBITS,
5016                    "Drive state check START");
5017         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5018                 pvr2_hdw_state_log_state(hdw);
5019         }
5020
5021         /* Process all state and get back over disposition */
5022         state_updated = pvr2_hdw_state_update(hdw);
5023
5024         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
5025
5026         /* Update master state based upon all other states. */
5027         if (!hdw->flag_ok) {
5028                 st = PVR2_STATE_DEAD;
5029         } else if (hdw->fw1_state != FW1_STATE_OK) {
5030                 st = PVR2_STATE_COLD;
5031         } else if ((analog_mode ||
5032                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
5033                    !hdw->state_encoder_ok) {
5034                 st = PVR2_STATE_WARM;
5035         } else if (hdw->flag_tripped ||
5036                    (analog_mode && hdw->flag_decoder_missed)) {
5037                 st = PVR2_STATE_ERROR;
5038         } else if (hdw->state_usbstream_run &&
5039                    (!analog_mode ||
5040                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
5041                 st = PVR2_STATE_RUN;
5042         } else {
5043                 st = PVR2_STATE_READY;
5044         }
5045         if (hdw->master_state != st) {
5046                 pvr2_trace(PVR2_TRACE_STATE,
5047                            "Device state change from %s to %s",
5048                            pvr2_get_state_name(hdw->master_state),
5049                            pvr2_get_state_name(st));
5050                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
5051                 hdw->master_state = st;
5052                 state_updated = !0;
5053                 callback_flag = !0;
5054         }
5055         if (state_updated) {
5056                 /* Trigger anyone waiting on any state changes here. */
5057                 wake_up(&hdw->state_wait_data);
5058         }
5059
5060         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5061                 pvr2_hdw_state_log_state(hdw);
5062         }
5063         pvr2_trace(PVR2_TRACE_STBITS,
5064                    "Drive state check DONE callback=%d",callback_flag);
5065
5066         return callback_flag;
5067 }
5068
5069
5070 /* Cause kernel thread to check / update driver state */
5071 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5072 {
5073         if (hdw->state_stale) return;
5074         hdw->state_stale = !0;
5075         trace_stbit("state_stale",hdw->state_stale);
5076         queue_work(hdw->workqueue,&hdw->workpoll);
5077 }
5078
5079
5080 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5081 {
5082         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5083 }
5084
5085
5086 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5087 {
5088         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5089 }
5090
5091
5092 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5093 {
5094         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5095 }
5096
5097
5098 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5099 {
5100         u32 cval,nval;
5101         int ret;
5102         if (~msk) {
5103                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5104                 if (ret) return ret;
5105                 nval = (cval & ~msk) | (val & msk);
5106                 pvr2_trace(PVR2_TRACE_GPIO,
5107                            "GPIO direction changing 0x%x:0x%x"
5108                            " from 0x%x to 0x%x",
5109                            msk,val,cval,nval);
5110         } else {
5111                 nval = val;
5112                 pvr2_trace(PVR2_TRACE_GPIO,
5113                            "GPIO direction changing to 0x%x",nval);
5114         }
5115         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5116 }
5117
5118
5119 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5120 {
5121         u32 cval,nval;
5122         int ret;
5123         if (~msk) {
5124                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5125                 if (ret) return ret;
5126                 nval = (cval & ~msk) | (val & msk);
5127                 pvr2_trace(PVR2_TRACE_GPIO,
5128                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5129                            msk,val,cval,nval);
5130         } else {
5131                 nval = val;
5132                 pvr2_trace(PVR2_TRACE_GPIO,
5133                            "GPIO output changing to 0x%x",nval);
5134         }
5135         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5136 }
5137
5138
5139 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5140 {
5141         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5142         memset(vtp, 0, sizeof(*vtp));
5143         hdw->tuner_signal_stale = 0;
5144         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5145            using v4l2-subdev - therefore we can't support that AT ALL right
5146            now.  (Of course, no sub-drivers seem to implement it either.
5147            But now it's a a chicken and egg problem...) */
5148         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5149                              &hdw->tuner_signal_info);
5150         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5151                    " type=%u strength=%u audio=0x%x cap=0x%x"
5152                    " low=%u hi=%u",
5153                    vtp->type,
5154                    vtp->signal, vtp->rxsubchans, vtp->capability,
5155                    vtp->rangelow, vtp->rangehigh);
5156
5157         /* We have to do this to avoid getting into constant polling if
5158            there's nobody to answer a poll of cropcap info. */
5159         hdw->cropcap_stale = 0;
5160 }
5161
5162
5163 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5164 {
5165         return hdw->input_avail_mask;
5166 }
5167
5168
5169 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5170 {
5171         return hdw->input_allowed_mask;
5172 }
5173
5174
5175 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5176 {
5177         if (hdw->input_val != v) {
5178                 hdw->input_val = v;
5179                 hdw->input_dirty = !0;
5180         }
5181
5182         /* Handle side effects - if we switch to a mode that needs the RF
5183            tuner, then select the right frequency choice as well and mark
5184            it dirty. */
5185         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5186                 hdw->freqSelector = 0;
5187                 hdw->freqDirty = !0;
5188         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5189                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5190                 hdw->freqSelector = 1;
5191                 hdw->freqDirty = !0;
5192         }
5193         return 0;
5194 }
5195
5196
5197 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5198                                unsigned int change_mask,
5199                                unsigned int change_val)
5200 {
5201         int ret = 0;
5202         unsigned int nv,m,idx;
5203         LOCK_TAKE(hdw->big_lock);
5204         do {
5205                 nv = hdw->input_allowed_mask & ~change_mask;
5206                 nv |= (change_val & change_mask);
5207                 nv &= hdw->input_avail_mask;
5208                 if (!nv) {
5209                         /* No legal modes left; return error instead. */
5210                         ret = -EPERM;
5211                         break;
5212                 }
5213                 hdw->input_allowed_mask = nv;
5214                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5215                         /* Current mode is still in the allowed mask, so
5216                            we're done. */
5217                         break;
5218                 }
5219                 /* Select and switch to a mode that is still in the allowed
5220                    mask */
5221                 if (!hdw->input_allowed_mask) {
5222                         /* Nothing legal; give up */
5223                         break;
5224                 }
5225                 m = hdw->input_allowed_mask;
5226                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5227                         if (!((1 << idx) & m)) continue;
5228                         pvr2_hdw_set_input(hdw,idx);
5229                         break;
5230                 }
5231         } while (0);
5232         LOCK_GIVE(hdw->big_lock);
5233         return ret;
5234 }
5235
5236
5237 /* Find I2C address of eeprom */
5238 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5239 {
5240         int result;
5241         LOCK_TAKE(hdw->ctl_lock); do {
5242                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5243                 result = pvr2_send_request(hdw,
5244                                            hdw->cmd_buffer,1,
5245                                            hdw->cmd_buffer,1);
5246                 if (result < 0) break;
5247                 result = hdw->cmd_buffer[0];
5248         } while(0); LOCK_GIVE(hdw->ctl_lock);
5249         return result;
5250 }
5251
5252
5253 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5254                              struct v4l2_dbg_match *match, u64 reg_id,
5255                              int setFl, u64 *val_ptr)
5256 {
5257 #ifdef CONFIG_VIDEO_ADV_DEBUG
5258         struct v4l2_dbg_register req;
5259         int stat = 0;
5260         int okFl = 0;
5261
5262         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5263
5264         req.match = *match;
5265         req.reg = reg_id;
5266         if (setFl) req.val = *val_ptr;
5267         /* It would be nice to know if a sub-device answered the request */
5268         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5269         if (!setFl) *val_ptr = req.val;
5270         if (okFl) {
5271                 return stat;
5272         }
5273         return -EINVAL;
5274 #else
5275         return -ENOSYS;
5276 #endif
5277 }
5278
5279
5280 /*
5281   Stuff for Emacs to see, in order to encourage consistent editing style:
5282   *** Local Variables: ***
5283   *** mode: c ***
5284   *** fill-column: 75 ***
5285   *** tab-width: 8 ***
5286   *** c-basic-offset: 8 ***
5287   *** End: ***
5288   */