1 #define EM_GPIO_0 (1 << 0)
2 #define EM_GPIO_1 (1 << 1)
3 #define EM_GPIO_2 (1 << 2)
4 #define EM_GPIO_3 (1 << 3)
5 #define EM_GPIO_4 (1 << 4)
6 #define EM_GPIO_5 (1 << 5)
7 #define EM_GPIO_6 (1 << 6)
8 #define EM_GPIO_7 (1 << 7)
10 #define EM_GPO_0 (1 << 0)
11 #define EM_GPO_1 (1 << 1)
12 #define EM_GPO_2 (1 << 2)
13 #define EM_GPO_3 (1 << 3)
15 /* em2800 registers */
16 #define EM2800_R08_AUDIOSRC 0x08
18 /* em28xx registers */
20 /* GPIO/GPO registers */
21 #define EM2880_R04_GPO 0x04 /* em2880-em2883 only */
22 #define EM28XX_R08_GPIO 0x08 /* em2820 or upper */
24 #define EM28XX_R06_I2C_CLK 0x06
25 #define EM28XX_R0A_CHIPID 0x0a
26 #define EM28XX_R0C_USBSUSP 0x0c /* */
28 #define EM28XX_R0E_AUDIOSRC 0x0e
29 #define EM28XX_R0F_XCLK 0x0f
31 #define EM28XX_R10_VINMODE 0x10
32 #define EM28XX_R11_VINCTRL 0x11
33 #define EM28XX_R12_VINENABLE 0x12 /* */
35 #define EM28XX_R14_GAMMA 0x14
36 #define EM28XX_R15_RGAIN 0x15
37 #define EM28XX_R16_GGAIN 0x16
38 #define EM28XX_R17_BGAIN 0x17
39 #define EM28XX_R18_ROFFSET 0x18
40 #define EM28XX_R19_GOFFSET 0x19
41 #define EM28XX_R1A_BOFFSET 0x1a
43 #define EM28XX_R1B_OFLOW 0x1b
44 #define EM28XX_R1C_HSTART 0x1c
45 #define EM28XX_R1D_VSTART 0x1d
46 #define EM28XX_R1E_CWIDTH 0x1e
47 #define EM28XX_R1F_CHEIGHT 0x1f
49 #define EM28XX_R20_YGAIN 0x20
50 #define EM28XX_R21_YOFFSET 0x21
51 #define EM28XX_R22_UVGAIN 0x22
52 #define EM28XX_R23_UOFFSET 0x23
53 #define EM28XX_R24_VOFFSET 0x24
54 #define EM28XX_R25_SHARPNESS 0x25
56 #define EM28XX_R26_COMPR 0x26
57 #define EM28XX_R27_OUTFMT 0x27
59 #define EM28XX_R28_XMIN 0x28
60 #define EM28XX_R29_XMAX 0x29
61 #define EM28XX_R2A_YMIN 0x2a
62 #define EM28XX_R2B_YMAX 0x2b
64 #define EM28XX_R30_HSCALELOW 0x30
65 #define EM28XX_R31_HSCALEHIGH 0x31
66 #define EM28XX_R32_VSCALELOW 0x32
67 #define EM28XX_R33_VSCALEHIGH 0x33
69 #define EM28XX_R40_AC97LSB 0x40
70 #define EM28XX_R41_AC97MSB 0x41
71 #define EM28XX_R42_AC97ADDR 0x42
72 #define EM28XX_R43_AC97BUSY 0x43
74 #define EM28XX_R45_IR 0x45
75 /* 0x45 bit 7 - parity bit
82 #define EM28XX_R02_MASTER_AC97 0x02
83 #define EM28XX_R10_LINE_IN_AC97 0x10
84 #define EM28XX_R14_VIDEO_AC97 0x14
86 /* em2874 registers */
87 #define EM2874_R50_IR_CONFIG 0x50
88 #define EM2874_R51_IR 0x51
89 #define EM2874_R5F_TS_ENABLE 0x5f
90 #define EM2874_R80_GPIO 0x80
92 /* em2874 IR config register (0x50) */
93 #define EM2874_IR_NEC 0x00
94 #define EM2874_IR_RC5 0x04
95 #define EM2874_IR_RC5_MODE_0 0x08
96 #define EM2874_IR_RC5_MODE_6A 0x0b
98 /* em2874 Transport Stream Enable Register (0x5f) */
99 #define EM2874_TS1_CAPTURE_ENABLE (1 << 0)
100 #define EM2874_TS1_FILTER_ENABLE (1 << 1)
101 #define EM2874_TS1_NULL_DISCARD (1 << 2)
102 #define EM2874_TS2_CAPTURE_ENABLE (1 << 4)
103 #define EM2874_TS2_FILTER_ENABLE (1 << 5)
104 #define EM2874_TS2_NULL_DISCARD (1 << 6)
106 /* register settings */
107 #define EM2800_AUDIO_SRC_TUNER 0x0d
108 #define EM2800_AUDIO_SRC_LINE 0x0c
109 #define EM28XX_AUDIO_SRC_TUNER 0xc0
110 #define EM28XX_AUDIO_SRC_LINE 0x80
112 /* FIXME: Need to be populated with the other chip ID's */
113 enum em28xx_chip_id {