SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/cx88/cx88-mpeg.c

   1 /*
   2  * $Id: cx88-mpeg.c,v 1.30 2005/07/05 19:44:40 mkrufky Exp $
   3  *
   4  *  Support for the mpeg transport stream transfers
   5  *  PCI function #2 of the cx2388x.
   6  *
   7  *    (c) 2004 Jelle Foks <jelle@foks.8m.com>
   8  *    (c) 2004 Chris Pascoe <c.pascoe@itee.uq.edu.au>
   9  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the Free Software
  23  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/init.h>
  29 #include <linux/device.h>
  30 #include <linux/interrupt.h>
  31 #include <asm/delay.h>
  32
  33 #include "cx88.h"
  34
  35 /* ------------------------------------------------------------------ */
  36
  37 MODULE_DESCRIPTION("mpeg driver for cx2388x based TV cards");
  38 MODULE_AUTHOR("Jelle Foks <jelle@foks.8m.com>");
  39 MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  40 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  41 MODULE_LICENSE("GPL");
  42
  43 static unsigned int debug = 0;
  44 module_param(debug,int,0644);
  45 MODULE_PARM_DESC(debug,"enable debug messages [mpeg]");
  46
  47 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  48         printk(KERN_DEBUG "%s/2: " fmt, dev->core->name , ## arg)
  49
  50 /* ------------------------------------------------------------------ */
  51
  52 static int cx8802_start_dma(struct cx8802_dev    *dev,
  53                             struct cx88_dmaqueue *q,
  54                             struct cx88_buffer   *buf)
  55 {
  56         struct cx88_core *core = dev->core;
  57
  58         dprintk(0, "cx8802_start_dma %d\n", buf->vb.width);
  59
  60         /* setup fifo + format */
  61         cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
  62                                 dev->ts_packet_size, buf->risc.dma);
  63
  64         /* write TS length to chip */
  65         cx_write(MO_TS_LNGTH, buf->vb.width);
  66
  67 #if 1
  68         /* FIXME: this needs a review.
  69          * also: move to cx88-blackbird + cx88-dvb source files? */
  70
  71         if (cx88_boards[core->board].dvb) {
  72                 /* negedge driven & software reset */
  73                 cx_write(TS_GEN_CNTRL, 0x0040 | dev->ts_gen_cntrl);
  74                 udelay(100);
  75                 cx_write(MO_PINMUX_IO, 0x00);
  76                 cx_write(TS_HW_SOP_CNTRL,0x47<<16|188<<4|0x01);
  77                 if ((core->board == CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q) ||
  78                     (core->board == CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T)) {
  79                         cx_write(TS_SOP_STAT, 0<<16 | 0<<14 | 1<<13 | 0<<12);
  80                 } else {
  81                         cx_write(TS_SOP_STAT,0x00);
  82                 }
  83                 cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl);
  84                 udelay(100);
  85         }
  86
  87         if (cx88_boards[core->board].blackbird) {
  88                 cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */
  89
  90                 // cx_write(TS_F2_CMD_STAT_MM, 0x2900106); /* F2_CMD_STAT_MM defaults + master + memory space */
  91                 cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */
  92                 udelay(100);
  93
  94                 cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */
  95                 //cx_write(TS_HW_SOP_CNTRL, 0x2F0BC0); /* mpeg start byte ts: 0x2F0BC0 ? */
  96                 cx_write(TS_VALERR_CNTRL, 0x2000);
  97
  98                 cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */
  99                 udelay(100);
 100         }
 101 #endif
 102
 103         /* reset counter */
 104         cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);
 105         q->count = 1;
 106
 107         /* enable irqs */
 108         dprintk( 0, "setting the interrupt mask\n" );
 109         cx_set(MO_PCI_INTMSK, core->pci_irqmask | 0x04);
 110         cx_set(MO_TS_INTMSK,  0x1f0011);
 111         //cx_write(MO_TS_INTMSK,  0x0f0011);
 112
 113         /* start dma */
 114         cx_set(MO_DEV_CNTRL2, (1<<5));
 115         cx_set(MO_TS_DMACNTRL, 0x11);
 116         return 0;
 117 }
 118
 119 static int cx8802_stop_dma(struct cx8802_dev *dev)
 120 {
 121         struct cx88_core *core = dev->core;
 122         dprintk( 0, "cx8802_stop_dma\n" );
 123
 124         /* stop dma */
 125         cx_clear(MO_TS_DMACNTRL, 0x11);
 126
 127         /* disable irqs */
 128         cx_clear(MO_PCI_INTMSK, 0x000004);
 129         cx_clear(MO_TS_INTMSK, 0x1f0011);
 130
 131         /* Reset the controller */
 132         cx_write(TS_GEN_CNTRL, 0xcd);
 133         return 0;
 134 }
 135
 136 static int cx8802_restart_queue(struct cx8802_dev    *dev,
 137                                 struct cx88_dmaqueue *q)
 138 {
 139         struct cx88_buffer *buf;
 140         struct list_head *item;
 141
 142         dprintk( 0, "cx8802_restart_queue\n" );
 143         if (list_empty(&q->active))
 144         {
 145                 dprintk( 0, "cx8802_restart_queue: queue is empty\n" );
 146                 return 0;
 147         }
 148
 149         buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
 150         dprintk(2,"restart_queue [%p/%d]: restart dma\n",
 151                 buf, buf->vb.i);
 152         cx8802_start_dma(dev, q, buf);
 153         list_for_each(item,&q->active) {
 154                 buf = list_entry(item, struct cx88_buffer, vb.queue);
 155                 buf->count = q->count++;
 156         }
 157         mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
 158         return 0;
 159 }
 160
 161 /* ------------------------------------------------------------------ */
 162
 163 int cx8802_buf_prepare(struct cx8802_dev *dev, struct cx88_buffer *buf)
 164 {
 165         int size = dev->ts_packet_size * dev->ts_packet_count;
 166         int rc;
 167
 168         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
 169         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
 170                 return -EINVAL;
 171
 172         if (STATE_NEEDS_INIT == buf->vb.state) {
 173                 buf->vb.width  = dev->ts_packet_size;
 174                 buf->vb.height = dev->ts_packet_count;
 175                 buf->vb.size   = size;
 176                 buf->vb.field  = V4L2_FIELD_TOP;
 177
 178                 if (0 != (rc = videobuf_iolock(dev->pci,&buf->vb,NULL)))
 179                         goto fail;
 180                 cx88_risc_databuffer(dev->pci, &buf->risc,
 181                                      buf->vb.dma.sglist,
 182                                      buf->vb.width, buf->vb.height);
 183         }
 184         buf->vb.state = STATE_PREPARED;
 185         return 0;
 186
 187  fail:
 188         cx88_free_buffer(dev->pci,buf);
 189         return rc;
 190 }
 191
 192 void cx8802_buf_queue(struct cx8802_dev *dev, struct cx88_buffer *buf)
 193 {
 194         struct cx88_buffer    *prev;
 195         struct cx88_dmaqueue  *q    = &dev->mpegq;
 196
 197         dprintk( 1, "cx8802_buf_queue\n" );
 198         /* add jump to stopper */
 199         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 200         buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
 201
 202         if (list_empty(&q->active)) {
 203                 dprintk( 0, "queue is empty - first active\n" );
 204                 list_add_tail(&buf->vb.queue,&q->active);
 205                 cx8802_start_dma(dev, q, buf);
 206                 buf->vb.state = STATE_ACTIVE;
 207                 buf->count    = q->count++;
 208                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
 209                 dprintk(0,"[%p/%d] %s - first active\n",
 210                         buf, buf->vb.i, __FUNCTION__);
 211                 //udelay(100);
 212
 213         } else {
 214                 dprintk( 1, "queue is not empty - append to active\n" );
 215                 prev = list_entry(q->active.prev, struct cx88_buffer, vb.queue);
 216                 list_add_tail(&buf->vb.queue,&q->active);
 217                 buf->vb.state = STATE_ACTIVE;
 218                 buf->count    = q->count++;
 219                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
 220                 dprintk( 1, "[%p/%d] %s - append to active\n",
 221                         buf, buf->vb.i, __FUNCTION__);
 222                 //udelay(100);
 223         }
 224 }
 225
 226 /* ----------------------------------------------------------- */
 227
 228 static void do_cancel_buffers(struct cx8802_dev *dev, char *reason, int restart)
 229 {
 230         struct cx88_dmaqueue *q = &dev->mpegq;
 231         struct cx88_buffer *buf;
 232         unsigned long flags;
 233
 234         spin_lock_irqsave(&dev->slock,flags);
 235         while (!list_empty(&q->active)) {
 236                 buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
 237                 list_del(&buf->vb.queue);
 238                 buf->vb.state = STATE_ERROR;
 239                 wake_up(&buf->vb.done);
 240                 dprintk(1,"[%p/%d] %s - dma=0x%08lx\n",
 241                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
 242         }
 243         if (restart)
 244         {
 245                 dprintk(0, "restarting queue\n" );
 246                 cx8802_restart_queue(dev,q);
 247         }
 248         spin_unlock_irqrestore(&dev->slock,flags);
 249 }
 250
 251 void cx8802_cancel_buffers(struct cx8802_dev *dev)
 252 {
 253         struct cx88_dmaqueue *q = &dev->mpegq;
 254
 255         dprintk( 1, "cx8802_cancel_buffers" );
 256         del_timer_sync(&q->timeout);
 257         cx8802_stop_dma(dev);
 258         do_cancel_buffers(dev,"cancel",0);
 259 }
 260
 261 static void cx8802_timeout(unsigned long data)
 262 {
 263         struct cx8802_dev *dev = (struct cx8802_dev*)data;
 264
 265         dprintk(0, "%s\n",__FUNCTION__);
 266
 267         if (debug)
 268                 cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
 269         cx8802_stop_dma(dev);
 270         do_cancel_buffers(dev,"timeout",1);
 271 }
 272
 273 static void cx8802_mpeg_irq(struct cx8802_dev *dev)
 274 {
 275         struct cx88_core *core = dev->core;
 276         u32 status, mask, count;
 277
 278         dprintk( 1, "cx8802_mpeg_irq\n" );
 279         status = cx_read(MO_TS_INTSTAT);
 280         mask   = cx_read(MO_TS_INTMSK);
 281         if (0 == (status & mask))
 282                 return;
 283
 284         cx_write(MO_TS_INTSTAT, status);
 285 #if 0
 286         cx88_print_irqbits(core->name, "irq mpeg ",
 287                         cx88_mpeg_irqs, status, mask);
 288 #endif
 289         if (debug || (status & mask & ~0xff))
 290                 cx88_print_irqbits(core->name, "irq mpeg ",
 291                                    cx88_mpeg_irqs, status, mask);
 292
 293         /* risc op code error */
 294         if (status & (1 << 16)) {
 295                 printk(KERN_WARNING "%s: mpeg risc op code error\n",core->name);
 296                 cx_clear(MO_TS_DMACNTRL, 0x11);
 297                 cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
 298         }
 299
 300         /* risc1 y */
 301         if (status & 0x01) {
 302                 dprintk( 1, "wake up\n" );
 303                 spin_lock(&dev->slock);
 304                 count = cx_read(MO_TS_GPCNT);
 305                 cx88_wakeup(dev->core, &dev->mpegq, count);
 306                 spin_unlock(&dev->slock);
 307         }
 308
 309         /* risc2 y */
 310         if (status & 0x10) {
 311                 spin_lock(&dev->slock);
 312                 cx8802_restart_queue(dev,&dev->mpegq);
 313                 spin_unlock(&dev->slock);
 314         }
 315
 316         /* other general errors */
 317         if (status & 0x1f0100) {
 318                 dprintk( 0, "general errors: 0x%08x\n", status & 0x1f0100 );
 319                 spin_lock(&dev->slock);
 320                 cx8802_stop_dma(dev);
 321                 cx8802_restart_queue(dev,&dev->mpegq);
 322                 spin_unlock(&dev->slock);
 323         }
 324 }
 325
 326 #define MAX_IRQ_LOOP 10
 327
 328 static irqreturn_t cx8802_irq(int irq, void *dev_id, struct pt_regs *regs)
 329 {
 330         struct cx8802_dev *dev = dev_id;
 331         struct cx88_core *core = dev->core;
 332         u32 status;
 333         int loop, handled = 0;
 334
 335         for (loop = 0; loop < MAX_IRQ_LOOP; loop++) {
 336                 status = cx_read(MO_PCI_INTSTAT) & (core->pci_irqmask | 0x04);
 337                 if (0 == status)
 338                         goto out;
 339                 dprintk( 1, "cx8802_irq\n" );
 340                 dprintk( 1, "    loop: %d/%d\n", loop, MAX_IRQ_LOOP );
 341                 dprintk( 1, "    status: %d\n", status );
 342                 handled = 1;
 343                 cx_write(MO_PCI_INTSTAT, status);
 344
 345                 if (status & core->pci_irqmask)
 346                         cx88_core_irq(core,status);
 347                 if (status & 0x04)
 348                         cx8802_mpeg_irq(dev);
 349         };
 350         if (MAX_IRQ_LOOP == loop) {
 351                 dprintk( 0, "clearing mask\n" );
 352                 printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
 353                        core->name);
 354                 cx_write(MO_PCI_INTMSK,0);
 355         }
 356
 357  out:
 358         return IRQ_RETVAL(handled);
 359 }
 360
 361 /* ----------------------------------------------------------- */
 362 /* exported stuff                                              */
 363
 364 int cx8802_init_common(struct cx8802_dev *dev)
 365 {
 366         struct cx88_core *core = dev->core;
 367         int err;
 368
 369         /* pci init */
 370         if (pci_enable_device(dev->pci))
 371                 return -EIO;
 372         pci_set_master(dev->pci);
 373         if (!pci_dma_supported(dev->pci,0xffffffff)) {
 374                 printk("%s/2: Oops: no 32bit PCI DMA ???\n",dev->core->name);
 375                 return -EIO;
 376         }
 377
 378         pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev);
 379         pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER,  &dev->pci_lat);
 380         printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, "
 381                "latency: %d, mmio: 0x%lx\n", dev->core->name,
 382                pci_name(dev->pci), dev->pci_rev, dev->pci->irq,
 383                dev->pci_lat,pci_resource_start(dev->pci,0));
 384
 385         /* initialize driver struct */
 386         init_MUTEX(&dev->lock);
 387         spin_lock_init(&dev->slock);
 388
 389         /* init dma queue */
 390         INIT_LIST_HEAD(&dev->mpegq.active);
 391         INIT_LIST_HEAD(&dev->mpegq.queued);
 392         dev->mpegq.timeout.function = cx8802_timeout;
 393         dev->mpegq.timeout.data     = (unsigned long)dev;
 394         init_timer(&dev->mpegq.timeout);
 395         cx88_risc_stopper(dev->pci,&dev->mpegq.stopper,
 396                           MO_TS_DMACNTRL,0x11,0x00);
 397
 398         /* get irq */
 399         err = request_irq(dev->pci->irq, cx8802_irq,
 400                           SA_SHIRQ | SA_INTERRUPT, dev->core->name, dev);
 401         if (err < 0) {
 402                 printk(KERN_ERR "%s: can't get IRQ %d\n",
 403                        dev->core->name, dev->pci->irq);
 404                 return err;
 405         }
 406         cx_set(MO_PCI_INTMSK, core->pci_irqmask);
 407
 408         /* everything worked */
 409         pci_set_drvdata(dev->pci,dev);
 410         return 0;
 411 }
 412
 413 void cx8802_fini_common(struct cx8802_dev *dev)
 414 {
 415         dprintk( 2, "cx8802_fini_common\n" );
 416         cx8802_stop_dma(dev);
 417         pci_disable_device(dev->pci);
 418
 419         /* unregister stuff */
 420         free_irq(dev->pci->irq, dev);
 421         pci_set_drvdata(dev->pci, NULL);
 422
 423         /* free memory */
 424         btcx_riscmem_free(dev->pci,&dev->mpegq.stopper);
 425 }
 426
 427 /* ----------------------------------------------------------- */
 428
 429 int cx8802_suspend_common(struct pci_dev *pci_dev, pm_message_t state)
 430 {
 431         struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
 432         struct cx88_core *core = dev->core;
 433
 434         /* stop mpeg dma */
 435         spin_lock(&dev->slock);
 436         if (!list_empty(&dev->mpegq.active)) {
 437                 dprintk( 2, "suspend\n" );
 438                 printk("%s: suspend mpeg\n", core->name);
 439                 cx8802_stop_dma(dev);
 440                 del_timer(&dev->mpegq.timeout);
 441         }
 442         spin_unlock(&dev->slock);
 443
 444 #if 1
 445         /* FIXME -- shutdown device */
 446         cx88_shutdown(dev->core);
 447 #endif
 448
 449         pci_save_state(pci_dev);
 450         if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) {
 451                 pci_disable_device(pci_dev);
 452                 dev->state.disabled = 1;
 453         }
 454         return 0;
 455 }
 456
 457 int cx8802_resume_common(struct pci_dev *pci_dev)
 458 {
 459         struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
 460         struct cx88_core *core = dev->core;
 461
 462         if (dev->state.disabled) {
 463                 pci_enable_device(pci_dev);
 464                 dev->state.disabled = 0;
 465         }
 466         pci_set_power_state(pci_dev, PCI_D0);
 467         pci_restore_state(pci_dev);
 468
 469 #if 1
 470         /* FIXME: re-initialize hardware */
 471         cx88_reset(dev->core);
 472 #endif
 473
 474         /* restart video+vbi capture */
 475         spin_lock(&dev->slock);
 476         if (!list_empty(&dev->mpegq.active)) {
 477                 printk("%s: resume mpeg\n", core->name);
 478                 cx8802_restart_queue(dev,&dev->mpegq);
 479         }
 480         spin_unlock(&dev->slock);
 481
 482         return 0;
 483 }
 484
 485 /* ----------------------------------------------------------- */
 486
 487 EXPORT_SYMBOL(cx8802_buf_prepare);
 488 EXPORT_SYMBOL(cx8802_buf_queue);
 489 EXPORT_SYMBOL(cx8802_cancel_buffers);
 490
 491 EXPORT_SYMBOL(cx8802_init_common);
 492 EXPORT_SYMBOL(cx8802_fini_common);
 493
 494 EXPORT_SYMBOL(cx8802_suspend_common);
 495 EXPORT_SYMBOL(cx8802_resume_common);
 496
 497 /* ----------------------------------------------------------- */
 498 /*
 499  * Local variables:
 500  * c-basic-offset: 8
 501  * End:
 502  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
 503  */