SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34
  35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
  37 MODULE_LICENSE("GPL");
  38
  39 static unsigned int debug = 0;
  40 module_param(debug,int,0644);
  41 MODULE_PARM_DESC(debug,"enable debug messages");
  42
  43 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  44 module_param_array(card,  int, NULL, 0444);
  45 MODULE_PARM_DESC(card,"card type");
  46
  47 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  48         printk(KERN_DEBUG "%s/0: " fmt, dev->name , ## arg)
  49
  50 static unsigned int cx23885_devcount;
  51
  52 static DEFINE_MUTEX(devlist);
  53 static LIST_HEAD(cx23885_devlist);
  54
  55 #define NO_SYNC_LINE (-1U)
  56
  57 /*
  58  * CX23885 Assumptions
  59  * 1 line = 16 bytes of CDT
  60  * cmds size = 80
  61  * cdt size = 16 * linesize
  62  * iqsize = 64
  63  * maxlines = 6
  64  *
  65  * Address Space:
  66  * 0x00000000 0x00008fff FIFO clusters
  67  * 0x00010000 0x000104af Channel Management Data Structures
  68  * 0x000104b0 0x000104ff Free
  69  * 0x00010500 0x000108bf 15 channels * iqsize
  70  * 0x000108c0 0x000108ff Free
  71  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  72  *                       15 channels * (iqsize + (maxlines * linesize))
  73  * 0x00010ea0 0x00010xxx Free
  74  */
  75
  76 struct sram_channel cx23885_sram_channels[] = {
  77         [SRAM_CH01] = {
  78                 .name           = "test ch1",
  79                 .cmds_start     = 0x10000,
  80                 .ctrl_start     = 0x10500,
  81                 .cdt            = 0x10900,
  82                 .fifo_start     = 0x3000,
  83                 .fifo_size      = 0x1000,
  84                 .ptr1_reg       = DMA1_PTR1,
  85                 .ptr2_reg       = DMA1_PTR2,
  86                 .cnt1_reg       = DMA1_CNT1,
  87                 .cnt2_reg       = DMA1_CNT2,
  88                 .jumponly       = 1,
  89         },
  90         [SRAM_CH02] = {
  91                 .name           = "ch2",
  92                 .cmds_start     = 0x0,
  93                 .ctrl_start     = 0x0,
  94                 .cdt            = 0x0,
  95                 .fifo_start     = 0x0,
  96                 .fifo_size      = 0x0,
  97                 .ptr1_reg       = DMA2_PTR1,
  98                 .ptr2_reg       = DMA2_PTR2,
  99                 .cnt1_reg       = DMA2_CNT1,
 100                 .cnt2_reg       = DMA2_CNT2,
 101         },
 102         [SRAM_CH03] = {
 103                 .name           = "TS1 B",
 104                 .cmds_start     = 0x100A0,
 105                 .ctrl_start     = 0x10780,
 106                 .cdt            = 0x10400,
 107                 .fifo_start     = 0x5000,
 108                 .fifo_size      = 0x1000,
 109                 .ptr1_reg       = DMA3_PTR1,
 110                 .ptr2_reg       = DMA3_PTR2,
 111                 .cnt1_reg       = DMA3_CNT1,
 112                 .cnt2_reg       = DMA3_CNT2,
 113         },
 114         [SRAM_CH04] = {
 115                 .name           = "ch4",
 116                 .cmds_start     = 0x0,
 117                 .ctrl_start     = 0x0,
 118                 .cdt            = 0x0,
 119                 .fifo_start     = 0x0,
 120                 .fifo_size      = 0x0,
 121                 .ptr1_reg       = DMA4_PTR1,
 122                 .ptr2_reg       = DMA4_PTR2,
 123                 .cnt1_reg       = DMA4_CNT1,
 124                 .cnt2_reg       = DMA4_CNT2,
 125         },
 126         [SRAM_CH05] = {
 127                 .name           = "ch5",
 128                 .cmds_start     = 0x0,
 129                 .ctrl_start     = 0x0,
 130                 .cdt            = 0x0,
 131                 .fifo_start     = 0x0,
 132                 .fifo_size      = 0x0,
 133                 .ptr1_reg       = DMA5_PTR1,
 134                 .ptr2_reg       = DMA5_PTR2,
 135                 .cnt1_reg       = DMA5_CNT1,
 136                 .cnt2_reg       = DMA5_CNT2,
 137         },
 138         [SRAM_CH06] = {
 139                 .name           = "TS2 C",
 140                 .cmds_start     = 0x10140,
 141                 .ctrl_start     = 0x10680,
 142                 .cdt            = 0x10480,
 143                 .fifo_start     = 0x6000,
 144                 .fifo_size      = 0x1000,
 145                 .ptr1_reg       = DMA5_PTR1,
 146                 .ptr2_reg       = DMA5_PTR2,
 147                 .cnt1_reg       = DMA5_CNT1,
 148                 .cnt2_reg       = DMA5_CNT2,
 149         },
 150         [SRAM_CH07] = {
 151                 .name           = "ch7",
 152                 .cmds_start     = 0x0,
 153                 .ctrl_start     = 0x0,
 154                 .cdt            = 0x0,
 155                 .fifo_start     = 0x0,
 156                 .fifo_size      = 0x0,
 157                 .ptr1_reg       = DMA6_PTR1,
 158                 .ptr2_reg       = DMA6_PTR2,
 159                 .cnt1_reg       = DMA6_CNT1,
 160                 .cnt2_reg       = DMA6_CNT2,
 161         },
 162         [SRAM_CH08] = {
 163                 .name           = "ch8",
 164                 .cmds_start     = 0x0,
 165                 .ctrl_start     = 0x0,
 166                 .cdt            = 0x0,
 167                 .fifo_start     = 0x0,
 168                 .fifo_size      = 0x0,
 169                 .ptr1_reg       = DMA7_PTR1,
 170                 .ptr2_reg       = DMA7_PTR2,
 171                 .cnt1_reg       = DMA7_CNT1,
 172                 .cnt2_reg       = DMA7_CNT2,
 173         },
 174         [SRAM_CH09] = {
 175                 .name           = "ch9",
 176                 .cmds_start     = 0x0,
 177                 .ctrl_start     = 0x0,
 178                 .cdt            = 0x0,
 179                 .fifo_start     = 0x0,
 180                 .fifo_size      = 0x0,
 181                 .ptr1_reg       = DMA8_PTR1,
 182                 .ptr2_reg       = DMA8_PTR2,
 183                 .cnt1_reg       = DMA8_CNT1,
 184                 .cnt2_reg       = DMA8_CNT2,
 185         },
 186 };
 187
 188 /* FIXME, these allocations will change when
 189  * analog arrives. The be reviewed.
 190  * CX23887 Assumptions
 191  * 1 line = 16 bytes of CDT
 192  * cmds size = 80
 193  * cdt size = 16 * linesize
 194  * iqsize = 64
 195  * maxlines = 6
 196  *
 197  * Address Space:
 198  * 0x00000000 0x00008fff FIFO clusters
 199  * 0x00010000 0x000104af Channel Management Data Structures
 200  * 0x000104b0 0x000104ff Free
 201  * 0x00010500 0x000108bf 15 channels * iqsize
 202  * 0x000108c0 0x000108ff Free
 203  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
 204  *                       15 channels * (iqsize + (maxlines * linesize))
 205  * 0x00010ea0 0x00010xxx Free
 206  */
 207
 208 struct sram_channel cx23887_sram_channels[] = {
 209         [SRAM_CH01] = {
 210                 .name           = "test ch1",
 211                 .cmds_start     = 0x0,
 212                 .ctrl_start     = 0x0,
 213                 .cdt            = 0x0,
 214                 .fifo_start     = 0x0,
 215                 .fifo_size      = 0x0,
 216                 .ptr1_reg       = DMA1_PTR1,
 217                 .ptr2_reg       = DMA1_PTR2,
 218                 .cnt1_reg       = DMA1_CNT1,
 219                 .cnt2_reg       = DMA1_CNT2,
 220         },
 221         [SRAM_CH02] = {
 222                 .name           = "ch2",
 223                 .cmds_start     = 0x0,
 224                 .ctrl_start     = 0x0,
 225                 .cdt            = 0x0,
 226                 .fifo_start     = 0x0,
 227                 .fifo_size      = 0x0,
 228                 .ptr1_reg       = DMA2_PTR1,
 229                 .ptr2_reg       = DMA2_PTR2,
 230                 .cnt1_reg       = DMA2_CNT1,
 231                 .cnt2_reg       = DMA2_CNT2,
 232         },
 233         [SRAM_CH03] = {
 234                 .name           = "ch3",
 235                 .cmds_start     = 0x0,
 236                 .ctrl_start     = 0x0,
 237                 .cdt            = 0x0,
 238                 .fifo_start     = 0x0,
 239                 .fifo_size      = 0x0,
 240                 .ptr1_reg       = DMA3_PTR1,
 241                 .ptr2_reg       = DMA3_PTR2,
 242                 .cnt1_reg       = DMA3_CNT1,
 243                 .cnt2_reg       = DMA3_CNT2,
 244         },
 245         [SRAM_CH04] = {
 246                 .name           = "ch4",
 247                 .cmds_start     = 0x0,
 248                 .ctrl_start     = 0x0,
 249                 .cdt            = 0x0,
 250                 .fifo_start     = 0x0,
 251                 .fifo_size      = 0x0,
 252                 .ptr1_reg       = DMA4_PTR1,
 253                 .ptr2_reg       = DMA4_PTR2,
 254                 .cnt1_reg       = DMA4_CNT1,
 255                 .cnt2_reg       = DMA4_CNT2,
 256         },
 257         [SRAM_CH05] = {
 258                 .name           = "ch5",
 259                 .cmds_start     = 0x0,
 260                 .ctrl_start     = 0x0,
 261                 .cdt            = 0x0,
 262                 .fifo_start     = 0x0,
 263                 .fifo_size      = 0x0,
 264                 .ptr1_reg       = DMA5_PTR1,
 265                 .ptr2_reg       = DMA5_PTR2,
 266                 .cnt1_reg       = DMA5_CNT1,
 267                 .cnt2_reg       = DMA5_CNT2,
 268         },
 269         [SRAM_CH06] = {
 270                 .name           = "TS2 C",
 271                 .cmds_start     = 0x10140,
 272                 .ctrl_start     = 0x10680,
 273                 .cdt            = 0x108d0,
 274                 .fifo_start     = 0x6000,
 275                 .fifo_size      = 0x1000,
 276                 .ptr1_reg       = DMA5_PTR1,
 277                 .ptr2_reg       = DMA5_PTR2,
 278                 .cnt1_reg       = DMA5_CNT1,
 279                 .cnt2_reg       = DMA5_CNT2,
 280         },
 281         [SRAM_CH07] = {
 282                 .name           = "ch7",
 283                 .cmds_start     = 0x0,
 284                 .ctrl_start     = 0x0,
 285                 .cdt            = 0x0,
 286                 .fifo_start     = 0x0,
 287                 .fifo_size      = 0x0,
 288                 .ptr1_reg       = DMA6_PTR1,
 289                 .ptr2_reg       = DMA6_PTR2,
 290                 .cnt1_reg       = DMA6_CNT1,
 291                 .cnt2_reg       = DMA6_CNT2,
 292         },
 293         [SRAM_CH08] = {
 294                 .name           = "ch8",
 295                 .cmds_start     = 0x0,
 296                 .ctrl_start     = 0x0,
 297                 .cdt            = 0x0,
 298                 .fifo_start     = 0x0,
 299                 .fifo_size      = 0x0,
 300                 .ptr1_reg       = DMA7_PTR1,
 301                 .ptr2_reg       = DMA7_PTR2,
 302                 .cnt1_reg       = DMA7_CNT1,
 303                 .cnt2_reg       = DMA7_CNT2,
 304         },
 305         [SRAM_CH09] = {
 306                 .name           = "ch9",
 307                 .cmds_start     = 0x0,
 308                 .ctrl_start     = 0x0,
 309                 .cdt            = 0x0,
 310                 .fifo_start     = 0x0,
 311                 .fifo_size      = 0x0,
 312                 .ptr1_reg       = DMA8_PTR1,
 313                 .ptr2_reg       = DMA8_PTR2,
 314                 .cnt1_reg       = DMA8_CNT1,
 315                 .cnt2_reg       = DMA8_CNT2,
 316         },
 317 };
 318
 319 static int cx23885_risc_decode(u32 risc)
 320 {
 321         static char *instr[16] = {
 322                 [ RISC_SYNC    >> 28 ] = "sync",
 323                 [ RISC_WRITE   >> 28 ] = "write",
 324                 [ RISC_WRITEC  >> 28 ] = "writec",
 325                 [ RISC_READ    >> 28 ] = "read",
 326                 [ RISC_READC   >> 28 ] = "readc",
 327                 [ RISC_JUMP    >> 28 ] = "jump",
 328                 [ RISC_SKIP    >> 28 ] = "skip",
 329                 [ RISC_WRITERM >> 28 ] = "writerm",
 330                 [ RISC_WRITECM >> 28 ] = "writecm",
 331                 [ RISC_WRITECR >> 28 ] = "writecr",
 332         };
 333         static int incr[16] = {
 334                 [ RISC_WRITE   >> 28 ] = 3,
 335                 [ RISC_JUMP    >> 28 ] = 3,
 336                 [ RISC_SKIP    >> 28 ] = 1,
 337                 [ RISC_SYNC    >> 28 ] = 1,
 338                 [ RISC_WRITERM >> 28 ] = 3,
 339                 [ RISC_WRITECM >> 28 ] = 3,
 340                 [ RISC_WRITECR >> 28 ] = 4,
 341         };
 342         static char *bits[] = {
 343                 "12",   "13",   "14",   "resync",
 344                 "cnt0", "cnt1", "18",   "19",
 345                 "20",   "21",   "22",   "23",
 346                 "irq1", "irq2", "eol",  "sol",
 347         };
 348         int i;
 349
 350         printk("0x%08x [ %s", risc,
 351                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 352         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 353                 if (risc & (1 << (i + 12)))
 354                         printk(" %s", bits[i]);
 355         printk(" count=%d ]\n", risc & 0xfff);
 356         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 357 }
 358
 359 void cx23885_wakeup(struct cx23885_tsport *port,
 360                     struct cx23885_dmaqueue *q, u32 count)
 361 {
 362         struct cx23885_dev *dev = port->dev;
 363         struct cx23885_buffer *buf;
 364         int bc;
 365
 366         for (bc = 0;; bc++) {
 367                 if (list_empty(&q->active))
 368                         break;
 369                 buf = list_entry(q->active.next,
 370                                  struct cx23885_buffer, vb.queue);
 371
 372                 /* count comes from the hw and is is 16bit wide --
 373                  * this trick handles wrap-arounds correctly for
 374                  * up to 32767 buffers in flight... */
 375                 if ((s16) (count - buf->count) < 0)
 376                         break;
 377
 378                 do_gettimeofday(&buf->vb.ts);
 379                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 380                         count, buf->count);
 381                 buf->vb.state = STATE_DONE;
 382                 list_del(&buf->vb.queue);
 383                 wake_up(&buf->vb.done);
 384         }
 385         if (list_empty(&q->active)) {
 386                 del_timer(&q->timeout);
 387         } else {
 388                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 389         }
 390         if (bc != 1)
 391                 printk("%s: %d buffers handled (should be 1)\n",
 392                        __FUNCTION__, bc);
 393 }
 394 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 395                                struct sram_channel *ch);
 396
 397 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 398                                struct sram_channel *ch,
 399                                unsigned int bpl, u32 risc)
 400 {
 401         unsigned int i, lines;
 402         u32 cdt;
 403
 404         if (ch->cmds_start == 0)
 405         {
 406                 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
 407                         ch->name);
 408                 cx_write(ch->ptr1_reg, 0);
 409                 cx_write(ch->ptr2_reg, 0);
 410                 cx_write(ch->cnt2_reg, 0);
 411                 cx_write(ch->cnt1_reg, 0);
 412                 return 0;
 413         } else {
 414                 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
 415                         ch->name);
 416         }
 417
 418         bpl   = (bpl + 7) & ~7; /* alignment */
 419         cdt   = ch->cdt;
 420         lines = ch->fifo_size / bpl;
 421         if (lines > 6)
 422                 lines = 6;
 423         BUG_ON(lines < 2);
 424
 425         cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
 426         cx_write(8 + 4, cpu_to_le32(8) );
 427         cx_write(8 + 8, cpu_to_le32(0) );
 428
 429         /* write CDT */
 430         for (i = 0; i < lines; i++) {
 431                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
 432                         ch->fifo_start + bpl*i);
 433                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 434                 cx_write(cdt + 16*i +  4, 0);
 435                 cx_write(cdt + 16*i +  8, 0);
 436                 cx_write(cdt + 16*i + 12, 0);
 437         }
 438
 439         /* write CMDS */
 440         if (ch->jumponly)
 441                 cx_write(ch->cmds_start +  0, 8);
 442         else
 443                 cx_write(ch->cmds_start +  0, risc);
 444         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 445         cx_write(ch->cmds_start +  8, cdt);
 446         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 447         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 448         if (ch->jumponly)
 449                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
 450         else
 451                 cx_write(ch->cmds_start + 20, 64 >> 2);
 452         for (i = 24; i < 80; i += 4)
 453                 cx_write(ch->cmds_start + i, 0);
 454
 455         /* fill registers */
 456         cx_write(ch->ptr1_reg, ch->fifo_start);
 457         cx_write(ch->ptr2_reg, cdt);
 458         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 459         cx_write(ch->cnt1_reg, (bpl >> 3) -1);
 460
 461         dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 462                 dev->bridge,
 463                 ch->name,
 464                 bpl,
 465                 lines);
 466
 467         return 0;
 468 }
 469
 470 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 471                                struct sram_channel *ch)
 472 {
 473         static char *name[] = {
 474                 "init risc lo",
 475                 "init risc hi",
 476                 "cdt base",
 477                 "cdt size",
 478                 "iq base",
 479                 "iq size",
 480                 "risc pc lo",
 481                 "risc pc hi",
 482                 "iq wr ptr",
 483                 "iq rd ptr",
 484                 "cdt current",
 485                 "pci target lo",
 486                 "pci target hi",
 487                 "line / byte",
 488         };
 489         u32 risc;
 490         unsigned int i, j, n;
 491
 492         printk("%s: %s - dma channel status dump\n",
 493                dev->name, ch->name);
 494         for (i = 0; i < ARRAY_SIZE(name); i++)
 495                 printk("%s:   cmds: %-15s: 0x%08x\n",
 496                        dev->name, name[i],
 497                        cx_read(ch->cmds_start + 4*i));
 498
 499         for (i = 0; i < 4; i++) {
 500                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 501                 printk("%s:   risc%d: ", dev->name, i);
 502                 cx23885_risc_decode(risc);
 503         }
 504         for (i = 0; i < (64 >> 2); i += n) {
 505                 risc = cx_read(ch->ctrl_start + 4 * i);
 506                 /* No consideration for bits 63-32 */
 507
 508                 printk("%s:   (0x%08x) iq %x: ", dev->name,
 509                        ch->ctrl_start + 4 * i, i);
 510                 n = cx23885_risc_decode(risc);
 511                 for (j = 1; j < n; j++) {
 512                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 513                         printk("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 514                                dev->name, i+j, risc, j);
 515                 }
 516         }
 517
 518         printk("%s: fifo: 0x%08x -> 0x%x\n",
 519                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 520         printk("%s: ctrl: 0x%08x -> 0x%x\n",
 521                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 522         printk("%s:   ptr1_reg: 0x%08x\n",
 523                dev->name, cx_read(ch->ptr1_reg));
 524         printk("%s:   ptr2_reg: 0x%08x\n",
 525                dev->name, cx_read(ch->ptr2_reg));
 526         printk("%s:   cnt1_reg: 0x%08x\n",
 527                dev->name, cx_read(ch->cnt1_reg));
 528         printk("%s:   cnt2_reg: 0x%08x\n",
 529                dev->name, cx_read(ch->cnt2_reg));
 530 }
 531
 532 void cx23885_risc_disasm(struct cx23885_tsport *port,
 533                          struct btcx_riscmem *risc)
 534 {
 535         struct cx23885_dev *dev = port->dev;
 536         unsigned int i, j, n;
 537
 538         printk("%s: risc disasm: %p [dma=0x%08lx]\n",
 539                dev->name, risc->cpu, (unsigned long)risc->dma);
 540         for (i = 0; i < (risc->size >> 2); i += n) {
 541                 printk("%s:   %04d: ", dev->name, i);
 542                 n = cx23885_risc_decode(risc->cpu[i]);
 543                 for (j = 1; j < n; j++)
 544                         printk("%s:   %04d: 0x%08x [ arg #%d ]\n",
 545                                dev->name, i + j, risc->cpu[i + j], j);
 546                 if (risc->cpu[i] == RISC_JUMP)
 547                         break;
 548         }
 549 }
 550
 551 void cx23885_shutdown(struct cx23885_dev *dev)
 552 {
 553         /* disable RISC controller */
 554         cx_write(DEV_CNTRL2, 0);
 555
 556         /* Disable all IR activity */
 557         cx_write(IR_CNTRL_REG, 0);
 558
 559         /* Disable Video A/B activity */
 560         cx_write(VID_A_DMA_CTL, 0);
 561         cx_write(VID_B_DMA_CTL, 0);
 562         cx_write(VID_C_DMA_CTL, 0);
 563
 564         /* Disable Audio activity */
 565         cx_write(AUD_INT_DMA_CTL, 0);
 566         cx_write(AUD_EXT_DMA_CTL, 0);
 567
 568         /* Disable Serial port */
 569         cx_write(UART_CTL, 0);
 570
 571         /* Disable Interrupts */
 572         cx_write(PCI_INT_MSK, 0);
 573         cx_write(VID_A_INT_MSK, 0);
 574         cx_write(VID_B_INT_MSK, 0);
 575         cx_write(VID_C_INT_MSK, 0);
 576         cx_write(AUDIO_INT_INT_MSK, 0);
 577         cx_write(AUDIO_EXT_INT_MSK, 0);
 578
 579 }
 580
 581 void cx23885_reset(struct cx23885_dev *dev)
 582 {
 583         dprintk(1, "%s()\n", __FUNCTION__);
 584
 585         cx23885_shutdown(dev);
 586
 587         cx_write(PCI_INT_STAT, 0xffffffff);
 588         cx_write(VID_A_INT_STAT, 0xffffffff);
 589         cx_write(VID_B_INT_STAT, 0xffffffff);
 590         cx_write(VID_C_INT_STAT, 0xffffffff);
 591         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 592         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 593         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 594
 595         mdelay(100);
 596
 597         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
 598         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
 599         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 188*4, 0);
 600         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
 601         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
 602         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
 603         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH07 ], 128, 0);
 604         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH08 ], 128, 0);
 605         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH09 ], 128, 0);
 606
 607         switch(dev->board) {
 608         case CX23885_BOARD_HAUPPAUGE_HVR1250:
 609                 /* GPIO-0 cx24227 demodulator reset */
 610                 dprintk( 1, "%s() Configuring HVR1250 GPIO's\n", __FUNCTION__);
 611                 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
 612                 break;
 613         case CX23885_BOARD_HAUPPAUGE_HVR1800:
 614                 /* GPIO-0 656_CLK */
 615                 /* GPIO-1 656_D0 */
 616                 /* GPIO-2 8295A Reset */
 617                 /* GPIO-3-10 cx23417 data0-7 */
 618                 /* GPIO-11-14 cx23417 addr0-3 */
 619                 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
 620                 /* GPIO-19 IR_RX */
 621                 dprintk( 1, "%s() Configuring HVR1800 GPIO's\n", __FUNCTION__);
 622                 // FIXME: Analog requires the tuner is brought out of reset
 623                 break;
 624         }
 625 }
 626
 627
 628 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 629 {
 630         dprintk(1, "%s()\n", __FUNCTION__);
 631
 632         /* The cx23885 bridge has a weird bug which causes NMI to be asserted
 633          * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
 634          * occur on the cx23887 bridge.
 635          */
 636         if(dev->bridge == CX23885_BRIDGE_885)
 637                 cx_clear(RDR_TLCTL0, 1 << 4);
 638
 639         return 0;
 640 }
 641
 642 static int get_resources(struct cx23885_dev *dev)
 643 {
 644         if (request_mem_region(pci_resource_start(dev->pci,0),
 645                                pci_resource_len(dev->pci,0),
 646                                dev->name))
 647                 return 0;
 648
 649         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 650                 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
 651
 652         return -EBUSY;
 653 }
 654
 655 static void cx23885_timeout(unsigned long data);
 656 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 657                          u32 reg, u32 mask, u32 value);
 658
 659 static int cx23885_ir_init(struct cx23885_dev *dev)
 660 {
 661         dprintk(1, "%s()\n", __FUNCTION__);
 662
 663         switch (dev->board) {
 664         case CX23885_BOARD_HAUPPAUGE_HVR1250:
 665         case CX23885_BOARD_HAUPPAUGE_HVR1800:
 666                 dprintk(1, "%s() FIXME - Implement IR support\n", __FUNCTION__);
 667                 break;
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int cx23885_dev_setup(struct cx23885_dev *dev)
 674 {
 675         int i;
 676
 677         mutex_init(&dev->lock);
 678
 679         atomic_inc(&dev->refcount);
 680
 681         dev->nr = cx23885_devcount++;
 682         sprintf(dev->name, "cx23885[%d]", dev->nr);
 683
 684         mutex_lock(&devlist);
 685         list_add_tail(&dev->devlist, &cx23885_devlist);
 686         mutex_unlock(&devlist);
 687
 688         /* Configure the internal memory */
 689         if(dev->pci->device == 0x8880) {
 690                 dev->bridge = CX23885_BRIDGE_887;
 691                 dev->sram_channels = cx23887_sram_channels;
 692         } else
 693         if(dev->pci->device == 0x8852) {
 694                 dev->bridge = CX23885_BRIDGE_885;
 695                 dev->sram_channels = cx23885_sram_channels;
 696         } else
 697                 BUG();
 698
 699         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 700                 __FUNCTION__, dev->bridge);
 701
 702         /* board config */
 703         dev->board = UNSET;
 704         if (card[dev->nr] < cx23885_bcount)
 705                 dev->board = card[dev->nr];
 706         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 707                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 708                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 709                         dev->board = cx23885_subids[i].card;
 710         if (UNSET == dev->board) {
 711                 dev->board = CX23885_BOARD_UNKNOWN;
 712                 cx23885_card_list(dev);
 713         }
 714
 715         dev->pci_bus  = dev->pci->bus->number;
 716         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 717         dev->pci_irqmask = 0x001f00;
 718
 719         /* External Master 1 Bus */
 720         dev->i2c_bus[0].nr = 0;
 721         dev->i2c_bus[0].dev = dev;
 722         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 723         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 724         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 725         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 726         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 727         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 728
 729         /* External Master 2 Bus */
 730         dev->i2c_bus[1].nr = 1;
 731         dev->i2c_bus[1].dev = dev;
 732         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 733         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 734         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 735         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 736         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 737         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 738
 739         /* Internal Master 3 Bus */
 740         dev->i2c_bus[2].nr = 2;
 741         dev->i2c_bus[2].dev = dev;
 742         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 743         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 744         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 745         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 746         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 747         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 748
 749         /* Transport bus init dma queue */
 750         spin_lock_init(&dev->ts2.slock);
 751         dev->ts2.dev = dev;
 752         dev->ts2.nr = 2;
 753
 754         INIT_LIST_HEAD(&dev->ts2.mpegq.active);
 755         INIT_LIST_HEAD(&dev->ts2.mpegq.queued);
 756         dev->ts2.mpegq.timeout.function = cx23885_timeout;
 757         dev->ts2.mpegq.timeout.data     = (unsigned long)&dev->ts2;
 758         init_timer(&dev->ts2.mpegq.timeout);
 759
 760         if (get_resources(dev) < 0) {
 761                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 762                        "subsystem: %04x:%04x\n",
 763                        dev->name, dev->pci->subsystem_vendor,
 764                        dev->pci->subsystem_device);
 765
 766                 cx23885_devcount--;
 767                 goto fail_free;
 768         }
 769
 770         /* PCIe stuff */
 771         dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
 772                              pci_resource_len(dev->pci,0));
 773
 774         dev->bmmio = (u8 __iomem *)dev->lmmio;
 775
 776         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 777                dev->name, dev->pci->subsystem_vendor,
 778                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 779                dev->board, card[dev->nr] == dev->board ?
 780                "insmod option" : "autodetected");
 781
 782         cx23885_pci_quirks(dev);
 783
 784         /* init hardware */
 785         cx23885_reset(dev);
 786
 787         cx23885_i2c_register(&dev->i2c_bus[0]);
 788         cx23885_i2c_register(&dev->i2c_bus[1]);
 789         cx23885_i2c_register(&dev->i2c_bus[2]);
 790         cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
 791
 792         cx23885_card_setup(dev);
 793         cx23885_ir_init(dev);
 794
 795         switch (dev->board) {
 796         case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
 797                 dev->ts2.reg_gpcnt          = VID_B_GPCNT;
 798                 dev->ts2.reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
 799                 dev->ts2.reg_dma_ctl        = VID_B_DMA_CTL;
 800                 dev->ts2.reg_lngth          = VID_B_LNGTH;
 801                 dev->ts2.reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
 802                 dev->ts2.reg_gen_ctrl       = VID_B_GEN_CTL;
 803                 dev->ts2.reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
 804                 dev->ts2.reg_sop_status     = VID_B_SOP_STATUS;
 805                 dev->ts2.reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
 806                 dev->ts2.reg_vld_misc       = VID_B_VLD_MISC;
 807                 dev->ts2.reg_ts_clk_en      = VID_B_TS_CLK_EN;
 808                 dev->ts2.reg_ts_int_msk     = VID_B_INT_MSK;
 809                 dev->ts2.reg_src_sel        = VID_B_SRC_SEL;
 810
 811                 // FIXME: Make this board specific
 812                 dev->ts2.pci_irqmask = 0x02; /* TS Port 2 bit */
 813                 dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
 814                 dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
 815                 dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
 816                 dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
 817                 dev->ts2.src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
 818
 819                 // Drive this from cards.c (portb/c) and move it outside of this switch
 820                 dev->ts2.sram_chno = SRAM_CH03;
 821                 break;
 822         default:
 823                 dev->ts2.reg_gpcnt          = VID_C_GPCNT;
 824                 dev->ts2.reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
 825                 dev->ts2.reg_dma_ctl        = VID_C_DMA_CTL;
 826                 dev->ts2.reg_lngth          = VID_C_LNGTH;
 827                 dev->ts2.reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
 828                 dev->ts2.reg_gen_ctrl       = VID_C_GEN_CTL;
 829                 dev->ts2.reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
 830                 dev->ts2.reg_sop_status     = VID_C_SOP_STATUS;
 831                 dev->ts2.reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 832                 dev->ts2.reg_vld_misc       = VID_C_VLD_MISC;
 833                 dev->ts2.reg_ts_clk_en      = VID_C_TS_CLK_EN;
 834                 dev->ts2.reg_ts_int_msk     = VID_C_INT_MSK;
 835                 dev->ts2.reg_src_sel        = 0;
 836
 837                 // FIXME: Make this board specific
 838                 dev->ts2.pci_irqmask = 0x04; /* TS Port 2 bit */
 839                 dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
 840                 dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
 841                 dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
 842                 dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
 843                 dev->ts2.src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
 844
 845                 // Drive this from cards.c (portb/c) and move it outside of this switch
 846                 dev->ts2.sram_chno = SRAM_CH06;
 847         }
 848
 849         cx23885_risc_stopper(dev->pci, &dev->ts2.mpegq.stopper,
 850                              dev->ts2.reg_dma_ctl, dev->ts2.dma_ctl_val, 0x00);
 851
 852         // FIXME: This should only be called if ts2 is being used, driven by cards.c
 853         if (cx23885_dvb_register(&dev->ts2) < 0) {
 854                 printk(KERN_ERR "%s() Failed to register dvb adapters\n",
 855                        __FUNCTION__);
 856         }
 857
 858         return 0;
 859
 860 fail_free:
 861         kfree(dev);
 862         return -ENODEV;
 863 }
 864
 865 void cx23885_dev_unregister(struct cx23885_dev *dev)
 866 {
 867         release_mem_region(pci_resource_start(dev->pci,0),
 868                            pci_resource_len(dev->pci,0));
 869
 870         if (!atomic_dec_and_test(&dev->refcount))
 871                 return;
 872
 873         cx23885_dvb_unregister(&dev->ts2);
 874         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 875         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 876         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 877
 878         iounmap(dev->lmmio);
 879 }
 880
 881 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
 882                                unsigned int offset, u32 sync_line,
 883                                unsigned int bpl, unsigned int padding,
 884                                unsigned int lines)
 885 {
 886         struct scatterlist *sg;
 887         unsigned int line, todo;
 888
 889         /* sync instruction */
 890         if (sync_line != NO_SYNC_LINE)
 891                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 892
 893         /* scan lines */
 894         sg = sglist;
 895         for (line = 0; line < lines; line++) {
 896                 while (offset && offset >= sg_dma_len(sg)) {
 897                         offset -= sg_dma_len(sg);
 898                         sg++;
 899                 }
 900                 if (bpl <= sg_dma_len(sg)-offset) {
 901                         /* fits into current chunk */
 902                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
 903                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 904                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 905                         offset+=bpl;
 906                 } else {
 907                         /* scanline needs to be split */
 908                         todo = bpl;
 909                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
 910                                             (sg_dma_len(sg)-offset));
 911                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 912                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 913                         todo -= (sg_dma_len(sg)-offset);
 914                         offset = 0;
 915                         sg++;
 916                         while (todo > sg_dma_len(sg)) {
 917                                 *(rp++)=cpu_to_le32(RISC_WRITE|
 918                                                     sg_dma_len(sg));
 919                                 *(rp++)=cpu_to_le32(sg_dma_address(sg));
 920                                 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 921                                 todo -= sg_dma_len(sg);
 922                                 sg++;
 923                         }
 924                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
 925                         *(rp++)=cpu_to_le32(sg_dma_address(sg));
 926                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 927                         offset += todo;
 928                 }
 929                 offset += padding;
 930         }
 931
 932         return rp;
 933 }
 934
 935 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 936                         struct scatterlist *sglist, unsigned int top_offset,
 937                         unsigned int bottom_offset, unsigned int bpl,
 938                         unsigned int padding, unsigned int lines)
 939 {
 940         u32 instructions, fields;
 941         u32 *rp;
 942         int rc;
 943
 944         fields = 0;
 945         if (UNSET != top_offset)
 946                 fields++;
 947         if (UNSET != bottom_offset)
 948                 fields++;
 949
 950         /* estimate risc mem: worst case is one write per page border +
 951            one write per scan line + syncs + jump (all 2 dwords).  Padding
 952            can cause next bpl to start close to a page border.  First DMA
 953            region may be smaller than PAGE_SIZE */
 954         /* write and jump need and extra dword */
 955         instructions  = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
 956         instructions += 2;
 957         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 958                 return rc;
 959
 960         /* write risc instructions */
 961         rp = risc->cpu;
 962         if (UNSET != top_offset)
 963                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
 964                                         bpl, padding, lines);
 965         if (UNSET != bottom_offset)
 966                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
 967                                         bpl, padding, lines);
 968
 969         /* save pointer to jmp instruction address */
 970         risc->jmp = rp;
 971         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 972         return 0;
 973 }
 974
 975 int cx23885_risc_databuffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 976                             struct scatterlist *sglist, unsigned int bpl,
 977                             unsigned int lines)
 978 {
 979         u32 instructions;
 980         u32 *rp;
 981         int rc;
 982
 983         /* estimate risc mem: worst case is one write per page border +
 984            one write per scan line + syncs + jump (all 2 dwords).  Here
 985            there is no padding and no sync.  First DMA region may be smaller
 986            than PAGE_SIZE */
 987         /* Jump and write need an extra dword */
 988         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
 989         instructions += 1;
 990
 991         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 992                 return rc;
 993
 994         /* write risc instructions */
 995         rp = risc->cpu;
 996         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
 997
 998         /* save pointer to jmp instruction address */
 999         risc->jmp = rp;
1000         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1001         return 0;
1002 }
1003
1004 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1005                          u32 reg, u32 mask, u32 value)
1006 {
1007         u32 *rp;
1008         int rc;
1009
1010         if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
1011                 return rc;
1012
1013         /* write risc instructions */
1014         rp = risc->cpu;
1015         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
1016         *(rp++) = cpu_to_le32(reg);
1017         *(rp++) = cpu_to_le32(value);
1018         *(rp++) = cpu_to_le32(mask);
1019         *(rp++) = cpu_to_le32(RISC_JUMP);
1020         *(rp++) = cpu_to_le32(risc->dma);
1021         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1022         return 0;
1023 }
1024
1025 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1026 {
1027         BUG_ON(in_interrupt());
1028         videobuf_waiton(&buf->vb, 0, 0);
1029         videobuf_dma_unmap(q, &buf->vb.dma);
1030         videobuf_dma_free(&buf->vb.dma);
1031         btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
1032         buf->vb.state = STATE_NEEDS_INIT;
1033 }
1034
1035 static int cx23885_start_dma(struct cx23885_tsport *port,
1036                              struct cx23885_dmaqueue *q,
1037                              struct cx23885_buffer   *buf)
1038 {
1039         struct cx23885_dev *dev = port->dev;
1040
1041         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
1042                 buf->vb.width, buf->vb.height, buf->vb.field);
1043
1044         /* setup fifo + format */
1045         cx23885_sram_channel_setup(dev,
1046                                    &dev->sram_channels[ port->sram_chno ],
1047                                    port->ts_packet_size, buf->risc.dma);
1048         if(debug > 5) {
1049                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1050                 cx23885_risc_disasm(port, &buf->risc);
1051         }
1052
1053         /* write TS length to chip */
1054         cx_write(port->reg_lngth, buf->vb.width);
1055
1056         if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1057                 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1058                 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1059                         __FUNCTION__,
1060                         cx23885_boards[dev->board].portb,
1061                         cx23885_boards[dev->board].portc );
1062                 return -EINVAL;
1063         }
1064
1065         udelay(100);
1066
1067         /* If the port supports SRC SELECT, configure it */
1068         if(port->reg_src_sel)
1069                 cx_write(port->reg_src_sel, port->src_sel_val);
1070
1071         cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1072         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1073         cx_write(port->reg_vld_misc, 0x00);
1074         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1075         udelay(100);
1076
1077         // NOTE: this is 2 (reserved) for portb, does it matter?
1078         /* reset counter to zero */
1079         cx_write(port->reg_gpcnt_ctl, 3);
1080         q->count = 1;
1081
1082         switch(dev->bridge) {
1083         case CX23885_BRIDGE_885:
1084         case CX23885_BRIDGE_887:
1085                 /* enable irqs */
1086                 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1087                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1088                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1089                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1090                 break;
1091         default:
1092                 BUG();
1093         }
1094
1095         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1096
1097         return 0;
1098 }
1099
1100 static int cx23885_stop_dma(struct cx23885_tsport *port)
1101 {
1102         struct cx23885_dev *dev = port->dev;
1103         dprintk(1, "%s()\n", __FUNCTION__);
1104
1105         /* Stop interrupts and DMA */
1106         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1107         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1108
1109         return 0;
1110 }
1111
1112 static int cx23885_restart_queue(struct cx23885_tsport *port,
1113                                 struct cx23885_dmaqueue *q)
1114 {
1115         struct cx23885_dev *dev = port->dev;
1116         struct cx23885_buffer *buf;
1117         struct list_head *item;
1118
1119         dprintk(5, "%s()\n", __FUNCTION__);
1120         if (list_empty(&q->active))
1121         {
1122                 struct cx23885_buffer *prev;
1123                 prev = NULL;
1124
1125                 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1126
1127                 for (;;) {
1128                         if (list_empty(&q->queued))
1129                                 return 0;
1130                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1131                                          vb.queue);
1132                         if (NULL == prev) {
1133                                 list_del(&buf->vb.queue);
1134                                 list_add_tail(&buf->vb.queue, &q->active);
1135                                 cx23885_start_dma(port, q, buf);
1136                                 buf->vb.state = STATE_ACTIVE;
1137                                 buf->count    = q->count++;
1138                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1139                                 dprintk(5, "[%p/%d] restart_queue - first active\n",
1140                                         buf, buf->vb.i);
1141
1142                         } else if (prev->vb.width  == buf->vb.width  &&
1143                                    prev->vb.height == buf->vb.height &&
1144                                    prev->fmt       == buf->fmt) {
1145                                 list_del(&buf->vb.queue);
1146                                 list_add_tail(&buf->vb.queue, &q->active);
1147                                 buf->vb.state = STATE_ACTIVE;
1148                                 buf->count    = q->count++;
1149                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1150                                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1151                                 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1152                                         buf, buf->vb.i);
1153                         } else {
1154                                 return 0;
1155                         }
1156                         prev = buf;
1157                 }
1158                 return 0;
1159         }
1160
1161         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1162         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1163                 buf, buf->vb.i);
1164         cx23885_start_dma(port, q, buf);
1165         list_for_each(item, &q->active) {
1166                 buf = list_entry(item, struct cx23885_buffer, vb.queue);
1167                 buf->count = q->count++;
1168         }
1169         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1170         return 0;
1171 }
1172
1173 /* ------------------------------------------------------------------ */
1174
1175 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1176                         struct cx23885_buffer *buf, enum v4l2_field field)
1177 {
1178         struct cx23885_dev *dev = port->dev;
1179         int size = port->ts_packet_size * port->ts_packet_count;
1180         int rc;
1181
1182         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1183         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1184                 return -EINVAL;
1185
1186         if (STATE_NEEDS_INIT == buf->vb.state) {
1187                 buf->vb.width  = port->ts_packet_size;
1188                 buf->vb.height = port->ts_packet_count;
1189                 buf->vb.size   = size;
1190                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1191
1192                 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1193                         goto fail;
1194                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1195                                      buf->vb.dma.sglist,
1196                                      buf->vb.width, buf->vb.height);
1197         }
1198         buf->vb.state = STATE_PREPARED;
1199         return 0;
1200
1201  fail:
1202         cx23885_free_buffer(q, buf);
1203         return rc;
1204 }
1205
1206 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1207 {
1208         struct cx23885_buffer    *prev;
1209         struct cx23885_dev *dev = port->dev;
1210         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1211
1212         /* add jump to stopper */
1213         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1214         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1215         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1216
1217         if (list_empty(&cx88q->active)) {
1218                 dprintk( 1, "queue is empty - first active\n" );
1219                 list_add_tail(&buf->vb.queue, &cx88q->active);
1220                 cx23885_start_dma(port, cx88q, buf);
1221                 buf->vb.state = STATE_ACTIVE;
1222                 buf->count    = cx88q->count++;
1223                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1224                 dprintk(1, "[%p/%d] %s - first active\n",
1225                         buf, buf->vb.i, __FUNCTION__);
1226         } else {
1227                 dprintk( 1, "queue is not empty - append to active\n" );
1228                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1229                                   vb.queue);
1230                 list_add_tail(&buf->vb.queue, &cx88q->active);
1231                 buf->vb.state = STATE_ACTIVE;
1232                 buf->count    = cx88q->count++;
1233                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1234                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1235                 dprintk( 1, "[%p/%d] %s - append to active\n",
1236                          buf, buf->vb.i, __FUNCTION__);
1237         }
1238 }
1239
1240 /* ----------------------------------------------------------- */
1241
1242 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1243                               int restart)
1244 {
1245         struct cx23885_dev *dev = port->dev;
1246         struct cx23885_dmaqueue *q = &port->mpegq;
1247         struct cx23885_buffer *buf;
1248         unsigned long flags;
1249
1250         spin_lock_irqsave(&port->slock, flags);
1251         while (!list_empty(&q->active)) {
1252                 buf = list_entry(q->active.next, struct cx23885_buffer,
1253                                  vb.queue);
1254                 list_del(&buf->vb.queue);
1255                 buf->vb.state = STATE_ERROR;
1256                 wake_up(&buf->vb.done);
1257                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1258                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1259         }
1260         if (restart) {
1261                 dprintk(1, "restarting queue\n" );
1262                 cx23885_restart_queue(port, q);
1263         }
1264         spin_unlock_irqrestore(&port->slock, flags);
1265 }
1266
1267 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1268 {
1269         struct cx23885_dev *dev = port->dev;
1270         struct cx23885_dmaqueue *q = &port->mpegq;
1271
1272         dprintk(1, "%s()\n", __FUNCTION__);
1273         del_timer_sync(&q->timeout);
1274         cx23885_stop_dma(port);
1275         do_cancel_buffers(port, "cancel", 0);
1276 }
1277
1278 static void cx23885_timeout(unsigned long data)
1279 {
1280         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1281         struct cx23885_dev *dev = port->dev;
1282
1283         dprintk(1, "%s()\n",__FUNCTION__);
1284
1285         if (debug > 5)
1286                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1287
1288         cx23885_stop_dma(port);
1289         do_cancel_buffers(port, "timeout", 1);
1290 }
1291
1292 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1293 {
1294         struct cx23885_dev *dev = dev_id;
1295         struct cx23885_tsport *port = &dev->ts2;
1296         u32 pci_status, pci_mask;
1297         u32 ts1_status, ts1_mask;
1298         u32 ts2_status, ts2_mask;
1299         int count = 0, handled = 0;
1300
1301         pci_status = cx_read(PCI_INT_STAT);
1302         pci_mask = cx_read(PCI_INT_MSK);
1303         ts1_status = cx_read(VID_B_INT_STAT);
1304         ts1_mask = cx_read(VID_B_INT_MSK);
1305         ts2_status = cx_read(VID_C_INT_STAT);
1306         ts2_mask = cx_read(VID_C_INT_MSK);
1307
1308         if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
1309                 goto out;
1310
1311         count = cx_read(port->reg_gpcnt);
1312         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n", pci_status, pci_mask );
1313         dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n", ts1_status, ts1_mask, count );
1314         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, count );
1315
1316         if ( (pci_status & PCI_MSK_RISC_RD) ||
1317              (pci_status & PCI_MSK_RISC_WR) ||
1318              (pci_status & PCI_MSK_AL_RD) ||
1319              (pci_status & PCI_MSK_AL_WR) ||
1320              (pci_status & PCI_MSK_APB_DMA) ||
1321              (pci_status & PCI_MSK_VID_C) ||
1322              (pci_status & PCI_MSK_VID_B) ||
1323              (pci_status & PCI_MSK_VID_A) ||
1324              (pci_status & PCI_MSK_AUD_INT) ||
1325              (pci_status & PCI_MSK_AUD_EXT) )
1326         {
1327
1328                 if (pci_status & PCI_MSK_RISC_RD)
1329                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n", PCI_MSK_RISC_RD);
1330                 if (pci_status & PCI_MSK_RISC_WR)
1331                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n", PCI_MSK_RISC_WR);
1332                 if (pci_status & PCI_MSK_AL_RD)
1333                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n", PCI_MSK_AL_RD);
1334                 if (pci_status & PCI_MSK_AL_WR)
1335                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n", PCI_MSK_AL_WR);
1336                 if (pci_status & PCI_MSK_APB_DMA)
1337                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n", PCI_MSK_APB_DMA);
1338                 if (pci_status & PCI_MSK_VID_C)
1339                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n", PCI_MSK_VID_C);
1340                 if (pci_status & PCI_MSK_VID_B)
1341                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n", PCI_MSK_VID_B);
1342                 if (pci_status & PCI_MSK_VID_A)
1343                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n", PCI_MSK_VID_A);
1344                 if (pci_status & PCI_MSK_AUD_INT)
1345                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n", PCI_MSK_AUD_INT);
1346                 if (pci_status & PCI_MSK_AUD_EXT)
1347                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n", PCI_MSK_AUD_EXT);
1348
1349         }
1350
1351         if ( (ts1_status & VID_B_MSK_OPC_ERR) ||
1352              (ts1_status & VID_B_MSK_BAD_PKT) ||
1353              (ts1_status & VID_B_MSK_SYNC) ||
1354              (ts1_status & VID_B_MSK_OF))
1355         {
1356                 if (ts1_status & VID_B_MSK_OPC_ERR)
1357                         dprintk(7, " (VID_B_MSK_OPC_ERR 0x%08x)\n", VID_B_MSK_OPC_ERR);
1358                 if (ts1_status & VID_B_MSK_BAD_PKT)
1359                         dprintk(7, " (VID_B_MSK_BAD_PKT 0x%08x)\n", VID_B_MSK_BAD_PKT);
1360                 if (ts1_status & VID_B_MSK_SYNC)
1361                         dprintk(7, " (VID_B_MSK_SYNC    0x%08x)\n", VID_B_MSK_SYNC);
1362                 if (ts1_status & VID_B_MSK_OF)
1363                         dprintk(7, " (VID_B_MSK_OF      0x%08x)\n", VID_B_MSK_OF);
1364
1365                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1366
1367                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1368                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1369
1370         } else if (ts1_status & VID_B_MSK_RISCI1) {
1371
1372                 dprintk(7, " (RISCI1            0x%08x)\n", VID_B_MSK_RISCI1);
1373
1374                 spin_lock(&port->slock);
1375                 count = cx_read(port->reg_gpcnt);
1376                 cx23885_wakeup(port, &port->mpegq, count);
1377                 spin_unlock(&port->slock);
1378
1379         } else if (ts1_status & VID_B_MSK_RISCI2) {
1380
1381                 dprintk(7, " (RISCI2            0x%08x)\n", VID_B_MSK_RISCI2);
1382
1383                 spin_lock(&port->slock);
1384                 cx23885_restart_queue(port, &port->mpegq);
1385                 spin_unlock(&port->slock);
1386
1387         }
1388         if (ts1_status) {
1389                 cx_write(VID_B_INT_STAT, ts1_status);
1390                 handled = 1;
1391         }
1392
1393         if ( (ts2_status & VID_C_MSK_OPC_ERR) ||
1394              (ts2_status & VID_C_MSK_BAD_PKT) ||
1395              (ts2_status & VID_C_MSK_SYNC) ||
1396              (ts2_status & VID_C_MSK_OF))
1397         {
1398                 if (ts2_status & VID_C_MSK_OPC_ERR)
1399                         dprintk(7, " (VID_C_MSK_OPC_ERR 0x%08x)\n", VID_C_MSK_OPC_ERR);
1400                 if (ts2_status & VID_C_MSK_BAD_PKT)
1401                         dprintk(7, " (VID_C_MSK_BAD_PKT 0x%08x)\n", VID_C_MSK_BAD_PKT);
1402                 if (ts2_status & VID_C_MSK_SYNC)
1403                         dprintk(7, " (VID_C_MSK_SYNC    0x%08x)\n", VID_C_MSK_SYNC);
1404                 if (ts2_status & VID_C_MSK_OF)
1405                         dprintk(7, " (VID_C_MSK_OF      0x%08x)\n", VID_C_MSK_OF);
1406
1407                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1408
1409                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1410                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1411
1412         } else if (ts2_status & VID_C_MSK_RISCI1) {
1413
1414                 dprintk(7, " (RISCI1            0x%08x)\n", VID_C_MSK_RISCI1);
1415
1416                 spin_lock(&port->slock);
1417                 count = cx_read(port->reg_gpcnt);
1418                 cx23885_wakeup(port, &port->mpegq, count);
1419                 spin_unlock(&port->slock);
1420
1421         } else if (ts2_status & VID_C_MSK_RISCI2) {
1422
1423                 dprintk(7, " (RISCI2            0x%08x)\n", VID_C_MSK_RISCI2);
1424
1425                 spin_lock(&port->slock);
1426                 cx23885_restart_queue(port, &port->mpegq);
1427                 spin_unlock(&port->slock);
1428
1429         }
1430
1431         if (ts2_status) {
1432                 cx_write(VID_C_INT_STAT, ts2_status);
1433                 handled = 1;
1434         }
1435
1436         if (handled)
1437                 cx_write(PCI_INT_STAT, pci_status);
1438 out:
1439         return IRQ_RETVAL(handled);
1440 }
1441
1442 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1443                                      const struct pci_device_id *pci_id)
1444 {
1445         struct cx23885_dev *dev;
1446         int err;
1447
1448         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1449         if (NULL == dev)
1450                 return -ENOMEM;
1451
1452         /* pci init */
1453         dev->pci = pci_dev;
1454         if (pci_enable_device(pci_dev)) {
1455                 err = -EIO;
1456                 goto fail_free;
1457         }
1458
1459         if (cx23885_dev_setup(dev) < 0) {
1460                 err = -EINVAL;
1461                 goto fail_free;
1462         }
1463
1464         /* print pci info */
1465         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1466         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1467         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1468                "latency: %d, mmio: 0x%llx\n", dev->name,
1469                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1470                dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1471
1472         pci_set_master(pci_dev);
1473         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1474                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1475                 err = -EIO;
1476                 goto fail_irq;
1477         }
1478
1479         err = request_irq(pci_dev->irq, cx23885_irq,
1480                           IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1481         if (err < 0) {
1482                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1483                        dev->name, pci_dev->irq);
1484                 goto fail_irq;
1485         }
1486
1487         pci_set_drvdata(pci_dev, dev);
1488         return 0;
1489
1490 fail_irq:
1491         cx23885_dev_unregister(dev);
1492 fail_free:
1493         kfree(dev);
1494         return err;
1495 }
1496
1497 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1498 {
1499         struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1500
1501         cx23885_shutdown(dev);
1502
1503         pci_disable_device(pci_dev);
1504
1505         /* unregister stuff */
1506         free_irq(pci_dev->irq, dev);
1507         pci_set_drvdata(pci_dev, NULL);
1508
1509         mutex_lock(&devlist);
1510         list_del(&dev->devlist);
1511         mutex_unlock(&devlist);
1512
1513         cx23885_dev_unregister(dev);
1514         kfree(dev);
1515 }
1516
1517 static struct pci_device_id cx23885_pci_tbl[] = {
1518         {
1519                 /* CX23885 */
1520                 .vendor       = 0x14f1,
1521                 .device       = 0x8852,
1522                 .subvendor    = PCI_ANY_ID,
1523                 .subdevice    = PCI_ANY_ID,
1524         },{
1525                 /* CX23887 Rev 2 */
1526                 .vendor       = 0x14f1,
1527                 .device       = 0x8880,
1528                 .subvendor    = PCI_ANY_ID,
1529                 .subdevice    = PCI_ANY_ID,
1530         },{
1531                 /* --- end of list --- */
1532         }
1533 };
1534 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1535
1536 static struct pci_driver cx23885_pci_driver = {
1537         .name     = "cx23885",
1538         .id_table = cx23885_pci_tbl,
1539         .probe    = cx23885_initdev,
1540         .remove   = __devexit_p(cx23885_finidev),
1541         /* TODO */
1542         .suspend  = NULL,
1543         .resume   = NULL,
1544 };
1545
1546 static int cx23885_init(void)
1547 {
1548         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1549                (CX23885_VERSION_CODE >> 16) & 0xff,
1550                (CX23885_VERSION_CODE >>  8) & 0xff,
1551                CX23885_VERSION_CODE & 0xff);
1552 #ifdef SNAPSHOT
1553         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1554                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1555 #endif
1556         return pci_register_driver(&cx23885_pci_driver);
1557 }
1558
1559 static void cx23885_fini(void)
1560 {
1561         pci_unregister_driver(&cx23885_pci_driver);
1562 }
1563
1564 module_init(cx23885_init);
1565 module_exit(cx23885_fini);
1566
1567 /* ----------------------------------------------------------- */
1568 /*
1569  * Local variables:
1570  * c-basic-offset: 8
1571  * End:
1572  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1573  */