SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/cx18/cx18-mailbox.c

   1 /*
   2  *  cx18 mailbox functions
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *  Copyright (C) 2008  Andy Walls <awalls@radix.net>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  20  *  02111-1307  USA
  21  */
  22
  23 #include <stdarg.h>
  24
  25 #include "cx18-driver.h"
  26 #include "cx18-io.h"
  27 #include "cx18-scb.h"
  28 #include "cx18-irq.h"
  29 #include "cx18-mailbox.h"
  30 #include "cx18-queue.h"
  31 #include "cx18-streams.h"
  32
  33 static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
  34
  35 #define API_FAST (1 << 2) /* Short timeout */
  36 #define API_SLOW (1 << 3) /* Additional 300ms timeout */
  37
  38 struct cx18_api_info {
  39         u32 cmd;
  40         u8 flags;               /* Flags, see above */
  41         u8 rpu;                 /* Processing unit */
  42         const char *name;       /* The name of the command */
  43 };
  44
  45 #define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
  46
  47 static const struct cx18_api_info api_info[] = {
  48         /* MPEG encoder API */
  49         API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE,               0),
  50         API_ENTRY(CPU, CX18_EPU_DEBUG,                          0),
  51         API_ENTRY(CPU, CX18_CREATE_TASK,                        0),
  52         API_ENTRY(CPU, CX18_DESTROY_TASK,                       0),
  53         API_ENTRY(CPU, CX18_CPU_CAPTURE_START,                  API_SLOW),
  54         API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP,                   API_SLOW),
  55         API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE,                  0),
  56         API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME,                 0),
  57         API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE,               0),
  58         API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE,         0),
  59         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN,                   0),
  60         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE,                 0),
  61         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION,           0),
  62         API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM,               0),
  63         API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE,        0),
  64         API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING,              0),
  65         API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE,                 0),
  66         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS,           0),
  67         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE,                 0),
  68         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE,                 0),
  69         API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS,            0),
  70         API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM,              API_SLOW),
  71         API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO,            0),
  72         API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT,                  0),
  73         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID,                  0),
  74         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID,                  0),
  75         API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE,              0),
  76         API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE,              0),
  77         API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION,     0),
  78         API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO,               0),
  79         API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME,           0),
  80         API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM,           0),
  81         API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER,      0),
  82         API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS,                    0),
  83         API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK,                 0),
  84         API_ENTRY(CPU, CX18_CPU_DE_SET_MDL,                     API_FAST),
  85         API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL,                 API_SLOW),
  86         API_ENTRY(APU, CX18_APU_START,                          0),
  87         API_ENTRY(APU, CX18_APU_STOP,                           0),
  88         API_ENTRY(APU, CX18_APU_RESETAI,                        0),
  89         API_ENTRY(CPU, CX18_CPU_DEBUG_PEEK32,                   0),
  90         API_ENTRY(0, 0,                                         0),
  91 };
  92
  93 static const struct cx18_api_info *find_api_info(u32 cmd)
  94 {
  95         int i;
  96
  97         for (i = 0; api_info[i].cmd; i++)
  98                 if (api_info[i].cmd == cmd)
  99                         return &api_info[i];
 100         return NULL;
 101 }
 102
 103 /* Call with buf of n*11+1 bytes */
 104 static char *u32arr2hex(u32 data[], int n, char *buf)
 105 {
 106         char *p;
 107         int i;
 108
 109         for (i = 0, p = buf; i < n; i++, p += 11) {
 110                 /* kernel snprintf() appends '\0' always */
 111                 snprintf(p, 12, " %#010x", data[i]);
 112         }
 113         *p = '\0';
 114         return buf;
 115 }
 116
 117 static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
 118 {
 119         char argstr[MAX_MB_ARGUMENTS*11+1];
 120
 121         if (!(cx18_debug & CX18_DBGFLG_API))
 122                 return;
 123
 124         CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
 125                        "\n", name, mb->request, mb->ack, mb->cmd, mb->error,
 126                        u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
 127 }
 128
 129
 130 /*
 131  * Functions that run in a work_queue work handling context
 132  */
 133
 134 static void cx18_mdl_send_to_dvb(struct cx18_stream *s, struct cx18_mdl *mdl)
 135 {
 136         struct cx18_buffer *buf;
 137
 138         if (!s->dvb.enabled || mdl->bytesused == 0)
 139                 return;
 140
 141         /* We ignore mdl and buf readpos accounting here - it doesn't matter */
 142
 143         /* The likely case */
 144         if (list_is_singular(&mdl->buf_list)) {
 145                 buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
 146                                        list);
 147                 if (buf->bytesused)
 148                         dvb_dmx_swfilter(&s->dvb.demux,
 149                                          buf->buf, buf->bytesused);
 150                 return;
 151         }
 152
 153         list_for_each_entry(buf, &mdl->buf_list, list) {
 154                 if (buf->bytesused == 0)
 155                         break;
 156                 dvb_dmx_swfilter(&s->dvb.demux, buf->buf, buf->bytesused);
 157         }
 158 }
 159
 160 static void epu_dma_done(struct cx18 *cx, struct cx18_in_work_order *order)
 161 {
 162         u32 handle, mdl_ack_count, id;
 163         struct cx18_mailbox *mb;
 164         struct cx18_mdl_ack *mdl_ack;
 165         struct cx18_stream *s;
 166         struct cx18_mdl *mdl;
 167         int i;
 168
 169         mb = &order->mb;
 170         handle = mb->args[0];
 171         s = cx18_handle_to_stream(cx, handle);
 172
 173         if (s == NULL) {
 174                 CX18_WARN("Got DMA done notification for unknown/inactive"
 175                           " handle %d, %s mailbox seq no %d\n", handle,
 176                           (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
 177                           "stale" : "good", mb->request);
 178                 return;
 179         }
 180
 181         mdl_ack_count = mb->args[2];
 182         mdl_ack = order->mdl_ack;
 183         for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
 184                 id = mdl_ack->id;
 185                 /*
 186                  * Simple integrity check for processing a stale (and possibly
 187                  * inconsistent mailbox): make sure the MDL id is in the
 188                  * valid range for the stream.
 189                  *
 190                  * We go through the trouble of dealing with stale mailboxes
 191                  * because most of the time, the mailbox data is still valid and
 192                  * unchanged (and in practice the firmware ping-pongs the
 193                  * two mdl_ack buffers so mdl_acks are not stale).
 194                  *
 195                  * There are occasions when we get a half changed mailbox,
 196                  * which this check catches for a handle & id mismatch.  If the
 197                  * handle and id do correspond, the worst case is that we
 198                  * completely lost the old MDL, but pick up the new MDL
 199                  * early (but the new mdl_ack is guaranteed to be good in this
 200                  * case as the firmware wouldn't point us to a new mdl_ack until
 201                  * it's filled in).
 202                  *
 203                  * cx18_queue_get_mdl() will detect the lost MDLs
 204                  * and send them back to q_free for fw rotation eventually.
 205                  */
 206                 if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
 207                     !(id >= s->mdl_base_idx &&
 208                       id < (s->mdl_base_idx + s->buffers))) {
 209                         CX18_WARN("Fell behind! Ignoring stale mailbox with "
 210                                   " inconsistent data. Lost MDL for mailbox "
 211                                   "seq no %d\n", mb->request);
 212                         break;
 213                 }
 214                 mdl = cx18_queue_get_mdl(s, id, mdl_ack->data_used);
 215
 216                 CX18_DEBUG_HI_DMA("DMA DONE for %s (MDL %d)\n", s->name, id);
 217                 if (mdl == NULL) {
 218                         CX18_WARN("Could not find MDL %d for stream %s\n",
 219                                   id, s->name);
 220                         continue;
 221                 }
 222
 223                 CX18_DEBUG_HI_DMA("%s recv bytesused = %d\n",
 224                                   s->name, mdl->bytesused);
 225
 226                 if (s->type != CX18_ENC_STREAM_TYPE_TS) {
 227                         cx18_enqueue(s, mdl, &s->q_full);
 228                         if (s->type == CX18_ENC_STREAM_TYPE_IDX)
 229                                 cx18_stream_rotate_idx_mdls(cx);
 230                 }
 231                 else {
 232                         cx18_mdl_send_to_dvb(s, mdl);
 233                         cx18_enqueue(s, mdl, &s->q_free);
 234                 }
 235         }
 236         /* Put as many MDLs as possible back into fw use */
 237         cx18_stream_load_fw_queue(s);
 238
 239         wake_up(&cx->dma_waitq);
 240         if (s->id != -1)
 241                 wake_up(&s->waitq);
 242 }
 243
 244 static void epu_debug(struct cx18 *cx, struct cx18_in_work_order *order)
 245 {
 246         char *p;
 247         char *str = order->str;
 248
 249         CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
 250         p = strchr(str, '.');
 251         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
 252                 CX18_INFO("FW version: %s\n", p - 1);
 253 }
 254
 255 static void epu_cmd(struct cx18 *cx, struct cx18_in_work_order *order)
 256 {
 257         switch (order->rpu) {
 258         case CPU:
 259         {
 260                 switch (order->mb.cmd) {
 261                 case CX18_EPU_DMA_DONE:
 262                         epu_dma_done(cx, order);
 263                         break;
 264                 case CX18_EPU_DEBUG:
 265                         epu_debug(cx, order);
 266                         break;
 267                 default:
 268                         CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
 269                                   order->mb.cmd);
 270                         break;
 271                 }
 272                 break;
 273         }
 274         case APU:
 275                 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
 276                           order->mb.cmd);
 277                 break;
 278         default:
 279                 break;
 280         }
 281 }
 282
 283 static
 284 void free_in_work_order(struct cx18 *cx, struct cx18_in_work_order *order)
 285 {
 286         atomic_set(&order->pending, 0);
 287 }
 288
 289 void cx18_in_work_handler(struct work_struct *work)
 290 {
 291         struct cx18_in_work_order *order =
 292                         container_of(work, struct cx18_in_work_order, work);
 293         struct cx18 *cx = order->cx;
 294         epu_cmd(cx, order);
 295         free_in_work_order(cx, order);
 296 }
 297
 298
 299 /*
 300  * Functions that run in an interrupt handling context
 301  */
 302
 303 static void mb_ack_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 304 {
 305         struct cx18_mailbox __iomem *ack_mb;
 306         u32 ack_irq, req;
 307
 308         switch (order->rpu) {
 309         case APU:
 310                 ack_irq = IRQ_EPU_TO_APU_ACK;
 311                 ack_mb = &cx->scb->apu2epu_mb;
 312                 break;
 313         case CPU:
 314                 ack_irq = IRQ_EPU_TO_CPU_ACK;
 315                 ack_mb = &cx->scb->cpu2epu_mb;
 316                 break;
 317         default:
 318                 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
 319                           order->rpu, order->mb.cmd);
 320                 return;
 321         }
 322
 323         req = order->mb.request;
 324         /* Don't ack if the RPU has gotten impatient and timed us out */
 325         if (req != cx18_readl(cx, &ack_mb->request) ||
 326             req == cx18_readl(cx, &ack_mb->ack)) {
 327                 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
 328                                 "incoming %s to EPU mailbox (sequence no. %u) "
 329                                 "while processing\n",
 330                                 rpu_str[order->rpu], rpu_str[order->rpu], req);
 331                 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
 332                 return;
 333         }
 334         cx18_writel(cx, req, &ack_mb->ack);
 335         cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
 336         return;
 337 }
 338
 339 static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 340 {
 341         u32 handle, mdl_ack_offset, mdl_ack_count;
 342         struct cx18_mailbox *mb;
 343
 344         mb = &order->mb;
 345         handle = mb->args[0];
 346         mdl_ack_offset = mb->args[1];
 347         mdl_ack_count = mb->args[2];
 348
 349         if (handle == CX18_INVALID_TASK_HANDLE ||
 350             mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
 351                 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
 352                         mb_ack_irq(cx, order);
 353                 return -1;
 354         }
 355
 356         cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
 357                            sizeof(struct cx18_mdl_ack) * mdl_ack_count);
 358
 359         if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
 360                 mb_ack_irq(cx, order);
 361         return 1;
 362 }
 363
 364 static
 365 int epu_debug_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 366 {
 367         u32 str_offset;
 368         char *str = order->str;
 369
 370         str[0] = '\0';
 371         str_offset = order->mb.args[1];
 372         if (str_offset) {
 373                 cx18_setup_page(cx, str_offset);
 374                 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
 375                 str[252] = '\0';
 376                 cx18_setup_page(cx, SCB_OFFSET);
 377         }
 378
 379         if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
 380                 mb_ack_irq(cx, order);
 381
 382         return str_offset ? 1 : 0;
 383 }
 384
 385 static inline
 386 int epu_cmd_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 387 {
 388         int ret = -1;
 389
 390         switch (order->rpu) {
 391         case CPU:
 392         {
 393                 switch (order->mb.cmd) {
 394                 case CX18_EPU_DMA_DONE:
 395                         ret = epu_dma_done_irq(cx, order);
 396                         break;
 397                 case CX18_EPU_DEBUG:
 398                         ret = epu_debug_irq(cx, order);
 399                         break;
 400                 default:
 401                         CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
 402                                   order->mb.cmd);
 403                         break;
 404                 }
 405                 break;
 406         }
 407         case APU:
 408                 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
 409                           order->mb.cmd);
 410                 break;
 411         default:
 412                 break;
 413         }
 414         return ret;
 415 }
 416
 417 static inline
 418 struct cx18_in_work_order *alloc_in_work_order_irq(struct cx18 *cx)
 419 {
 420         int i;
 421         struct cx18_in_work_order *order = NULL;
 422
 423         for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
 424                 /*
 425                  * We only need "pending" atomic to inspect its contents,
 426                  * and need not do a check and set because:
 427                  * 1. Any work handler thread only clears "pending" and only
 428                  * on one, particular work order at a time, per handler thread.
 429                  * 2. "pending" is only set here, and we're serialized because
 430                  * we're called in an IRQ handler context.
 431                  */
 432                 if (atomic_read(&cx->in_work_order[i].pending) == 0) {
 433                         order = &cx->in_work_order[i];
 434                         atomic_set(&order->pending, 1);
 435                         break;
 436                 }
 437         }
 438         return order;
 439 }
 440
 441 void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
 442 {
 443         struct cx18_mailbox __iomem *mb;
 444         struct cx18_mailbox *order_mb;
 445         struct cx18_in_work_order *order;
 446         int submit;
 447
 448         switch (rpu) {
 449         case CPU:
 450                 mb = &cx->scb->cpu2epu_mb;
 451                 break;
 452         case APU:
 453                 mb = &cx->scb->apu2epu_mb;
 454                 break;
 455         default:
 456                 return;
 457         }
 458
 459         order = alloc_in_work_order_irq(cx);
 460         if (order == NULL) {
 461                 CX18_WARN("Unable to find blank work order form to schedule "
 462                           "incoming mailbox command processing\n");
 463                 return;
 464         }
 465
 466         order->flags = 0;
 467         order->rpu = rpu;
 468         order_mb = &order->mb;
 469
 470         /* mb->cmd and mb->args[0] through mb->args[2] */
 471         cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32));
 472         /* mb->request and mb->ack.  N.B. we want to read mb->ack last */
 473         cx18_memcpy_fromio(cx, &order_mb->request, &mb->request,
 474                            2 * sizeof(u32));
 475
 476         if (order_mb->request == order_mb->ack) {
 477                 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
 478                                 "incoming %s to EPU mailbox (sequence no. %u)"
 479                                 "\n",
 480                                 rpu_str[rpu], rpu_str[rpu], order_mb->request);
 481                 if (cx18_debug & CX18_DBGFLG_WARN)
 482                         dump_mb(cx, order_mb, "incoming");
 483                 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
 484         }
 485
 486         /*
 487          * Individual EPU command processing is responsible for ack-ing
 488          * a non-stale mailbox as soon as possible
 489          */
 490         submit = epu_cmd_irq(cx, order);
 491         if (submit > 0) {
 492                 queue_work(cx->in_work_queue, &order->work);
 493         }
 494 }
 495
 496
 497 /*
 498  * Functions called from a non-interrupt, non work_queue context
 499  */
 500
 501 static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
 502 {
 503         const struct cx18_api_info *info = find_api_info(cmd);
 504         u32 state, irq, req, ack, err;
 505         struct cx18_mailbox __iomem *mb;
 506         u32 __iomem *xpu_state;
 507         wait_queue_head_t *waitq;
 508         struct mutex *mb_lock;
 509         unsigned long int t0, timeout, ret;
 510         int i;
 511         char argstr[MAX_MB_ARGUMENTS*11+1];
 512         DEFINE_WAIT(w);
 513
 514         if (info == NULL) {
 515                 CX18_WARN("unknown cmd %x\n", cmd);
 516                 return -EINVAL;
 517         }
 518
 519         if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */
 520                 if (cmd == CX18_CPU_DE_SET_MDL) {
 521                         if (cx18_debug & CX18_DBGFLG_HIGHVOL)
 522                                 CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n",
 523                                                 info->name, cmd,
 524                                                 u32arr2hex(data, args, argstr));
 525                 } else
 526                         CX18_DEBUG_API("%s\tcmd %#010x args%s\n",
 527                                        info->name, cmd,
 528                                        u32arr2hex(data, args, argstr));
 529         }
 530
 531         switch (info->rpu) {
 532         case APU:
 533                 waitq = &cx->mb_apu_waitq;
 534                 mb_lock = &cx->epu2apu_mb_lock;
 535                 irq = IRQ_EPU_TO_APU;
 536                 mb = &cx->scb->epu2apu_mb;
 537                 xpu_state = &cx->scb->apu_state;
 538                 break;
 539         case CPU:
 540                 waitq = &cx->mb_cpu_waitq;
 541                 mb_lock = &cx->epu2cpu_mb_lock;
 542                 irq = IRQ_EPU_TO_CPU;
 543                 mb = &cx->scb->epu2cpu_mb;
 544                 xpu_state = &cx->scb->cpu_state;
 545                 break;
 546         default:
 547                 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
 548                 return -EINVAL;
 549         }
 550
 551         mutex_lock(mb_lock);
 552         /*
 553          * Wait for an in-use mailbox to complete
 554          *
 555          * If the XPU is responding with Ack's, the mailbox shouldn't be in
 556          * a busy state, since we serialize access to it on our end.
 557          *
 558          * If the wait for ack after sending a previous command was interrupted
 559          * by a signal, we may get here and find a busy mailbox.  After waiting,
 560          * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
 561          */
 562         state = cx18_readl(cx, xpu_state);
 563         req = cx18_readl(cx, &mb->request);
 564         timeout = msecs_to_jiffies(10);
 565         ret = wait_event_timeout(*waitq,
 566                                  (ack = cx18_readl(cx, &mb->ack)) == req,
 567                                  timeout);
 568         if (req != ack) {
 569                 /* waited long enough, make the mbox "not busy" from our end */
 570                 cx18_writel(cx, req, &mb->ack);
 571                 CX18_ERR("mbox was found stuck busy when setting up for %s; "
 572                          "clearing busy and trying to proceed\n", info->name);
 573         } else if (ret != timeout)
 574                 CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
 575                                jiffies_to_msecs(timeout-ret));
 576
 577         /* Build the outgoing mailbox */
 578         req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
 579
 580         cx18_writel(cx, cmd, &mb->cmd);
 581         for (i = 0; i < args; i++)
 582                 cx18_writel(cx, data[i], &mb->args[i]);
 583         cx18_writel(cx, 0, &mb->error);
 584         cx18_writel(cx, req, &mb->request);
 585         cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
 586
 587         /*
 588          * Notify the XPU and wait for it to send an Ack back
 589          */
 590         timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
 591
 592         CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
 593                           irq, info->name);
 594
 595         /* So we don't miss the wakeup, prepare to wait before notifying fw */
 596         prepare_to_wait(waitq, &w, TASK_UNINTERRUPTIBLE);
 597         cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
 598
 599         t0 = jiffies;
 600         ack = cx18_readl(cx, &mb->ack);
 601         if (ack != req) {
 602                 schedule_timeout(timeout);
 603                 ret = jiffies - t0;
 604                 ack = cx18_readl(cx, &mb->ack);
 605         } else {
 606                 ret = jiffies - t0;
 607         }
 608
 609         finish_wait(waitq, &w);
 610
 611         if (req != ack) {
 612                 mutex_unlock(mb_lock);
 613                 if (ret >= timeout) {
 614                         /* Timed out */
 615                         CX18_DEBUG_WARN("sending %s timed out waiting %d msecs "
 616                                         "for RPU acknowledgement\n",
 617                                         info->name, jiffies_to_msecs(ret));
 618                 } else {
 619                         CX18_DEBUG_WARN("woken up before mailbox ack was ready "
 620                                         "after submitting %s to RPU.  only "
 621                                         "waited %d msecs on req %u but awakened"
 622                                         " with unmatched ack %u\n",
 623                                         info->name,
 624                                         jiffies_to_msecs(ret),
 625                                         req, ack);
 626                 }
 627                 return -EINVAL;
 628         }
 629
 630         if (ret >= timeout)
 631                 CX18_DEBUG_WARN("failed to be awakened upon RPU acknowledgment "
 632                                 "sending %s; timed out waiting %d msecs\n",
 633                                 info->name, jiffies_to_msecs(ret));
 634         else
 635                 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
 636                                   jiffies_to_msecs(ret), info->name);
 637
 638         /* Collect data returned by the XPU */
 639         for (i = 0; i < MAX_MB_ARGUMENTS; i++)
 640                 data[i] = cx18_readl(cx, &mb->args[i]);
 641         err = cx18_readl(cx, &mb->error);
 642         mutex_unlock(mb_lock);
 643
 644         /*
 645          * Wait for XPU to perform extra actions for the caller in some cases.
 646          * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all MDLs
 647          * back in a burst shortly thereafter
 648          */
 649         if (info->flags & API_SLOW)
 650                 cx18_msleep_timeout(300, 0);
 651
 652         if (err)
 653                 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
 654                                 info->name);
 655         return err ? -EIO : 0;
 656 }
 657
 658 int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
 659 {
 660         return cx18_api_call(cx, cmd, args, data);
 661 }
 662
 663 static int cx18_set_filter_param(struct cx18_stream *s)
 664 {
 665         struct cx18 *cx = s->cx;
 666         u32 mode;
 667         int ret;
 668
 669         mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
 670         ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
 671                         s->handle, 1, mode, cx->spatial_strength);
 672         mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
 673         ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
 674                         s->handle, 0, mode, cx->temporal_strength);
 675         ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
 676                         s->handle, 2, cx->filter_mode >> 2, 0);
 677         return ret;
 678 }
 679
 680 int cx18_api_func(void *priv, u32 cmd, int in, int out,
 681                 u32 data[CX2341X_MBOX_MAX_DATA])
 682 {
 683         struct cx18_api_func_private *api_priv = priv;
 684         struct cx18 *cx = api_priv->cx;
 685         struct cx18_stream *s = api_priv->s;
 686
 687         switch (cmd) {
 688         case CX2341X_ENC_SET_OUTPUT_PORT:
 689                 return 0;
 690         case CX2341X_ENC_SET_FRAME_RATE:
 691                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
 692                                 s->handle, 0, 0, 0, 0, data[0]);
 693         case CX2341X_ENC_SET_FRAME_SIZE:
 694                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
 695                                 s->handle, data[1], data[0]);
 696         case CX2341X_ENC_SET_STREAM_TYPE:
 697                 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
 698                                 s->handle, data[0]);
 699         case CX2341X_ENC_SET_ASPECT_RATIO:
 700                 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
 701                                 s->handle, data[0]);
 702
 703         case CX2341X_ENC_SET_GOP_PROPERTIES:
 704                 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
 705                                 s->handle, data[0], data[1]);
 706         case CX2341X_ENC_SET_GOP_CLOSURE:
 707                 return 0;
 708         case CX2341X_ENC_SET_AUDIO_PROPERTIES:
 709                 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
 710                                 s->handle, data[0]);
 711         case CX2341X_ENC_MUTE_AUDIO:
 712                 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
 713                                 s->handle, data[0]);
 714         case CX2341X_ENC_SET_BIT_RATE:
 715                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
 716                                 s->handle, data[0], data[1], data[2], data[3]);
 717         case CX2341X_ENC_MUTE_VIDEO:
 718                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
 719                                 s->handle, data[0]);
 720         case CX2341X_ENC_SET_FRAME_DROP_RATE:
 721                 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
 722                                 s->handle, data[0]);
 723         case CX2341X_ENC_MISC:
 724                 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
 725                                 s->handle, data[0], data[1], data[2]);
 726         case CX2341X_ENC_SET_DNR_FILTER_MODE:
 727                 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
 728                 return cx18_set_filter_param(s);
 729         case CX2341X_ENC_SET_DNR_FILTER_PROPS:
 730                 cx->spatial_strength = data[0];
 731                 cx->temporal_strength = data[1];
 732                 return cx18_set_filter_param(s);
 733         case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
 734                 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
 735                                 s->handle, data[0], data[1]);
 736         case CX2341X_ENC_SET_CORING_LEVELS:
 737                 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
 738                                 s->handle, data[0], data[1], data[2], data[3]);
 739         }
 740         CX18_WARN("Unknown cmd %x\n", cmd);
 741         return 0;
 742 }
 743
 744 int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
 745                 u32 cmd, int args, ...)
 746 {
 747         va_list ap;
 748         int i;
 749
 750         va_start(ap, args);
 751         for (i = 0; i < args; i++)
 752                 data[i] = va_arg(ap, u32);
 753         va_end(ap);
 754         return cx18_api(cx, cmd, args, data);
 755 }
 756
 757 int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
 758 {
 759         u32 data[MAX_MB_ARGUMENTS];
 760         va_list ap;
 761         int i;
 762
 763         if (cx == NULL) {
 764                 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
 765                 return 0;
 766         }
 767         if (args > MAX_MB_ARGUMENTS) {
 768                 CX18_ERR("args too big (cmd=%x)\n", cmd);
 769                 args = MAX_MB_ARGUMENTS;
 770         }
 771         va_start(ap, args);
 772         for (i = 0; i < args; i++)
 773                 data[i] = va_arg(ap, u32);
 774         va_end(ap);
 775         return cx18_api(cx, cmd, args, data);
 776 }