2 * cx18 mailbox functions
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
24 #include "cx18-driver.h"
28 #include "cx18-mailbox.h"
29 #include "cx18-queue.h"
30 #include "cx18-streams.h"
32 static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
34 #define API_FAST (1 << 2) /* Short timeout */
35 #define API_SLOW (1 << 3) /* Additional 300ms timeout */
37 struct cx18_api_info {
39 u8 flags; /* Flags, see above */
40 u8 rpu; /* Processing unit */
41 const char *name; /* The name of the command */
44 #define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
46 static const struct cx18_api_info api_info[] = {
47 /* MPEG encoder API */
48 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
49 API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
50 API_ENTRY(CPU, CX18_CREATE_TASK, 0),
51 API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
52 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
53 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
54 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
55 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
56 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
57 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
58 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0),
59 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0),
60 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0),
61 API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0),
62 API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0),
63 API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0),
64 API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0),
65 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0),
66 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0),
67 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0),
68 API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0),
69 API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW),
70 API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0),
71 API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0),
72 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0),
73 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0),
74 API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0),
75 API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0),
76 API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0),
77 API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0),
78 API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0),
79 API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
80 API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
81 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
82 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
84 API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST),
85 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
89 static const struct cx18_api_info *find_api_info(u32 cmd)
93 for (i = 0; api_info[i].cmd; i++)
94 if (api_info[i].cmd == cmd)
99 static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
101 char argstr[MAX_MB_ARGUMENTS*11+1];
105 if (!(cx18_debug & CX18_DBGFLG_API))
108 for (i = 0, p = argstr; i < MAX_MB_ARGUMENTS; i++, p += 11) {
109 /* kernel snprintf() appends '\0' always */
110 snprintf(p, 12, " %#010x", mb->args[i]);
112 CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
113 "\n", name, mb->request, mb->ack, mb->cmd, mb->error, argstr);
118 * Functions that run in a work_queue work handling context
121 static void epu_dma_done(struct cx18 *cx, struct cx18_epu_work_order *order)
123 u32 handle, mdl_ack_count;
124 struct cx18_mailbox *mb;
125 struct cx18_mdl_ack *mdl_ack;
126 struct cx18_stream *s;
127 struct cx18_buffer *buf;
131 handle = mb->args[0];
132 s = cx18_handle_to_stream(cx, handle);
135 CX18_WARN("Got DMA done notification for unknown/inactive"
136 " handle %d\n", handle);
140 mdl_ack_count = mb->args[2];
141 mdl_ack = order->mdl_ack;
142 for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
143 buf = cx18_queue_get_buf(s, mdl_ack->id, mdl_ack->data_used);
144 CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name,
147 CX18_WARN("Could not find buf %d for stream %s\n",
148 mdl_ack->id, s->name);
152 cx18_buf_sync_for_cpu(s, buf);
153 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
154 CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n",
157 dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
160 cx18_buf_sync_for_device(s, buf);
162 if (s->handle != CX18_INVALID_TASK_HANDLE &&
163 test_bit(CX18_F_S_STREAMING, &s->s_flags))
165 CX18_CPU_DE_SET_MDL, 5, s->handle,
167 &cx->scb->cpu_mdl[buf->id] - cx->enc_mem,
168 1, buf->id, s->buf_size);
170 set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags);
172 wake_up(&cx->dma_waitq);
177 static void epu_debug(struct cx18 *cx, struct cx18_epu_work_order *order)
180 char *str = order->str;
182 CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
183 p = strchr(str, '.');
184 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
185 CX18_INFO("FW version: %s\n", p - 1);
188 static void epu_cmd(struct cx18 *cx, struct cx18_epu_work_order *order)
190 switch (order->rpu) {
193 switch (order->mb.cmd) {
194 case CX18_EPU_DMA_DONE:
195 epu_dma_done(cx, order);
198 epu_debug(cx, order);
201 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
208 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
217 void free_epu_work_order(struct cx18 *cx, struct cx18_epu_work_order *order)
219 atomic_set(&order->pending, 0);
222 void cx18_epu_work_handler(struct work_struct *work)
224 struct cx18_epu_work_order *order =
225 container_of(work, struct cx18_epu_work_order, work);
226 struct cx18 *cx = order->cx;
228 free_epu_work_order(cx, order);
233 * Functions that run in an interrupt handling context
236 static void mb_ack_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
238 struct cx18_mailbox __iomem *ack_mb;
241 switch (order->rpu) {
243 ack_irq = IRQ_EPU_TO_APU_ACK;
244 ack_mb = &cx->scb->apu2epu_mb;
247 ack_irq = IRQ_EPU_TO_CPU_ACK;
248 ack_mb = &cx->scb->cpu2epu_mb;
251 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
252 order->rpu, order->mb.cmd);
256 req = order->mb.request;
257 /* Don't ack if the RPU has gotten impatient and timed us out */
258 if (req != cx18_readl(cx, &ack_mb->request) ||
259 req == cx18_readl(cx, &ack_mb->ack)) {
260 CX18_WARN("Possibly falling behind: %s self-ack'ed our incoming"
261 " %s to EPU mailbox (sequence no. %u) while "
263 rpu_str[order->rpu], rpu_str[order->rpu], req);
264 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
267 cx18_writel(cx, req, &ack_mb->ack);
268 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
272 static int epu_dma_done_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
274 u32 handle, mdl_ack_offset, mdl_ack_count;
275 struct cx18_mailbox *mb;
278 handle = mb->args[0];
279 mdl_ack_offset = mb->args[1];
280 mdl_ack_count = mb->args[2];
282 if (handle == CX18_INVALID_TASK_HANDLE ||
283 mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
284 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
285 mb_ack_irq(cx, order);
289 cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
290 sizeof(struct cx18_mdl_ack) * mdl_ack_count);
292 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
293 mb_ack_irq(cx, order);
298 int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
301 char *str = order->str;
304 str_offset = order->mb.args[1];
306 cx18_setup_page(cx, str_offset);
307 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
309 cx18_setup_page(cx, SCB_OFFSET);
312 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
313 mb_ack_irq(cx, order);
315 return str_offset ? 1 : 0;
319 int epu_cmd_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
323 switch (order->rpu) {
326 switch (order->mb.cmd) {
327 case CX18_EPU_DMA_DONE:
328 ret = epu_dma_done_irq(cx, order);
331 ret = epu_debug_irq(cx, order);
334 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
341 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
351 struct cx18_epu_work_order *alloc_epu_work_order_irq(struct cx18 *cx)
354 struct cx18_epu_work_order *order = NULL;
356 for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++) {
358 * We only need "pending" atomic to inspect its contents,
359 * and need not do a check and set because:
360 * 1. Any work handler thread only clears "pending" and only
361 * on one, particular work order at a time, per handler thread.
362 * 2. "pending" is only set here, and we're serialized because
363 * we're called in an IRQ handler context.
365 if (atomic_read(&cx->epu_work_order[i].pending) == 0) {
366 order = &cx->epu_work_order[i];
367 atomic_set(&order->pending, 1);
374 void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
376 struct cx18_mailbox __iomem *mb;
377 struct cx18_mailbox *order_mb;
378 struct cx18_epu_work_order *order;
383 mb = &cx->scb->cpu2epu_mb;
386 mb = &cx->scb->apu2epu_mb;
392 order = alloc_epu_work_order_irq(cx);
394 CX18_WARN("Unable to find blank work order form to schedule "
395 "incoming mailbox command processing\n");
401 order_mb = &order->mb;
402 cx18_memcpy_fromio(cx, order_mb, mb, sizeof(struct cx18_mailbox));
404 if (order_mb->request == order_mb->ack) {
405 CX18_WARN("Possibly falling behind: %s self-ack'ed our incoming"
406 " %s to EPU mailbox (sequence no. %u)\n",
407 rpu_str[rpu], rpu_str[rpu], order_mb->request);
408 dump_mb(cx, order_mb, "incoming");
409 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
413 * Individual EPU command processing is responsible for ack-ing
414 * a non-stale mailbox as soon as possible
416 submit = epu_cmd_irq(cx, order);
418 queue_work(cx18_work_queue, &order->work);
424 * Functions called from a non-interrupt, non work_queue context
427 static void cx18_api_log_ack_delay(struct cx18 *cx, int msecs)
429 if (msecs > CX18_MAX_MB_ACK_DELAY)
430 msecs = CX18_MAX_MB_ACK_DELAY;
431 atomic_inc(&cx->mbox_stats.mb_ack_delay[msecs]);
434 static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
436 const struct cx18_api_info *info = find_api_info(cmd);
437 u32 state, irq, req, ack, err;
438 struct cx18_mailbox __iomem *mb;
439 u32 __iomem *xpu_state;
440 wait_queue_head_t *waitq;
441 struct mutex *mb_lock;
442 long int timeout, ret;
446 CX18_WARN("unknown cmd %x\n", cmd);
450 if (cmd == CX18_CPU_DE_SET_MDL)
451 CX18_DEBUG_HI_API("%s\n", info->name);
453 CX18_DEBUG_API("%s\n", info->name);
457 waitq = &cx->mb_apu_waitq;
458 mb_lock = &cx->epu2apu_mb_lock;
459 irq = IRQ_EPU_TO_APU;
460 mb = &cx->scb->epu2apu_mb;
461 xpu_state = &cx->scb->apu_state;
464 waitq = &cx->mb_cpu_waitq;
465 mb_lock = &cx->epu2cpu_mb_lock;
466 irq = IRQ_EPU_TO_CPU;
467 mb = &cx->scb->epu2cpu_mb;
468 xpu_state = &cx->scb->cpu_state;
471 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
477 * Wait for an in-use mailbox to complete
479 * If the XPU is responding with Ack's, the mailbox shouldn't be in
480 * a busy state, since we serialize access to it on our end.
482 * If the wait for ack after sending a previous command was interrupted
483 * by a signal, we may get here and find a busy mailbox. After waiting,
484 * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
486 state = cx18_readl(cx, xpu_state);
487 req = cx18_readl(cx, &mb->request);
488 timeout = msecs_to_jiffies(20); /* 1 field at 50 Hz vertical refresh */
489 ret = wait_event_timeout(*waitq,
490 (ack = cx18_readl(cx, &mb->ack)) == req,
493 /* waited long enough, make the mbox "not busy" from our end */
494 cx18_writel(cx, req, &mb->ack);
495 CX18_ERR("mbox was found stuck busy when setting up for %s; "
496 "clearing busy and trying to proceed\n", info->name);
497 } else if (ret != timeout)
498 CX18_DEBUG_API("waited %u usecs for busy mbox to be acked\n",
499 jiffies_to_usecs(timeout-ret));
501 /* Build the outgoing mailbox */
502 req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
504 cx18_writel(cx, cmd, &mb->cmd);
505 for (i = 0; i < args; i++)
506 cx18_writel(cx, data[i], &mb->args[i]);
507 cx18_writel(cx, 0, &mb->error);
508 cx18_writel(cx, req, &mb->request);
509 cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
512 * Notify the XPU and wait for it to send an Ack back
513 * 21 ms = ~ 0.5 frames at a frame rate of 24 fps
514 * 42 ms = ~ 1 frame at a frame rate of 24 fps
516 timeout = msecs_to_jiffies((info->flags & API_FAST) ? 21 : 42);
518 CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
520 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
522 ret = wait_event_timeout(
524 cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request),
528 mutex_unlock(mb_lock);
529 i = jiffies_to_msecs(timeout);
530 cx18_api_log_ack_delay(cx, i);
531 CX18_WARN("sending %s timed out waiting %d msecs for RPU "
532 "acknowledgement\n", info->name, i);
534 } else if (ret < 0) {
536 mutex_unlock(mb_lock);
537 CX18_WARN("sending %s was interrupted waiting for RPU"
538 "acknowledgement\n", info->name);
542 i = jiffies_to_msecs(timeout-ret);
543 cx18_api_log_ack_delay(cx, i);
545 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
548 /* Collect data returned by the XPU */
549 for (i = 0; i < MAX_MB_ARGUMENTS; i++)
550 data[i] = cx18_readl(cx, &mb->args[i]);
551 err = cx18_readl(cx, &mb->error);
552 mutex_unlock(mb_lock);
555 * Wait for XPU to perform extra actions for the caller in some cases.
556 * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers
557 * back in a burst shortly thereafter
559 if (info->flags & API_SLOW)
560 cx18_msleep_timeout(300, 0);
563 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
565 return err ? -EIO : 0;
568 int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
570 return cx18_api_call(cx, cmd, args, data);
573 static int cx18_set_filter_param(struct cx18_stream *s)
575 struct cx18 *cx = s->cx;
579 mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
580 ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
581 s->handle, 1, mode, cx->spatial_strength);
582 mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
583 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
584 s->handle, 0, mode, cx->temporal_strength);
585 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
586 s->handle, 2, cx->filter_mode >> 2, 0);
590 int cx18_api_func(void *priv, u32 cmd, int in, int out,
591 u32 data[CX2341X_MBOX_MAX_DATA])
593 struct cx18 *cx = priv;
594 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
597 case CX2341X_ENC_SET_OUTPUT_PORT:
599 case CX2341X_ENC_SET_FRAME_RATE:
600 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
601 s->handle, 0, 0, 0, 0, data[0]);
602 case CX2341X_ENC_SET_FRAME_SIZE:
603 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
604 s->handle, data[1], data[0]);
605 case CX2341X_ENC_SET_STREAM_TYPE:
606 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
608 case CX2341X_ENC_SET_ASPECT_RATIO:
609 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
612 case CX2341X_ENC_SET_GOP_PROPERTIES:
613 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
614 s->handle, data[0], data[1]);
615 case CX2341X_ENC_SET_GOP_CLOSURE:
617 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
618 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
620 case CX2341X_ENC_MUTE_AUDIO:
621 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
623 case CX2341X_ENC_SET_BIT_RATE:
624 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
625 s->handle, data[0], data[1], data[2], data[3]);
626 case CX2341X_ENC_MUTE_VIDEO:
627 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
629 case CX2341X_ENC_SET_FRAME_DROP_RATE:
630 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
632 case CX2341X_ENC_MISC:
633 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
634 s->handle, data[0], data[1], data[2]);
635 case CX2341X_ENC_SET_DNR_FILTER_MODE:
636 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
637 return cx18_set_filter_param(s);
638 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
639 cx->spatial_strength = data[0];
640 cx->temporal_strength = data[1];
641 return cx18_set_filter_param(s);
642 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
643 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
644 s->handle, data[0], data[1]);
645 case CX2341X_ENC_SET_CORING_LEVELS:
646 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
647 s->handle, data[0], data[1], data[2], data[3]);
649 CX18_WARN("Unknown cmd %x\n", cmd);
653 int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
654 u32 cmd, int args, ...)
660 for (i = 0; i < args; i++)
661 data[i] = va_arg(ap, u32);
663 return cx18_api(cx, cmd, args, data);
666 int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
668 u32 data[MAX_MB_ARGUMENTS];
673 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
676 if (args > MAX_MB_ARGUMENTS) {
677 CX18_ERR("args too big (cmd=%x)\n", cmd);
678 args = MAX_MB_ARGUMENTS;
681 for (i = 0; i < args; i++)
682 data[i] = va_arg(ap, u32);
684 return cx18_api(cx, cmd, args, data);