SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/cx18/cx18-mailbox.c

   1 /*
   2  *  cx18 mailbox functions
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *  Copyright (C) 2008  Andy Walls <awalls@radix.net>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  20  *  02111-1307  USA
  21  */
  22
  23 #include <stdarg.h>
  24
  25 #include "cx18-driver.h"
  26 #include "cx18-io.h"
  27 #include "cx18-scb.h"
  28 #include "cx18-irq.h"
  29 #include "cx18-mailbox.h"
  30 #include "cx18-queue.h"
  31 #include "cx18-streams.h"
  32
  33 static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
  34
  35 #define API_FAST (1 << 2) /* Short timeout */
  36 #define API_SLOW (1 << 3) /* Additional 300ms timeout */
  37
  38 struct cx18_api_info {
  39         u32 cmd;
  40         u8 flags;               /* Flags, see above */
  41         u8 rpu;                 /* Processing unit */
  42         const char *name;       /* The name of the command */
  43 };
  44
  45 #define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
  46
  47 static const struct cx18_api_info api_info[] = {
  48         /* MPEG encoder API */
  49         API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE,               0),
  50         API_ENTRY(CPU, CX18_EPU_DEBUG,                          0),
  51         API_ENTRY(CPU, CX18_CREATE_TASK,                        0),
  52         API_ENTRY(CPU, CX18_DESTROY_TASK,                       0),
  53         API_ENTRY(CPU, CX18_CPU_CAPTURE_START,                  API_SLOW),
  54         API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP,                   API_SLOW),
  55         API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE,                  0),
  56         API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME,                 0),
  57         API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE,               0),
  58         API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE,         0),
  59         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN,                   0),
  60         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE,                 0),
  61         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION,           0),
  62         API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM,               0),
  63         API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE,        0),
  64         API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING,              0),
  65         API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE,                 0),
  66         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS,           0),
  67         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE,                 0),
  68         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE,                 0),
  69         API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS,            0),
  70         API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM,              API_SLOW),
  71         API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO,            0),
  72         API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT,                  0),
  73         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID,                  0),
  74         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID,                  0),
  75         API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE,              0),
  76         API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE,              0),
  77         API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION,     0),
  78         API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO,               0),
  79         API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME,           0),
  80         API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM,           0),
  81         API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER,      0),
  82         API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS,                    0),
  83         API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK,                 0),
  84         API_ENTRY(CPU, CX18_CPU_DE_SET_MDL,                     API_FAST),
  85         API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL,                 API_SLOW),
  86         API_ENTRY(APU, CX18_APU_START,                          0),
  87         API_ENTRY(APU, CX18_APU_STOP,                           0),
  88         API_ENTRY(APU, CX18_APU_RESETAI,                        0),
  89         API_ENTRY(CPU, CX18_CPU_DEBUG_PEEK32,                   0),
  90         API_ENTRY(0, 0,                                         0),
  91 };
  92
  93 static const struct cx18_api_info *find_api_info(u32 cmd)
  94 {
  95         int i;
  96
  97         for (i = 0; api_info[i].cmd; i++)
  98                 if (api_info[i].cmd == cmd)
  99                         return &api_info[i];
 100         return NULL;
 101 }
 102
 103 /* Call with buf of n*11+1 bytes */
 104 static char *u32arr2hex(u32 data[], int n, char *buf)
 105 {
 106         char *p;
 107         int i;
 108
 109         for (i = 0, p = buf; i < n; i++, p += 11) {
 110                 /* kernel snprintf() appends '\0' always */
 111                 snprintf(p, 12, " %#010x", data[i]);
 112         }
 113         *p = '\0';
 114         return buf;
 115 }
 116
 117 static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
 118 {
 119         char argstr[MAX_MB_ARGUMENTS*11+1];
 120
 121         if (!(cx18_debug & CX18_DBGFLG_API))
 122                 return;
 123
 124         CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
 125                        "\n", name, mb->request, mb->ack, mb->cmd, mb->error,
 126                        u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
 127 }
 128
 129
 130 /*
 131  * Functions that run in a work_queue work handling context
 132  */
 133
 134 static void cx18_mdl_send_to_dvb(struct cx18_stream *s, struct cx18_mdl *mdl)
 135 {
 136         struct cx18_buffer *buf;
 137
 138         if (!s->dvb.enabled || mdl->bytesused == 0)
 139                 return;
 140
 141         /* We ignore mdl and buf readpos accounting here - it doesn't matter */
 142
 143         /* The likely case */
 144         if (list_is_singular(&mdl->buf_list)) {
 145                 buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
 146                                        list);
 147                 if (buf->bytesused)
 148                         dvb_dmx_swfilter(&s->dvb.demux,
 149                                          buf->buf, buf->bytesused);
 150                 return;
 151         }
 152
 153         list_for_each_entry(buf, &mdl->buf_list, list) {
 154                 if (buf->bytesused == 0)
 155                         break;
 156                 dvb_dmx_swfilter(&s->dvb.demux, buf->buf, buf->bytesused);
 157         }
 158 }
 159
 160 static void epu_dma_done(struct cx18 *cx, struct cx18_in_work_order *order)
 161 {
 162         u32 handle, mdl_ack_count, id;
 163         struct cx18_mailbox *mb;
 164         struct cx18_mdl_ack *mdl_ack;
 165         struct cx18_stream *s;
 166         struct cx18_mdl *mdl;
 167         int i;
 168
 169         mb = &order->mb;
 170         handle = mb->args[0];
 171         s = cx18_handle_to_stream(cx, handle);
 172
 173         if (s == NULL) {
 174                 CX18_WARN("Got DMA done notification for unknown/inactive"
 175                           " handle %d, %s mailbox seq no %d\n", handle,
 176                           (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
 177                           "stale" : "good", mb->request);
 178                 return;
 179         }
 180
 181         mdl_ack_count = mb->args[2];
 182         mdl_ack = order->mdl_ack;
 183         for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
 184                 id = mdl_ack->id;
 185                 /*
 186                  * Simple integrity check for processing a stale (and possibly
 187                  * inconsistent mailbox): make sure the MDL id is in the
 188                  * valid range for the stream.
 189                  *
 190                  * We go through the trouble of dealing with stale mailboxes
 191                  * because most of the time, the mailbox data is still valid and
 192                  * unchanged (and in practice the firmware ping-pongs the
 193                  * two mdl_ack buffers so mdl_acks are not stale).
 194                  *
 195                  * There are occasions when we get a half changed mailbox,
 196                  * which this check catches for a handle & id mismatch.  If the
 197                  * handle and id do correspond, the worst case is that we
 198                  * completely lost the old MDL, but pick up the new MDL
 199                  * early (but the new mdl_ack is guaranteed to be good in this
 200                  * case as the firmware wouldn't point us to a new mdl_ack until
 201                  * it's filled in).
 202                  *
 203                  * cx18_queue_get_mdl() will detect the lost MDLs
 204                  * and send them back to q_free for fw rotation eventually.
 205                  */
 206                 if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
 207                     !(id >= s->mdl_base_idx &&
 208                       id < (s->mdl_base_idx + s->buffers))) {
 209                         CX18_WARN("Fell behind! Ignoring stale mailbox with "
 210                                   " inconsistent data. Lost MDL for mailbox "
 211                                   "seq no %d\n", mb->request);
 212                         break;
 213                 }
 214                 mdl = cx18_queue_get_mdl(s, id, mdl_ack->data_used);
 215
 216                 CX18_DEBUG_HI_DMA("DMA DONE for %s (MDL %d)\n", s->name, id);
 217                 if (mdl == NULL) {
 218                         CX18_WARN("Could not find MDL %d for stream %s\n",
 219                                   id, s->name);
 220                         continue;
 221                 }
 222
 223                 CX18_DEBUG_HI_DMA("%s recv bytesused = %d\n",
 224                                   s->name, mdl->bytesused);
 225
 226                 if (s->type != CX18_ENC_STREAM_TYPE_TS)
 227                         cx18_enqueue(s, mdl, &s->q_full);
 228                 else {
 229                         cx18_mdl_send_to_dvb(s, mdl);
 230                         cx18_enqueue(s, mdl, &s->q_free);
 231                 }
 232         }
 233         /* Put as many MDLs as possible back into fw use */
 234         cx18_stream_load_fw_queue(s);
 235
 236         wake_up(&cx->dma_waitq);
 237         if (s->id != -1)
 238                 wake_up(&s->waitq);
 239 }
 240
 241 static void epu_debug(struct cx18 *cx, struct cx18_in_work_order *order)
 242 {
 243         char *p;
 244         char *str = order->str;
 245
 246         CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
 247         p = strchr(str, '.');
 248         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
 249                 CX18_INFO("FW version: %s\n", p - 1);
 250 }
 251
 252 static void epu_cmd(struct cx18 *cx, struct cx18_in_work_order *order)
 253 {
 254         switch (order->rpu) {
 255         case CPU:
 256         {
 257                 switch (order->mb.cmd) {
 258                 case CX18_EPU_DMA_DONE:
 259                         epu_dma_done(cx, order);
 260                         break;
 261                 case CX18_EPU_DEBUG:
 262                         epu_debug(cx, order);
 263                         break;
 264                 default:
 265                         CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
 266                                   order->mb.cmd);
 267                         break;
 268                 }
 269                 break;
 270         }
 271         case APU:
 272                 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
 273                           order->mb.cmd);
 274                 break;
 275         default:
 276                 break;
 277         }
 278 }
 279
 280 static
 281 void free_in_work_order(struct cx18 *cx, struct cx18_in_work_order *order)
 282 {
 283         atomic_set(&order->pending, 0);
 284 }
 285
 286 void cx18_in_work_handler(struct work_struct *work)
 287 {
 288         struct cx18_in_work_order *order =
 289                         container_of(work, struct cx18_in_work_order, work);
 290         struct cx18 *cx = order->cx;
 291         epu_cmd(cx, order);
 292         free_in_work_order(cx, order);
 293 }
 294
 295
 296 /*
 297  * Functions that run in an interrupt handling context
 298  */
 299
 300 static void mb_ack_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 301 {
 302         struct cx18_mailbox __iomem *ack_mb;
 303         u32 ack_irq, req;
 304
 305         switch (order->rpu) {
 306         case APU:
 307                 ack_irq = IRQ_EPU_TO_APU_ACK;
 308                 ack_mb = &cx->scb->apu2epu_mb;
 309                 break;
 310         case CPU:
 311                 ack_irq = IRQ_EPU_TO_CPU_ACK;
 312                 ack_mb = &cx->scb->cpu2epu_mb;
 313                 break;
 314         default:
 315                 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
 316                           order->rpu, order->mb.cmd);
 317                 return;
 318         }
 319
 320         req = order->mb.request;
 321         /* Don't ack if the RPU has gotten impatient and timed us out */
 322         if (req != cx18_readl(cx, &ack_mb->request) ||
 323             req == cx18_readl(cx, &ack_mb->ack)) {
 324                 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
 325                                 "incoming %s to EPU mailbox (sequence no. %u) "
 326                                 "while processing\n",
 327                                 rpu_str[order->rpu], rpu_str[order->rpu], req);
 328                 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
 329                 return;
 330         }
 331         cx18_writel(cx, req, &ack_mb->ack);
 332         cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
 333         return;
 334 }
 335
 336 static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 337 {
 338         u32 handle, mdl_ack_offset, mdl_ack_count;
 339         struct cx18_mailbox *mb;
 340
 341         mb = &order->mb;
 342         handle = mb->args[0];
 343         mdl_ack_offset = mb->args[1];
 344         mdl_ack_count = mb->args[2];
 345
 346         if (handle == CX18_INVALID_TASK_HANDLE ||
 347             mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
 348                 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
 349                         mb_ack_irq(cx, order);
 350                 return -1;
 351         }
 352
 353         cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
 354                            sizeof(struct cx18_mdl_ack) * mdl_ack_count);
 355
 356         if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
 357                 mb_ack_irq(cx, order);
 358         return 1;
 359 }
 360
 361 static
 362 int epu_debug_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 363 {
 364         u32 str_offset;
 365         char *str = order->str;
 366
 367         str[0] = '\0';
 368         str_offset = order->mb.args[1];
 369         if (str_offset) {
 370                 cx18_setup_page(cx, str_offset);
 371                 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
 372                 str[252] = '\0';
 373                 cx18_setup_page(cx, SCB_OFFSET);
 374         }
 375
 376         if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
 377                 mb_ack_irq(cx, order);
 378
 379         return str_offset ? 1 : 0;
 380 }
 381
 382 static inline
 383 int epu_cmd_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 384 {
 385         int ret = -1;
 386
 387         switch (order->rpu) {
 388         case CPU:
 389         {
 390                 switch (order->mb.cmd) {
 391                 case CX18_EPU_DMA_DONE:
 392                         ret = epu_dma_done_irq(cx, order);
 393                         break;
 394                 case CX18_EPU_DEBUG:
 395                         ret = epu_debug_irq(cx, order);
 396                         break;
 397                 default:
 398                         CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
 399                                   order->mb.cmd);
 400                         break;
 401                 }
 402                 break;
 403         }
 404         case APU:
 405                 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
 406                           order->mb.cmd);
 407                 break;
 408         default:
 409                 break;
 410         }
 411         return ret;
 412 }
 413
 414 static inline
 415 struct cx18_in_work_order *alloc_in_work_order_irq(struct cx18 *cx)
 416 {
 417         int i;
 418         struct cx18_in_work_order *order = NULL;
 419
 420         for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
 421                 /*
 422                  * We only need "pending" atomic to inspect its contents,
 423                  * and need not do a check and set because:
 424                  * 1. Any work handler thread only clears "pending" and only
 425                  * on one, particular work order at a time, per handler thread.
 426                  * 2. "pending" is only set here, and we're serialized because
 427                  * we're called in an IRQ handler context.
 428                  */
 429                 if (atomic_read(&cx->in_work_order[i].pending) == 0) {
 430                         order = &cx->in_work_order[i];
 431                         atomic_set(&order->pending, 1);
 432                         break;
 433                 }
 434         }
 435         return order;
 436 }
 437
 438 void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
 439 {
 440         struct cx18_mailbox __iomem *mb;
 441         struct cx18_mailbox *order_mb;
 442         struct cx18_in_work_order *order;
 443         int submit;
 444
 445         switch (rpu) {
 446         case CPU:
 447                 mb = &cx->scb->cpu2epu_mb;
 448                 break;
 449         case APU:
 450                 mb = &cx->scb->apu2epu_mb;
 451                 break;
 452         default:
 453                 return;
 454         }
 455
 456         order = alloc_in_work_order_irq(cx);
 457         if (order == NULL) {
 458                 CX18_WARN("Unable to find blank work order form to schedule "
 459                           "incoming mailbox command processing\n");
 460                 return;
 461         }
 462
 463         order->flags = 0;
 464         order->rpu = rpu;
 465         order_mb = &order->mb;
 466
 467         /* mb->cmd and mb->args[0] through mb->args[2] */
 468         cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32));
 469         /* mb->request and mb->ack.  N.B. we want to read mb->ack last */
 470         cx18_memcpy_fromio(cx, &order_mb->request, &mb->request,
 471                            2 * sizeof(u32));
 472
 473         if (order_mb->request == order_mb->ack) {
 474                 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
 475                                 "incoming %s to EPU mailbox (sequence no. %u)"
 476                                 "\n",
 477                                 rpu_str[rpu], rpu_str[rpu], order_mb->request);
 478                 if (cx18_debug & CX18_DBGFLG_WARN)
 479                         dump_mb(cx, order_mb, "incoming");
 480                 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
 481         }
 482
 483         /*
 484          * Individual EPU command processing is responsible for ack-ing
 485          * a non-stale mailbox as soon as possible
 486          */
 487         submit = epu_cmd_irq(cx, order);
 488         if (submit > 0) {
 489                 queue_work(cx->in_work_queue, &order->work);
 490         }
 491 }
 492
 493
 494 /*
 495  * Functions called from a non-interrupt, non work_queue context
 496  */
 497
 498 static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
 499 {
 500         const struct cx18_api_info *info = find_api_info(cmd);
 501         u32 state, irq, req, ack, err;
 502         struct cx18_mailbox __iomem *mb;
 503         u32 __iomem *xpu_state;
 504         wait_queue_head_t *waitq;
 505         struct mutex *mb_lock;
 506         unsigned long int t0, timeout, ret;
 507         int i;
 508         char argstr[MAX_MB_ARGUMENTS*11+1];
 509         DEFINE_WAIT(w);
 510
 511         if (info == NULL) {
 512                 CX18_WARN("unknown cmd %x\n", cmd);
 513                 return -EINVAL;
 514         }
 515
 516         if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */
 517                 if (cmd == CX18_CPU_DE_SET_MDL) {
 518                         if (cx18_debug & CX18_DBGFLG_HIGHVOL)
 519                                 CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n",
 520                                                 info->name, cmd,
 521                                                 u32arr2hex(data, args, argstr));
 522                 } else
 523                         CX18_DEBUG_API("%s\tcmd %#010x args%s\n",
 524                                        info->name, cmd,
 525                                        u32arr2hex(data, args, argstr));
 526         }
 527
 528         switch (info->rpu) {
 529         case APU:
 530                 waitq = &cx->mb_apu_waitq;
 531                 mb_lock = &cx->epu2apu_mb_lock;
 532                 irq = IRQ_EPU_TO_APU;
 533                 mb = &cx->scb->epu2apu_mb;
 534                 xpu_state = &cx->scb->apu_state;
 535                 break;
 536         case CPU:
 537                 waitq = &cx->mb_cpu_waitq;
 538                 mb_lock = &cx->epu2cpu_mb_lock;
 539                 irq = IRQ_EPU_TO_CPU;
 540                 mb = &cx->scb->epu2cpu_mb;
 541                 xpu_state = &cx->scb->cpu_state;
 542                 break;
 543         default:
 544                 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
 545                 return -EINVAL;
 546         }
 547
 548         mutex_lock(mb_lock);
 549         /*
 550          * Wait for an in-use mailbox to complete
 551          *
 552          * If the XPU is responding with Ack's, the mailbox shouldn't be in
 553          * a busy state, since we serialize access to it on our end.
 554          *
 555          * If the wait for ack after sending a previous command was interrupted
 556          * by a signal, we may get here and find a busy mailbox.  After waiting,
 557          * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
 558          */
 559         state = cx18_readl(cx, xpu_state);
 560         req = cx18_readl(cx, &mb->request);
 561         timeout = msecs_to_jiffies(10);
 562         ret = wait_event_timeout(*waitq,
 563                                  (ack = cx18_readl(cx, &mb->ack)) == req,
 564                                  timeout);
 565         if (req != ack) {
 566                 /* waited long enough, make the mbox "not busy" from our end */
 567                 cx18_writel(cx, req, &mb->ack);
 568                 CX18_ERR("mbox was found stuck busy when setting up for %s; "
 569                          "clearing busy and trying to proceed\n", info->name);
 570         } else if (ret != timeout)
 571                 CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
 572                                jiffies_to_msecs(timeout-ret));
 573
 574         /* Build the outgoing mailbox */
 575         req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
 576
 577         cx18_writel(cx, cmd, &mb->cmd);
 578         for (i = 0; i < args; i++)
 579                 cx18_writel(cx, data[i], &mb->args[i]);
 580         cx18_writel(cx, 0, &mb->error);
 581         cx18_writel(cx, req, &mb->request);
 582         cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
 583
 584         /*
 585          * Notify the XPU and wait for it to send an Ack back
 586          */
 587         timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
 588
 589         CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
 590                           irq, info->name);
 591
 592         /* So we don't miss the wakeup, prepare to wait before notifying fw */
 593         prepare_to_wait(waitq, &w, TASK_UNINTERRUPTIBLE);
 594         cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
 595
 596         t0 = jiffies;
 597         ack = cx18_readl(cx, &mb->ack);
 598         if (ack != req) {
 599                 schedule_timeout(timeout);
 600                 ret = jiffies - t0;
 601                 ack = cx18_readl(cx, &mb->ack);
 602         } else {
 603                 ret = jiffies - t0;
 604         }
 605
 606         finish_wait(waitq, &w);
 607
 608         if (req != ack) {
 609                 mutex_unlock(mb_lock);
 610                 if (ret >= timeout) {
 611                         /* Timed out */
 612                         CX18_DEBUG_WARN("sending %s timed out waiting %d msecs "
 613                                         "for RPU acknowledgement\n",
 614                                         info->name, jiffies_to_msecs(ret));
 615                 } else {
 616                         CX18_DEBUG_WARN("woken up before mailbox ack was ready "
 617                                         "after submitting %s to RPU.  only "
 618                                         "waited %d msecs on req %u but awakened"
 619                                         " with unmatched ack %u\n",
 620                                         info->name,
 621                                         jiffies_to_msecs(ret),
 622                                         req, ack);
 623                 }
 624                 return -EINVAL;
 625         }
 626
 627         if (ret >= timeout)
 628                 CX18_DEBUG_WARN("failed to be awakened upon RPU acknowledgment "
 629                                 "sending %s; timed out waiting %d msecs\n",
 630                                 info->name, jiffies_to_msecs(ret));
 631         else
 632                 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
 633                                   jiffies_to_msecs(ret), info->name);
 634
 635         /* Collect data returned by the XPU */
 636         for (i = 0; i < MAX_MB_ARGUMENTS; i++)
 637                 data[i] = cx18_readl(cx, &mb->args[i]);
 638         err = cx18_readl(cx, &mb->error);
 639         mutex_unlock(mb_lock);
 640
 641         /*
 642          * Wait for XPU to perform extra actions for the caller in some cases.
 643          * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all MDLs
 644          * back in a burst shortly thereafter
 645          */
 646         if (info->flags & API_SLOW)
 647                 cx18_msleep_timeout(300, 0);
 648
 649         if (err)
 650                 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
 651                                 info->name);
 652         return err ? -EIO : 0;
 653 }
 654
 655 int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
 656 {
 657         return cx18_api_call(cx, cmd, args, data);
 658 }
 659
 660 static int cx18_set_filter_param(struct cx18_stream *s)
 661 {
 662         struct cx18 *cx = s->cx;
 663         u32 mode;
 664         int ret;
 665
 666         mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
 667         ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
 668                         s->handle, 1, mode, cx->spatial_strength);
 669         mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
 670         ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
 671                         s->handle, 0, mode, cx->temporal_strength);
 672         ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
 673                         s->handle, 2, cx->filter_mode >> 2, 0);
 674         return ret;
 675 }
 676
 677 int cx18_api_func(void *priv, u32 cmd, int in, int out,
 678                 u32 data[CX2341X_MBOX_MAX_DATA])
 679 {
 680         struct cx18_api_func_private *api_priv = priv;
 681         struct cx18 *cx = api_priv->cx;
 682         struct cx18_stream *s = api_priv->s;
 683
 684         switch (cmd) {
 685         case CX2341X_ENC_SET_OUTPUT_PORT:
 686                 return 0;
 687         case CX2341X_ENC_SET_FRAME_RATE:
 688                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
 689                                 s->handle, 0, 0, 0, 0, data[0]);
 690         case CX2341X_ENC_SET_FRAME_SIZE:
 691                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
 692                                 s->handle, data[1], data[0]);
 693         case CX2341X_ENC_SET_STREAM_TYPE:
 694                 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
 695                                 s->handle, data[0]);
 696         case CX2341X_ENC_SET_ASPECT_RATIO:
 697                 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
 698                                 s->handle, data[0]);
 699
 700         case CX2341X_ENC_SET_GOP_PROPERTIES:
 701                 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
 702                                 s->handle, data[0], data[1]);
 703         case CX2341X_ENC_SET_GOP_CLOSURE:
 704                 return 0;
 705         case CX2341X_ENC_SET_AUDIO_PROPERTIES:
 706                 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
 707                                 s->handle, data[0]);
 708         case CX2341X_ENC_MUTE_AUDIO:
 709                 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
 710                                 s->handle, data[0]);
 711         case CX2341X_ENC_SET_BIT_RATE:
 712                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
 713                                 s->handle, data[0], data[1], data[2], data[3]);
 714         case CX2341X_ENC_MUTE_VIDEO:
 715                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
 716                                 s->handle, data[0]);
 717         case CX2341X_ENC_SET_FRAME_DROP_RATE:
 718                 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
 719                                 s->handle, data[0]);
 720         case CX2341X_ENC_MISC:
 721                 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
 722                                 s->handle, data[0], data[1], data[2]);
 723         case CX2341X_ENC_SET_DNR_FILTER_MODE:
 724                 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
 725                 return cx18_set_filter_param(s);
 726         case CX2341X_ENC_SET_DNR_FILTER_PROPS:
 727                 cx->spatial_strength = data[0];
 728                 cx->temporal_strength = data[1];
 729                 return cx18_set_filter_param(s);
 730         case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
 731                 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
 732                                 s->handle, data[0], data[1]);
 733         case CX2341X_ENC_SET_CORING_LEVELS:
 734                 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
 735                                 s->handle, data[0], data[1], data[2], data[3]);
 736         }
 737         CX18_WARN("Unknown cmd %x\n", cmd);
 738         return 0;
 739 }
 740
 741 int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
 742                 u32 cmd, int args, ...)
 743 {
 744         va_list ap;
 745         int i;
 746
 747         va_start(ap, args);
 748         for (i = 0; i < args; i++)
 749                 data[i] = va_arg(ap, u32);
 750         va_end(ap);
 751         return cx18_api(cx, cmd, args, data);
 752 }
 753
 754 int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
 755 {
 756         u32 data[MAX_MB_ARGUMENTS];
 757         va_list ap;
 758         int i;
 759
 760         if (cx == NULL) {
 761                 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
 762                 return 0;
 763         }
 764         if (args > MAX_MB_ARGUMENTS) {
 765                 CX18_ERR("args too big (cmd=%x)\n", cmd);
 766                 args = MAX_MB_ARGUMENTS;
 767         }
 768         va_start(ap, args);
 769         for (i = 0; i < args; i++)
 770                 data[i] = va_arg(ap, u32);
 771         va_end(ap);
 772         return cx18_api(cx, cmd, args, data);
 773 }