2 * cx18 mailbox functions
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
5 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
25 #include "cx18-driver.h"
29 #include "cx18-mailbox.h"
30 #include "cx18-queue.h"
31 #include "cx18-streams.h"
33 static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
35 #define API_FAST (1 << 2) /* Short timeout */
36 #define API_SLOW (1 << 3) /* Additional 300ms timeout */
38 struct cx18_api_info {
40 u8 flags; /* Flags, see above */
41 u8 rpu; /* Processing unit */
42 const char *name; /* The name of the command */
45 #define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
47 static const struct cx18_api_info api_info[] = {
48 /* MPEG encoder API */
49 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
50 API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
51 API_ENTRY(CPU, CX18_CREATE_TASK, 0),
52 API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
53 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
54 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
55 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
56 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
57 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
58 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
59 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0),
60 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0),
61 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0),
62 API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0),
63 API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0),
64 API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0),
65 API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0),
66 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0),
67 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0),
68 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0),
69 API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0),
70 API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW),
71 API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0),
72 API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0),
73 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0),
74 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0),
75 API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0),
76 API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0),
77 API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0),
78 API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0),
79 API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0),
80 API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
81 API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
82 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
84 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
85 API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST),
86 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
90 static const struct cx18_api_info *find_api_info(u32 cmd)
94 for (i = 0; api_info[i].cmd; i++)
95 if (api_info[i].cmd == cmd)
100 static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
102 char argstr[MAX_MB_ARGUMENTS*11+1];
106 if (!(cx18_debug & CX18_DBGFLG_API))
109 for (i = 0, p = argstr; i < MAX_MB_ARGUMENTS; i++, p += 11) {
110 /* kernel snprintf() appends '\0' always */
111 snprintf(p, 12, " %#010x", mb->args[i]);
113 CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
114 "\n", name, mb->request, mb->ack, mb->cmd, mb->error, argstr);
119 * Functions that run in a work_queue work handling context
122 static void epu_dma_done(struct cx18 *cx, struct cx18_epu_work_order *order)
124 u32 handle, mdl_ack_count, id;
125 struct cx18_mailbox *mb;
126 struct cx18_mdl_ack *mdl_ack;
127 struct cx18_stream *s;
128 struct cx18_buffer *buf;
132 handle = mb->args[0];
133 s = cx18_handle_to_stream(cx, handle);
136 CX18_WARN("Got DMA done notification for unknown/inactive"
137 " handle %d, %s mailbox seq no %d\n", handle,
138 (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
139 "stale" : "good", mb->request);
143 mdl_ack_count = mb->args[2];
144 mdl_ack = order->mdl_ack;
145 for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
148 * Simple integrity check for processing a stale (and possibly
149 * inconsistent mailbox): make sure the buffer id is in the
150 * valid range for the stream.
152 * We go through the trouble of dealing with stale mailboxes
153 * because most of the time, the mailbox data is still valid and
154 * unchanged (and in practice the firmware ping-pongs the
155 * two mdl_ack buffers so mdl_acks are not stale).
157 * There are occasions when we get a half changed mailbox,
158 * which this check catches for a handle & id mismatch. If the
159 * handle and id do correspond, the worst case is that we
160 * completely lost the old buffer, but pick up the new buffer
161 * early (but the new mdl_ack is guaranteed to be good in this
162 * case as the firmware wouldn't point us to a new mdl_ack until
165 * cx18_queue_get buf() will detect the lost buffers
166 * and send them back to q_free for fw rotation eventually.
168 if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
169 !(id >= s->mdl_offset &&
170 id < (s->mdl_offset + s->buffers))) {
171 CX18_WARN("Fell behind! Ignoring stale mailbox with "
172 " inconsistent data. Lost buffer for mailbox "
173 "seq no %d\n", mb->request);
176 buf = cx18_queue_get_buf(s, id, mdl_ack->data_used);
178 CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id);
180 CX18_WARN("Could not find buf %d for stream %s\n",
182 /* Put as many buffers as possible back into fw use */
183 cx18_stream_load_fw_queue(s);
187 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
188 CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n",
190 dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
193 /* Put as many buffers as possible back into fw use */
194 cx18_stream_load_fw_queue(s);
195 /* Put back TS buffer, since it was removed from all queues */
196 if (s->type == CX18_ENC_STREAM_TYPE_TS)
197 cx18_stream_put_buf_fw(s, buf);
199 wake_up(&cx->dma_waitq);
204 static void epu_debug(struct cx18 *cx, struct cx18_epu_work_order *order)
207 char *str = order->str;
209 CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
210 p = strchr(str, '.');
211 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
212 CX18_INFO("FW version: %s\n", p - 1);
215 static void epu_cmd(struct cx18 *cx, struct cx18_epu_work_order *order)
217 switch (order->rpu) {
220 switch (order->mb.cmd) {
221 case CX18_EPU_DMA_DONE:
222 epu_dma_done(cx, order);
225 epu_debug(cx, order);
228 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
235 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
244 void free_epu_work_order(struct cx18 *cx, struct cx18_epu_work_order *order)
246 atomic_set(&order->pending, 0);
249 void cx18_epu_work_handler(struct work_struct *work)
251 struct cx18_epu_work_order *order =
252 container_of(work, struct cx18_epu_work_order, work);
253 struct cx18 *cx = order->cx;
255 free_epu_work_order(cx, order);
260 * Functions that run in an interrupt handling context
263 static void mb_ack_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
265 struct cx18_mailbox __iomem *ack_mb;
268 switch (order->rpu) {
270 ack_irq = IRQ_EPU_TO_APU_ACK;
271 ack_mb = &cx->scb->apu2epu_mb;
274 ack_irq = IRQ_EPU_TO_CPU_ACK;
275 ack_mb = &cx->scb->cpu2epu_mb;
278 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
279 order->rpu, order->mb.cmd);
283 req = order->mb.request;
284 /* Don't ack if the RPU has gotten impatient and timed us out */
285 if (req != cx18_readl(cx, &ack_mb->request) ||
286 req == cx18_readl(cx, &ack_mb->ack)) {
287 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
288 "incoming %s to EPU mailbox (sequence no. %u) "
289 "while processing\n",
290 rpu_str[order->rpu], rpu_str[order->rpu], req);
291 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
294 cx18_writel(cx, req, &ack_mb->ack);
295 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
299 static int epu_dma_done_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
301 u32 handle, mdl_ack_offset, mdl_ack_count;
302 struct cx18_mailbox *mb;
305 handle = mb->args[0];
306 mdl_ack_offset = mb->args[1];
307 mdl_ack_count = mb->args[2];
309 if (handle == CX18_INVALID_TASK_HANDLE ||
310 mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
311 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
312 mb_ack_irq(cx, order);
316 cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
317 sizeof(struct cx18_mdl_ack) * mdl_ack_count);
319 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
320 mb_ack_irq(cx, order);
325 int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
328 char *str = order->str;
331 str_offset = order->mb.args[1];
333 cx18_setup_page(cx, str_offset);
334 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
336 cx18_setup_page(cx, SCB_OFFSET);
339 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
340 mb_ack_irq(cx, order);
342 return str_offset ? 1 : 0;
346 int epu_cmd_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
350 switch (order->rpu) {
353 switch (order->mb.cmd) {
354 case CX18_EPU_DMA_DONE:
355 ret = epu_dma_done_irq(cx, order);
358 ret = epu_debug_irq(cx, order);
361 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
368 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
378 struct cx18_epu_work_order *alloc_epu_work_order_irq(struct cx18 *cx)
381 struct cx18_epu_work_order *order = NULL;
383 for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++) {
385 * We only need "pending" atomic to inspect its contents,
386 * and need not do a check and set because:
387 * 1. Any work handler thread only clears "pending" and only
388 * on one, particular work order at a time, per handler thread.
389 * 2. "pending" is only set here, and we're serialized because
390 * we're called in an IRQ handler context.
392 if (atomic_read(&cx->epu_work_order[i].pending) == 0) {
393 order = &cx->epu_work_order[i];
394 atomic_set(&order->pending, 1);
401 void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
403 struct cx18_mailbox __iomem *mb;
404 struct cx18_mailbox *order_mb;
405 struct cx18_epu_work_order *order;
410 mb = &cx->scb->cpu2epu_mb;
413 mb = &cx->scb->apu2epu_mb;
419 order = alloc_epu_work_order_irq(cx);
421 CX18_WARN("Unable to find blank work order form to schedule "
422 "incoming mailbox command processing\n");
428 order_mb = &order->mb;
430 /* mb->cmd and mb->args[0] through mb->args[2] */
431 cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32));
432 /* mb->request and mb->ack. N.B. we want to read mb->ack last */
433 cx18_memcpy_fromio(cx, &order_mb->request, &mb->request,
436 if (order_mb->request == order_mb->ack) {
437 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
438 "incoming %s to EPU mailbox (sequence no. %u)"
440 rpu_str[rpu], rpu_str[rpu], order_mb->request);
441 dump_mb(cx, order_mb, "incoming");
442 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
446 * Individual EPU command processing is responsible for ack-ing
447 * a non-stale mailbox as soon as possible
449 submit = epu_cmd_irq(cx, order);
451 queue_work(cx->work_queue, &order->work);
457 * Functions called from a non-interrupt, non work_queue context
460 static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
462 const struct cx18_api_info *info = find_api_info(cmd);
463 u32 state, irq, req, ack, err;
464 struct cx18_mailbox __iomem *mb;
465 u32 __iomem *xpu_state;
466 wait_queue_head_t *waitq;
467 struct mutex *mb_lock;
468 long int timeout, ret;
472 CX18_WARN("unknown cmd %x\n", cmd);
476 if (cmd == CX18_CPU_DE_SET_MDL)
477 CX18_DEBUG_HI_API("%s\n", info->name);
479 CX18_DEBUG_API("%s\n", info->name);
483 waitq = &cx->mb_apu_waitq;
484 mb_lock = &cx->epu2apu_mb_lock;
485 irq = IRQ_EPU_TO_APU;
486 mb = &cx->scb->epu2apu_mb;
487 xpu_state = &cx->scb->apu_state;
490 waitq = &cx->mb_cpu_waitq;
491 mb_lock = &cx->epu2cpu_mb_lock;
492 irq = IRQ_EPU_TO_CPU;
493 mb = &cx->scb->epu2cpu_mb;
494 xpu_state = &cx->scb->cpu_state;
497 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
503 * Wait for an in-use mailbox to complete
505 * If the XPU is responding with Ack's, the mailbox shouldn't be in
506 * a busy state, since we serialize access to it on our end.
508 * If the wait for ack after sending a previous command was interrupted
509 * by a signal, we may get here and find a busy mailbox. After waiting,
510 * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
512 state = cx18_readl(cx, xpu_state);
513 req = cx18_readl(cx, &mb->request);
514 timeout = msecs_to_jiffies(10);
515 ret = wait_event_timeout(*waitq,
516 (ack = cx18_readl(cx, &mb->ack)) == req,
519 /* waited long enough, make the mbox "not busy" from our end */
520 cx18_writel(cx, req, &mb->ack);
521 CX18_ERR("mbox was found stuck busy when setting up for %s; "
522 "clearing busy and trying to proceed\n", info->name);
523 } else if (ret != timeout)
524 CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
525 jiffies_to_msecs(timeout-ret));
527 /* Build the outgoing mailbox */
528 req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
530 cx18_writel(cx, cmd, &mb->cmd);
531 for (i = 0; i < args; i++)
532 cx18_writel(cx, data[i], &mb->args[i]);
533 cx18_writel(cx, 0, &mb->error);
534 cx18_writel(cx, req, &mb->request);
535 cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
538 * Notify the XPU and wait for it to send an Ack back
540 timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
542 CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
544 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
546 ret = wait_event_timeout(
548 cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request),
553 mutex_unlock(mb_lock);
554 CX18_DEBUG_WARN("sending %s timed out waiting %d msecs for RPU "
556 info->name, jiffies_to_msecs(timeout));
561 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
562 jiffies_to_msecs(timeout-ret), info->name);
564 /* Collect data returned by the XPU */
565 for (i = 0; i < MAX_MB_ARGUMENTS; i++)
566 data[i] = cx18_readl(cx, &mb->args[i]);
567 err = cx18_readl(cx, &mb->error);
568 mutex_unlock(mb_lock);
571 * Wait for XPU to perform extra actions for the caller in some cases.
572 * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers
573 * back in a burst shortly thereafter
575 if (info->flags & API_SLOW)
576 cx18_msleep_timeout(300, 0);
579 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
581 return err ? -EIO : 0;
584 int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
586 return cx18_api_call(cx, cmd, args, data);
589 static int cx18_set_filter_param(struct cx18_stream *s)
591 struct cx18 *cx = s->cx;
595 mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
596 ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
597 s->handle, 1, mode, cx->spatial_strength);
598 mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
599 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
600 s->handle, 0, mode, cx->temporal_strength);
601 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
602 s->handle, 2, cx->filter_mode >> 2, 0);
606 int cx18_api_func(void *priv, u32 cmd, int in, int out,
607 u32 data[CX2341X_MBOX_MAX_DATA])
609 struct cx18_api_func_private *api_priv = priv;
610 struct cx18 *cx = api_priv->cx;
611 struct cx18_stream *s = api_priv->s;
614 case CX2341X_ENC_SET_OUTPUT_PORT:
616 case CX2341X_ENC_SET_FRAME_RATE:
617 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
618 s->handle, 0, 0, 0, 0, data[0]);
619 case CX2341X_ENC_SET_FRAME_SIZE:
620 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
621 s->handle, data[1], data[0]);
622 case CX2341X_ENC_SET_STREAM_TYPE:
623 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
625 case CX2341X_ENC_SET_ASPECT_RATIO:
626 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
629 case CX2341X_ENC_SET_GOP_PROPERTIES:
630 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
631 s->handle, data[0], data[1]);
632 case CX2341X_ENC_SET_GOP_CLOSURE:
634 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
635 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
637 case CX2341X_ENC_MUTE_AUDIO:
638 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
640 case CX2341X_ENC_SET_BIT_RATE:
641 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
642 s->handle, data[0], data[1], data[2], data[3]);
643 case CX2341X_ENC_MUTE_VIDEO:
644 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
646 case CX2341X_ENC_SET_FRAME_DROP_RATE:
647 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
649 case CX2341X_ENC_MISC:
650 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
651 s->handle, data[0], data[1], data[2]);
652 case CX2341X_ENC_SET_DNR_FILTER_MODE:
653 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
654 return cx18_set_filter_param(s);
655 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
656 cx->spatial_strength = data[0];
657 cx->temporal_strength = data[1];
658 return cx18_set_filter_param(s);
659 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
660 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
661 s->handle, data[0], data[1]);
662 case CX2341X_ENC_SET_CORING_LEVELS:
663 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
664 s->handle, data[0], data[1], data[2], data[3]);
666 CX18_WARN("Unknown cmd %x\n", cmd);
670 int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
671 u32 cmd, int args, ...)
677 for (i = 0; i < args; i++)
678 data[i] = va_arg(ap, u32);
680 return cx18_api(cx, cmd, args, data);
683 int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
685 u32 data[MAX_MB_ARGUMENTS];
690 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
693 if (args > MAX_MB_ARGUMENTS) {
694 CX18_ERR("args too big (cmd=%x)\n", cmd);
695 args = MAX_MB_ARGUMENTS;
698 for (i = 0; i < args; i++)
699 data[i] = va_arg(ap, u32);
701 return cx18_api(cx, cmd, args, data);