SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/dvb/ngene/ngene-core.c

   1 /*
   2  * ngene.c: nGene PCIe bridge driver
   3  *
   4  * Copyright (C) 2005-2007 Micronas
   5  *
   6  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
   7  *                         Modifications for new nGene firmware,
   8  *                         support for EEPROM-copying,
   9  *                         support for new dual DVB-S2 card prototype
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * version 2 only, as published by the Free Software Foundation.
  15  *
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  26  * 02110-1301, USA
  27  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/init.h>
  32 #include <linux/delay.h>
  33 #include <linux/slab.h>
  34 #include <linux/poll.h>
  35 #include <asm/io.h>
  36 #include <asm/div64.h>
  37 #include <linux/pci.h>
  38 #include <linux/pci_ids.h>
  39 #include <linux/smp_lock.h>
  40 #include <linux/timer.h>
  41 #include <linux/version.h>
  42 #include <linux/byteorder/generic.h>
  43 #include <linux/firmware.h>
  44
  45 #include "ngene.h"
  46
  47 #include "stv6110x.h"
  48 #include "stv090x.h"
  49 #include "lnbh24.h"
  50
  51 static int one_adapter = 1;
  52 module_param(one_adapter, int, 0444);
  53 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
  54
  55
  56 static int debug;
  57 module_param(debug, int, 0444);
  58 MODULE_PARM_DESC(debug, "Print debugging information.");
  59
  60 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  61
  62 #define dprintk if (debug) printk
  63
  64 #define DEVICE_NAME "ngene"
  65
  66 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  67 #define ngwritel(dat, adr)         writel((dat), (char *)(dev->iomem + (adr)))
  68 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  69 #define ngreadl(adr)               readl(dev->iomem + (adr))
  70 #define ngreadb(adr)               readb(dev->iomem + (adr))
  71 #define ngcpyto(adr, src, count)   memcpy_toio((char *) \
  72                                    (dev->iomem + (adr)), (src), (count))
  73 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
  74                                    (dev->iomem + (adr)), (count))
  75
  76 /****************************************************************************/
  77 /* nGene interrupt handler **************************************************/
  78 /****************************************************************************/
  79
  80 static void event_tasklet(unsigned long data)
  81 {
  82         struct ngene *dev = (struct ngene *)data;
  83
  84         while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
  85                 struct EVENT_BUFFER Event =
  86                         dev->EventQueue[dev->EventQueueReadIndex];
  87                 dev->EventQueueReadIndex =
  88                         (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
  89
  90                 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
  91                         dev->TxEventNotify(dev, Event.TimeStamp);
  92                 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
  93                         dev->RxEventNotify(dev, Event.TimeStamp,
  94                                            Event.RXCharacter);
  95         }
  96 }
  97
  98 static void demux_tasklet(unsigned long data)
  99 {
 100         struct ngene_channel *chan = (struct ngene_channel *)data;
 101         struct SBufferHeader *Cur = chan->nextBuffer;
 102
 103         spin_lock_irq(&chan->state_lock);
 104
 105         while (Cur->ngeneBuffer.SR.Flags & 0x80) {
 106                 if (chan->mode & NGENE_IO_TSOUT) {
 107                         u32 Flags = chan->DataFormatFlags;
 108                         if (Cur->ngeneBuffer.SR.Flags & 0x20)
 109                                 Flags |= BEF_OVERFLOW;
 110                         if (chan->pBufferExchange) {
 111                                 if (!chan->pBufferExchange(chan,
 112                                                            Cur->Buffer1,
 113                                                            chan->Capture1Length,
 114                                                            Cur->ngeneBuffer.SR.
 115                                                            Clock, Flags)) {
 116                                         /*
 117                                            We didn't get data
 118                                            Clear in service flag to make sure we
 119                                            get called on next interrupt again.
 120                                            leave fill/empty (0x80) flag alone
 121                                            to avoid hardware running out of
 122                                            buffers during startup, we hold only
 123                                            in run state ( the source may be late
 124                                            delivering data )
 125                                         */
 126
 127                                         if (chan->HWState == HWSTATE_RUN) {
 128                                                 Cur->ngeneBuffer.SR.Flags &=
 129                                                         ~0x40;
 130                                                 break;
 131                                                 /* Stop proccessing stream */
 132                                         }
 133                                 } else {
 134                                         /* We got a valid buffer,
 135                                            so switch to run state */
 136                                         chan->HWState = HWSTATE_RUN;
 137                                 }
 138                         } else {
 139                                 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
 140                                 if (chan->HWState == HWSTATE_RUN) {
 141                                         Cur->ngeneBuffer.SR.Flags &= ~0x40;
 142                                         break;  /* Stop proccessing stream */
 143                                 }
 144                         }
 145                         if (chan->AudioDTOUpdated) {
 146                                 printk(KERN_INFO DEVICE_NAME
 147                                        ": Update AudioDTO = %d\n",
 148                                        chan->AudioDTOValue);
 149                                 Cur->ngeneBuffer.SR.DTOUpdate =
 150                                         chan->AudioDTOValue;
 151                                 chan->AudioDTOUpdated = 0;
 152                         }
 153                 } else {
 154                         if (chan->HWState == HWSTATE_RUN) {
 155                                 u32 Flags = 0;
 156                                 if (Cur->ngeneBuffer.SR.Flags & 0x01)
 157                                         Flags |= BEF_EVEN_FIELD;
 158                                 if (Cur->ngeneBuffer.SR.Flags & 0x20)
 159                                         Flags |= BEF_OVERFLOW;
 160                                 if (chan->pBufferExchange)
 161                                         chan->pBufferExchange(chan,
 162                                                               Cur->Buffer1,
 163                                                               chan->
 164                                                               Capture1Length,
 165                                                               Cur->ngeneBuffer.
 166                                                               SR.Clock, Flags);
 167                                 if (chan->pBufferExchange2)
 168                                         chan->pBufferExchange2(chan,
 169                                                                Cur->Buffer2,
 170                                                                chan->
 171                                                                Capture2Length,
 172                                                                Cur->ngeneBuffer.
 173                                                                SR.Clock, Flags);
 174                         } else if (chan->HWState != HWSTATE_STOP)
 175                                 chan->HWState = HWSTATE_RUN;
 176                 }
 177                 Cur->ngeneBuffer.SR.Flags = 0x00;
 178                 Cur = Cur->Next;
 179         }
 180         chan->nextBuffer = Cur;
 181
 182         spin_unlock_irq(&chan->state_lock);
 183 }
 184
 185 static irqreturn_t irq_handler(int irq, void *dev_id)
 186 {
 187         struct ngene *dev = (struct ngene *)dev_id;
 188         u32 icounts = 0;
 189         irqreturn_t rc = IRQ_NONE;
 190         u32 i = MAX_STREAM;
 191         u8 *tmpCmdDoneByte;
 192
 193         if (dev->BootFirmware) {
 194                 icounts = ngreadl(NGENE_INT_COUNTS);
 195                 if (icounts != dev->icounts) {
 196                         ngwritel(0, FORCE_NMI);
 197                         dev->cmd_done = 1;
 198                         wake_up(&dev->cmd_wq);
 199                         dev->icounts = icounts;
 200                         rc = IRQ_HANDLED;
 201                 }
 202                 return rc;
 203         }
 204
 205         ngwritel(0, FORCE_NMI);
 206
 207         spin_lock(&dev->cmd_lock);
 208         tmpCmdDoneByte = dev->CmdDoneByte;
 209         if (tmpCmdDoneByte &&
 210             (*tmpCmdDoneByte ||
 211             (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
 212                 dev->CmdDoneByte = NULL;
 213                 dev->cmd_done = 1;
 214                 wake_up(&dev->cmd_wq);
 215                 rc = IRQ_HANDLED;
 216         }
 217         spin_unlock(&dev->cmd_lock);
 218
 219         if (dev->EventBuffer->EventStatus & 0x80) {
 220                 u8 nextWriteIndex =
 221                         (dev->EventQueueWriteIndex + 1) &
 222                         (EVENT_QUEUE_SIZE - 1);
 223                 if (nextWriteIndex != dev->EventQueueReadIndex) {
 224                         dev->EventQueue[dev->EventQueueWriteIndex] =
 225                                 *(dev->EventBuffer);
 226                         dev->EventQueueWriteIndex = nextWriteIndex;
 227                 } else {
 228                         printk(KERN_ERR DEVICE_NAME ": event overflow\n");
 229                         dev->EventQueueOverflowCount += 1;
 230                         dev->EventQueueOverflowFlag = 1;
 231                 }
 232                 dev->EventBuffer->EventStatus &= ~0x80;
 233                 tasklet_schedule(&dev->event_tasklet);
 234                 rc = IRQ_HANDLED;
 235         }
 236
 237         while (i > 0) {
 238                 i--;
 239                 spin_lock(&dev->channel[i].state_lock);
 240                 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
 241                 if (dev->channel[i].nextBuffer) {
 242                         if ((dev->channel[i].nextBuffer->
 243                              ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
 244                                 dev->channel[i].nextBuffer->
 245                                         ngeneBuffer.SR.Flags |= 0x40;
 246                                 tasklet_schedule(
 247                                         &dev->channel[i].demux_tasklet);
 248                                 rc = IRQ_HANDLED;
 249                         }
 250                 }
 251                 spin_unlock(&dev->channel[i].state_lock);
 252         }
 253
 254         return rc;
 255 }
 256
 257 /****************************************************************************/
 258 /* nGene command interface **************************************************/
 259 /****************************************************************************/
 260
 261 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
 262 {
 263         int ret;
 264         u8 *tmpCmdDoneByte;
 265
 266         dev->cmd_done = 0;
 267
 268         if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
 269                 dev->BootFirmware = 1;
 270                 dev->icounts = ngreadl(NGENE_INT_COUNTS);
 271                 ngwritel(0, NGENE_COMMAND);
 272                 ngwritel(0, NGENE_COMMAND_HI);
 273                 ngwritel(0, NGENE_STATUS);
 274                 ngwritel(0, NGENE_STATUS_HI);
 275                 ngwritel(0, NGENE_EVENT);
 276                 ngwritel(0, NGENE_EVENT_HI);
 277         } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
 278                 u64 fwio = dev->PAFWInterfaceBuffer;
 279
 280                 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
 281                 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
 282                 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
 283                 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
 284                 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
 285                 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
 286         }
 287
 288         memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
 289
 290         if (dev->BootFirmware)
 291                 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
 292
 293         spin_lock_irq(&dev->cmd_lock);
 294         tmpCmdDoneByte = dev->ngenetohost + com->out_len;
 295         if (!com->out_len)
 296                 tmpCmdDoneByte++;
 297         *tmpCmdDoneByte = 0;
 298         dev->ngenetohost[0] = 0;
 299         dev->ngenetohost[1] = 0;
 300         dev->CmdDoneByte = tmpCmdDoneByte;
 301         spin_unlock_irq(&dev->cmd_lock);
 302
 303         /* Notify 8051. */
 304         ngwritel(1, FORCE_INT);
 305
 306         ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
 307         if (!ret) {
 308                 /*ngwritel(0, FORCE_NMI);*/
 309
 310                 printk(KERN_ERR DEVICE_NAME
 311                        ": Command timeout cmd=%02x prev=%02x\n",
 312                        com->cmd.hdr.Opcode, dev->prev_cmd);
 313                 return -1;
 314         }
 315         if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
 316                 dev->BootFirmware = 0;
 317
 318         dev->prev_cmd = com->cmd.hdr.Opcode;
 319
 320         if (!com->out_len)
 321                 return 0;
 322
 323         memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
 324
 325         return 0;
 326 }
 327
 328 static int ngene_command(struct ngene *dev, struct ngene_command *com)
 329 {
 330         int result;
 331
 332         down(&dev->cmd_mutex);
 333         result = ngene_command_mutex(dev, com);
 334         up(&dev->cmd_mutex);
 335         return result;
 336 }
 337
 338
 339 static int ngene_command_i2c_read(struct ngene *dev, u8 adr,
 340                            u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
 341 {
 342         struct ngene_command com;
 343
 344         com.cmd.hdr.Opcode = CMD_I2C_READ;
 345         com.cmd.hdr.Length = outlen + 3;
 346         com.cmd.I2CRead.Device = adr << 1;
 347         memcpy(com.cmd.I2CRead.Data, out, outlen);
 348         com.cmd.I2CRead.Data[outlen] = inlen;
 349         com.cmd.I2CRead.Data[outlen + 1] = 0;
 350         com.in_len = outlen + 3;
 351         com.out_len = inlen + 1;
 352
 353         if (ngene_command(dev, &com) < 0)
 354                 return -EIO;
 355
 356         if ((com.cmd.raw8[0] >> 1) != adr)
 357                 return -EIO;
 358
 359         if (flag)
 360                 memcpy(in, com.cmd.raw8, inlen + 1);
 361         else
 362                 memcpy(in, com.cmd.raw8 + 1, inlen);
 363         return 0;
 364 }
 365
 366 static int ngene_command_i2c_write(struct ngene *dev, u8 adr,
 367                                    u8 *out, u8 outlen)
 368 {
 369         struct ngene_command com;
 370
 371
 372         com.cmd.hdr.Opcode = CMD_I2C_WRITE;
 373         com.cmd.hdr.Length = outlen + 1;
 374         com.cmd.I2CRead.Device = adr << 1;
 375         memcpy(com.cmd.I2CRead.Data, out, outlen);
 376         com.in_len = outlen + 1;
 377         com.out_len = 1;
 378
 379         if (ngene_command(dev, &com) < 0)
 380                 return -EIO;
 381
 382         if (com.cmd.raw8[0] == 1)
 383                 return -EIO;
 384
 385         return 0;
 386 }
 387
 388 static int ngene_command_load_firmware(struct ngene *dev,
 389                                        u8 *ngene_fw, u32 size)
 390 {
 391 #define FIRSTCHUNK (1024)
 392         u32 cleft;
 393         struct ngene_command com;
 394
 395         com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
 396         com.cmd.hdr.Length = 0;
 397         com.in_len = 0;
 398         com.out_len = 0;
 399
 400         ngene_command(dev, &com);
 401
 402         cleft = (size + 3) & ~3;
 403         if (cleft > FIRSTCHUNK) {
 404                 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
 405                         cleft - FIRSTCHUNK);
 406                 cleft = FIRSTCHUNK;
 407         }
 408         ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
 409
 410         memset(&com, 0, sizeof(struct ngene_command));
 411         com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
 412         com.cmd.hdr.Length = 4;
 413         com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
 414         com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
 415         com.in_len = 4;
 416         com.out_len = 0;
 417
 418         return ngene_command(dev, &com);
 419 }
 420
 421
 422 static int ngene_command_config_buf(struct ngene *dev, u8 config)
 423 {
 424         struct ngene_command com;
 425
 426         com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
 427         com.cmd.hdr.Length = 1;
 428         com.cmd.ConfigureBuffers.config = config;
 429         com.in_len = 1;
 430         com.out_len = 0;
 431
 432         if (ngene_command(dev, &com) < 0)
 433                 return -EIO;
 434         return 0;
 435 }
 436
 437 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
 438 {
 439         struct ngene_command com;
 440
 441         com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
 442         com.cmd.hdr.Length = 6;
 443         memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
 444         com.in_len = 6;
 445         com.out_len = 0;
 446
 447         if (ngene_command(dev, &com) < 0)
 448                 return -EIO;
 449
 450         return 0;
 451 }
 452
 453 static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
 454 {
 455         struct ngene_command com;
 456
 457         com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
 458         com.cmd.hdr.Length = 1;
 459         com.cmd.SetGpioPin.select = select | (level << 7);
 460         com.in_len = 1;
 461         com.out_len = 0;
 462
 463         return ngene_command(dev, &com);
 464 }
 465
 466
 467 /*
 468  02000640 is sample on rising edge.
 469  02000740 is sample on falling edge.
 470  02000040 is ignore "valid" signal
 471
 472  0: FD_CTL1 Bit 7,6 must be 0,1
 473     7   disable(fw controlled)
 474     6   0-AUX,1-TS
 475     5   0-par,1-ser
 476     4   0-lsb/1-msb
 477     3,2 reserved
 478     1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
 479  1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
 480  2: FD_STA is read-only. 0-sync
 481  3: FD_INSYNC is number of 47s to trigger "in sync".
 482  4: FD_OUTSYNC is number of 47s to trigger "out of sync".
 483  5: FD_MAXBYTE1 is low-order of bytes per packet.
 484  6: FD_MAXBYTE2 is high-order of bytes per packet.
 485  7: Top byte is unused.
 486 */
 487
 488 /****************************************************************************/
 489
 490 static u8 TSFeatureDecoderSetup[8 * 4] = {
 491         0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
 492         0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
 493         0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
 494         0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
 495 };
 496
 497 /* Set NGENE I2S Config to 16 bit packed */
 498 static u8 I2SConfiguration[] = {
 499         0x00, 0x10, 0x00, 0x00,
 500         0x80, 0x10, 0x00, 0x00,
 501 };
 502
 503 static u8 SPDIFConfiguration[10] = {
 504         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 505 };
 506
 507 /* Set NGENE I2S Config to transport stream compatible mode */
 508
 509 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
 510
 511 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
 512
 513 static u8 ITUDecoderSetup[4][16] = {
 514         {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20,  /* SDTV */
 515          0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
 516         {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
 517          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 518         {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00,  /* HDTV 1080i50 */
 519          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 520         {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,  /* HDTV 1080i60 */
 521          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 522 };
 523
 524 /*
 525  * 50 48 60 gleich
 526  * 27p50 9f 00 22 80 42 69 18 ...
 527  * 27p60 93 00 22 80 82 69 1c ...
 528  */
 529
 530 /* Maxbyte to 1144 (for raw data) */
 531 static u8 ITUFeatureDecoderSetup[8] = {
 532         0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
 533 };
 534
 535 static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
 536 {
 537         u32 *ptr = Buffer;
 538
 539         memset(Buffer, Length, 0xff);
 540         while (Length > 0) {
 541                 if (Flags & DF_SWAP32)
 542                         *ptr = 0x471FFF10;
 543                 else
 544                         *ptr = 0x10FF1F47;
 545                 ptr += (188 / 4);
 546                 Length -= 188;
 547         }
 548 }
 549
 550
 551 static void flush_buffers(struct ngene_channel *chan)
 552 {
 553         u8 val;
 554
 555         do {
 556                 msleep(1);
 557                 spin_lock_irq(&chan->state_lock);
 558                 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
 559                 spin_unlock_irq(&chan->state_lock);
 560         } while (val);
 561 }
 562
 563 static void clear_buffers(struct ngene_channel *chan)
 564 {
 565         struct SBufferHeader *Cur = chan->nextBuffer;
 566
 567         do {
 568                 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
 569                 if (chan->mode & NGENE_IO_TSOUT)
 570                         FillTSBuffer(Cur->Buffer1,
 571                                      chan->Capture1Length,
 572                                      chan->DataFormatFlags);
 573                 Cur = Cur->Next;
 574         } while (Cur != chan->nextBuffer);
 575
 576         if (chan->mode & NGENE_IO_TSOUT) {
 577                 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
 578                         chan->AudioDTOValue;
 579                 chan->AudioDTOUpdated = 0;
 580
 581                 Cur = chan->TSIdleBuffer.Head;
 582
 583                 do {
 584                         memset(&Cur->ngeneBuffer.SR, 0,
 585                                sizeof(Cur->ngeneBuffer.SR));
 586                         FillTSBuffer(Cur->Buffer1,
 587                                      chan->Capture1Length,
 588                                      chan->DataFormatFlags);
 589                         Cur = Cur->Next;
 590                 } while (Cur != chan->TSIdleBuffer.Head);
 591         }
 592 }
 593
 594 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
 595                                         u8 control, u8 mode, u8 flags)
 596 {
 597         struct ngene_channel *chan = &dev->channel[stream];
 598         struct ngene_command com;
 599         u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
 600         u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
 601         u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
 602         u16 BsSDO = 0x9B00;
 603
 604         /* down(&dev->stream_mutex); */
 605         while (down_trylock(&dev->stream_mutex)) {
 606                 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
 607                 msleep(1);
 608         }
 609         memset(&com, 0, sizeof(com));
 610         com.cmd.hdr.Opcode = CMD_CONTROL;
 611         com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
 612         com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
 613         if (chan->mode & NGENE_IO_TSOUT)
 614                 com.cmd.StreamControl.Stream |= 0x07;
 615         com.cmd.StreamControl.Control = control |
 616                 (flags & SFLAG_ORDER_LUMA_CHROMA);
 617         com.cmd.StreamControl.Mode = mode;
 618         com.in_len = sizeof(struct FW_STREAM_CONTROL);
 619         com.out_len = 0;
 620
 621         dprintk(KERN_INFO DEVICE_NAME
 622                 ": Stream=%02x, Control=%02x, Mode=%02x\n",
 623                 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
 624                 com.cmd.StreamControl.Mode);
 625
 626         chan->Mode = mode;
 627
 628         if (!(control & 0x80)) {
 629                 spin_lock_irq(&chan->state_lock);
 630                 if (chan->State == KSSTATE_RUN) {
 631                         chan->State = KSSTATE_ACQUIRE;
 632                         chan->HWState = HWSTATE_STOP;
 633                         spin_unlock_irq(&chan->state_lock);
 634                         if (ngene_command(dev, &com) < 0) {
 635                                 up(&dev->stream_mutex);
 636                                 return -1;
 637                         }
 638                         /* clear_buffers(chan); */
 639                         flush_buffers(chan);
 640                         up(&dev->stream_mutex);
 641                         return 0;
 642                 }
 643                 spin_unlock_irq(&chan->state_lock);
 644                 up(&dev->stream_mutex);
 645                 return 0;
 646         }
 647
 648         if (mode & SMODE_AUDIO_CAPTURE) {
 649                 com.cmd.StreamControl.CaptureBlockCount =
 650                         chan->Capture1Length / AUDIO_BLOCK_SIZE;
 651                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 652         } else if (mode & SMODE_TRANSPORT_STREAM) {
 653                 com.cmd.StreamControl.CaptureBlockCount =
 654                         chan->Capture1Length / TS_BLOCK_SIZE;
 655                 com.cmd.StreamControl.MaxLinesPerField =
 656                         chan->Capture1Length / TS_BLOCK_SIZE;
 657                 com.cmd.StreamControl.Buffer_Address =
 658                         chan->TSRingBuffer.PAHead;
 659                 if (chan->mode & NGENE_IO_TSOUT) {
 660                         com.cmd.StreamControl.BytesPerVBILine =
 661                                 chan->Capture1Length / TS_BLOCK_SIZE;
 662                         com.cmd.StreamControl.Stream |= 0x07;
 663                 }
 664         } else {
 665                 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
 666                 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
 667                 com.cmd.StreamControl.MinLinesPerField = 100;
 668                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 669
 670                 if (mode & SMODE_VBI_CAPTURE) {
 671                         com.cmd.StreamControl.MaxVBILinesPerField =
 672                                 chan->nVBILines;
 673                         com.cmd.StreamControl.MinVBILinesPerField = 0;
 674                         com.cmd.StreamControl.BytesPerVBILine =
 675                                 chan->nBytesPerVBILine;
 676                 }
 677                 if (flags & SFLAG_COLORBAR)
 678                         com.cmd.StreamControl.Stream |= 0x04;
 679         }
 680
 681         spin_lock_irq(&chan->state_lock);
 682         if (mode & SMODE_AUDIO_CAPTURE) {
 683                 chan->nextBuffer = chan->RingBuffer.Head;
 684                 if (mode & SMODE_AUDIO_SPDIF) {
 685                         com.cmd.StreamControl.SetupDataLen =
 686                                 sizeof(SPDIFConfiguration);
 687                         com.cmd.StreamControl.SetupDataAddr = BsSPI;
 688                         memcpy(com.cmd.StreamControl.SetupData,
 689                                SPDIFConfiguration, sizeof(SPDIFConfiguration));
 690                 } else {
 691                         com.cmd.StreamControl.SetupDataLen = 4;
 692                         com.cmd.StreamControl.SetupDataAddr = BsSDI;
 693                         memcpy(com.cmd.StreamControl.SetupData,
 694                                I2SConfiguration +
 695                                4 * dev->card_info->i2s[stream], 4);
 696                 }
 697         } else if (mode & SMODE_TRANSPORT_STREAM) {
 698                 chan->nextBuffer = chan->TSRingBuffer.Head;
 699                 if (stream >= STREAM_AUDIOIN1) {
 700                         if (chan->mode & NGENE_IO_TSOUT) {
 701                                 com.cmd.StreamControl.SetupDataLen =
 702                                         sizeof(TS_I2SOutConfiguration);
 703                                 com.cmd.StreamControl.SetupDataAddr = BsSDO;
 704                                 memcpy(com.cmd.StreamControl.SetupData,
 705                                        TS_I2SOutConfiguration,
 706                                        sizeof(TS_I2SOutConfiguration));
 707                         } else {
 708                                 com.cmd.StreamControl.SetupDataLen =
 709                                         sizeof(TS_I2SConfiguration);
 710                                 com.cmd.StreamControl.SetupDataAddr = BsSDI;
 711                                 memcpy(com.cmd.StreamControl.SetupData,
 712                                        TS_I2SConfiguration,
 713                                        sizeof(TS_I2SConfiguration));
 714                         }
 715                 } else {
 716                         com.cmd.StreamControl.SetupDataLen = 8;
 717                         com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
 718                         memcpy(com.cmd.StreamControl.SetupData,
 719                                TSFeatureDecoderSetup +
 720                                8 * dev->card_info->tsf[stream], 8);
 721                 }
 722         } else {
 723                 chan->nextBuffer = chan->RingBuffer.Head;
 724                 com.cmd.StreamControl.SetupDataLen =
 725                         16 + sizeof(ITUFeatureDecoderSetup);
 726                 com.cmd.StreamControl.SetupDataAddr = BsUVI;
 727                 memcpy(com.cmd.StreamControl.SetupData,
 728                        ITUDecoderSetup[chan->itumode], 16);
 729                 memcpy(com.cmd.StreamControl.SetupData + 16,
 730                        ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
 731         }
 732         clear_buffers(chan);
 733         chan->State = KSSTATE_RUN;
 734         if (mode & SMODE_TRANSPORT_STREAM)
 735                 chan->HWState = HWSTATE_RUN;
 736         else
 737                 chan->HWState = HWSTATE_STARTUP;
 738         spin_unlock_irq(&chan->state_lock);
 739
 740         if (ngene_command(dev, &com) < 0) {
 741                 up(&dev->stream_mutex);
 742                 return -1;
 743         }
 744         up(&dev->stream_mutex);
 745         return 0;
 746 }
 747
 748
 749 /****************************************************************************/
 750 /* I2C **********************************************************************/
 751 /****************************************************************************/
 752
 753 static void ngene_i2c_set_bus(struct ngene *dev, int bus)
 754 {
 755         if (!(dev->card_info->i2c_access & 2))
 756                 return;
 757         if (dev->i2c_current_bus == bus)
 758                 return;
 759
 760         switch (bus) {
 761         case 0:
 762                 ngene_command_gpio_set(dev, 3, 0);
 763                 ngene_command_gpio_set(dev, 2, 1);
 764                 break;
 765
 766         case 1:
 767                 ngene_command_gpio_set(dev, 2, 0);
 768                 ngene_command_gpio_set(dev, 3, 1);
 769                 break;
 770         }
 771         dev->i2c_current_bus = bus;
 772 }
 773
 774 static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
 775                                  struct i2c_msg msg[], int num)
 776 {
 777         struct ngene_channel *chan =
 778                 (struct ngene_channel *)i2c_get_adapdata(adapter);
 779         struct ngene *dev = chan->dev;
 780
 781         down(&dev->i2c_switch_mutex);
 782         ngene_i2c_set_bus(dev, chan->number);
 783
 784         if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
 785                 if (!ngene_command_i2c_read(dev, msg[0].addr,
 786                                             msg[0].buf, msg[0].len,
 787                                             msg[1].buf, msg[1].len, 0))
 788                         goto done;
 789
 790         if (num == 1 && !(msg[0].flags & I2C_M_RD))
 791                 if (!ngene_command_i2c_write(dev, msg[0].addr,
 792                                              msg[0].buf, msg[0].len))
 793                         goto done;
 794         if (num == 1 && (msg[0].flags & I2C_M_RD))
 795                 if (!ngene_command_i2c_read(dev, msg[0].addr, 0, 0,
 796                                             msg[0].buf, msg[0].len, 0))
 797                         goto done;
 798
 799         up(&dev->i2c_switch_mutex);
 800         return -EIO;
 801
 802 done:
 803         up(&dev->i2c_switch_mutex);
 804         return num;
 805 }
 806
 807
 808 static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
 809 {
 810         return I2C_FUNC_SMBUS_EMUL;
 811 }
 812
 813 static struct i2c_algorithm ngene_i2c_algo = {
 814         .master_xfer = ngene_i2c_master_xfer,
 815         .functionality = ngene_i2c_functionality,
 816 };
 817
 818 static int ngene_i2c_init(struct ngene *dev, int dev_nr)
 819 {
 820         struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
 821
 822         i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
 823 #ifdef I2C_ADAP_CLASS_TV_DIGITAL
 824         adap->class = I2C_ADAP_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
 825 #else
 826         adap->class = I2C_CLASS_TV_ANALOG;
 827 #endif
 828
 829         strcpy(adap->name, "nGene");
 830
 831         adap->algo = &ngene_i2c_algo;
 832         adap->algo_data = (void *)&(dev->channel[dev_nr]);
 833         adap->dev.parent = &dev->pci_dev->dev;
 834
 835         mutex_init(&adap->bus_lock);
 836         return i2c_add_adapter(adap);
 837 }
 838
 839
 840 /****************************************************************************/
 841 /* DVB functions and API interface ******************************************/
 842 /****************************************************************************/
 843
 844 static void swap_buffer(u32 *p, u32 len)
 845 {
 846         while (len) {
 847                 *p = swab32(*p);
 848                 p++;
 849                 len -= 4;
 850         }
 851 }
 852
 853
 854 static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
 855 {
 856         struct ngene_channel *chan = priv;
 857
 858
 859         dvb_dmx_swfilter(&chan->demux, buf, len);
 860         return 0;
 861 }
 862
 863 u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
 864
 865 static void *tsout_exchange(void *priv, void *buf, u32 len,
 866                             u32 clock, u32 flags)
 867 {
 868         struct ngene_channel *chan = priv;
 869         struct ngene *dev = chan->dev;
 870         u32 alen;
 871
 872         alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
 873         alen -= alen % 188;
 874
 875         if (alen < len)
 876                 FillTSBuffer(buf + alen, len - alen, flags);
 877         else
 878                 alen = len;
 879         dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
 880         if (flags & DF_SWAP32)
 881                 swap_buffer((u32 *)buf, alen);
 882         wake_up_interruptible(&dev->tsout_rbuf.queue);
 883         return buf;
 884 }
 885
 886
 887 static void set_transfer(struct ngene_channel *chan, int state)
 888 {
 889         u8 control = 0, mode = 0, flags = 0;
 890         struct ngene *dev = chan->dev;
 891         int ret;
 892
 893         /*
 894         if (chan->running)
 895                 return;
 896         */
 897
 898         /*
 899         printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
 900         msleep(100);
 901         */
 902
 903         if (state) {
 904                 if (chan->running) {
 905                         printk(KERN_INFO DEVICE_NAME ": already running\n");
 906                         return;
 907                 }
 908         } else {
 909                 if (!chan->running) {
 910                         printk(KERN_INFO DEVICE_NAME ": already stopped\n");
 911                         return;
 912                 }
 913         }
 914
 915         if (dev->card_info->switch_ctrl)
 916                 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
 917
 918         if (state) {
 919                 spin_lock_irq(&chan->state_lock);
 920
 921                 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
 922                           ngreadl(0x9310)); */
 923                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 924                 control = 0x80;
 925                 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
 926                         chan->Capture1Length = 512 * 188;
 927                         mode = SMODE_TRANSPORT_STREAM;
 928                 }
 929                 if (chan->mode & NGENE_IO_TSOUT) {
 930                         chan->pBufferExchange = tsout_exchange;
 931                         /* 0x66666666 = 50MHz *2^33 /250MHz */
 932                         chan->AudioDTOValue = 0x66666666;
 933                         /* set_dto(chan, 38810700+1000); */
 934                         /* set_dto(chan, 19392658); */
 935                 }
 936                 if (chan->mode & NGENE_IO_TSIN)
 937                         chan->pBufferExchange = tsin_exchange;
 938                 /* ngwritel(0, 0x9310); */
 939                 spin_unlock_irq(&chan->state_lock);
 940         } else
 941                 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
 942                            ngreadl(0x9310)); */
 943
 944         ret = ngene_command_stream_control(dev, chan->number,
 945                                            control, mode, flags);
 946         if (!ret)
 947                 chan->running = state;
 948         else
 949                 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
 950                        state);
 951         if (!state) {
 952                 spin_lock_irq(&chan->state_lock);
 953                 chan->pBufferExchange = 0;
 954                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 955                 spin_unlock_irq(&chan->state_lock);
 956         }
 957 }
 958
 959 static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
 960 {
 961         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
 962         struct ngene_channel *chan = dvbdmx->priv;
 963
 964         if (chan->users == 0) {
 965                 set_transfer(chan, 1);
 966                 /* msleep(10); */
 967         }
 968
 969         return ++chan->users;
 970 }
 971
 972 static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
 973 {
 974         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
 975         struct ngene_channel *chan = dvbdmx->priv;
 976
 977         if (--chan->users)
 978                 return chan->users;
 979
 980         set_transfer(chan, 0);
 981
 982         return 0;
 983 }
 984
 985
 986
 987 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
 988                                    int (*start_feed)(struct dvb_demux_feed *),
 989                                    int (*stop_feed)(struct dvb_demux_feed *),
 990                                    void *priv)
 991 {
 992         dvbdemux->priv = priv;
 993
 994         dvbdemux->filternum = 256;
 995         dvbdemux->feednum = 256;
 996         dvbdemux->start_feed = start_feed;
 997         dvbdemux->stop_feed = stop_feed;
 998         dvbdemux->write_to_decoder = 0;
 999         dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
1000                                       DMX_SECTION_FILTERING |
1001                                       DMX_MEMORY_BASED_FILTERING);
1002         return dvb_dmx_init(dvbdemux);
1003 }
1004
1005 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
1006                                       struct dvb_demux *dvbdemux,
1007                                       struct dmx_frontend *hw_frontend,
1008                                       struct dmx_frontend *mem_frontend,
1009                                       struct dvb_adapter *dvb_adapter)
1010 {
1011         int ret;
1012
1013         dmxdev->filternum = 256;
1014         dmxdev->demux = &dvbdemux->dmx;
1015         dmxdev->capabilities = 0;
1016         ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
1017         if (ret < 0)
1018                 return ret;
1019
1020         hw_frontend->source = DMX_FRONTEND_0;
1021         dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
1022         mem_frontend->source = DMX_MEMORY_FE;
1023         dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
1024         return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
1025 }
1026
1027
1028 /****************************************************************************/
1029 /* nGene hardware init and release functions ********************************/
1030 /****************************************************************************/
1031
1032 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
1033 {
1034         struct SBufferHeader *Cur = rb->Head;
1035         u32 j;
1036
1037         if (!Cur)
1038                 return;
1039
1040         for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
1041                 if (Cur->Buffer1)
1042                         pci_free_consistent(dev->pci_dev,
1043                                             rb->Buffer1Length,
1044                                             Cur->Buffer1,
1045                                             Cur->scList1->Address);
1046
1047                 if (Cur->Buffer2)
1048                         pci_free_consistent(dev->pci_dev,
1049                                             rb->Buffer2Length,
1050                                             Cur->Buffer2,
1051                                             Cur->scList2->Address);
1052         }
1053
1054         if (rb->SCListMem)
1055                 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
1056                                     rb->SCListMem, rb->PASCListMem);
1057
1058         pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
1059 }
1060
1061 static void free_idlebuffer(struct ngene *dev,
1062                      struct SRingBufferDescriptor *rb,
1063                      struct SRingBufferDescriptor *tb)
1064 {
1065         int j;
1066         struct SBufferHeader *Cur = tb->Head;
1067
1068         if (!rb->Head)
1069                 return;
1070         free_ringbuffer(dev, rb);
1071         for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
1072                 Cur->Buffer2 = 0;
1073                 Cur->scList2 = 0;
1074                 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
1075                 Cur->ngeneBuffer.Number_of_entries_2 = 0;
1076         }
1077 }
1078
1079 static void free_common_buffers(struct ngene *dev)
1080 {
1081         u32 i;
1082         struct ngene_channel *chan;
1083
1084         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1085                 chan = &dev->channel[i];
1086                 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
1087                 free_ringbuffer(dev, &chan->RingBuffer);
1088                 free_ringbuffer(dev, &chan->TSRingBuffer);
1089         }
1090
1091         if (dev->OverflowBuffer)
1092                 pci_free_consistent(dev->pci_dev,
1093                                     OVERFLOW_BUFFER_SIZE,
1094                                     dev->OverflowBuffer, dev->PAOverflowBuffer);
1095
1096         if (dev->FWInterfaceBuffer)
1097                 pci_free_consistent(dev->pci_dev,
1098                                     4096,
1099                                     dev->FWInterfaceBuffer,
1100                                     dev->PAFWInterfaceBuffer);
1101 }
1102
1103 /****************************************************************************/
1104 /* Ring buffer handling *****************************************************/
1105 /****************************************************************************/
1106
1107 static int create_ring_buffer(struct pci_dev *pci_dev,
1108                        struct SRingBufferDescriptor *descr, u32 NumBuffers)
1109 {
1110         dma_addr_t tmp;
1111         struct SBufferHeader *Head;
1112         u32 i;
1113         u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
1114         u64 PARingBufferHead;
1115         u64 PARingBufferCur;
1116         u64 PARingBufferNext;
1117         struct SBufferHeader *Cur, *Next;
1118
1119         descr->Head = 0;
1120         descr->MemSize = 0;
1121         descr->PAHead = 0;
1122         descr->NumBuffers = 0;
1123
1124         if (MemSize < 4096)
1125                 MemSize = 4096;
1126
1127         Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
1128         PARingBufferHead = tmp;
1129
1130         if (!Head)
1131                 return -ENOMEM;
1132
1133         memset(Head, 0, MemSize);
1134
1135         PARingBufferCur = PARingBufferHead;
1136         Cur = Head;
1137
1138         for (i = 0; i < NumBuffers - 1; i++) {
1139                 Next = (struct SBufferHeader *)
1140                         (((u8 *) Cur) + SIZEOF_SBufferHeader);
1141                 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
1142                 Cur->Next = Next;
1143                 Cur->ngeneBuffer.Next = PARingBufferNext;
1144                 Cur = Next;
1145                 PARingBufferCur = PARingBufferNext;
1146         }
1147         /* Last Buffer points back to first one */
1148         Cur->Next = Head;
1149         Cur->ngeneBuffer.Next = PARingBufferHead;
1150
1151         descr->Head       = Head;
1152         descr->MemSize    = MemSize;
1153         descr->PAHead     = PARingBufferHead;
1154         descr->NumBuffers = NumBuffers;
1155
1156         return 0;
1157 }
1158
1159 static int AllocateRingBuffers(struct pci_dev *pci_dev,
1160                                dma_addr_t of,
1161                                struct SRingBufferDescriptor *pRingBuffer,
1162                                u32 Buffer1Length, u32 Buffer2Length)
1163 {
1164         dma_addr_t tmp;
1165         u32 i, j;
1166         int status = 0;
1167         u32 SCListMemSize = pRingBuffer->NumBuffers
1168                 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
1169                     NUM_SCATTER_GATHER_ENTRIES)
1170                 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1171
1172         u64 PASCListMem;
1173         PHW_SCATTER_GATHER_ELEMENT SCListEntry;
1174         u64 PASCListEntry;
1175         struct SBufferHeader *Cur;
1176         void *SCListMem;
1177
1178         if (SCListMemSize < 4096)
1179                 SCListMemSize = 4096;
1180
1181         SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
1182
1183         PASCListMem = tmp;
1184         if (SCListMem == NULL)
1185                 return -ENOMEM;
1186
1187         memset(SCListMem, 0, SCListMemSize);
1188
1189         pRingBuffer->SCListMem = SCListMem;
1190         pRingBuffer->PASCListMem = PASCListMem;
1191         pRingBuffer->SCListMemSize = SCListMemSize;
1192         pRingBuffer->Buffer1Length = Buffer1Length;
1193         pRingBuffer->Buffer2Length = Buffer2Length;
1194
1195         SCListEntry = (PHW_SCATTER_GATHER_ELEMENT) SCListMem;
1196         PASCListEntry = PASCListMem;
1197         Cur = pRingBuffer->Head;
1198
1199         for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
1200                 u64 PABuffer;
1201
1202                 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
1203                                                     &tmp);
1204                 PABuffer = tmp;
1205
1206                 if (Buffer == NULL)
1207                         return -ENOMEM;
1208
1209                 Cur->Buffer1 = Buffer;
1210
1211                 SCListEntry->Address = PABuffer;
1212                 SCListEntry->Length  = Buffer1Length;
1213
1214                 Cur->scList1 = SCListEntry;
1215                 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
1216                 Cur->ngeneBuffer.Number_of_entries_1 =
1217                         NUM_SCATTER_GATHER_ENTRIES;
1218
1219                 SCListEntry += 1;
1220                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1221
1222 #if NUM_SCATTER_GATHER_ENTRIES > 1
1223                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
1224                         SCListEntry->Address = of;
1225                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1226                         SCListEntry += 1;
1227                         PASCListEntry +=
1228                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1229                 }
1230 #endif
1231
1232                 if (!Buffer2Length)
1233                         continue;
1234
1235                 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
1236                 PABuffer = tmp;
1237
1238                 if (Buffer == NULL)
1239                         return -ENOMEM;
1240
1241                 Cur->Buffer2 = Buffer;
1242
1243                 SCListEntry->Address = PABuffer;
1244                 SCListEntry->Length  = Buffer2Length;
1245
1246                 Cur->scList2 = SCListEntry;
1247                 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1248                 Cur->ngeneBuffer.Number_of_entries_2 =
1249                         NUM_SCATTER_GATHER_ENTRIES;
1250
1251                 SCListEntry   += 1;
1252                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1253
1254 #if NUM_SCATTER_GATHER_ENTRIES > 1
1255                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1256                         SCListEntry->Address = of;
1257                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1258                         SCListEntry += 1;
1259                         PASCListEntry +=
1260                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1261                 }
1262 #endif
1263
1264         }
1265
1266         return status;
1267 }
1268
1269 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1270                             struct SRingBufferDescriptor *pRingBuffer)
1271 {
1272         int status = 0;
1273
1274         /* Copy pointer to scatter gather list in TSRingbuffer
1275            structure for buffer 2
1276            Load number of buffer
1277         */
1278         u32 n = pRingBuffer->NumBuffers;
1279
1280         /* Point to first buffer entry */
1281         struct SBufferHeader *Cur = pRingBuffer->Head;
1282         int i;
1283         /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1284         for (i = 0; i < n; i++) {
1285                 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1286                 Cur->scList2 = pIdleBuffer->Head->scList1;
1287                 Cur->ngeneBuffer.Address_of_first_entry_2 =
1288                         pIdleBuffer->Head->ngeneBuffer.
1289                         Address_of_first_entry_1;
1290                 Cur->ngeneBuffer.Number_of_entries_2 =
1291                         pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1292                 Cur = Cur->Next;
1293         }
1294         return status;
1295 }
1296
1297 static u32 RingBufferSizes[MAX_STREAM] = {
1298         RING_SIZE_VIDEO,
1299         RING_SIZE_VIDEO,
1300         RING_SIZE_AUDIO,
1301         RING_SIZE_AUDIO,
1302         RING_SIZE_AUDIO,
1303 };
1304
1305 static u32 Buffer1Sizes[MAX_STREAM] = {
1306         MAX_VIDEO_BUFFER_SIZE,
1307         MAX_VIDEO_BUFFER_SIZE,
1308         MAX_AUDIO_BUFFER_SIZE,
1309         MAX_AUDIO_BUFFER_SIZE,
1310         MAX_AUDIO_BUFFER_SIZE
1311 };
1312
1313 static u32 Buffer2Sizes[MAX_STREAM] = {
1314         MAX_VBI_BUFFER_SIZE,
1315         MAX_VBI_BUFFER_SIZE,
1316         0,
1317         0,
1318         0
1319 };
1320
1321
1322 static int AllocCommonBuffers(struct ngene *dev)
1323 {
1324         int status = 0, i;
1325
1326         dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1327                                                      &dev->PAFWInterfaceBuffer);
1328         if (!dev->FWInterfaceBuffer)
1329                 return -ENOMEM;
1330         dev->hosttongene = dev->FWInterfaceBuffer;
1331         dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1332         dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1333
1334         dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1335                                                    OVERFLOW_BUFFER_SIZE,
1336                                                    &dev->PAOverflowBuffer);
1337         if (!dev->OverflowBuffer)
1338                 return -ENOMEM;
1339         memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1340
1341         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1342                 int type = dev->card_info->io_type[i];
1343
1344                 dev->channel[i].State = KSSTATE_STOP;
1345
1346                 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1347                         status = create_ring_buffer(dev->pci_dev,
1348                                                     &dev->channel[i].RingBuffer,
1349                                                     RingBufferSizes[i]);
1350                         if (status < 0)
1351                                 break;
1352
1353                         if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1354                                 status = AllocateRingBuffers(dev->pci_dev,
1355                                                              dev->
1356                                                              PAOverflowBuffer,
1357                                                              &dev->channel[i].
1358                                                              RingBuffer,
1359                                                              Buffer1Sizes[i],
1360                                                              Buffer2Sizes[i]);
1361                                 if (status < 0)
1362                                         break;
1363                         } else if (type & NGENE_IO_HDTV) {
1364                                 status = AllocateRingBuffers(dev->pci_dev,
1365                                                              dev->
1366                                                              PAOverflowBuffer,
1367                                                              &dev->channel[i].
1368                                                              RingBuffer,
1369                                                            MAX_HDTV_BUFFER_SIZE,
1370                                                              0);
1371                                 if (status < 0)
1372                                         break;
1373                         }
1374                 }
1375
1376                 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1377
1378                         status = create_ring_buffer(dev->pci_dev,
1379                                                     &dev->channel[i].
1380                                                     TSRingBuffer, RING_SIZE_TS);
1381                         if (status < 0)
1382                                 break;
1383
1384                         status = AllocateRingBuffers(dev->pci_dev,
1385                                                      dev->PAOverflowBuffer,
1386                                                      &dev->channel[i].
1387                                                      TSRingBuffer,
1388                                                      MAX_TS_BUFFER_SIZE, 0);
1389                         if (status)
1390                                 break;
1391                 }
1392
1393                 if (type & NGENE_IO_TSOUT) {
1394                         status = create_ring_buffer(dev->pci_dev,
1395                                                     &dev->channel[i].
1396                                                     TSIdleBuffer, 1);
1397                         if (status < 0)
1398                                 break;
1399                         status = AllocateRingBuffers(dev->pci_dev,
1400                                                      dev->PAOverflowBuffer,
1401                                                      &dev->channel[i].
1402                                                      TSIdleBuffer,
1403                                                      MAX_TS_BUFFER_SIZE, 0);
1404                         if (status)
1405                                 break;
1406                         FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1407                                          &dev->channel[i].TSRingBuffer);
1408                 }
1409         }
1410         return status;
1411 }
1412
1413 static void ngene_release_buffers(struct ngene *dev)
1414 {
1415         if (dev->iomem)
1416                 iounmap(dev->iomem);
1417         free_common_buffers(dev);
1418         vfree(dev->tsout_buf);
1419         vfree(dev->ain_buf);
1420         vfree(dev->vin_buf);
1421         vfree(dev);
1422 }
1423
1424 static int ngene_get_buffers(struct ngene *dev)
1425 {
1426         if (AllocCommonBuffers(dev))
1427                 return -ENOMEM;
1428         if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1429                 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1430                 if (!dev->tsout_buf)
1431                         return -ENOMEM;
1432                 dvb_ringbuffer_init(&dev->tsout_rbuf,
1433                                     dev->tsout_buf, TSOUT_BUF_SIZE);
1434         }
1435         if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1436                 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1437                 if (!dev->ain_buf)
1438                         return -ENOMEM;
1439                 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1440         }
1441         if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1442                 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1443                 if (!dev->vin_buf)
1444                         return -ENOMEM;
1445                 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1446         }
1447         dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1448                              pci_resource_len(dev->pci_dev, 0));
1449         if (!dev->iomem)
1450                 return -ENOMEM;
1451
1452         return 0;
1453 }
1454
1455 static void ngene_init(struct ngene *dev)
1456 {
1457         int i;
1458
1459         tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1460
1461         memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1462         memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1463
1464         for (i = 0; i < MAX_STREAM; i++) {
1465                 dev->channel[i].dev = dev;
1466                 dev->channel[i].number = i;
1467         }
1468
1469         dev->fw_interface_version = 0;
1470
1471         ngwritel(0, NGENE_INT_ENABLE);
1472
1473         dev->icounts = ngreadl(NGENE_INT_COUNTS);
1474
1475         dev->device_version = ngreadl(DEV_VER) & 0x0f;
1476         printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1477                dev->device_version);
1478 }
1479
1480 static int ngene_load_firm(struct ngene *dev)
1481 {
1482         u32 size;
1483         const struct firmware *fw = NULL;
1484         u8 *ngene_fw;
1485         char *fw_name;
1486         int err, version;
1487
1488         version = dev->card_info->fw_version;
1489
1490         switch (version) {
1491         default:
1492         case 15:
1493                 version = 15;
1494                 size = 23466;
1495                 fw_name = "ngene_15.fw";
1496                 break;
1497         case 16:
1498                 size = 23498;
1499                 fw_name = "ngene_16.fw";
1500                 break;
1501         case 17:
1502                 size = 24446;
1503                 fw_name = "ngene_17.fw";
1504                 break;
1505         }
1506
1507         if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1508                 printk(KERN_ERR DEVICE_NAME
1509                         ": Could not load firmware file %s.\n", fw_name);
1510                 printk(KERN_INFO DEVICE_NAME
1511                         ": Copy %s to your hotplug directory!\n", fw_name);
1512                 return -1;
1513         }
1514         if (size != fw->size) {
1515                 printk(KERN_ERR DEVICE_NAME
1516                         ": Firmware %s has invalid size!", fw_name);
1517                 err = -1;
1518         } else {
1519                 printk(KERN_INFO DEVICE_NAME
1520                         ": Loading firmware file %s.\n", fw_name);
1521                 ngene_fw = (u8 *) fw->data;
1522                 err = ngene_command_load_firmware(dev, ngene_fw, size);
1523         }
1524
1525         release_firmware(fw);
1526
1527         return err;
1528 }
1529
1530 static void ngene_stop(struct ngene *dev)
1531 {
1532         down(&dev->cmd_mutex);
1533         i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1534         i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1535         ngwritel(0, NGENE_INT_ENABLE);
1536         ngwritel(0, NGENE_COMMAND);
1537         ngwritel(0, NGENE_COMMAND_HI);
1538         ngwritel(0, NGENE_STATUS);
1539         ngwritel(0, NGENE_STATUS_HI);
1540         ngwritel(0, NGENE_EVENT);
1541         ngwritel(0, NGENE_EVENT_HI);
1542         free_irq(dev->pci_dev->irq, dev);
1543 }
1544
1545 static int ngene_start(struct ngene *dev)
1546 {
1547         int stat;
1548         int i;
1549
1550         pci_set_master(dev->pci_dev);
1551         ngene_init(dev);
1552
1553         stat = request_irq(dev->pci_dev->irq, irq_handler,
1554                            IRQF_SHARED, "nGene",
1555                            (void *)dev);
1556         if (stat < 0)
1557                 return stat;
1558
1559         init_waitqueue_head(&dev->cmd_wq);
1560         init_waitqueue_head(&dev->tx_wq);
1561         init_waitqueue_head(&dev->rx_wq);
1562         sema_init(&dev->cmd_mutex, 1);
1563         sema_init(&dev->stream_mutex, 1);
1564         sema_init(&dev->pll_mutex, 1);
1565         sema_init(&dev->i2c_switch_mutex, 1);
1566         spin_lock_init(&dev->cmd_lock);
1567         for (i = 0; i < MAX_STREAM; i++)
1568                 spin_lock_init(&dev->channel[i].state_lock);
1569         ngwritel(1, TIMESTAMPS);
1570
1571         ngwritel(1, NGENE_INT_ENABLE);
1572
1573         stat = ngene_load_firm(dev);
1574         if (stat < 0)
1575                 goto fail;
1576
1577         stat = ngene_i2c_init(dev, 0);
1578         if (stat < 0)
1579                 goto fail;
1580
1581         stat = ngene_i2c_init(dev, 1);
1582         if (stat < 0)
1583                 goto fail;
1584
1585         if (dev->card_info->fw_version == 17) {
1586                 u8 tsin4_config[6] =
1587                         {3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
1588                 u8 default_config[6] =
1589                         {4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
1590                 u8 *bconf = default_config;
1591
1592                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1593                         bconf = tsin4_config;
1594                 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
1595                 stat = ngene_command_config_free_buf(dev, bconf);
1596         } else {
1597                 int bconf = BUFFER_CONFIG_4422;
1598                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1599                         bconf = BUFFER_CONFIG_3333;
1600                 stat = ngene_command_config_buf(dev, bconf);
1601         }
1602         return stat;
1603 fail:
1604         ngwritel(0, NGENE_INT_ENABLE);
1605         free_irq(dev->pci_dev->irq, dev);
1606         return stat;
1607 }
1608
1609
1610
1611 /****************************************************************************/
1612 /* Switch control (I2C gates, etc.) *****************************************/
1613 /****************************************************************************/
1614
1615
1616 /****************************************************************************/
1617 /* Demod/tuner attachment ***************************************************/
1618 /****************************************************************************/
1619
1620 static int tuner_attach_stv6110(struct ngene_channel *chan)
1621 {
1622         struct stv090x_config *feconf = (struct stv090x_config *)
1623                 chan->dev->card_info->fe_config[chan->number];
1624         struct stv6110x_config *tunerconf = (struct stv6110x_config *)
1625                 chan->dev->card_info->tuner_config[chan->number];
1626         struct stv6110x_devctl *ctl;
1627
1628         ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf,
1629                          &chan->i2c_adapter);
1630         if (ctl == NULL) {
1631                 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
1632                 return -ENODEV;
1633         }
1634
1635         feconf->tuner_init          = ctl->tuner_init;
1636         feconf->tuner_set_mode      = ctl->tuner_set_mode;
1637         feconf->tuner_set_frequency = ctl->tuner_set_frequency;
1638         feconf->tuner_get_frequency = ctl->tuner_get_frequency;
1639         feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
1640         feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
1641         feconf->tuner_set_bbgain    = ctl->tuner_set_bbgain;
1642         feconf->tuner_get_bbgain    = ctl->tuner_get_bbgain;
1643         feconf->tuner_set_refclk    = ctl->tuner_set_refclk;
1644         feconf->tuner_get_status    = ctl->tuner_get_status;
1645
1646         return 0;
1647 }
1648
1649
1650 static int demod_attach_stv0900(struct ngene_channel *chan)
1651 {
1652         struct stv090x_config *feconf = (struct stv090x_config *)
1653                 chan->dev->card_info->fe_config[chan->number];
1654
1655         chan->fe = dvb_attach(stv090x_attach,
1656                         feconf,
1657                         &chan->i2c_adapter,
1658                         chan->number == 0 ? STV090x_DEMODULATOR_0 :
1659                                             STV090x_DEMODULATOR_1);
1660         if (chan->fe == NULL) {
1661                 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
1662                 return -ENODEV;
1663         }
1664
1665         if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0,
1666                         0, chan->dev->card_info->lnb[chan->number])) {
1667                 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
1668                 dvb_frontend_detach(chan->fe);
1669                 return -ENODEV;
1670         }
1671
1672         return 0;
1673 }
1674
1675 /****************************************************************************/
1676 /****************************************************************************/
1677 /****************************************************************************/
1678
1679 static void release_channel(struct ngene_channel *chan)
1680 {
1681         struct dvb_demux *dvbdemux = &chan->demux;
1682         struct ngene *dev = chan->dev;
1683         struct ngene_info *ni = dev->card_info;
1684         int io = ni->io_type[chan->number];
1685
1686         tasklet_kill(&chan->demux_tasklet);
1687
1688         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1689                 if (chan->fe) {
1690                         dvb_unregister_frontend(chan->fe);
1691                         dvb_frontend_detach(chan->fe);
1692                         chan->fe = 0;
1693                 }
1694                 dvbdemux->dmx.close(&dvbdemux->dmx);
1695                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1696                                               &chan->hw_frontend);
1697                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1698                                               &chan->mem_frontend);
1699                 dvb_dmxdev_release(&chan->dmxdev);
1700                 dvb_dmx_release(&chan->demux);
1701
1702                 if (chan->number == 0 || !one_adapter)
1703                         dvb_unregister_adapter(&dev->adapter[chan->number]);
1704         }
1705 }
1706
1707 static int init_channel(struct ngene_channel *chan)
1708 {
1709         int ret = 0, nr = chan->number;
1710         struct dvb_adapter *adapter = NULL;
1711         struct dvb_demux *dvbdemux = &chan->demux;
1712         struct ngene *dev = chan->dev;
1713         struct ngene_info *ni = dev->card_info;
1714         int io = ni->io_type[nr];
1715
1716         tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1717         chan->users = 0;
1718         chan->type = io;
1719         chan->mode = chan->type;        /* for now only one mode */
1720
1721         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1722                 if (nr >= STREAM_AUDIOIN1)
1723                         chan->DataFormatFlags = DF_SWAP32;
1724                 if (nr == 0 || !one_adapter) {
1725                         adapter = &dev->adapter[nr];
1726                         ret = dvb_register_adapter(adapter, "nGene",
1727                                                    THIS_MODULE,
1728                                                    &chan->dev->pci_dev->dev,
1729                                                    adapter_nr);
1730                         if (ret < 0)
1731                                 return ret;
1732                 } else {
1733                         adapter = &dev->adapter[0];
1734                 }
1735
1736                 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1737                                               ngene_start_feed,
1738                                               ngene_stop_feed, chan);
1739                 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1740                                                  &chan->hw_frontend,
1741                                                  &chan->mem_frontend, adapter);
1742         }
1743
1744         if (io & NGENE_IO_TSIN) {
1745                 chan->fe = NULL;
1746                 if (ni->demod_attach[nr])
1747                         ni->demod_attach[nr](chan);
1748                 if (chan->fe) {
1749                         if (dvb_register_frontend(adapter, chan->fe) < 0) {
1750                                 if (chan->fe->ops.release)
1751                                         chan->fe->ops.release(chan->fe);
1752                                 chan->fe = NULL;
1753                         }
1754                 }
1755                 if (chan->fe && ni->tuner_attach[nr])
1756                         if (ni->tuner_attach[nr] (chan) < 0) {
1757                                 printk(KERN_ERR DEVICE_NAME
1758                                        ": Tuner attach failed on channel %d!\n",
1759                                        nr);
1760                         }
1761         }
1762         return ret;
1763 }
1764
1765 static int init_channels(struct ngene *dev)
1766 {
1767         int i, j;
1768
1769         for (i = 0; i < MAX_STREAM; i++) {
1770                 if (init_channel(&dev->channel[i]) < 0) {
1771                         for (j = i - 1; j >= 0; j--)
1772                                 release_channel(&dev->channel[j]);
1773                         return -1;
1774                 }
1775         }
1776         return 0;
1777 }
1778
1779 /****************************************************************************/
1780 /* device probe/remove calls ************************************************/
1781 /****************************************************************************/
1782
1783 static void __devexit ngene_remove(struct pci_dev *pdev)
1784 {
1785         struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1786         int i;
1787
1788         tasklet_kill(&dev->event_tasklet);
1789         for (i = MAX_STREAM - 1; i >= 0; i--)
1790                 release_channel(&dev->channel[i]);
1791         ngene_stop(dev);
1792         ngene_release_buffers(dev);
1793         pci_set_drvdata(pdev, 0);
1794         pci_disable_device(pdev);
1795 }
1796
1797 static int __devinit ngene_probe(struct pci_dev *pci_dev,
1798                                  const struct pci_device_id *id)
1799 {
1800         struct ngene *dev;
1801         int stat = 0;
1802
1803         if (pci_enable_device(pci_dev) < 0)
1804                 return -ENODEV;
1805
1806         dev = vmalloc(sizeof(struct ngene));
1807         if (dev == NULL) {
1808                 stat = -ENOMEM;
1809                 goto fail0;
1810         }
1811         memset(dev, 0, sizeof(struct ngene));
1812
1813         dev->pci_dev = pci_dev;
1814         dev->card_info = (struct ngene_info *)id->driver_data;
1815         printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1816
1817         pci_set_drvdata(pci_dev, dev);
1818
1819         /* Alloc buffers and start nGene */
1820         stat = ngene_get_buffers(dev);
1821         if (stat < 0)
1822                 goto fail1;
1823         stat = ngene_start(dev);
1824         if (stat < 0)
1825                 goto fail1;
1826
1827         dev->i2c_current_bus = -1;
1828
1829         /* Register DVB adapters and devices for both channels */
1830         if (init_channels(dev) < 0)
1831                 goto fail2;
1832
1833         return 0;
1834
1835 fail2:
1836         ngene_stop(dev);
1837 fail1:
1838         ngene_release_buffers(dev);
1839 fail0:
1840         pci_disable_device(pci_dev);
1841         pci_set_drvdata(pci_dev, 0);
1842         return stat;
1843 }
1844
1845 /****************************************************************************/
1846 /* Card configs *************************************************************/
1847 /****************************************************************************/
1848
1849 static struct stv090x_config fe_mps2 = {
1850         .device         = STV0900,
1851         .demod_mode     = STV090x_DUAL,
1852         .clk_mode       = STV090x_CLK_EXT,
1853
1854         .xtal           = 27000000,
1855         .address        = 0x68,
1856
1857         .ts1_mode       = STV090x_TSMODE_SERIAL_PUNCTURED,
1858         .ts2_mode       = STV090x_TSMODE_SERIAL_PUNCTURED,
1859
1860         .repeater_level = STV090x_RPTLEVEL_16,
1861
1862         .adc1_range     = STV090x_ADC_1Vpp,
1863         .adc2_range     = STV090x_ADC_1Vpp,
1864
1865         .diseqc_envelope_mode = true,
1866 };
1867
1868 static struct stv6110x_config tuner_mps2_0 = {
1869         .addr   = 0x60,
1870         .refclk = 27000000,
1871         .clk_div = 1,
1872 };
1873
1874 static struct stv6110x_config tuner_mps2_1 = {
1875         .addr   = 0x63,
1876         .refclk = 27000000,
1877         .clk_div = 1,
1878 };
1879
1880 static struct ngene_info ngene_info_mps2 = {
1881         .type           = NGENE_SIDEWINDER,
1882         .name           = "Media-Pointer MP-S2/CineS2 DVB-S2 Twin Tuner",
1883         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1884         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1885         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1886         .fe_config      = {&fe_mps2, &fe_mps2},
1887         .tuner_config   = {&tuner_mps2_0, &tuner_mps2_1},
1888         .lnb            = {0x0b, 0x08},
1889         .tsf            = {3, 3},
1890         .fw_version     = 17,
1891 };
1892
1893 static struct ngene_info ngene_info_satixs2 = {
1894         .type           = NGENE_SIDEWINDER,
1895         .name           = "Mystique SaTiX-S2 Dual",
1896         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1897         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1898         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1899         .fe_config      = {&fe_mps2, &fe_mps2},
1900         .tuner_config   = {&tuner_mps2_0, &tuner_mps2_1},
1901         .lnb            = {0x0b, 0x08},
1902         .tsf            = {3, 3},
1903         .fw_version     = 17,
1904 };
1905
1906 /****************************************************************************/
1907
1908
1909
1910 /****************************************************************************/
1911 /* PCI Subsystem ID *********************************************************/
1912 /****************************************************************************/
1913
1914 #define NGENE_ID(_subvend, _subdev, _driverdata) { \
1915         .vendor = NGENE_VID, .device = NGENE_PID, \
1916         .subvendor = _subvend, .subdevice = _subdev, \
1917         .driver_data = (unsigned long) &_driverdata }
1918
1919 /****************************************************************************/
1920
1921 static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
1922         NGENE_ID(0x18c3, 0xabc3, ngene_info_mps2),
1923         NGENE_ID(0x18c3, 0xabc4, ngene_info_mps2),
1924         NGENE_ID(0x18c3, 0xdb01, ngene_info_satixs2),
1925         {0}
1926 };
1927 MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
1928
1929 /****************************************************************************/
1930 /* Init/Exit ****************************************************************/
1931 /****************************************************************************/
1932
1933 static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
1934                                              enum pci_channel_state state)
1935 {
1936         printk(KERN_ERR DEVICE_NAME ": PCI error\n");
1937         if (state == pci_channel_io_perm_failure)
1938                 return PCI_ERS_RESULT_DISCONNECT;
1939         if (state == pci_channel_io_frozen)
1940                 return PCI_ERS_RESULT_NEED_RESET;
1941         return PCI_ERS_RESULT_CAN_RECOVER;
1942 }
1943
1944 static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
1945 {
1946         printk(KERN_INFO DEVICE_NAME ": link reset\n");
1947         return 0;
1948 }
1949
1950 static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
1951 {
1952         printk(KERN_INFO DEVICE_NAME ": slot reset\n");
1953         return 0;
1954 }
1955
1956 static void ngene_resume(struct pci_dev *dev)
1957 {
1958         printk(KERN_INFO DEVICE_NAME ": resume\n");
1959 }
1960
1961 static struct pci_error_handlers ngene_errors = {
1962         .error_detected = ngene_error_detected,
1963         .link_reset = ngene_link_reset,
1964         .slot_reset = ngene_slot_reset,
1965         .resume = ngene_resume,
1966 };
1967
1968 static struct pci_driver ngene_pci_driver = {
1969         .name        = "ngene",
1970         .id_table    = ngene_id_tbl,
1971         .probe       = ngene_probe,
1972         .remove      = __devexit_p(ngene_remove),
1973         .err_handler = &ngene_errors,
1974 };
1975
1976 static __init int module_init_ngene(void)
1977 {
1978         printk(KERN_INFO
1979                "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
1980         return pci_register_driver(&ngene_pci_driver);
1981 }
1982
1983 static __exit void module_exit_ngene(void)
1984 {
1985         pci_unregister_driver(&ngene_pci_driver);
1986 }
1987
1988 module_init(module_init_ngene);
1989 module_exit(module_exit_ngene);
1990
1991 MODULE_DESCRIPTION("nGene");
1992 MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
1993 MODULE_LICENSE("GPL");