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   1 /*
   2  * Driver for DiBcom DiB3000MC/P-demodulator.
   3  *
   4  * Copyright (C) 2004-7 DiBcom (http://www.dibcom.fr/)
   5  * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
   6  *
   7  * This code is partially based on the previous dib3000mc.c .
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  *      modify it under the terms of the GNU General Public License as
  11  *      published by the Free Software Foundation, version 2.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/i2c.h>
  16 //#include <linux/init.h>
  17 //#include <linux/delay.h>
  18 //#include <linux/string.h>
  19 //#include <linux/slab.h>
  20
  21 #include "dvb_frontend.h"
  22
  23 #include "dib3000mc.h"
  24
  25 static int debug;
  26 module_param(debug, int, 0644);
  27 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
  28
  29 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB3000MC/P:"); printk(args); printk("\n"); } } while (0)
  30
  31 struct dib3000mc_state {
  32         struct dvb_frontend demod;
  33         struct dib3000mc_config *cfg;
  34
  35         u8 i2c_addr;
  36         struct i2c_adapter *i2c_adap;
  37
  38         struct dibx000_i2c_master i2c_master;
  39
  40         u32 timf;
  41
  42         fe_bandwidth_t current_bandwidth;
  43
  44         u16 dev_id;
  45 };
  46
  47 static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg)
  48 {
  49         u8 wb[2] = { (reg >> 8) | 0x80, reg & 0xff };
  50         u8 rb[2];
  51         struct i2c_msg msg[2] = {
  52                 { .addr = state->i2c_addr >> 1, .flags = 0,        .buf = wb, .len = 2 },
  53                 { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 },
  54         };
  55
  56         if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
  57                 dprintk("i2c read error on %d\n",reg);
  58
  59         return (rb[0] << 8) | rb[1];
  60 }
  61
  62 static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val)
  63 {
  64         u8 b[4] = {
  65                 (reg >> 8) & 0xff, reg & 0xff,
  66                 (val >> 8) & 0xff, val & 0xff,
  67         };
  68         struct i2c_msg msg = {
  69                 .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
  70         };
  71         return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
  72 }
  73
  74 static int dib3000mc_identify(struct dib3000mc_state *state)
  75 {
  76         u16 value;
  77         if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) {
  78                 dprintk("-E-  DiB3000MC/P: wrong Vendor ID (read=0x%x)\n",value);
  79                 return -EREMOTEIO;
  80         }
  81
  82         value = dib3000mc_read_word(state, 1026);
  83         if (value != 0x3001 && value != 0x3002) {
  84                 dprintk("-E-  DiB3000MC/P: wrong Device ID (%x)\n",value);
  85                 return -EREMOTEIO;
  86         }
  87         state->dev_id = value;
  88
  89         dprintk("-I-  found DiB3000MC/P: %x\n",state->dev_id);
  90
  91         return 0;
  92 }
  93
  94 static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset)
  95 {
  96         u32 timf;
  97
  98         if (state->timf == 0) {
  99                 timf = 1384402; // default value for 8MHz
 100                 if (update_offset)
 101                         msleep(200); // first time we do an update
 102         } else
 103                 timf = state->timf;
 104
 105         timf *= (bw / 1000);
 106
 107         if (update_offset) {
 108                 s16 tim_offs = dib3000mc_read_word(state, 416);
 109
 110                 if (tim_offs &  0x2000)
 111                         tim_offs -= 0x4000;
 112
 113                 if (nfft == TRANSMISSION_MODE_2K)
 114                         tim_offs *= 4;
 115
 116                 timf += tim_offs;
 117                 state->timf = timf / (bw / 1000);
 118         }
 119
 120         dprintk("timf: %d\n", timf);
 121
 122         dib3000mc_write_word(state, 23, (u16) (timf >> 16));
 123         dib3000mc_write_word(state, 24, (u16) (timf      ) & 0xffff);
 124
 125         return 0;
 126 }
 127
 128 static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state)
 129 {
 130         u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb;
 131     if (state->cfg->pwm3_inversion) {
 132                 reg_51 =  (2 << 14) | (0 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
 133                 reg_52 |= (1 << 2);
 134         } else {
 135                 reg_51 = (2 << 14) | (4 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
 136                 reg_52 |= (1 << 8);
 137         }
 138         dib3000mc_write_word(state, 51, reg_51);
 139         dib3000mc_write_word(state, 52, reg_52);
 140
 141     if (state->cfg->use_pwm3)
 142                 dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0));
 143         else
 144                 dib3000mc_write_word(state, 245, 0);
 145
 146     dib3000mc_write_word(state, 1040, 0x3);
 147         return 0;
 148 }
 149
 150 static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode)
 151 {
 152         int    ret = 0;
 153         u16 fifo_threshold = 1792;
 154         u16 outreg = 0;
 155         u16 outmode = 0;
 156         u16 elecout = 1;
 157         u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */
 158
 159         dprintk("-I-  Setting output mode for demod %p to %d\n",
 160                         &state->demod, mode);
 161
 162         switch (mode) {
 163                 case OUTMODE_HIGH_Z:  // disable
 164                         elecout = 0;
 165                         break;
 166                 case OUTMODE_MPEG2_PAR_GATED_CLK:   // STBs with parallel gated clock
 167                         outmode = 0;
 168                         break;
 169                 case OUTMODE_MPEG2_PAR_CONT_CLK:    // STBs with parallel continues clock
 170                         outmode = 1;
 171                         break;
 172                 case OUTMODE_MPEG2_SERIAL:          // STBs with serial input
 173                         outmode = 2;
 174                         break;
 175                 case OUTMODE_MPEG2_FIFO:            // e.g. USB feeding
 176                         elecout = 3;
 177                         /*ADDR @ 206 :
 178                         P_smo_error_discard  [1;6:6] = 0
 179                         P_smo_rs_discard     [1;5:5] = 0
 180                         P_smo_pid_parse      [1;4:4] = 0
 181                         P_smo_fifo_flush     [1;3:3] = 0
 182                         P_smo_mode           [2;2:1] = 11
 183                         P_smo_ovf_prot       [1;0:0] = 0
 184                         */
 185                         smo_reg |= 3 << 1;
 186                         fifo_threshold = 512;
 187                         outmode = 5;
 188                         break;
 189                 case OUTMODE_DIVERSITY:
 190                         outmode = 4;
 191                         elecout = 1;
 192                         break;
 193                 default:
 194                         dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod);
 195                         outmode = 0;
 196                         break;
 197         }
 198
 199         if ((state->cfg->output_mpeg2_in_188_bytes))
 200                 smo_reg |= (1 << 5); // P_smo_rs_discard     [1;5:5] = 1
 201
 202         outreg = dib3000mc_read_word(state, 244) & 0x07FF;
 203         outreg |= (outmode << 11);
 204         ret |= dib3000mc_write_word(state,  244, outreg);
 205         ret |= dib3000mc_write_word(state,  206, smo_reg);   /*smo_ mode*/
 206         ret |= dib3000mc_write_word(state,  207, fifo_threshold); /* synchronous fread */
 207         ret |= dib3000mc_write_word(state, 1040, elecout);         /* P_out_cfg */
 208         return ret;
 209 }
 210
 211 static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw)
 212 {
 213         u16 bw_cfg[6] = { 0 };
 214         u16 imp_bw_cfg[3] = { 0 };
 215         u16 reg;
 216
 217 /* settings here are for 27.7MHz */
 218         switch (bw) {
 219                 case 8000:
 220                         bw_cfg[0] = 0x0019; bw_cfg[1] = 0x5c30; bw_cfg[2] = 0x0054; bw_cfg[3] = 0x88a0; bw_cfg[4] = 0x01a6; bw_cfg[5] = 0xab20;
 221                         imp_bw_cfg[0] = 0x04db; imp_bw_cfg[1] = 0x00db; imp_bw_cfg[2] = 0x00b7;
 222                         break;
 223
 224                 case 7000:
 225                         bw_cfg[0] = 0x001c; bw_cfg[1] = 0xfba5; bw_cfg[2] = 0x0060; bw_cfg[3] = 0x9c25; bw_cfg[4] = 0x01e3; bw_cfg[5] = 0x0cb7;
 226                         imp_bw_cfg[0] = 0x04c0; imp_bw_cfg[1] = 0x00c0; imp_bw_cfg[2] = 0x00a0;
 227                         break;
 228
 229                 case 6000:
 230                         bw_cfg[0] = 0x0021; bw_cfg[1] = 0xd040; bw_cfg[2] = 0x0070; bw_cfg[3] = 0xb62b; bw_cfg[4] = 0x0233; bw_cfg[5] = 0x8ed5;
 231                         imp_bw_cfg[0] = 0x04a5; imp_bw_cfg[1] = 0x00a5; imp_bw_cfg[2] = 0x0089;
 232                         break;
 233
 234                 case 5000:
 235                         bw_cfg[0] = 0x0028; bw_cfg[1] = 0x9380; bw_cfg[2] = 0x0087; bw_cfg[3] = 0x4100; bw_cfg[4] = 0x02a4; bw_cfg[5] = 0x4500;
 236                         imp_bw_cfg[0] = 0x0489; imp_bw_cfg[1] = 0x0089; imp_bw_cfg[2] = 0x0072;
 237                         break;
 238
 239                 default: return -EINVAL;
 240         }
 241
 242         for (reg = 6; reg < 12; reg++)
 243                 dib3000mc_write_word(state, reg, bw_cfg[reg - 6]);
 244         dib3000mc_write_word(state, 12, 0x0000);
 245         dib3000mc_write_word(state, 13, 0x03e8);
 246         dib3000mc_write_word(state, 14, 0x0000);
 247         dib3000mc_write_word(state, 15, 0x03f2);
 248         dib3000mc_write_word(state, 16, 0x0001);
 249         dib3000mc_write_word(state, 17, 0xb0d0);
 250         // P_sec_len
 251         dib3000mc_write_word(state, 18, 0x0393);
 252         dib3000mc_write_word(state, 19, 0x8700);
 253
 254         for (reg = 55; reg < 58; reg++)
 255                 dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]);
 256
 257         // Timing configuration
 258         dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0);
 259
 260         return 0;
 261 }
 262
 263 static u16 impulse_noise_val[29] =
 264
 265 {
 266         0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c, 0x3ffe, 0x7f3,
 267         0x2d94, 0x76, 0x53d, 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3, 0x3feb, 0x7d2,
 268         0x365e, 0x76, 0x48c, 0x3ffe, 0x5b3, 0x3feb, 0x76, 0x0000, 0xd
 269 };
 270
 271 static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, s16 nfft)
 272 {
 273         u16 i;
 274         for (i = 58; i < 87; i++)
 275                 dib3000mc_write_word(state, i, impulse_noise_val[i-58]);
 276
 277         if (nfft == TRANSMISSION_MODE_8K) {
 278                 dib3000mc_write_word(state, 58, 0x3b);
 279                 dib3000mc_write_word(state, 84, 0x00);
 280                 dib3000mc_write_word(state, 85, 0x8200);
 281         }
 282
 283         dib3000mc_write_word(state, 34, 0x1294);
 284         dib3000mc_write_word(state, 35, 0x1ff8);
 285         if (mode == 1)
 286                 dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10));
 287 }
 288
 289 static int dib3000mc_init(struct dvb_frontend *demod)
 290 {
 291         struct dib3000mc_state *state = demod->demodulator_priv;
 292         struct dibx000_agc_config *agc = state->cfg->agc;
 293
 294         // Restart Configuration
 295         dib3000mc_write_word(state, 1027, 0x8000);
 296         dib3000mc_write_word(state, 1027, 0x0000);
 297
 298         // power up the demod + mobility configuration
 299         dib3000mc_write_word(state, 140, 0x0000);
 300         dib3000mc_write_word(state, 1031, 0);
 301
 302         if (state->cfg->mobile_mode) {
 303                 dib3000mc_write_word(state, 139,  0x0000);
 304                 dib3000mc_write_word(state, 141,  0x0000);
 305                 dib3000mc_write_word(state, 175,  0x0002);
 306                 dib3000mc_write_word(state, 1032, 0x0000);
 307         } else {
 308                 dib3000mc_write_word(state, 139,  0x0001);
 309                 dib3000mc_write_word(state, 141,  0x0000);
 310                 dib3000mc_write_word(state, 175,  0x0000);
 311                 dib3000mc_write_word(state, 1032, 0x012C);
 312         }
 313         dib3000mc_write_word(state, 1033, 0x0000);
 314
 315         // P_clk_cfg
 316         dib3000mc_write_word(state, 1037, 0x3130);
 317
 318         // other configurations
 319
 320         // P_ctrl_sfreq
 321         dib3000mc_write_word(state, 33, (5 << 0));
 322         dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0));
 323
 324         // Phase noise control
 325         // P_fft_phacor_inh, P_fft_phacor_cpe, P_fft_powrange
 326         dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0));
 327
 328         if (state->cfg->phase_noise_mode == 0)
 329                 dib3000mc_write_word(state, 111, 0x00);
 330         else
 331                 dib3000mc_write_word(state, 111, 0x02);
 332
 333         // P_agc_global
 334         dib3000mc_write_word(state, 50, 0x8000);
 335
 336         // agc setup misc
 337         dib3000mc_setup_pwm_state(state);
 338
 339         // P_agc_counter_lock
 340         dib3000mc_write_word(state, 53, 0x87);
 341         // P_agc_counter_unlock
 342         dib3000mc_write_word(state, 54, 0x87);
 343
 344         /* agc */
 345         dib3000mc_write_word(state, 36, state->cfg->max_time);
 346         dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0));
 347         dib3000mc_write_word(state, 38, state->cfg->pwm3_value);
 348         dib3000mc_write_word(state, 39, state->cfg->ln_adc_level);
 349
 350         // set_agc_loop_Bw
 351         dib3000mc_write_word(state, 40, 0x0179);
 352         dib3000mc_write_word(state, 41, 0x03f0);
 353
 354         dib3000mc_write_word(state, 42, agc->agc1_max);
 355         dib3000mc_write_word(state, 43, agc->agc1_min);
 356         dib3000mc_write_word(state, 44, agc->agc2_max);
 357         dib3000mc_write_word(state, 45, agc->agc2_min);
 358         dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
 359         dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
 360         dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
 361         dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
 362
 363 // Begin: TimeOut registers
 364         // P_pha3_thres
 365         dib3000mc_write_word(state, 110, 3277);
 366         // P_timf_alpha = 6, P_corm_alpha = 6, P_corm_thres = 0x80
 367         dib3000mc_write_word(state,  26, 0x6680);
 368         // lock_mask0
 369         dib3000mc_write_word(state, 1, 4);
 370         // lock_mask1
 371         dib3000mc_write_word(state, 2, 4);
 372         // lock_mask2
 373         dib3000mc_write_word(state, 3, 0x1000);
 374         // P_search_maxtrial=1
 375         dib3000mc_write_word(state, 5, 1);
 376
 377         dib3000mc_set_bandwidth(state, 8000);
 378
 379         // div_lock_mask
 380         dib3000mc_write_word(state,  4, 0x814);
 381
 382         dib3000mc_write_word(state, 21, (1 << 9) | 0x164);
 383         dib3000mc_write_word(state, 22, 0x463d);
 384
 385         // Spurious rm cfg
 386         // P_cspu_regul, P_cspu_win_cut
 387         dib3000mc_write_word(state, 120, 0x200f);
 388         // P_adp_selec_monit
 389         dib3000mc_write_word(state, 134, 0);
 390
 391         // Fec cfg
 392         dib3000mc_write_word(state, 195, 0x10);
 393
 394         // diversity register: P_dvsy_sync_wait..
 395         dib3000mc_write_word(state, 180, 0x2FF0);
 396
 397         // Impulse noise configuration
 398         dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K);
 399
 400         // output mode set-up
 401         dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
 402
 403         /* close the i2c-gate */
 404         dib3000mc_write_word(state, 769, (1 << 7) );
 405
 406         return 0;
 407 }
 408
 409 static int dib3000mc_sleep(struct dvb_frontend *demod)
 410 {
 411         struct dib3000mc_state *state = demod->demodulator_priv;
 412
 413         dib3000mc_write_word(state, 1031, 0xFFFF);
 414         dib3000mc_write_word(state, 1032, 0xFFFF);
 415         dib3000mc_write_word(state, 1033, 0xFFF0);
 416
 417     return 0;
 418 }
 419
 420 static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam)
 421 {
 422         u16 cfg[4] = { 0 },reg;
 423         switch (qam) {
 424                 case QPSK:
 425                         cfg[0] = 0x099a; cfg[1] = 0x7fae; cfg[2] = 0x0333; cfg[3] = 0x7ff0;
 426                         break;
 427                 case QAM_16:
 428                         cfg[0] = 0x023d; cfg[1] = 0x7fdf; cfg[2] = 0x00a4; cfg[3] = 0x7ff0;
 429                         break;
 430                 case QAM_64:
 431                         cfg[0] = 0x0148; cfg[1] = 0x7ff0; cfg[2] = 0x00a4; cfg[3] = 0x7ff8;
 432                         break;
 433         }
 434         for (reg = 129; reg < 133; reg++)
 435                 dib3000mc_write_word(state, reg, cfg[reg - 129]);
 436 }
 437
 438 static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dvb_frontend_parameters *ch, u16 seq)
 439 {
 440         u16 value;
 441     dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
 442         dib3000mc_set_timing(state, ch->u.ofdm.transmission_mode, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth), 0);
 443
 444 //      if (boost)
 445 //              dib3000mc_write_word(state, 100, (11 << 6) + 6);
 446 //      else
 447                 dib3000mc_write_word(state, 100, (16 << 6) + 9);
 448
 449         dib3000mc_write_word(state, 1027, 0x0800);
 450         dib3000mc_write_word(state, 1027, 0x0000);
 451
 452         //Default cfg isi offset adp
 453         dib3000mc_write_word(state, 26,  0x6680);
 454         dib3000mc_write_word(state, 29,  0x1273);
 455         dib3000mc_write_word(state, 33,       5);
 456         dib3000mc_set_adp_cfg(state, QAM_16);
 457         dib3000mc_write_word(state, 133,  15564);
 458
 459         dib3000mc_write_word(state, 12 , 0x0);
 460         dib3000mc_write_word(state, 13 , 0x3e8);
 461         dib3000mc_write_word(state, 14 , 0x0);
 462         dib3000mc_write_word(state, 15 , 0x3f2);
 463
 464         dib3000mc_write_word(state, 93,0);
 465         dib3000mc_write_word(state, 94,0);
 466         dib3000mc_write_word(state, 95,0);
 467         dib3000mc_write_word(state, 96,0);
 468         dib3000mc_write_word(state, 97,0);
 469         dib3000mc_write_word(state, 98,0);
 470
 471         dib3000mc_set_impulse_noise(state, 0, ch->u.ofdm.transmission_mode);
 472
 473         value = 0;
 474         switch (ch->u.ofdm.transmission_mode) {
 475                 case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
 476                 default:
 477                 case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
 478         }
 479         switch (ch->u.ofdm.guard_interval) {
 480                 case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
 481                 case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
 482                 case GUARD_INTERVAL_1_4:  value |= (3 << 5); break;
 483                 default:
 484                 case GUARD_INTERVAL_1_8:  value |= (2 << 5); break;
 485         }
 486         switch (ch->u.ofdm.constellation) {
 487                 case QPSK:  value |= (0 << 3); break;
 488                 case QAM_16: value |= (1 << 3); break;
 489                 default:
 490                 case QAM_64: value |= (2 << 3); break;
 491         }
 492         switch (HIERARCHY_1) {
 493                 case HIERARCHY_2: value |= 2; break;
 494                 case HIERARCHY_4: value |= 4; break;
 495                 default:
 496                 case HIERARCHY_1: value |= 1; break;
 497         }
 498         dib3000mc_write_word(state, 0, value);
 499         dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));
 500
 501         value = 0;
 502         if (ch->u.ofdm.hierarchy_information == 1)
 503                 value |= (1 << 4);
 504         if (1 == 1)
 505                 value |= 1;
 506         switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {
 507                 case FEC_2_3: value |= (2 << 1); break;
 508                 case FEC_3_4: value |= (3 << 1); break;
 509                 case FEC_5_6: value |= (5 << 1); break;
 510                 case FEC_7_8: value |= (7 << 1); break;
 511                 default:
 512                 case FEC_1_2: value |= (1 << 1); break;
 513         }
 514         dib3000mc_write_word(state, 181, value);
 515
 516         // diversity synchro delay add 50% SFN margin
 517         switch (ch->u.ofdm.transmission_mode) {
 518                 case TRANSMISSION_MODE_8K: value = 256; break;
 519                 case TRANSMISSION_MODE_2K:
 520                 default: value = 64; break;
 521         }
 522         switch (ch->u.ofdm.guard_interval) {
 523                 case GUARD_INTERVAL_1_16: value *= 2; break;
 524                 case GUARD_INTERVAL_1_8:  value *= 4; break;
 525                 case GUARD_INTERVAL_1_4:  value *= 8; break;
 526                 default:
 527                 case GUARD_INTERVAL_1_32: value *= 1; break;
 528         }
 529         value <<= 4;
 530         value |= dib3000mc_read_word(state, 180) & 0x000f;
 531         dib3000mc_write_word(state, 180, value);
 532
 533         // restart demod
 534         value = dib3000mc_read_word(state, 0);
 535         dib3000mc_write_word(state, 0, value | (1 << 9));
 536         dib3000mc_write_word(state, 0, value);
 537
 538         msleep(30);
 539
 540         dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->u.ofdm.transmission_mode);
 541 }
 542
 543 static int dib3000mc_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *chan)
 544 {
 545         struct dib3000mc_state *state = demod->demodulator_priv;
 546         u16 reg;
 547 //      u32 val;
 548         struct dvb_frontend_parameters schan;
 549
 550         schan = *chan;
 551
 552         /* TODO what is that ? */
 553
 554         /* a channel for autosearch */
 555         schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 556         schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 557         schan.u.ofdm.constellation = QAM_64;
 558         schan.u.ofdm.code_rate_HP = FEC_2_3;
 559         schan.u.ofdm.code_rate_LP = FEC_2_3;
 560         schan.u.ofdm.hierarchy_information = 0;
 561
 562         dib3000mc_set_channel_cfg(state, &schan, 11);
 563
 564         reg = dib3000mc_read_word(state, 0);
 565         dib3000mc_write_word(state, 0, reg | (1 << 8));
 566         dib3000mc_read_word(state, 511);
 567         dib3000mc_write_word(state, 0, reg);
 568
 569         return 0;
 570 }
 571
 572 static int dib3000mc_autosearch_is_irq(struct dvb_frontend *demod)
 573 {
 574         struct dib3000mc_state *state = demod->demodulator_priv;
 575         u16 irq_pending = dib3000mc_read_word(state, 511);
 576
 577         if (irq_pending & 0x1) // failed
 578                 return 1;
 579
 580         if (irq_pending & 0x2) // succeeded
 581                 return 2;
 582
 583         return 0; // still pending
 584 }
 585
 586 static int dib3000mc_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
 587 {
 588         struct dib3000mc_state *state = demod->demodulator_priv;
 589
 590         // ** configure demod **
 591         dib3000mc_set_channel_cfg(state, ch, 0);
 592
 593         // activates isi
 594         dib3000mc_write_word(state, 29, 0x1073);
 595
 596         dib3000mc_set_adp_cfg(state, (u8)ch->u.ofdm.constellation);
 597         if (ch->u.ofdm.transmission_mode == TRANSMISSION_MODE_8K) {
 598                 dib3000mc_write_word(state, 26, 38528);
 599                 dib3000mc_write_word(state, 33, 8);
 600         } else {
 601                 dib3000mc_write_word(state, 26, 30336);
 602                 dib3000mc_write_word(state, 33, 6);
 603         }
 604
 605         if (dib3000mc_read_word(state, 509) & 0x80)
 606                 dib3000mc_set_timing(state, ch->u.ofdm.transmission_mode, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth), 1);
 607
 608         return 0;
 609 }
 610
 611 struct i2c_adapter * dib3000mc_get_tuner_i2c_master(struct dvb_frontend *demod, int gating)
 612 {
 613         struct dib3000mc_state *st = demod->demodulator_priv;
 614         return dibx000_get_i2c_adapter(&st->i2c_master, DIBX000_I2C_INTERFACE_TUNER, gating);
 615 }
 616
 617 EXPORT_SYMBOL(dib3000mc_get_tuner_i2c_master);
 618
 619 static int dib3000mc_get_frontend(struct dvb_frontend* fe,
 620                                 struct dvb_frontend_parameters *fep)
 621 {
 622         struct dib3000mc_state *state = fe->demodulator_priv;
 623         u16 tps = dib3000mc_read_word(state,458);
 624
 625         fep->inversion = INVERSION_AUTO;
 626
 627         fep->u.ofdm.bandwidth = state->current_bandwidth;
 628
 629         switch ((tps >> 8) & 0x1) {
 630                 case 0: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; break;
 631                 case 1: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; break;
 632         }
 633
 634         switch (tps & 0x3) {
 635                 case 0: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; break;
 636                 case 1: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; break;
 637                 case 2: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; break;
 638                 case 3: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; break;
 639         }
 640
 641         switch ((tps >> 13) & 0x3) {
 642                 case 0: fep->u.ofdm.constellation = QPSK; break;
 643                 case 1: fep->u.ofdm.constellation = QAM_16; break;
 644                 case 2:
 645                 default: fep->u.ofdm.constellation = QAM_64; break;
 646         }
 647
 648         /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
 649         /* (tps >> 12) & 0x1 == hrch is used, (tps >> 9) & 0x7 == alpha */
 650
 651         fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 652         switch ((tps >> 5) & 0x7) {
 653                 case 1: fep->u.ofdm.code_rate_HP = FEC_1_2; break;
 654                 case 2: fep->u.ofdm.code_rate_HP = FEC_2_3; break;
 655                 case 3: fep->u.ofdm.code_rate_HP = FEC_3_4; break;
 656                 case 5: fep->u.ofdm.code_rate_HP = FEC_5_6; break;
 657                 case 7:
 658                 default: fep->u.ofdm.code_rate_HP = FEC_7_8; break;
 659
 660         }
 661
 662         switch ((tps >> 2) & 0x7) {
 663                 case 1: fep->u.ofdm.code_rate_LP = FEC_1_2; break;
 664                 case 2: fep->u.ofdm.code_rate_LP = FEC_2_3; break;
 665                 case 3: fep->u.ofdm.code_rate_LP = FEC_3_4; break;
 666                 case 5: fep->u.ofdm.code_rate_LP = FEC_5_6; break;
 667                 case 7:
 668                 default: fep->u.ofdm.code_rate_LP = FEC_7_8; break;
 669         }
 670
 671         return 0;
 672 }
 673
 674 static int dib3000mc_set_frontend(struct dvb_frontend* fe,
 675                                 struct dvb_frontend_parameters *fep)
 676 {
 677         struct dib3000mc_state *state = fe->demodulator_priv;
 678
 679         state->current_bandwidth = fep->u.ofdm.bandwidth;
 680         dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->u.ofdm.bandwidth));
 681
 682         if (fe->ops.tuner_ops.set_params) {
 683                 fe->ops.tuner_ops.set_params(fe, fep);
 684                 msleep(100);
 685         }
 686
 687         if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
 688                 fep->u.ofdm.guard_interval    == GUARD_INTERVAL_AUTO ||
 689                 fep->u.ofdm.constellation     == QAM_AUTO ||
 690                 fep->u.ofdm.code_rate_HP      == FEC_AUTO) {
 691                 int i = 100, found;
 692
 693                 dib3000mc_autosearch_start(fe, fep);
 694                 do {
 695                         msleep(1);
 696                         found = dib3000mc_autosearch_is_irq(fe);
 697                 } while (found == 0 && i--);
 698
 699                 dprintk("autosearch returns: %d\n",found);
 700                 if (found == 0 || found == 1)
 701                         return 0; // no channel found
 702
 703                 dib3000mc_get_frontend(fe, fep);
 704         }
 705
 706         /* make this a config parameter */
 707         dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO);
 708
 709         return dib3000mc_tune(fe, fep);
 710 }
 711
 712 static int dib3000mc_read_status(struct dvb_frontend *fe, fe_status_t *stat)
 713 {
 714         struct dib3000mc_state *state = fe->demodulator_priv;
 715         u16 lock = dib3000mc_read_word(state, 509);
 716
 717         *stat = 0;
 718
 719         if (lock & 0x8000)
 720                 *stat |= FE_HAS_SIGNAL;
 721         if (lock & 0x3000)
 722                 *stat |= FE_HAS_CARRIER;
 723         if (lock & 0x0100)
 724                 *stat |= FE_HAS_VITERBI;
 725         if (lock & 0x0010)
 726                 *stat |= FE_HAS_SYNC;
 727         if (lock & 0x0008)
 728                 *stat |= FE_HAS_LOCK;
 729
 730         return 0;
 731 }
 732
 733 static int dib3000mc_read_ber(struct dvb_frontend *fe, u32 *ber)
 734 {
 735         struct dib3000mc_state *state = fe->demodulator_priv;
 736         *ber = (dib3000mc_read_word(state, 500) << 16) | dib3000mc_read_word(state, 501);
 737         return 0;
 738 }
 739
 740 static int dib3000mc_read_unc_blocks(struct dvb_frontend *fe, u32 *unc)
 741 {
 742         struct dib3000mc_state *state = fe->demodulator_priv;
 743         *unc = dib3000mc_read_word(state, 508);
 744         return 0;
 745 }
 746
 747 static int dib3000mc_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
 748 {
 749         struct dib3000mc_state *state = fe->demodulator_priv;
 750         u16 val = dib3000mc_read_word(state, 392);
 751         *strength = 65535 - val;
 752         return 0;
 753 }
 754
 755 static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr)
 756 {
 757         *snr = 0x0000;
 758         return 0;
 759 }
 760
 761 static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
 762 {
 763         tune->min_delay_ms = 1000;
 764         return 0;
 765 }
 766
 767 static void dib3000mc_release(struct dvb_frontend *fe)
 768 {
 769         struct dib3000mc_state *state = fe->demodulator_priv;
 770         dibx000_exit_i2c_master(&state->i2c_master);
 771         kfree(state);
 772 }
 773
 774 int dib3000mc_pid_control(struct dvb_frontend *fe, int index, int pid,int onoff)
 775 {
 776         struct dib3000mc_state *state = fe->demodulator_priv;
 777         dib3000mc_write_word(state, 212 + index,  onoff ? (1 << 13) | pid : 0);
 778         return 0;
 779 }
 780 EXPORT_SYMBOL(dib3000mc_pid_control);
 781
 782 int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff)
 783 {
 784         struct dib3000mc_state *state = fe->demodulator_priv;
 785         u16 tmp = dib3000mc_read_word(state, 206) & ~(1 << 4);
 786         tmp |= (onoff << 4);
 787         return dib3000mc_write_word(state, 206, tmp);
 788 }
 789 EXPORT_SYMBOL(dib3000mc_pid_parse);
 790
 791 void dib3000mc_set_config(struct dvb_frontend *fe, struct dib3000mc_config *cfg)
 792 {
 793         struct dib3000mc_state *state = fe->demodulator_priv;
 794         state->cfg = cfg;
 795 }
 796 EXPORT_SYMBOL(dib3000mc_set_config);
 797
 798 int dib3000mc_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib3000mc_config cfg[])
 799 {
 800         struct dib3000mc_state st = { .i2c_adap = i2c };
 801         int k;
 802         u8 new_addr;
 803
 804         static u8 DIB3000MC_I2C_ADDRESS[] = {20,22,24,26};
 805
 806         for (k = no_of_demods-1; k >= 0; k--) {
 807                 st.cfg = &cfg[k];
 808
 809                 /* designated i2c address */
 810                 new_addr          = DIB3000MC_I2C_ADDRESS[k];
 811                 st.i2c_addr = new_addr;
 812                 if (dib3000mc_identify(&st) != 0) {
 813                         st.i2c_addr = default_addr;
 814                         if (dib3000mc_identify(&st) != 0) {
 815                                 dprintk("-E-  DiB3000P/MC #%d: not identified\n", k);
 816                                 return -ENODEV;
 817                         }
 818                 }
 819
 820                 dib3000mc_set_output_mode(&st, OUTMODE_MPEG2_PAR_CONT_CLK);
 821
 822                 // set new i2c address and force divstr (Bit 1) to value 0 (Bit 0)
 823                 dib3000mc_write_word(&st, 1024, (new_addr << 3) | 0x1);
 824                 st.i2c_addr = new_addr;
 825         }
 826
 827         for (k = 0; k < no_of_demods; k++) {
 828                 st.cfg = &cfg[k];
 829                 st.i2c_addr = DIB3000MC_I2C_ADDRESS[k];
 830
 831                 dib3000mc_write_word(&st, 1024, st.i2c_addr << 3);
 832
 833                 /* turn off data output */
 834                 dib3000mc_set_output_mode(&st, OUTMODE_HIGH_Z);
 835         }
 836         return 0;
 837 }
 838 EXPORT_SYMBOL(dib3000mc_i2c_enumeration);
 839
 840 static struct dvb_frontend_ops dib3000mc_ops;
 841
 842 struct dvb_frontend * dib3000mc_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib3000mc_config *cfg)
 843 {
 844         struct dvb_frontend *demod;
 845         struct dib3000mc_state *st;
 846         st = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL);
 847         if (st == NULL)
 848                 return NULL;
 849
 850         st->cfg = cfg;
 851         st->i2c_adap = i2c_adap;
 852         st->i2c_addr = i2c_addr;
 853
 854         demod                   = &st->demod;
 855         demod->demodulator_priv = st;
 856         memcpy(&st->demod.ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops));
 857
 858         if (dib3000mc_identify(st) != 0)
 859                 goto error;
 860
 861         dibx000_init_i2c_master(&st->i2c_master, DIB3000MC, st->i2c_adap, st->i2c_addr);
 862
 863         dib3000mc_write_word(st, 1037, 0x3130);
 864
 865         return demod;
 866
 867 error:
 868         kfree(st);
 869         return NULL;
 870 }
 871 EXPORT_SYMBOL(dib3000mc_attach);
 872
 873 static struct dvb_frontend_ops dib3000mc_ops = {
 874         .info = {
 875                 .name = "DiBcom 3000MC/P",
 876                 .type = FE_OFDM,
 877                 .frequency_min      = 44250000,
 878                 .frequency_max      = 867250000,
 879                 .frequency_stepsize = 62500,
 880                 .caps = FE_CAN_INVERSION_AUTO |
 881                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 882                         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 883                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 884                         FE_CAN_TRANSMISSION_MODE_AUTO |
 885                         FE_CAN_GUARD_INTERVAL_AUTO |
 886                         FE_CAN_RECOVER |
 887                         FE_CAN_HIERARCHY_AUTO,
 888         },
 889
 890         .release              = dib3000mc_release,
 891
 892         .init                 = dib3000mc_init,
 893         .sleep                = dib3000mc_sleep,
 894
 895         .set_frontend         = dib3000mc_set_frontend,
 896         .get_tune_settings    = dib3000mc_fe_get_tune_settings,
 897         .get_frontend         = dib3000mc_get_frontend,
 898
 899         .read_status          = dib3000mc_read_status,
 900         .read_ber             = dib3000mc_read_ber,
 901         .read_signal_strength = dib3000mc_read_signal_strength,
 902         .read_snr             = dib3000mc_read_snr,
 903         .read_ucblocks        = dib3000mc_read_unc_blocks,
 904 };
 905
 906 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
 907 MODULE_DESCRIPTION("Driver for the DiBcom 3000MC/P COFDM demodulator");
 908 MODULE_LICENSE("GPL");