SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/isdn/hardware/mISDN/hfcmulti.c

   1 /*
   2  * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
   3  *
   4  * Author       Andreas Eversberg (jolly@eversberg.eu)
   5  * ported to mqueue mechanism:
   6  *              Peter Sprenger (sprengermoving-bytes.de)
   7  *
   8  * inspired by existing hfc-pci driver:
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil (kkeil@suse.de)
  11  * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2, or (at your option)
  16  * any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  * Thanks to Cologne Chip AG for this great controller!
  29  */
  30
  31 /*
  32  * module parameters:
  33  * type:
  34  *      By default (0), the card is automatically detected.
  35  *      Or use the following combinations:
  36  *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
  37  * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
  38  * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
  39  *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
  40  *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
  41  *      Bit 10    = spare
  42  *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
  43  * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
  44  *      Bit 13    = spare
  45  *      Bit 14    = 0x04000 = Use external ram (128K)
  46  *      Bit 15    = 0x08000 = Use external ram (512K)
  47  *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
  48  * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
  49  *      Bit 18    = spare
  50  *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
  51  * (all other bits are reserved and shall be 0)
  52  *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
  53  *               bus (PCM master)
  54  *
  55  * port: (optional or required for all ports on all installed cards)
  56  *      HFC-4S/HFC-8S only bits:
  57  *      Bit 0     = 0x001 = Use master clock for this S/T interface
  58  *                          (ony once per chip).
  59  *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
  60  *                          Don't use this unless you know what you are doing!
  61  *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
  62  *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
  63  *               received from port 1
  64  *
  65  *      HFC-E1 only bits:
  66  *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
  67  *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
  68  *      Bit 2     = 0x0004 = Report LOS
  69  *      Bit 3     = 0x0008 = Report AIS
  70  *      Bit 4     = 0x0010 = Report SLIP
  71  *      Bit 5     = 0x0020 = Report RDI
  72  *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
  73  *                           mode instead.
  74  *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
  75  * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
  76  *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
  77  *                           (E1 only)
  78  *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
  79  *                           for default.
  80  * (all other bits are reserved and shall be 0)
  81  *
  82  * debug:
  83  *      NOTE: only one debug value must be given for all cards
  84  *      enable debugging (see hfc_multi.h for debug options)
  85  *
  86  * poll:
  87  *      NOTE: only one poll value must be given for all cards
  88  *      Give the number of samples for each fifo process.
  89  *      By default 128 is used. Decrease to reduce delay, increase to
  90  *      reduce cpu load. If unsure, don't mess with it!
  91  *      Valid is 8, 16, 32, 64, 128, 256.
  92  *
  93  * pcm:
  94  *      NOTE: only one pcm value must be given for every card.
  95  *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
  96  *      By default (0), the PCM bus id is 100 for the card that is PCM master.
  97  *      If multiple cards are PCM master (because they are not interconnected),
  98  *      each card with PCM master will have increasing PCM id.
  99  *      All PCM busses with the same ID are expected to be connected and have
 100  *      common time slots slots.
 101  *      Only one chip of the PCM bus must be master, the others slave.
 102  *      -1 means no support of PCM bus not even.
 103  *      Omit this value, if all cards are interconnected or none is connected.
 104  *      If unsure, don't give this parameter.
 105  *
 106  * dslot:
 107  *      NOTE: only one dslot value must be given for every card.
 108  *      Also this value must be given for non-E1 cards. If omitted, the E1
 109  *      card has D-channel on time slot 16, which is default.
 110  *      If 1..15 or 17..31, an alternate time slot is used for D-channel.
 111  *      In this case, the application must be able to handle this.
 112  *      If -1 is given, the D-channel is disabled and all 31 slots can be used
 113  *      for B-channel. (only for specific applications)
 114  *      If you don't know how to use it, you don't need it!
 115  *
 116  * iomode:
 117  *      NOTE: only one mode value must be given for every card.
 118  *      -> See hfc_multi.h for HFC_IO_MODE_* values
 119  *      By default, the IO mode is pci memory IO (MEMIO).
 120  *      Some cards requre specific IO mode, so it cannot be changed.
 121  *      It may be usefull to set IO mode to register io (REGIO) to solve
 122  *      PCI bridge problems.
 123  *      If unsure, don't give this parameter.
 124  *
 125  * clockdelay_nt:
 126  *      NOTE: only one clockdelay_nt value must be given once for all cards.
 127  *      Give the value of the clock control register (A_ST_CLK_DLY)
 128  *      of the S/T interfaces in NT mode.
 129  *      This register is needed for the TBR3 certification, so don't change it.
 130  *
 131  * clockdelay_te:
 132  *      NOTE: only one clockdelay_te value must be given once
 133  *      Give the value of the clock control register (A_ST_CLK_DLY)
 134  *      of the S/T interfaces in TE mode.
 135  *      This register is needed for the TBR3 certification, so don't change it.
 136  *
 137  * clock:
 138  *      NOTE: only one clock value must be given once
 139  *      Selects interface with clock source for mISDN and applications.
 140  *      Set to card number starting with 1. Set to -1 to disable.
 141  *      By default, the first card is used as clock source.
 142  *
 143  * hwid:
 144  *      NOTE: only one hwid value must be given once
 145  *      Enable special embedded devices with XHFC controllers.
 146  */
 147
 148 /*
 149  * debug register access (never use this, it will flood your system log)
 150  * #define HFC_REGISTER_DEBUG
 151  */
 152
 153 #define HFC_MULTI_VERSION       "2.03"
 154
 155 #include <linux/module.h>
 156 #include <linux/pci.h>
 157 #include <linux/delay.h>
 158 #include <linux/mISDNhw.h>
 159 #include <linux/mISDNdsp.h>
 160
 161 /*
 162 #define IRQCOUNT_DEBUG
 163 #define IRQ_DEBUG
 164 */
 165
 166 #include "hfc_multi.h"
 167 #ifdef ECHOPREP
 168 #include "gaintab.h"
 169 #endif
 170
 171 #define MAX_CARDS       8
 172 #define MAX_PORTS       (8 * MAX_CARDS)
 173
 174 static LIST_HEAD(HFClist);
 175 static spinlock_t HFClock; /* global hfc list lock */
 176
 177 static void ph_state_change(struct dchannel *);
 178
 179 static struct hfc_multi *syncmaster;
 180 static int plxsd_master; /* if we have a master card (yet) */
 181 static spinlock_t plx_lock; /* may not acquire other lock inside */
 182
 183 #define TYP_E1          1
 184 #define TYP_4S          4
 185 #define TYP_8S          8
 186
 187 static int poll_timer = 6;      /* default = 128 samples = 16ms */
 188 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
 189 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
 190 #define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
 191 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
 192                                    (0x60 MUST be included!) */
 193
 194 #define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
 195 #define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
 196 #define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */
 197
 198 /*
 199  * module stuff
 200  */
 201
 202 static uint     type[MAX_CARDS];
 203 static int      pcm[MAX_CARDS];
 204 static int      dslot[MAX_CARDS];
 205 static uint     iomode[MAX_CARDS];
 206 static uint     port[MAX_PORTS];
 207 static uint     debug;
 208 static uint     poll;
 209 static int      clock;
 210 static uint     timer;
 211 static uint     clockdelay_te = CLKDEL_TE;
 212 static uint     clockdelay_nt = CLKDEL_NT;
 213 #define HWID_NONE       0
 214 #define HWID_MINIP4     1
 215 #define HWID_MINIP8     2
 216 #define HWID_MINIP16    3
 217 static uint     hwid = HWID_NONE;
 218
 219 static int      HFC_cnt, Port_cnt, PCM_cnt = 99;
 220
 221 MODULE_AUTHOR("Andreas Eversberg");
 222 MODULE_LICENSE("GPL");
 223 MODULE_VERSION(HFC_MULTI_VERSION);
 224 module_param(debug, uint, S_IRUGO | S_IWUSR);
 225 module_param(poll, uint, S_IRUGO | S_IWUSR);
 226 module_param(clock, int, S_IRUGO | S_IWUSR);
 227 module_param(timer, uint, S_IRUGO | S_IWUSR);
 228 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
 229 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
 230 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
 231 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
 232 module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
 233 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
 234 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
 235 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
 236
 237 #ifdef HFC_REGISTER_DEBUG
 238 #define HFC_outb(hc, reg, val) \
 239         (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
 240 #define HFC_outb_nodebug(hc, reg, val) \
 241         (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
 242 #define HFC_inb(hc, reg) \
 243         (hc->HFC_inb(hc, reg, __func__, __LINE__))
 244 #define HFC_inb_nodebug(hc, reg) \
 245         (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
 246 #define HFC_inw(hc, reg) \
 247         (hc->HFC_inw(hc, reg, __func__, __LINE__))
 248 #define HFC_inw_nodebug(hc, reg) \
 249         (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
 250 #define HFC_wait(hc) \
 251         (hc->HFC_wait(hc, __func__, __LINE__))
 252 #define HFC_wait_nodebug(hc) \
 253         (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
 254 #else
 255 #define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
 256 #define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
 257 #define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
 258 #define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
 259 #define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
 260 #define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
 261 #define HFC_wait(hc)                    (hc->HFC_wait(hc))
 262 #define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
 263 #endif
 264
 265 #ifdef CONFIG_MISDN_HFCMULTI_8xx
 266 #include "hfc_multi_8xx.h"
 267 #endif
 268
 269 /* HFC_IO_MODE_PCIMEM */
 270 static void
 271 #ifdef HFC_REGISTER_DEBUG
 272 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
 273                 const char *function, int line)
 274 #else
 275 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
 276 #endif
 277 {
 278         writeb(val, hc->pci_membase + reg);
 279 }
 280 static u_char
 281 #ifdef HFC_REGISTER_DEBUG
 282 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 283 #else
 284 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
 285 #endif
 286 {
 287         return readb(hc->pci_membase + reg);
 288 }
 289 static u_short
 290 #ifdef HFC_REGISTER_DEBUG
 291 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 292 #else
 293 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
 294 #endif
 295 {
 296         return readw(hc->pci_membase + reg);
 297 }
 298 static void
 299 #ifdef HFC_REGISTER_DEBUG
 300 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
 301 #else
 302 HFC_wait_pcimem(struct hfc_multi *hc)
 303 #endif
 304 {
 305         while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
 306                 cpu_relax();
 307 }
 308
 309 /* HFC_IO_MODE_REGIO */
 310 static void
 311 #ifdef HFC_REGISTER_DEBUG
 312 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
 313         const char *function, int line)
 314 #else
 315 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
 316 #endif
 317 {
 318         outb(reg, hc->pci_iobase + 4);
 319         outb(val, hc->pci_iobase);
 320 }
 321 static u_char
 322 #ifdef HFC_REGISTER_DEBUG
 323 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 324 #else
 325 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
 326 #endif
 327 {
 328         outb(reg, hc->pci_iobase + 4);
 329         return inb(hc->pci_iobase);
 330 }
 331 static u_short
 332 #ifdef HFC_REGISTER_DEBUG
 333 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 334 #else
 335 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
 336 #endif
 337 {
 338         outb(reg, hc->pci_iobase + 4);
 339         return inw(hc->pci_iobase);
 340 }
 341 static void
 342 #ifdef HFC_REGISTER_DEBUG
 343 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
 344 #else
 345 HFC_wait_regio(struct hfc_multi *hc)
 346 #endif
 347 {
 348         outb(R_STATUS, hc->pci_iobase + 4);
 349         while (inb(hc->pci_iobase) & V_BUSY)
 350                 cpu_relax();
 351 }
 352
 353 #ifdef HFC_REGISTER_DEBUG
 354 static void
 355 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
 356                 const char *function, int line)
 357 {
 358         char regname[256] = "", bits[9] = "xxxxxxxx";
 359         int i;
 360
 361         i = -1;
 362         while (hfc_register_names[++i].name) {
 363                 if (hfc_register_names[i].reg == reg)
 364                         strcat(regname, hfc_register_names[i].name);
 365         }
 366         if (regname[0] == '\0')
 367                 strcpy(regname, "register");
 368
 369         bits[7] = '0' + (!!(val & 1));
 370         bits[6] = '0' + (!!(val & 2));
 371         bits[5] = '0' + (!!(val & 4));
 372         bits[4] = '0' + (!!(val & 8));
 373         bits[3] = '0' + (!!(val & 16));
 374         bits[2] = '0' + (!!(val & 32));
 375         bits[1] = '0' + (!!(val & 64));
 376         bits[0] = '0' + (!!(val & 128));
 377         printk(KERN_DEBUG
 378             "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
 379             hc->id, reg, regname, val, bits, function, line);
 380         HFC_outb_nodebug(hc, reg, val);
 381 }
 382 static u_char
 383 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 384 {
 385         char regname[256] = "", bits[9] = "xxxxxxxx";
 386         u_char val = HFC_inb_nodebug(hc, reg);
 387         int i;
 388
 389         i = 0;
 390         while (hfc_register_names[i++].name)
 391                 ;
 392         while (hfc_register_names[++i].name) {
 393                 if (hfc_register_names[i].reg == reg)
 394                         strcat(regname, hfc_register_names[i].name);
 395         }
 396         if (regname[0] == '\0')
 397                 strcpy(regname, "register");
 398
 399         bits[7] = '0' + (!!(val & 1));
 400         bits[6] = '0' + (!!(val & 2));
 401         bits[5] = '0' + (!!(val & 4));
 402         bits[4] = '0' + (!!(val & 8));
 403         bits[3] = '0' + (!!(val & 16));
 404         bits[2] = '0' + (!!(val & 32));
 405         bits[1] = '0' + (!!(val & 64));
 406         bits[0] = '0' + (!!(val & 128));
 407         printk(KERN_DEBUG
 408             "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
 409             hc->id, reg, regname, val, bits, function, line);
 410         return val;
 411 }
 412 static u_short
 413 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 414 {
 415         char regname[256] = "";
 416         u_short val = HFC_inw_nodebug(hc, reg);
 417         int i;
 418
 419         i = 0;
 420         while (hfc_register_names[i++].name)
 421                 ;
 422         while (hfc_register_names[++i].name) {
 423                 if (hfc_register_names[i].reg == reg)
 424                         strcat(regname, hfc_register_names[i].name);
 425         }
 426         if (regname[0] == '\0')
 427                 strcpy(regname, "register");
 428
 429         printk(KERN_DEBUG
 430             "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
 431             hc->id, reg, regname, val, function, line);
 432         return val;
 433 }
 434 static void
 435 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
 436 {
 437         printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
 438             hc->id, function, line);
 439         HFC_wait_nodebug(hc);
 440 }
 441 #endif
 442
 443 /* write fifo data (REGIO) */
 444 static void
 445 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 446 {
 447         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 448         while (len>>2) {
 449                 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
 450                 data += 4;
 451                 len -= 4;
 452         }
 453         while (len>>1) {
 454                 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
 455                 data += 2;
 456                 len -= 2;
 457         }
 458         while (len) {
 459                 outb(*data, hc->pci_iobase);
 460                 data++;
 461                 len--;
 462         }
 463 }
 464 /* write fifo data (PCIMEM) */
 465 static void
 466 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 467 {
 468         while (len>>2) {
 469                 writel(cpu_to_le32(*(u32 *)data),
 470                         hc->pci_membase + A_FIFO_DATA0);
 471                 data += 4;
 472                 len -= 4;
 473         }
 474         while (len>>1) {
 475                 writew(cpu_to_le16(*(u16 *)data),
 476                         hc->pci_membase + A_FIFO_DATA0);
 477                 data += 2;
 478                 len -= 2;
 479         }
 480         while (len) {
 481                 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
 482                 data++;
 483                 len--;
 484         }
 485 }
 486
 487 /* read fifo data (REGIO) */
 488 static void
 489 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 490 {
 491         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 492         while (len>>2) {
 493                 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
 494                 data += 4;
 495                 len -= 4;
 496         }
 497         while (len>>1) {
 498                 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
 499                 data += 2;
 500                 len -= 2;
 501         }
 502         while (len) {
 503                 *data = inb(hc->pci_iobase);
 504                 data++;
 505                 len--;
 506         }
 507 }
 508
 509 /* read fifo data (PCIMEM) */
 510 static void
 511 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 512 {
 513         while (len>>2) {
 514                 *(u32 *)data =
 515                         le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
 516                 data += 4;
 517                 len -= 4;
 518         }
 519         while (len>>1) {
 520                 *(u16 *)data =
 521                         le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
 522                 data += 2;
 523                 len -= 2;
 524         }
 525         while (len) {
 526                 *data = readb(hc->pci_membase + A_FIFO_DATA0);
 527                 data++;
 528                 len--;
 529         }
 530 }
 531
 532 static void
 533 enable_hwirq(struct hfc_multi *hc)
 534 {
 535         hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
 536         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 537 }
 538
 539 static void
 540 disable_hwirq(struct hfc_multi *hc)
 541 {
 542         hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
 543         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 544 }
 545
 546 #define NUM_EC 2
 547 #define MAX_TDM_CHAN 32
 548
 549
 550 inline void
 551 enablepcibridge(struct hfc_multi *c)
 552 {
 553         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
 554 }
 555
 556 inline void
 557 disablepcibridge(struct hfc_multi *c)
 558 {
 559         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
 560 }
 561
 562 inline unsigned char
 563 readpcibridge(struct hfc_multi *hc, unsigned char address)
 564 {
 565         unsigned short cipv;
 566         unsigned char data;
 567
 568         if (!hc->pci_iobase)
 569                 return 0;
 570
 571         /* slow down a PCI read access by 1 PCI clock cycle */
 572         HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
 573
 574         if (address == 0)
 575                 cipv = 0x4000;
 576         else
 577                 cipv = 0x5800;
 578
 579         /* select local bridge port address by writing to CIP port */
 580         /* data = HFC_inb(c, cipv); * was _io before */
 581         outw(cipv, hc->pci_iobase + 4);
 582         data = inb(hc->pci_iobase);
 583
 584         /* restore R_CTRL for normal PCI read cycle speed */
 585         HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
 586
 587         return data;
 588 }
 589
 590 inline void
 591 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
 592 {
 593         unsigned short cipv;
 594         unsigned int datav;
 595
 596         if (!hc->pci_iobase)
 597                 return;
 598
 599         if (address == 0)
 600                 cipv = 0x4000;
 601         else
 602                 cipv = 0x5800;
 603
 604         /* select local bridge port address by writing to CIP port */
 605         outw(cipv, hc->pci_iobase + 4);
 606         /* define a 32 bit dword with 4 identical bytes for write sequence */
 607         datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
 608             ((__u32) data << 24);
 609
 610         /*
 611          * write this 32 bit dword to the bridge data port
 612          * this will initiate a write sequence of up to 4 writes to the same
 613          * address on the local bus interface the number of write accesses
 614          * is undefined but >=1 and depends on the next PCI transaction
 615          * during write sequence on the local bus
 616          */
 617         outl(datav, hc->pci_iobase);
 618 }
 619
 620 inline void
 621 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
 622 {
 623         /* Do data pin read low byte */
 624         HFC_outb(hc, R_GPIO_OUT1, reg);
 625 }
 626
 627 inline void
 628 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
 629 {
 630         cpld_set_reg(hc, reg);
 631
 632         enablepcibridge(hc);
 633         writepcibridge(hc, 1, val);
 634         disablepcibridge(hc);
 635
 636         return;
 637 }
 638
 639 inline unsigned char
 640 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
 641 {
 642         unsigned char bytein;
 643
 644         cpld_set_reg(hc, reg);
 645
 646         /* Do data pin read low byte */
 647         HFC_outb(hc, R_GPIO_OUT1, reg);
 648
 649         enablepcibridge(hc);
 650         bytein = readpcibridge(hc, 1);
 651         disablepcibridge(hc);
 652
 653         return bytein;
 654 }
 655
 656 inline void
 657 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
 658 {
 659         cpld_write_reg(hc, 0, 0xff & addr);
 660         cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
 661 }
 662
 663 inline unsigned short
 664 vpm_read_address(struct hfc_multi *c)
 665 {
 666         unsigned short addr;
 667         unsigned short highbit;
 668
 669         addr = cpld_read_reg(c, 0);
 670         highbit = cpld_read_reg(c, 1);
 671
 672         addr = addr | (highbit << 8);
 673
 674         return addr & 0x1ff;
 675 }
 676
 677 inline unsigned char
 678 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
 679 {
 680         unsigned char res;
 681
 682         vpm_write_address(c, addr);
 683
 684         if (!which)
 685                 cpld_set_reg(c, 2);
 686         else
 687                 cpld_set_reg(c, 3);
 688
 689         enablepcibridge(c);
 690         res = readpcibridge(c, 1);
 691         disablepcibridge(c);
 692
 693         cpld_set_reg(c, 0);
 694
 695         return res;
 696 }
 697
 698 inline void
 699 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
 700     unsigned char data)
 701 {
 702         vpm_write_address(c, addr);
 703
 704         enablepcibridge(c);
 705
 706         if (!which)
 707                 cpld_set_reg(c, 2);
 708         else
 709                 cpld_set_reg(c, 3);
 710
 711         writepcibridge(c, 1, data);
 712
 713         cpld_set_reg(c, 0);
 714
 715         disablepcibridge(c);
 716
 717         {
 718         unsigned char regin;
 719         regin = vpm_in(c, which, addr);
 720         if (regin != data)
 721                 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
 722                         "0x%x\n", data, addr, regin);
 723         }
 724
 725 }
 726
 727
 728 static void
 729 vpm_init(struct hfc_multi *wc)
 730 {
 731         unsigned char reg;
 732         unsigned int mask;
 733         unsigned int i, x, y;
 734         unsigned int ver;
 735
 736         for (x = 0; x < NUM_EC; x++) {
 737                 /* Setup GPIO's */
 738                 if (!x) {
 739                         ver = vpm_in(wc, x, 0x1a0);
 740                         printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
 741                 }
 742
 743                 for (y = 0; y < 4; y++) {
 744                         vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
 745                         vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
 746                         vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
 747                 }
 748
 749                 /* Setup TDM path - sets fsync and tdm_clk as inputs */
 750                 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
 751                 vpm_out(wc, x, 0x1a3, reg & ~2);
 752
 753                 /* Setup Echo length (256 taps) */
 754                 vpm_out(wc, x, 0x022, 1);
 755                 vpm_out(wc, x, 0x023, 0xff);
 756
 757                 /* Setup timeslots */
 758                 vpm_out(wc, x, 0x02f, 0x00);
 759                 mask = 0x02020202 << (x * 4);
 760
 761                 /* Setup the tdm channel masks for all chips */
 762                 for (i = 0; i < 4; i++)
 763                         vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
 764
 765                 /* Setup convergence rate */
 766                 printk(KERN_DEBUG "VPM: A-law mode\n");
 767                 reg = 0x00 | 0x10 | 0x01;
 768                 vpm_out(wc, x, 0x20, reg);
 769                 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
 770                 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
 771
 772                 vpm_out(wc, x, 0x24, 0x02);
 773                 reg = vpm_in(wc, x, 0x24);
 774                 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
 775
 776                 /* Initialize echo cans */
 777                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 778                         if (mask & (0x00000001 << i))
 779                                 vpm_out(wc, x, i, 0x00);
 780                 }
 781
 782                 /*
 783                  * ARM arch at least disallows a udelay of
 784                  * more than 2ms... it gives a fake "__bad_udelay"
 785                  * reference at link-time.
 786                  * long delays in kernel code are pretty sucky anyway
 787                  * for now work around it using 5 x 2ms instead of 1 x 10ms
 788                  */
 789
 790                 udelay(2000);
 791                 udelay(2000);
 792                 udelay(2000);
 793                 udelay(2000);
 794                 udelay(2000);
 795
 796                 /* Put in bypass mode */
 797                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 798                         if (mask & (0x00000001 << i))
 799                                 vpm_out(wc, x, i, 0x01);
 800                 }
 801
 802                 /* Enable bypass */
 803                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 804                         if (mask & (0x00000001 << i))
 805                                 vpm_out(wc, x, 0x78 + i, 0x01);
 806                 }
 807
 808         }
 809 }
 810
 811 #ifdef UNUSED
 812 static void
 813 vpm_check(struct hfc_multi *hctmp)
 814 {
 815         unsigned char gpi2;
 816
 817         gpi2 = HFC_inb(hctmp, R_GPI_IN2);
 818
 819         if ((gpi2 & 0x3) != 0x3)
 820                 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
 821 }
 822 #endif /* UNUSED */
 823
 824
 825 /*
 826  * Interface to enable/disable the HW Echocan
 827  *
 828  * these functions are called within a spin_lock_irqsave on
 829  * the channel instance lock, so we are not disturbed by irqs
 830  *
 831  * we can later easily change the interface to make  other
 832  * things configurable, for now we configure the taps
 833  *
 834  */
 835
 836 static void
 837 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
 838 {
 839         unsigned int timeslot;
 840         unsigned int unit;
 841         struct bchannel *bch = hc->chan[ch].bch;
 842 #ifdef TXADJ
 843         int txadj = -4;
 844         struct sk_buff *skb;
 845 #endif
 846         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 847                 return;
 848
 849         if (!bch)
 850                 return;
 851
 852 #ifdef TXADJ
 853         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 854                 sizeof(int), &txadj, GFP_ATOMIC);
 855         if (skb)
 856                 recv_Bchannel_skb(bch, skb);
 857 #endif
 858
 859         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 860         unit = ch % 4;
 861
 862         printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
 863             taps, timeslot);
 864
 865         vpm_out(hc, unit, timeslot, 0x7e);
 866 }
 867
 868 static void
 869 vpm_echocan_off(struct hfc_multi *hc, int ch)
 870 {
 871         unsigned int timeslot;
 872         unsigned int unit;
 873         struct bchannel *bch = hc->chan[ch].bch;
 874 #ifdef TXADJ
 875         int txadj = 0;
 876         struct sk_buff *skb;
 877 #endif
 878
 879         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 880                 return;
 881
 882         if (!bch)
 883                 return;
 884
 885 #ifdef TXADJ
 886         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 887                 sizeof(int), &txadj, GFP_ATOMIC);
 888         if (skb)
 889                 recv_Bchannel_skb(bch, skb);
 890 #endif
 891
 892         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 893         unit = ch % 4;
 894
 895         printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
 896             timeslot);
 897         /* FILLME */
 898         vpm_out(hc, unit, timeslot, 0x01);
 899 }
 900
 901
 902 /*
 903  * Speech Design resync feature
 904  * NOTE: This is called sometimes outside interrupt handler.
 905  * We must lock irqsave, so no other interrupt (other card) will occurr!
 906  * Also multiple interrupts may nest, so must lock each access (lists, card)!
 907  */
 908 static inline void
 909 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
 910 {
 911         struct hfc_multi *hc, *next, *pcmmaster = NULL;
 912         void __iomem *plx_acc_32;
 913         u_int pv;
 914         u_long flags;
 915
 916         spin_lock_irqsave(&HFClock, flags);
 917         spin_lock(&plx_lock); /* must be locked inside other locks */
 918
 919         if (debug & DEBUG_HFCMULTI_PLXSD)
 920                 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
 921                         __func__, syncmaster);
 922
 923         /* select new master */
 924         if (newmaster) {
 925                 if (debug & DEBUG_HFCMULTI_PLXSD)
 926                         printk(KERN_DEBUG "using provided controller\n");
 927         } else {
 928                 list_for_each_entry_safe(hc, next, &HFClist, list) {
 929                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 930                                 if (hc->syncronized) {
 931                                         newmaster = hc;
 932                                         break;
 933                                 }
 934                         }
 935                 }
 936         }
 937
 938         /* Disable sync of all cards */
 939         list_for_each_entry_safe(hc, next, &HFClist, list) {
 940                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 941                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 942                         pv = readl(plx_acc_32);
 943                         pv &= ~PLX_SYNC_O_EN;
 944                         writel(pv, plx_acc_32);
 945                         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
 946                                 pcmmaster = hc;
 947                                 if (hc->ctype == HFC_TYPE_E1) {
 948                                         if (debug & DEBUG_HFCMULTI_PLXSD)
 949                                                 printk(KERN_DEBUG
 950                                                         "Schedule SYNC_I\n");
 951                                         hc->e1_resync |= 1; /* get SYNC_I */
 952                                 }
 953                         }
 954                 }
 955         }
 956
 957         if (newmaster) {
 958                 hc = newmaster;
 959                 if (debug & DEBUG_HFCMULTI_PLXSD)
 960                         printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
 961                                 "interface.\n", hc->id, hc);
 962                 /* Enable new sync master */
 963                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 964                 pv = readl(plx_acc_32);
 965                 pv |= PLX_SYNC_O_EN;
 966                 writel(pv, plx_acc_32);
 967                 /* switch to jatt PLL, if not disabled by RX_SYNC */
 968                 if (hc->ctype == HFC_TYPE_E1
 969                                 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
 970                         if (debug & DEBUG_HFCMULTI_PLXSD)
 971                                 printk(KERN_DEBUG "Schedule jatt PLL\n");
 972                         hc->e1_resync |= 2; /* switch to jatt */
 973                 }
 974         } else {
 975                 if (pcmmaster) {
 976                         hc = pcmmaster;
 977                         if (debug & DEBUG_HFCMULTI_PLXSD)
 978                                 printk(KERN_DEBUG
 979                                         "id=%d (0x%p) = PCM master syncronized "
 980                                         "with QUARTZ\n", hc->id, hc);
 981                         if (hc->ctype == HFC_TYPE_E1) {
 982                                 /* Use the crystal clock for the PCM
 983                                    master card */
 984                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 985                                         printk(KERN_DEBUG
 986                                             "Schedule QUARTZ for HFC-E1\n");
 987                                 hc->e1_resync |= 4; /* switch quartz */
 988                         } else {
 989                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 990                                         printk(KERN_DEBUG
 991                                             "QUARTZ is automatically "
 992                                             "enabled by HFC-%dS\n", hc->ctype);
 993                         }
 994                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 995                         pv = readl(plx_acc_32);
 996                         pv |= PLX_SYNC_O_EN;
 997                         writel(pv, plx_acc_32);
 998                 } else
 999                         if (!rm)
1000                                 printk(KERN_ERR "%s no pcm master, this MUST "
1001                                         "not happen!\n", __func__);
1002         }
1003         syncmaster = newmaster;
1004
1005         spin_unlock(&plx_lock);
1006         spin_unlock_irqrestore(&HFClock, flags);
1007 }
1008
1009 /* This must be called AND hc must be locked irqsave!!! */
1010 inline void
1011 plxsd_checksync(struct hfc_multi *hc, int rm)
1012 {
1013         if (hc->syncronized) {
1014                 if (syncmaster == NULL) {
1015                         if (debug & DEBUG_HFCMULTI_PLXSD)
1016                                 printk(KERN_DEBUG "%s: GOT sync on card %d"
1017                                         " (id=%d)\n", __func__, hc->id + 1,
1018                                         hc->id);
1019                         hfcmulti_resync(hc, hc, rm);
1020                 }
1021         } else {
1022                 if (syncmaster == hc) {
1023                         if (debug & DEBUG_HFCMULTI_PLXSD)
1024                                 printk(KERN_DEBUG "%s: LOST sync on card %d"
1025                                         " (id=%d)\n", __func__, hc->id + 1,
1026                                         hc->id);
1027                         hfcmulti_resync(hc, NULL, rm);
1028                 }
1029         }
1030 }
1031
1032
1033 /*
1034  * free hardware resources used by driver
1035  */
1036 static void
1037 release_io_hfcmulti(struct hfc_multi *hc)
1038 {
1039         void __iomem *plx_acc_32;
1040         u_int   pv;
1041         u_long  plx_flags;
1042
1043         if (debug & DEBUG_HFCMULTI_INIT)
1044                 printk(KERN_DEBUG "%s: entered\n", __func__);
1045
1046         /* soft reset also masks all interrupts */
1047         hc->hw.r_cirm |= V_SRES;
1048         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1049         udelay(1000);
1050         hc->hw.r_cirm &= ~V_SRES;
1051         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1052         udelay(1000); /* instead of 'wait' that may cause locking */
1053
1054         /* release Speech Design card, if PLX was initialized */
1055         if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1056                 if (debug & DEBUG_HFCMULTI_PLXSD)
1057                         printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1058                             __func__, hc->id + 1);
1059                 spin_lock_irqsave(&plx_lock, plx_flags);
1060                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1061                 writel(PLX_GPIOC_INIT, plx_acc_32);
1062                 pv = readl(plx_acc_32);
1063                 /* Termination off */
1064                 pv &= ~PLX_TERM_ON;
1065                 /* Disconnect the PCM */
1066                 pv |= PLX_SLAVE_EN_N;
1067                 pv &= ~PLX_MASTER_EN;
1068                 pv &= ~PLX_SYNC_O_EN;
1069                 /* Put the DSP in Reset */
1070                 pv &= ~PLX_DSP_RES_N;
1071                 writel(pv, plx_acc_32);
1072                 if (debug & DEBUG_HFCMULTI_INIT)
1073                         printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
1074                                 __func__, pv);
1075                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1076         }
1077
1078         /* disable memory mapped ports / io ports */
1079         test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1080         if (hc->pci_dev)
1081                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1082         if (hc->pci_membase)
1083                 iounmap(hc->pci_membase);
1084         if (hc->plx_membase)
1085                 iounmap(hc->plx_membase);
1086         if (hc->pci_iobase)
1087                 release_region(hc->pci_iobase, 8);
1088         if (hc->xhfc_membase)
1089                 iounmap((void *)hc->xhfc_membase);
1090
1091         if (hc->pci_dev) {
1092                 pci_disable_device(hc->pci_dev);
1093                 pci_set_drvdata(hc->pci_dev, NULL);
1094         }
1095         if (debug & DEBUG_HFCMULTI_INIT)
1096                 printk(KERN_DEBUG "%s: done\n", __func__);
1097 }
1098
1099 /*
1100  * function called to reset the HFC chip. A complete software reset of chip
1101  * and fifos is done. All configuration of the chip is done.
1102  */
1103
1104 static int
1105 init_chip(struct hfc_multi *hc)
1106 {
1107         u_long                  flags, val, val2 = 0, rev;
1108         int                     i, err = 0;
1109         u_char                  r_conf_en, rval;
1110         void __iomem            *plx_acc_32;
1111         u_int                   pv;
1112         u_long                  plx_flags, hfc_flags;
1113         int                     plx_count;
1114         struct hfc_multi        *pos, *next, *plx_last_hc;
1115
1116         spin_lock_irqsave(&hc->lock, flags);
1117         /* reset all registers */
1118         memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1119
1120         /* revision check */
1121         if (debug & DEBUG_HFCMULTI_INIT)
1122                 printk(KERN_DEBUG "%s: entered\n", __func__);
1123         val = HFC_inb(hc, R_CHIP_ID);
1124         if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1125             (val >> 1) != 0x31) {
1126                 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1127                 err = -EIO;
1128                 goto out;
1129         }
1130         rev = HFC_inb(hc, R_CHIP_RV);
1131         printk(KERN_INFO
1132             "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1133             val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1134                 " (old FIFO handling)" : "");
1135         if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1136                 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1137                 printk(KERN_WARNING
1138                     "HFC_multi: NOTE: Your chip is revision 0, "
1139                     "ask Cologne Chip for update. Newer chips "
1140                     "have a better FIFO handling. Old chips "
1141                     "still work but may have slightly lower "
1142                     "HDLC transmit performance.\n");
1143         }
1144         if (rev > 1) {
1145                 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1146                     "consider chip revision = %ld. The chip / "
1147                     "bridge may not work.\n", rev);
1148         }
1149
1150         /* set s-ram size */
1151         hc->Flen = 0x10;
1152         hc->Zmin = 0x80;
1153         hc->Zlen = 384;
1154         hc->DTMFbase = 0x1000;
1155         if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1156                 if (debug & DEBUG_HFCMULTI_INIT)
1157                         printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1158                             __func__);
1159                 hc->hw.r_ctrl |= V_EXT_RAM;
1160                 hc->hw.r_ram_sz = 1;
1161                 hc->Flen = 0x20;
1162                 hc->Zmin = 0xc0;
1163                 hc->Zlen = 1856;
1164                 hc->DTMFbase = 0x2000;
1165         }
1166         if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1167                 if (debug & DEBUG_HFCMULTI_INIT)
1168                         printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1169                             __func__);
1170                 hc->hw.r_ctrl |= V_EXT_RAM;
1171                 hc->hw.r_ram_sz = 2;
1172                 hc->Flen = 0x20;
1173                 hc->Zmin = 0xc0;
1174                 hc->Zlen = 8000;
1175                 hc->DTMFbase = 0x2000;
1176         }
1177         if (hc->ctype == HFC_TYPE_XHFC) {
1178                 hc->Flen = 0x8;
1179                 hc->Zmin = 0x0;
1180                 hc->Zlen = 64;
1181                 hc->DTMFbase = 0x0;
1182         }
1183         hc->max_trans = poll << 1;
1184         if (hc->max_trans > hc->Zlen)
1185                 hc->max_trans = hc->Zlen;
1186
1187         /* Speech Design PLX bridge */
1188         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1189                 if (debug & DEBUG_HFCMULTI_PLXSD)
1190                         printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1191                             __func__, hc->id + 1);
1192                 spin_lock_irqsave(&plx_lock, plx_flags);
1193                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1194                 writel(PLX_GPIOC_INIT, plx_acc_32);
1195                 pv = readl(plx_acc_32);
1196                 /* The first and the last cards are terminating the PCM bus */
1197                 pv |= PLX_TERM_ON; /* hc is currently the last */
1198                 /* Disconnect the PCM */
1199                 pv |= PLX_SLAVE_EN_N;
1200                 pv &= ~PLX_MASTER_EN;
1201                 pv &= ~PLX_SYNC_O_EN;
1202                 /* Put the DSP in Reset */
1203                 pv &= ~PLX_DSP_RES_N;
1204                 writel(pv, plx_acc_32);
1205                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1206                 if (debug & DEBUG_HFCMULTI_INIT)
1207                         printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
1208                                 __func__, pv);
1209                 /*
1210                  * If we are the 3rd PLXSD card or higher, we must turn
1211                  * termination of last PLXSD card off.
1212                  */
1213                 spin_lock_irqsave(&HFClock, hfc_flags);
1214                 plx_count = 0;
1215                 plx_last_hc = NULL;
1216                 list_for_each_entry_safe(pos, next, &HFClist, list) {
1217                         if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1218                                 plx_count++;
1219                                 if (pos != hc)
1220                                         plx_last_hc = pos;
1221                         }
1222                 }
1223                 if (plx_count >= 3) {
1224                         if (debug & DEBUG_HFCMULTI_PLXSD)
1225                                 printk(KERN_DEBUG "%s: card %d is between, so "
1226                                         "we disable termination\n",
1227                                     __func__, plx_last_hc->id + 1);
1228                         spin_lock_irqsave(&plx_lock, plx_flags);
1229                         plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1230                         pv = readl(plx_acc_32);
1231                         pv &= ~PLX_TERM_ON;
1232                         writel(pv, plx_acc_32);
1233                         spin_unlock_irqrestore(&plx_lock, plx_flags);
1234                         if (debug & DEBUG_HFCMULTI_INIT)
1235                                 printk(KERN_DEBUG
1236                                     "%s: term off: PLX_GPIO=%x\n",
1237                                     __func__, pv);
1238                 }
1239                 spin_unlock_irqrestore(&HFClock, hfc_flags);
1240                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1241         }
1242
1243         if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1244                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1245
1246         /* we only want the real Z2 read-pointer for revision > 0 */
1247         if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1248                 hc->hw.r_ram_sz |= V_FZ_MD;
1249
1250         /* select pcm mode */
1251         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1252                 if (debug & DEBUG_HFCMULTI_INIT)
1253                         printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1254                             __func__);
1255         } else
1256         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1257                 if (debug & DEBUG_HFCMULTI_INIT)
1258                         printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1259                             __func__);
1260                 hc->hw.r_pcm_md0 |= V_PCM_MD;
1261         } else {
1262                 if (debug & DEBUG_HFCMULTI_INIT)
1263                         printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1264                             __func__);
1265         }
1266
1267         /* soft reset */
1268         HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1269         if (hc->ctype == HFC_TYPE_XHFC)
1270                 HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1271                                 0x11 /* 16 Bytes TX/RX */);
1272         else
1273                 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1274         HFC_outb(hc, R_FIFO_MD, 0);
1275         if (hc->ctype == HFC_TYPE_XHFC)
1276                 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1277         else
1278                 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1279                         | V_RLD_EPR;
1280         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1281         udelay(100);
1282         hc->hw.r_cirm = 0;
1283         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1284         udelay(100);
1285         if (hc->ctype != HFC_TYPE_XHFC)
1286                 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1287
1288         /* Speech Design PLX bridge pcm and sync mode */
1289         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1290                 spin_lock_irqsave(&plx_lock, plx_flags);
1291                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1292                 pv = readl(plx_acc_32);
1293                 /* Connect PCM */
1294                 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1295                         pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1296                         pv |= PLX_SYNC_O_EN;
1297                         if (debug & DEBUG_HFCMULTI_INIT)
1298                                 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
1299                                         __func__, pv);
1300                 } else {
1301                         pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1302                         pv &= ~PLX_SYNC_O_EN;
1303                         if (debug & DEBUG_HFCMULTI_INIT)
1304                                 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
1305                                         __func__, pv);
1306                 }
1307                 writel(pv, plx_acc_32);
1308                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1309         }
1310
1311         /* PCM setup */
1312         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1313         if (hc->slots == 32)
1314                 HFC_outb(hc, R_PCM_MD1, 0x00);
1315         if (hc->slots == 64)
1316                 HFC_outb(hc, R_PCM_MD1, 0x10);
1317         if (hc->slots == 128)
1318                 HFC_outb(hc, R_PCM_MD1, 0x20);
1319         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1320         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1321                 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1322         else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1323                 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1324         else
1325                 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1326         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1327         for (i = 0; i < 256; i++) {
1328                 HFC_outb_nodebug(hc, R_SLOT, i);
1329                 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1330                 if (hc->ctype != HFC_TYPE_XHFC)
1331                         HFC_outb_nodebug(hc, A_CONF, 0);
1332                 hc->slot_owner[i] = -1;
1333         }
1334
1335         /* set clock speed */
1336         if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1337                 if (debug & DEBUG_HFCMULTI_INIT)
1338                         printk(KERN_DEBUG
1339                             "%s: setting double clock\n", __func__);
1340                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1341         }
1342
1343         if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1344                 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1345
1346         /* B410P GPIO */
1347         if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1348                 printk(KERN_NOTICE "Setting GPIOs\n");
1349                 HFC_outb(hc, R_GPIO_SEL, 0x30);
1350                 HFC_outb(hc, R_GPIO_EN1, 0x3);
1351                 udelay(1000);
1352                 printk(KERN_NOTICE "calling vpm_init\n");
1353                 vpm_init(hc);
1354         }
1355
1356         /* check if R_F0_CNT counts (8 kHz frame count) */
1357         val = HFC_inb(hc, R_F0_CNTL);
1358         val += HFC_inb(hc, R_F0_CNTH) << 8;
1359         if (debug & DEBUG_HFCMULTI_INIT)
1360                 printk(KERN_DEBUG
1361                     "HFC_multi F0_CNT %ld after reset\n", val);
1362         spin_unlock_irqrestore(&hc->lock, flags);
1363         set_current_state(TASK_UNINTERRUPTIBLE);
1364         schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1365         spin_lock_irqsave(&hc->lock, flags);
1366         val2 = HFC_inb(hc, R_F0_CNTL);
1367         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1368         if (debug & DEBUG_HFCMULTI_INIT)
1369                 printk(KERN_DEBUG
1370                         "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1371                     val2);
1372         if (val2 >= val+8) { /* 1 ms */
1373                 /* it counts, so we keep the pcm mode */
1374                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1375                         printk(KERN_INFO "controller is PCM bus MASTER\n");
1376                 else
1377                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1378                         printk(KERN_INFO "controller is PCM bus SLAVE\n");
1379                 else {
1380                         test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1381                         printk(KERN_INFO "controller is PCM bus SLAVE "
1382                                 "(auto detected)\n");
1383                 }
1384         } else {
1385                 /* does not count */
1386                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1387 controller_fail:
1388                         printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1389                             "pulse. Seems that controller fails.\n");
1390                         err = -EIO;
1391                         goto out;
1392                 }
1393                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1394                         printk(KERN_INFO "controller is PCM bus SLAVE "
1395                                 "(ignoring missing PCM clock)\n");
1396                 } else {
1397                         /* only one pcm master */
1398                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1399                                 && plxsd_master) {
1400                                 printk(KERN_ERR "HFC_multi ERROR, no clock "
1401                                     "on another Speech Design card found. "
1402                                     "Please be sure to connect PCM cable.\n");
1403                                 err = -EIO;
1404                                 goto out;
1405                         }
1406                         /* retry with master clock */
1407                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1408                                 spin_lock_irqsave(&plx_lock, plx_flags);
1409                                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1410                                 pv = readl(plx_acc_32);
1411                                 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1412                                 pv |= PLX_SYNC_O_EN;
1413                                 writel(pv, plx_acc_32);
1414                                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1415                                 if (debug & DEBUG_HFCMULTI_INIT)
1416                                         printk(KERN_DEBUG "%s: master: "
1417                                             "PLX_GPIO=%x\n", __func__, pv);
1418                         }
1419                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1420                         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1421                         spin_unlock_irqrestore(&hc->lock, flags);
1422                         set_current_state(TASK_UNINTERRUPTIBLE);
1423                         schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1424                         spin_lock_irqsave(&hc->lock, flags);
1425                         val2 = HFC_inb(hc, R_F0_CNTL);
1426                         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1427                         if (debug & DEBUG_HFCMULTI_INIT)
1428                                 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1429                                         "10 ms (2nd try)\n", val2);
1430                         if (val2 >= val+8) { /* 1 ms */
1431                                 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1432                                         &hc->chip);
1433                                 printk(KERN_INFO "controller is PCM bus MASTER "
1434                                         "(auto detected)\n");
1435                         } else
1436                                 goto controller_fail;
1437                 }
1438         }
1439
1440         /* Release the DSP Reset */
1441         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1442                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1443                         plxsd_master = 1;
1444                 spin_lock_irqsave(&plx_lock, plx_flags);
1445                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1446                 pv = readl(plx_acc_32);
1447                 pv |=  PLX_DSP_RES_N;
1448                 writel(pv, plx_acc_32);
1449                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1450                 if (debug & DEBUG_HFCMULTI_INIT)
1451                         printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
1452                                 __func__, pv);
1453         }
1454
1455         /* pcm id */
1456         if (hc->pcm)
1457                 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1458                         hc->pcm);
1459         else {
1460                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1461                  || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1462                         PCM_cnt++; /* SD has proprietary bridging */
1463                 }
1464                 hc->pcm = PCM_cnt;
1465                 printk(KERN_INFO "controller has PCM BUS ID %d "
1466                         "(auto selected)\n", hc->pcm);
1467         }
1468
1469         /* set up timer */
1470         HFC_outb(hc, R_TI_WD, poll_timer);
1471         hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1472
1473         /* set E1 state machine IRQ */
1474         if (hc->ctype == HFC_TYPE_E1)
1475                 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1476
1477         /* set DTMF detection */
1478         if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1479                 if (debug & DEBUG_HFCMULTI_INIT)
1480                         printk(KERN_DEBUG "%s: enabling DTMF detection "
1481                             "for all B-channel\n", __func__);
1482                 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1483                 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1484                         hc->hw.r_dtmf |= V_ULAW_SEL;
1485                 HFC_outb(hc, R_DTMF_N, 102 - 1);
1486                 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1487         }
1488
1489         /* conference engine */
1490         if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1491                 r_conf_en = V_CONF_EN | V_ULAW;
1492         else
1493                 r_conf_en = V_CONF_EN;
1494         if (hc->ctype != HFC_TYPE_XHFC)
1495                 HFC_outb(hc, R_CONF_EN, r_conf_en);
1496
1497         /* setting leds */
1498         switch (hc->leds) {
1499         case 1: /* HFC-E1 OEM */
1500                 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1501                         HFC_outb(hc, R_GPIO_SEL, 0x32);
1502                 else
1503                         HFC_outb(hc, R_GPIO_SEL, 0x30);
1504
1505                 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1506                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1507
1508                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1509                 break;
1510
1511         case 2: /* HFC-4S OEM */
1512         case 3:
1513                 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1514                 HFC_outb(hc, R_GPIO_EN1, 0xff);
1515                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1516                 break;
1517         }
1518
1519         if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1520                 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1521                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1522         }
1523
1524         /* set master clock */
1525         if (hc->masterclk >= 0) {
1526                 if (debug & DEBUG_HFCMULTI_INIT)
1527                         printk(KERN_DEBUG "%s: setting ST master clock "
1528                             "to port %d (0..%d)\n",
1529                             __func__, hc->masterclk, hc->ports-1);
1530                 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1531                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1532         }
1533
1534
1535
1536         /* setting misc irq */
1537         HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1538         if (debug & DEBUG_HFCMULTI_INIT)
1539                 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1540                     hc->hw.r_irqmsk_misc);
1541
1542         /* RAM access test */
1543         HFC_outb(hc, R_RAM_ADDR0, 0);
1544         HFC_outb(hc, R_RAM_ADDR1, 0);
1545         HFC_outb(hc, R_RAM_ADDR2, 0);
1546         for (i = 0; i < 256; i++) {
1547                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1548                 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1549         }
1550         for (i = 0; i < 256; i++) {
1551                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1552                 HFC_inb_nodebug(hc, R_RAM_DATA);
1553                 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1554                 if (rval != ((i * 3) & 0xff)) {
1555                         printk(KERN_DEBUG
1556                             "addr:%x val:%x should:%x\n", i, rval,
1557                             (i * 3) & 0xff);
1558                         err++;
1559                 }
1560         }
1561         if (err) {
1562                 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1563                 err = -EIO;
1564                 goto out;
1565         }
1566
1567         if (debug & DEBUG_HFCMULTI_INIT)
1568                 printk(KERN_DEBUG "%s: done\n", __func__);
1569 out:
1570         spin_unlock_irqrestore(&hc->lock, flags);
1571         return err;
1572 }
1573
1574
1575 /*
1576  * control the watchdog
1577  */
1578 static void
1579 hfcmulti_watchdog(struct hfc_multi *hc)
1580 {
1581         hc->wdcount++;
1582
1583         if (hc->wdcount > 10) {
1584                 hc->wdcount = 0;
1585                 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1586                     V_GPIO_OUT3 : V_GPIO_OUT2;
1587
1588         /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1589                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1590                 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1591         }
1592 }
1593
1594
1595
1596 /*
1597  * output leds
1598  */
1599 static void
1600 hfcmulti_leds(struct hfc_multi *hc)
1601 {
1602         unsigned long lled;
1603         unsigned long leddw;
1604         int i, state, active, leds;
1605         struct dchannel *dch;
1606         int led[4];
1607
1608         hc->ledcount += poll;
1609         if (hc->ledcount > 4096) {
1610                 hc->ledcount -= 4096;
1611                 hc->ledstate = 0xAFFEAFFE;
1612         }
1613
1614         switch (hc->leds) {
1615         case 1: /* HFC-E1 OEM */
1616                 /* 2 red blinking: NT mode deactivate
1617                  * 2 red steady:   TE mode deactivate
1618                  * left green:     L1 active
1619                  * left red:       frame sync, but no L1
1620                  * right green:    L2 active
1621                  */
1622                 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1623                         if (hc->chan[hc->dslot].dch->dev.D.protocol
1624                                 != ISDN_P_NT_E1) {
1625                                 led[0] = 1;
1626                                 led[1] = 1;
1627                         } else if (hc->ledcount>>11) {
1628                                 led[0] = 1;
1629                                 led[1] = 1;
1630                         } else {
1631                                 led[0] = 0;
1632                                 led[1] = 0;
1633                         }
1634                         led[2] = 0;
1635                         led[3] = 0;
1636                 } else { /* with frame sync */
1637                         /* TODO make it work */
1638                         led[0] = 0;
1639                         led[1] = 0;
1640                         led[2] = 0;
1641                         led[3] = 1;
1642                 }
1643                 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1644                         /* leds are inverted */
1645                 if (leds != (int)hc->ledstate) {
1646                         HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1647                         hc->ledstate = leds;
1648                 }
1649                 break;
1650
1651         case 2: /* HFC-4S OEM */
1652                 /* red blinking = PH_DEACTIVATE NT Mode
1653                  * red steady   = PH_DEACTIVATE TE Mode
1654                  * green steady = PH_ACTIVATE
1655                  */
1656                 for (i = 0; i < 4; i++) {
1657                         state = 0;
1658                         active = -1;
1659                         dch = hc->chan[(i << 2) | 2].dch;
1660                         if (dch) {
1661                                 state = dch->state;
1662                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1663                                         active = 3;
1664                                 else
1665                                         active = 7;
1666                         }
1667                         if (state) {
1668                                 if (state == active) {
1669                                         led[i] = 1; /* led green */
1670                                 } else
1671                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1672                                                 /* TE mode: led red */
1673                                                 led[i] = 2;
1674                                         else
1675                                                 if (hc->ledcount>>11)
1676                                                         /* led red */
1677                                                         led[i] = 2;
1678                                                 else
1679                                                         /* led off */
1680                                                         led[i] = 0;
1681                         } else
1682                                 led[i] = 0; /* led off */
1683                 }
1684                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1685                         leds = 0;
1686                         for (i = 0; i < 4; i++) {
1687                                 if (led[i] == 1) {
1688                                         /*green*/
1689                                         leds |= (0x2 << (i * 2));
1690                                 } else if (led[i] == 2) {
1691                                         /*red*/
1692                                         leds |= (0x1 << (i * 2));
1693                                 }
1694                         }
1695                         if (leds != (int)hc->ledstate) {
1696                                 vpm_out(hc, 0, 0x1a8 + 3, leds);
1697                                 hc->ledstate = leds;
1698                         }
1699                 } else {
1700                         leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1701                             ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1702                             ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1703                             ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1704                         if (leds != (int)hc->ledstate) {
1705                                 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1706                                 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1707                                 hc->ledstate = leds;
1708                         }
1709                 }
1710                 break;
1711
1712         case 3: /* HFC 1S/2S Beronet */
1713                 /* red blinking = PH_DEACTIVATE NT Mode
1714                  * red steady   = PH_DEACTIVATE TE Mode
1715                  * green steady = PH_ACTIVATE
1716                  */
1717                 for (i = 0; i < 2; i++) {
1718                         state = 0;
1719                         active = -1;
1720                         dch = hc->chan[(i << 2) | 2].dch;
1721                         if (dch) {
1722                                 state = dch->state;
1723                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1724                                         active = 3;
1725                                 else
1726                                         active = 7;
1727                         }
1728                         if (state) {
1729                                 if (state == active) {
1730                                         led[i] = 1; /* led green */
1731                                 } else
1732                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1733                                                 /* TE mode: led red */
1734                                                 led[i] = 2;
1735                                         else
1736                                                 if (hc->ledcount >> 11)
1737                                                         /* led red */
1738                                                         led[i] = 2;
1739                                                 else
1740                                                         /* led off */
1741                                                         led[i] = 0;
1742                         } else
1743                                 led[i] = 0; /* led off */
1744                 }
1745
1746
1747                 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1748                         | ((led[1]&1)<<3);
1749                 if (leds != (int)hc->ledstate) {
1750                         HFC_outb_nodebug(hc, R_GPIO_EN1,
1751                             ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1752                         HFC_outb_nodebug(hc, R_GPIO_OUT1,
1753                             ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1754                         hc->ledstate = leds;
1755                 }
1756                 break;
1757         case 8: /* HFC 8S+ Beronet */
1758                 lled = 0;
1759
1760                 for (i = 0; i < 8; i++) {
1761                         state = 0;
1762                         active = -1;
1763                         dch = hc->chan[(i << 2) | 2].dch;
1764                         if (dch) {
1765                                 state = dch->state;
1766                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1767                                         active = 3;
1768                                 else
1769                                         active = 7;
1770                         }
1771                         if (state) {
1772                                 if (state == active) {
1773                                         lled |= 0 << i;
1774                                 } else
1775                                         if (hc->ledcount >> 11)
1776                                                 lled |= 0 << i;
1777                                         else
1778                                                 lled |= 1 << i;
1779                         } else
1780                                 lled |= 1 << i;
1781                 }
1782                 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1783                 if (leddw != hc->ledstate) {
1784                         /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1785                         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1786                         /* was _io before */
1787                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1788                         outw(0x4000, hc->pci_iobase + 4);
1789                         outl(leddw, hc->pci_iobase);
1790                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1791                         hc->ledstate = leddw;
1792                 }
1793                 break;
1794         }
1795 }
1796 /*
1797  * read dtmf coefficients
1798  */
1799
1800 static void
1801 hfcmulti_dtmf(struct hfc_multi *hc)
1802 {
1803         s32             *coeff;
1804         u_int           mantissa;
1805         int             co, ch;
1806         struct bchannel *bch = NULL;
1807         u8              exponent;
1808         int             dtmf = 0;
1809         int             addr;
1810         u16             w_float;
1811         struct sk_buff  *skb;
1812         struct mISDNhead *hh;
1813
1814         if (debug & DEBUG_HFCMULTI_DTMF)
1815                 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1816         for (ch = 0; ch <= 31; ch++) {
1817                 /* only process enabled B-channels */
1818                 bch = hc->chan[ch].bch;
1819                 if (!bch)
1820                         continue;
1821                 if (!hc->created[hc->chan[ch].port])
1822                         continue;
1823                 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1824                         continue;
1825                 if (debug & DEBUG_HFCMULTI_DTMF)
1826                         printk(KERN_DEBUG "%s: dtmf channel %d:",
1827                                 __func__, ch);
1828                 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1829                 dtmf = 1;
1830                 for (co = 0; co < 8; co++) {
1831                         /* read W(n-1) coefficient */
1832                         addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1833                         HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1834                         HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1835                         HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1836                                 | V_ADDR_INC);
1837                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1838                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1839                         if (debug & DEBUG_HFCMULTI_DTMF)
1840                                 printk(" %04x", w_float);
1841
1842                         /* decode float (see chip doc) */
1843                         mantissa = w_float & 0x0fff;
1844                         if (w_float & 0x8000)
1845                                 mantissa |= 0xfffff000;
1846                         exponent = (w_float>>12) & 0x7;
1847                         if (exponent) {
1848                                 mantissa ^= 0x1000;
1849                                 mantissa <<= (exponent-1);
1850                         }
1851
1852                         /* store coefficient */
1853                         coeff[co<<1] = mantissa;
1854
1855                         /* read W(n) coefficient */
1856                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1857                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1858                         if (debug & DEBUG_HFCMULTI_DTMF)
1859                                 printk(" %04x", w_float);
1860
1861                         /* decode float (see chip doc) */
1862                         mantissa = w_float & 0x0fff;
1863                         if (w_float & 0x8000)
1864                                 mantissa |= 0xfffff000;
1865                         exponent = (w_float>>12) & 0x7;
1866                         if (exponent) {
1867                                 mantissa ^= 0x1000;
1868                                 mantissa <<= (exponent-1);
1869                         }
1870
1871                         /* store coefficient */
1872                         coeff[(co<<1)|1] = mantissa;
1873                 }
1874                 if (debug & DEBUG_HFCMULTI_DTMF)
1875                         printk(" DTMF ready %08x %08x %08x %08x "
1876                             "%08x %08x %08x %08x\n",
1877                             coeff[0], coeff[1], coeff[2], coeff[3],
1878                             coeff[4], coeff[5], coeff[6], coeff[7]);
1879                 hc->chan[ch].coeff_count++;
1880                 if (hc->chan[ch].coeff_count == 8) {
1881                         hc->chan[ch].coeff_count = 0;
1882                         skb = mI_alloc_skb(512, GFP_ATOMIC);
1883                         if (!skb) {
1884                                 printk(KERN_DEBUG "%s: No memory for skb\n",
1885                                     __func__);
1886                                 continue;
1887                         }
1888                         hh = mISDN_HEAD_P(skb);
1889                         hh->prim = PH_CONTROL_IND;
1890                         hh->id = DTMF_HFC_COEF;
1891                         memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1892                         recv_Bchannel_skb(bch, skb);
1893                 }
1894         }
1895
1896         /* restart DTMF processing */
1897         hc->dtmf = dtmf;
1898         if (dtmf)
1899                 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1900 }
1901
1902
1903 /*
1904  * fill fifo as much as possible
1905  */
1906
1907 static void
1908 hfcmulti_tx(struct hfc_multi *hc, int ch)
1909 {
1910         int i, ii, temp, len = 0;
1911         int Zspace, z1, z2; /* must be int for calculation */
1912         int Fspace, f1, f2;
1913         u_char *d;
1914         int *txpending, slot_tx;
1915         struct  bchannel *bch;
1916         struct  dchannel *dch;
1917         struct  sk_buff **sp = NULL;
1918         int *idxp;
1919
1920         bch = hc->chan[ch].bch;
1921         dch = hc->chan[ch].dch;
1922         if ((!dch) && (!bch))
1923                 return;
1924
1925         txpending = &hc->chan[ch].txpending;
1926         slot_tx = hc->chan[ch].slot_tx;
1927         if (dch) {
1928                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1929                         return;
1930                 sp = &dch->tx_skb;
1931                 idxp = &dch->tx_idx;
1932         } else {
1933                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1934                         return;
1935                 sp = &bch->tx_skb;
1936                 idxp = &bch->tx_idx;
1937         }
1938         if (*sp)
1939                 len = (*sp)->len;
1940
1941         if ((!len) && *txpending != 1)
1942                 return; /* no data */
1943
1944         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1945             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1946             (hc->chan[ch].slot_rx < 0) &&
1947             (hc->chan[ch].slot_tx < 0))
1948                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1949         else
1950                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1951         HFC_wait_nodebug(hc);
1952
1953         if (*txpending == 2) {
1954                 /* reset fifo */
1955                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1956                 HFC_wait_nodebug(hc);
1957                 HFC_outb(hc, A_SUBCH_CFG, 0);
1958                 *txpending = 1;
1959         }
1960 next_frame:
1961         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1962                 f1 = HFC_inb_nodebug(hc, A_F1);
1963                 f2 = HFC_inb_nodebug(hc, A_F2);
1964                 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1965                         if (debug & DEBUG_HFCMULTI_FIFO)
1966                                 printk(KERN_DEBUG
1967                                     "%s(card %d): reread f2 because %d!=%d\n",
1968                                     __func__, hc->id + 1, temp, f2);
1969                         f2 = temp; /* repeat until F2 is equal */
1970                 }
1971                 Fspace = f2 - f1 - 1;
1972                 if (Fspace < 0)
1973                         Fspace += hc->Flen;
1974                 /*
1975                  * Old FIFO handling doesn't give us the current Z2 read
1976                  * pointer, so we cannot send the next frame before the fifo
1977                  * is empty. It makes no difference except for a slightly
1978                  * lower performance.
1979                  */
1980                 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1981                         if (f1 != f2)
1982                                 Fspace = 0;
1983                         else
1984                                 Fspace = 1;
1985                 }
1986                 /* one frame only for ST D-channels, to allow resending */
1987                 if (hc->ctype != HFC_TYPE_E1 && dch) {
1988                         if (f1 != f2)
1989                                 Fspace = 0;
1990                 }
1991                 /* F-counter full condition */
1992                 if (Fspace == 0)
1993                         return;
1994         }
1995         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1996         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1997         while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1998                 if (debug & DEBUG_HFCMULTI_FIFO)
1999                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2000                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2001                 z2 = temp; /* repeat unti Z2 is equal */
2002         }
2003         hc->chan[ch].Zfill = z1 - z2;
2004         if (hc->chan[ch].Zfill < 0)
2005                 hc->chan[ch].Zfill += hc->Zlen;
2006         Zspace = z2 - z1;
2007         if (Zspace <= 0)
2008                 Zspace += hc->Zlen;
2009         Zspace -= 4; /* keep not too full, so pointers will not overrun */
2010         /* fill transparent data only to maxinum transparent load (minus 4) */
2011         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2012                 Zspace = Zspace - hc->Zlen + hc->max_trans;
2013         if (Zspace <= 0) /* no space of 4 bytes */
2014                 return;
2015
2016         /* if no data */
2017         if (!len) {
2018                 if (z1 == z2) { /* empty */
2019                         /* if done with FIFO audio data during PCM connection */
2020                         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2021                             *txpending && slot_tx >= 0) {
2022                                 if (debug & DEBUG_HFCMULTI_MODE)
2023                                         printk(KERN_DEBUG
2024                                             "%s: reconnecting PCM due to no "
2025                                             "more FIFO data: channel %d "
2026                                             "slot_tx %d\n",
2027                                             __func__, ch, slot_tx);
2028                                 /* connect slot */
2029                                 if (hc->ctype == HFC_TYPE_XHFC)
2030                                         HFC_outb(hc, A_CON_HDLC, 0xc0
2031                                             | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2032                                                 /* Enable FIFO, no interrupt */
2033                                 else
2034                                         HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2035                                             V_HDLC_TRP | V_IFF);
2036                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2037                                 HFC_wait_nodebug(hc);
2038                                 if (hc->ctype == HFC_TYPE_XHFC)
2039                                         HFC_outb(hc, A_CON_HDLC, 0xc0
2040                                             | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2041                                                 /* Enable FIFO, no interrupt */
2042                                 else
2043                                         HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2044                                             V_HDLC_TRP | V_IFF);
2045                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2046                                 HFC_wait_nodebug(hc);
2047                         }
2048                         *txpending = 0;
2049                 }
2050                 return; /* no data */
2051         }
2052
2053         /* "fill fifo if empty" feature */
2054         if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2055                 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2056                 if (debug & DEBUG_HFCMULTI_FILL)
2057                         printk(KERN_DEBUG "%s: buffer empty, so we have "
2058                                 "underrun\n", __func__);
2059                 /* fill buffer, to prevent future underrun */
2060                 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2061                 Zspace -= (poll >> 1);
2062         }
2063
2064         /* if audio data and connected slot */
2065         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2066                 && slot_tx >= 0) {
2067                 if (debug & DEBUG_HFCMULTI_MODE)
2068                         printk(KERN_DEBUG "%s: disconnecting PCM due to "
2069                             "FIFO data: channel %d slot_tx %d\n",
2070                             __func__, ch, slot_tx);
2071                 /* disconnect slot */
2072                 if (hc->ctype == HFC_TYPE_XHFC)
2073                         HFC_outb(hc, A_CON_HDLC, 0x80
2074                             | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2075                                 /* Enable FIFO, no interrupt */
2076                 else
2077                         HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2078                             V_HDLC_TRP | V_IFF);
2079                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2080                 HFC_wait_nodebug(hc);
2081                 if (hc->ctype == HFC_TYPE_XHFC)
2082                         HFC_outb(hc, A_CON_HDLC, 0x80
2083                             | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2084                                 /* Enable FIFO, no interrupt */
2085                 else
2086                         HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2087                             V_HDLC_TRP | V_IFF);
2088                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2089                 HFC_wait_nodebug(hc);
2090         }
2091         *txpending = 1;
2092
2093         /* show activity */
2094         hc->activity[hc->chan[ch].port] = 1;
2095
2096         /* fill fifo to what we have left */
2097         ii = len;
2098         if (dch || test_bit(FLG_HDLC, &bch->Flags))
2099                 temp = 1;
2100         else
2101                 temp = 0;
2102         i = *idxp;
2103         d = (*sp)->data + i;
2104         if (ii - i > Zspace)
2105                 ii = Zspace + i;
2106         if (debug & DEBUG_HFCMULTI_FIFO)
2107                 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2108                     "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2109                         __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2110                         temp ? "HDLC" : "TRANS");
2111
2112         /* Have to prep the audio data */
2113         hc->write_fifo(hc, d, ii - i);
2114         hc->chan[ch].Zfill += ii - i;
2115         *idxp = ii;
2116
2117         /* if not all data has been written */
2118         if (ii != len) {
2119                 /* NOTE: fifo is started by the calling function */
2120                 return;
2121         }
2122
2123         /* if all data has been written, terminate frame */
2124         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2125                 /* increment f-counter */
2126                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2127                 HFC_wait_nodebug(hc);
2128         }
2129
2130         /* send confirm, since get_net_bframe will not do it with trans */
2131         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2132                 confirm_Bsend(bch);
2133
2134         /* check for next frame */
2135         dev_kfree_skb(*sp);
2136         if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2137                 len = (*sp)->len;
2138                 goto next_frame;
2139         }
2140         if (dch && get_next_dframe(dch)) {
2141                 len = (*sp)->len;
2142                 goto next_frame;
2143         }
2144
2145         /*
2146          * now we have no more data, so in case of transparent,
2147          * we set the last byte in fifo to 'silence' in case we will get
2148          * no more data at all. this prevents sending an undefined value.
2149          */
2150         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2151                 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2152 }
2153
2154
2155 /* NOTE: only called if E1 card is in active state */
2156 static void
2157 hfcmulti_rx(struct hfc_multi *hc, int ch)
2158 {
2159         int temp;
2160         int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2161         int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2162         int again = 0;
2163         struct  bchannel *bch;
2164         struct  dchannel *dch;
2165         struct sk_buff  *skb, **sp = NULL;
2166         int     maxlen;
2167
2168         bch = hc->chan[ch].bch;
2169         dch = hc->chan[ch].dch;
2170         if ((!dch) && (!bch))
2171                 return;
2172         if (dch) {
2173                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2174                         return;
2175                 sp = &dch->rx_skb;
2176                 maxlen = dch->maxlen;
2177         } else {
2178                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2179                         return;
2180                 sp = &bch->rx_skb;
2181                 maxlen = bch->maxlen;
2182         }
2183 next_frame:
2184         /* on first AND before getting next valid frame, R_FIFO must be written
2185            to. */
2186         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2187             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2188             (hc->chan[ch].slot_rx < 0) &&
2189             (hc->chan[ch].slot_tx < 0))
2190                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2191         else
2192                 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2193         HFC_wait_nodebug(hc);
2194
2195         /* ignore if rx is off BUT change fifo (above) to start pending TX */
2196         if (hc->chan[ch].rx_off)
2197                 return;
2198
2199         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2200                 f1 = HFC_inb_nodebug(hc, A_F1);
2201                 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2202                         if (debug & DEBUG_HFCMULTI_FIFO)
2203                                 printk(KERN_DEBUG
2204                                     "%s(card %d): reread f1 because %d!=%d\n",
2205                                     __func__, hc->id + 1, temp, f1);
2206                         f1 = temp; /* repeat until F1 is equal */
2207                 }
2208                 f2 = HFC_inb_nodebug(hc, A_F2);
2209         }
2210         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2211         while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2212                 if (debug & DEBUG_HFCMULTI_FIFO)
2213                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2214                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2215                 z1 = temp; /* repeat until Z1 is equal */
2216         }
2217         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2218         Zsize = z1 - z2;
2219         if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2220                 /* complete hdlc frame */
2221                 Zsize++;
2222         if (Zsize < 0)
2223                 Zsize += hc->Zlen;
2224         /* if buffer is empty */
2225         if (Zsize <= 0)
2226                 return;
2227
2228         if (*sp == NULL) {
2229                 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2230                 if (*sp == NULL) {
2231                         printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2232                             __func__);
2233                         return;
2234                 }
2235         }
2236         /* show activity */
2237         hc->activity[hc->chan[ch].port] = 1;
2238
2239         /* empty fifo with what we have */
2240         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2241                 if (debug & DEBUG_HFCMULTI_FIFO)
2242                         printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2243                             "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2244                             "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2245                             Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2246                             f1, f2, Zsize + (*sp)->len, again);
2247                 /* HDLC */
2248                 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2249                         if (debug & DEBUG_HFCMULTI_FIFO)
2250                                 printk(KERN_DEBUG
2251                                     "%s(card %d): hdlc-frame too large.\n",
2252                                     __func__, hc->id + 1);
2253                         skb_trim(*sp, 0);
2254                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2255                         HFC_wait_nodebug(hc);
2256                         return;
2257                 }
2258
2259                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2260
2261                 if (f1 != f2) {
2262                         /* increment Z2,F2-counter */
2263                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2264                         HFC_wait_nodebug(hc);
2265                         /* check size */
2266                         if ((*sp)->len < 4) {
2267                                 if (debug & DEBUG_HFCMULTI_FIFO)
2268                                         printk(KERN_DEBUG
2269                                             "%s(card %d): Frame below minimum "
2270                                             "size\n", __func__, hc->id + 1);
2271                                 skb_trim(*sp, 0);
2272                                 goto next_frame;
2273                         }
2274                         /* there is at least one complete frame, check crc */
2275                         if ((*sp)->data[(*sp)->len - 1]) {
2276                                 if (debug & DEBUG_HFCMULTI_CRC)
2277                                         printk(KERN_DEBUG
2278                                             "%s: CRC-error\n", __func__);
2279                                 skb_trim(*sp, 0);
2280                                 goto next_frame;
2281                         }
2282                         skb_trim(*sp, (*sp)->len - 3);
2283                         if ((*sp)->len < MISDN_COPY_SIZE) {
2284                                 skb = *sp;
2285                                 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2286                                 if (*sp) {
2287                                         memcpy(skb_put(*sp, skb->len),
2288                                             skb->data, skb->len);
2289                                         skb_trim(skb, 0);
2290                                 } else {
2291                                         printk(KERN_DEBUG "%s: No mem\n",
2292                                             __func__);
2293                                         *sp = skb;
2294                                         skb = NULL;
2295                                 }
2296                         } else {
2297                                 skb = NULL;
2298                         }
2299                         if (debug & DEBUG_HFCMULTI_FIFO) {
2300                                 printk(KERN_DEBUG "%s(card %d):",
2301                                         __func__, hc->id + 1);
2302                                 temp = 0;
2303                                 while (temp < (*sp)->len)
2304                                         printk(" %02x", (*sp)->data[temp++]);
2305                                 printk("\n");
2306                         }
2307                         if (dch)
2308                                 recv_Dchannel(dch);
2309                         else
2310                                 recv_Bchannel(bch, MISDN_ID_ANY);
2311                         *sp = skb;
2312                         again++;
2313                         goto next_frame;
2314                 }
2315                 /* there is an incomplete frame */
2316         } else {
2317                 /* transparent */
2318                 if (Zsize > skb_tailroom(*sp))
2319                         Zsize = skb_tailroom(*sp);
2320                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2321                 if (((*sp)->len) < MISDN_COPY_SIZE) {
2322                         skb = *sp;
2323                         *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2324                         if (*sp) {
2325                                 memcpy(skb_put(*sp, skb->len),
2326                                     skb->data, skb->len);
2327                                 skb_trim(skb, 0);
2328                         } else {
2329                                 printk(KERN_DEBUG "%s: No mem\n", __func__);
2330                                 *sp = skb;
2331                                 skb = NULL;
2332                         }
2333                 } else {
2334                         skb = NULL;
2335                 }
2336                 if (debug & DEBUG_HFCMULTI_FIFO)
2337                         printk(KERN_DEBUG
2338                             "%s(card %d): fifo(%d) reading %d bytes "
2339                             "(z1=%04x, z2=%04x) TRANS\n",
2340                                 __func__, hc->id + 1, ch, Zsize, z1, z2);
2341                 /* only bch is transparent */
2342                 recv_Bchannel(bch, hc->chan[ch].Zfill);
2343                 *sp = skb;
2344         }
2345 }
2346
2347
2348 /*
2349  * Interrupt handler
2350  */
2351 static void
2352 signal_state_up(struct dchannel *dch, int info, char *msg)
2353 {
2354         struct sk_buff  *skb;
2355         int             id, data = info;
2356
2357         if (debug & DEBUG_HFCMULTI_STATE)
2358                 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2359
2360         id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2361
2362         skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2363                 GFP_ATOMIC);
2364         if (!skb)
2365                 return;
2366         recv_Dchannel_skb(dch, skb);
2367 }
2368
2369 static inline void
2370 handle_timer_irq(struct hfc_multi *hc)
2371 {
2372         int             ch, temp;
2373         struct dchannel *dch;
2374         u_long          flags;
2375
2376         /* process queued resync jobs */
2377         if (hc->e1_resync) {
2378                 /* lock, so e1_resync gets not changed */
2379                 spin_lock_irqsave(&HFClock, flags);
2380                 if (hc->e1_resync & 1) {
2381                         if (debug & DEBUG_HFCMULTI_PLXSD)
2382                                 printk(KERN_DEBUG "Enable SYNC_I\n");
2383                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2384                         /* disable JATT, if RX_SYNC is set */
2385                         if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2386                                 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2387                 }
2388                 if (hc->e1_resync & 2) {
2389                         if (debug & DEBUG_HFCMULTI_PLXSD)
2390                                 printk(KERN_DEBUG "Enable jatt PLL\n");
2391                         HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2392                 }
2393                 if (hc->e1_resync & 4) {
2394                         if (debug & DEBUG_HFCMULTI_PLXSD)
2395                                 printk(KERN_DEBUG
2396                                     "Enable QUARTZ for HFC-E1\n");
2397                         /* set jatt to quartz */
2398                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2399                                 | V_JATT_OFF);
2400                         /* switch to JATT, in case it is not already */
2401                         HFC_outb(hc, R_SYNC_OUT, 0);
2402                 }
2403                 hc->e1_resync = 0;
2404                 spin_unlock_irqrestore(&HFClock, flags);
2405         }
2406
2407         if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2408                 for (ch = 0; ch <= 31; ch++) {
2409                         if (hc->created[hc->chan[ch].port]) {
2410                                 hfcmulti_tx(hc, ch);
2411                                 /* fifo is started when switching to rx-fifo */
2412                                 hfcmulti_rx(hc, ch);
2413                                 if (hc->chan[ch].dch &&
2414                                     hc->chan[ch].nt_timer > -1) {
2415                                         dch = hc->chan[ch].dch;
2416                                         if (!(--hc->chan[ch].nt_timer)) {
2417                                                 schedule_event(dch,
2418                                                     FLG_PHCHANGE);
2419                                                 if (debug &
2420                                                     DEBUG_HFCMULTI_STATE)
2421                                                         printk(KERN_DEBUG
2422                                                             "%s: nt_timer at "
2423                                                             "state %x\n",
2424                                                             __func__,
2425                                                             dch->state);
2426                                         }
2427                                 }
2428                         }
2429                 }
2430         if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2431                 dch = hc->chan[hc->dslot].dch;
2432                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2433                         /* LOS */
2434                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2435                         if (!temp && hc->chan[hc->dslot].los)
2436                                 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2437                                     "LOS detected");
2438                         if (temp && !hc->chan[hc->dslot].los)
2439                                 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2440                                     "LOS gone");
2441                         hc->chan[hc->dslot].los = temp;
2442                 }
2443                 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2444                         /* AIS */
2445                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2446                         if (!temp && hc->chan[hc->dslot].ais)
2447                                 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2448                                     "AIS detected");
2449                         if (temp && !hc->chan[hc->dslot].ais)
2450                                 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2451                                     "AIS gone");
2452                         hc->chan[hc->dslot].ais = temp;
2453                 }
2454                 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2455                         /* SLIP */
2456                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2457                         if (!temp && hc->chan[hc->dslot].slip_rx)
2458                                 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2459                                     " bit SLIP detected RX");
2460                         hc->chan[hc->dslot].slip_rx = temp;
2461                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2462                         if (!temp && hc->chan[hc->dslot].slip_tx)
2463                                 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2464                                     " bit SLIP detected TX");
2465                         hc->chan[hc->dslot].slip_tx = temp;
2466                 }
2467                 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2468                         /* RDI */
2469                         temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2470                         if (!temp && hc->chan[hc->dslot].rdi)
2471                                 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2472                                     "RDI detected");
2473                         if (temp && !hc->chan[hc->dslot].rdi)
2474                                 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2475                                     "RDI gone");
2476                         hc->chan[hc->dslot].rdi = temp;
2477                 }
2478                 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2479                 switch (hc->chan[hc->dslot].sync) {
2480                 case 0:
2481                         if ((temp & 0x60) == 0x60) {
2482                                 if (debug & DEBUG_HFCMULTI_SYNC)
2483                                         printk(KERN_DEBUG
2484                                             "%s: (id=%d) E1 now "
2485                                             "in clock sync\n",
2486                                             __func__, hc->id);
2487                                 HFC_outb(hc, R_RX_OFF,
2488                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2489                                 HFC_outb(hc, R_TX_OFF,
2490                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2491                                 hc->chan[hc->dslot].sync = 1;
2492                                 goto check_framesync;
2493                         }
2494                         break;
2495                 case 1:
2496                         if ((temp & 0x60) != 0x60) {
2497                                 if (debug & DEBUG_HFCMULTI_SYNC)
2498                                         printk(KERN_DEBUG
2499                                             "%s: (id=%d) E1 "
2500                                             "lost clock sync\n",
2501                                             __func__, hc->id);
2502                                 hc->chan[hc->dslot].sync = 0;
2503                                 break;
2504                         }
2505 check_framesync:
2506                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2507                         if (temp == 0x27) {
2508                                 if (debug & DEBUG_HFCMULTI_SYNC)
2509                                         printk(KERN_DEBUG
2510                                             "%s: (id=%d) E1 "
2511                                             "now in frame sync\n",
2512                                             __func__, hc->id);
2513                                 hc->chan[hc->dslot].sync = 2;
2514                         }
2515                         break;
2516                 case 2:
2517                         if ((temp & 0x60) != 0x60) {
2518                                 if (debug & DEBUG_HFCMULTI_SYNC)
2519                                         printk(KERN_DEBUG
2520                                             "%s: (id=%d) E1 lost "
2521                                             "clock & frame sync\n",
2522                                             __func__, hc->id);
2523                                 hc->chan[hc->dslot].sync = 0;
2524                                 break;
2525                         }
2526                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2527                         if (temp != 0x27) {
2528                                 if (debug & DEBUG_HFCMULTI_SYNC)
2529                                         printk(KERN_DEBUG
2530                                             "%s: (id=%d) E1 "
2531                                             "lost frame sync\n",
2532                                             __func__, hc->id);
2533                                 hc->chan[hc->dslot].sync = 1;
2534                         }
2535                         break;
2536                 }
2537         }
2538
2539         if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2540                 hfcmulti_watchdog(hc);
2541
2542         if (hc->leds)
2543                 hfcmulti_leds(hc);
2544 }
2545
2546 static void
2547 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2548 {
2549         struct dchannel *dch;
2550         int             ch;
2551         int             active;
2552         u_char          st_status, temp;
2553
2554         /* state machine */
2555         for (ch = 0; ch <= 31; ch++) {
2556                 if (hc->chan[ch].dch) {
2557                         dch = hc->chan[ch].dch;
2558                         if (r_irq_statech & 1) {
2559                                 HFC_outb_nodebug(hc, R_ST_SEL,
2560                                         hc->chan[ch].port);
2561                                 /* undocumented: delay after R_ST_SEL */
2562                                 udelay(1);
2563                                 /* undocumented: status changes during read */
2564                                 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2565                                 while (st_status != (temp =
2566                                         HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2567                                         if (debug & DEBUG_HFCMULTI_STATE)
2568                                                 printk(KERN_DEBUG "%s: reread "
2569                                                     "STATE because %d!=%d\n",
2570                                                     __func__, temp,
2571                                                     st_status);
2572                                         st_status = temp; /* repeat */
2573                                 }
2574
2575                                 /* Speech Design TE-sync indication */
2576                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2577                                         dch->dev.D.protocol == ISDN_P_TE_S0) {
2578                                         if (st_status & V_FR_SYNC_ST)
2579                                                 hc->syncronized |=
2580                                                     (1 << hc->chan[ch].port);
2581                                         else
2582                                                 hc->syncronized &=
2583                                                    ~(1 << hc->chan[ch].port);
2584                                 }
2585                                 dch->state = st_status & 0x0f;
2586                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2587                                         active = 3;
2588                                 else
2589                                         active = 7;
2590                                 if (dch->state == active) {
2591                                         HFC_outb_nodebug(hc, R_FIFO,
2592                                                 (ch << 1) | 1);
2593                                         HFC_wait_nodebug(hc);
2594                                         HFC_outb_nodebug(hc,
2595                                                 R_INC_RES_FIFO, V_RES_F);
2596                                         HFC_wait_nodebug(hc);
2597                                         dch->tx_idx = 0;
2598                                 }
2599                                 schedule_event(dch, FLG_PHCHANGE);
2600                                 if (debug & DEBUG_HFCMULTI_STATE)
2601                                         printk(KERN_DEBUG
2602                                             "%s: S/T newstate %x port %d\n",
2603                                             __func__, dch->state,
2604                                             hc->chan[ch].port);
2605                         }
2606                         r_irq_statech >>= 1;
2607                 }
2608         }
2609         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2610                 plxsd_checksync(hc, 0);
2611 }
2612
2613 static void
2614 fifo_irq(struct hfc_multi *hc, int block)
2615 {
2616         int     ch, j;
2617         struct dchannel *dch;
2618         struct bchannel *bch;
2619         u_char r_irq_fifo_bl;
2620
2621         r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2622         j = 0;
2623         while (j < 8) {
2624                 ch = (block << 2) + (j >> 1);
2625                 dch = hc->chan[ch].dch;
2626                 bch = hc->chan[ch].bch;
2627                 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2628                         j += 2;
2629                         continue;
2630                 }
2631                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2632                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2633                         hfcmulti_tx(hc, ch);
2634                         /* start fifo */
2635                         HFC_outb_nodebug(hc, R_FIFO, 0);
2636                         HFC_wait_nodebug(hc);
2637                 }
2638                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2639                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2640                         hfcmulti_tx(hc, ch);
2641                         /* start fifo */
2642                         HFC_outb_nodebug(hc, R_FIFO, 0);
2643                         HFC_wait_nodebug(hc);
2644                 }
2645                 j++;
2646                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2647                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2648                         hfcmulti_rx(hc, ch);
2649                 }
2650                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2651                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2652                         hfcmulti_rx(hc, ch);
2653                 }
2654                 j++;
2655         }
2656 }
2657
2658 #ifdef IRQ_DEBUG
2659 int irqsem;
2660 #endif
2661 static irqreturn_t
2662 hfcmulti_interrupt(int intno, void *dev_id)
2663 {
2664 #ifdef IRQCOUNT_DEBUG
2665         static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2666             iq5 = 0, iq6 = 0, iqcnt = 0;
2667 #endif
2668         struct hfc_multi        *hc = dev_id;
2669         struct dchannel         *dch;
2670         u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
2671         int                     i;
2672         void __iomem            *plx_acc;
2673         u_short                 wval;
2674         u_char                  e1_syncsta, temp;
2675         u_long                  flags;
2676
2677         if (!hc) {
2678                 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2679                 return IRQ_NONE;
2680         }
2681
2682         spin_lock(&hc->lock);
2683
2684 #ifdef IRQ_DEBUG
2685         if (irqsem)
2686                 printk(KERN_ERR "irq for card %d during irq from "
2687                 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2688         irqsem = hc->id + 1;
2689 #endif
2690 #ifdef CONFIG_MISDN_HFCMULTI_8xx
2691         if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2692                 goto irq_notforus;
2693 #endif
2694         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2695                 spin_lock_irqsave(&plx_lock, flags);
2696                 plx_acc = hc->plx_membase + PLX_INTCSR;
2697                 wval = readw(plx_acc);
2698                 spin_unlock_irqrestore(&plx_lock, flags);
2699                 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2700                         goto irq_notforus;
2701         }
2702
2703         status = HFC_inb_nodebug(hc, R_STATUS);
2704         r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2705 #ifdef IRQCOUNT_DEBUG
2706         if (r_irq_statech)
2707                 iq1++;
2708         if (status & V_DTMF_STA)
2709                 iq2++;
2710         if (status & V_LOST_STA)
2711                 iq3++;
2712         if (status & V_EXT_IRQSTA)
2713                 iq4++;
2714         if (status & V_MISC_IRQSTA)
2715                 iq5++;
2716         if (status & V_FR_IRQSTA)
2717                 iq6++;
2718         if (iqcnt++ > 5000) {
2719                 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2720                     iq1, iq2, iq3, iq4, iq5, iq6);
2721                 iqcnt = 0;
2722         }
2723 #endif
2724
2725         if (!r_irq_statech &&
2726             !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2727             V_MISC_IRQSTA | V_FR_IRQSTA))) {
2728                 /* irq is not for us */
2729                 goto irq_notforus;
2730         }
2731         hc->irqcnt++;
2732         if (r_irq_statech) {
2733                 if (hc->ctype != HFC_TYPE_E1)
2734                         ph_state_irq(hc, r_irq_statech);
2735         }
2736         if (status & V_EXT_IRQSTA)
2737                 ; /* external IRQ */
2738         if (status & V_LOST_STA) {
2739                 /* LOST IRQ */
2740                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2741         }
2742         if (status & V_MISC_IRQSTA) {
2743                 /* misc IRQ */
2744                 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2745                 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2746                 if (r_irq_misc & V_STA_IRQ) {
2747                         if (hc->ctype == HFC_TYPE_E1) {
2748                                 /* state machine */
2749                                 dch = hc->chan[hc->dslot].dch;
2750                                 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2751                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2752                                  && hc->e1_getclock) {
2753                                         if (e1_syncsta & V_FR_SYNC_E1)
2754                                                 hc->syncronized = 1;
2755                                         else
2756                                                 hc->syncronized = 0;
2757                                 }
2758                                 /* undocumented: status changes during read */
2759                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2760                                 while (dch->state != (temp =
2761                                         HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2762                                         if (debug & DEBUG_HFCMULTI_STATE)
2763                                                 printk(KERN_DEBUG "%s: reread "
2764                                                     "STATE because %d!=%d\n",
2765                                                     __func__, temp,
2766                                                     dch->state);
2767                                         dch->state = temp; /* repeat */
2768                                 }
2769                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2770                                         & 0x7;
2771                                 schedule_event(dch, FLG_PHCHANGE);
2772                                 if (debug & DEBUG_HFCMULTI_STATE)
2773                                         printk(KERN_DEBUG
2774                                             "%s: E1 (id=%d) newstate %x\n",
2775                                             __func__, hc->id, dch->state);
2776                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2777                                         plxsd_checksync(hc, 0);
2778                         }
2779                 }
2780                 if (r_irq_misc & V_TI_IRQ) {
2781                         if (hc->iclock_on)
2782                                 mISDN_clock_update(hc->iclock, poll, NULL);
2783                         handle_timer_irq(hc);
2784                 }
2785
2786                 if (r_irq_misc & V_DTMF_IRQ)
2787                         hfcmulti_dtmf(hc);
2788
2789                 if (r_irq_misc & V_IRQ_PROC) {
2790                         static int irq_proc_cnt;
2791                         if (!irq_proc_cnt++)
2792                                 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2793                                     " this should not happen\n", __func__);
2794                 }
2795
2796         }
2797         if (status & V_FR_IRQSTA) {
2798                 /* FIFO IRQ */
2799                 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2800                 for (i = 0; i < 8; i++) {
2801                         if (r_irq_oview & (1 << i))
2802                                 fifo_irq(hc, i);
2803                 }
2804         }
2805
2806 #ifdef IRQ_DEBUG
2807         irqsem = 0;
2808 #endif
2809         spin_unlock(&hc->lock);
2810         return IRQ_HANDLED;
2811
2812 irq_notforus:
2813 #ifdef IRQ_DEBUG
2814         irqsem = 0;
2815 #endif
2816         spin_unlock(&hc->lock);
2817         return IRQ_NONE;
2818 }
2819
2820
2821 /*
2822  * timer callback for D-chan busy resolution. Currently no function
2823  */
2824
2825 static void
2826 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2827 {
2828 }
2829
2830
2831 /*
2832  * activate/deactivate hardware for selected channels and mode
2833  *
2834  * configure B-channel with the given protocol
2835  * ch eqals to the HFC-channel (0-31)
2836  * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2837  * for S/T, 1-31 for E1)
2838  * the hdlc interrupts will be set/unset
2839  */
2840 static int
2841 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2842     int bank_tx, int slot_rx, int bank_rx)
2843 {
2844         int flow_tx = 0, flow_rx = 0, routing = 0;
2845         int oslot_tx, oslot_rx;
2846         int conf;
2847
2848         if (ch < 0 || ch > 31)
2849                 return EINVAL;
2850         oslot_tx = hc->chan[ch].slot_tx;
2851         oslot_rx = hc->chan[ch].slot_rx;
2852         conf = hc->chan[ch].conf;
2853
2854         if (debug & DEBUG_HFCMULTI_MODE)
2855                 printk(KERN_DEBUG
2856                     "%s: card %d channel %d protocol %x slot old=%d new=%d "
2857                     "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2858                     __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2859                     bank_tx, oslot_rx, slot_rx, bank_rx);
2860
2861         if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2862                 /* remove from slot */
2863                 if (debug & DEBUG_HFCMULTI_MODE)
2864                         printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2865                             __func__, oslot_tx);
2866                 if (hc->slot_owner[oslot_tx<<1] == ch) {
2867                         HFC_outb(hc, R_SLOT, oslot_tx << 1);
2868                         HFC_outb(hc, A_SL_CFG, 0);
2869                         if (hc->ctype != HFC_TYPE_XHFC)
2870                                 HFC_outb(hc, A_CONF, 0);
2871                         hc->slot_owner[oslot_tx<<1] = -1;
2872                 } else {
2873                         if (debug & DEBUG_HFCMULTI_MODE)
2874                                 printk(KERN_DEBUG
2875                                     "%s: we are not owner of this tx slot "
2876                                     "anymore, channel %d is.\n",
2877                                     __func__, hc->slot_owner[oslot_tx<<1]);
2878                 }
2879         }
2880
2881         if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2882                 /* remove from slot */
2883                 if (debug & DEBUG_HFCMULTI_MODE)
2884                         printk(KERN_DEBUG
2885                             "%s: remove from slot %d (RX)\n",
2886                             __func__, oslot_rx);
2887                 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2888                         HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2889                         HFC_outb(hc, A_SL_CFG, 0);
2890                         hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2891                 } else {
2892                         if (debug & DEBUG_HFCMULTI_MODE)
2893                                 printk(KERN_DEBUG
2894                                     "%s: we are not owner of this rx slot "
2895                                     "anymore, channel %d is.\n",
2896                                     __func__,
2897                                     hc->slot_owner[(oslot_rx << 1) | 1]);
2898                 }
2899         }
2900
2901         if (slot_tx < 0) {
2902                 flow_tx = 0x80; /* FIFO->ST */
2903                 /* disable pcm slot */
2904                 hc->chan[ch].slot_tx = -1;
2905                 hc->chan[ch].bank_tx = 0;
2906         } else {
2907                 /* set pcm slot */
2908                 if (hc->chan[ch].txpending)
2909                         flow_tx = 0x80; /* FIFO->ST */
2910                 else
2911                         flow_tx = 0xc0; /* PCM->ST */
2912                 /* put on slot */
2913                 routing = bank_tx ? 0xc0 : 0x80;
2914                 if (conf >= 0 || bank_tx > 1)
2915                         routing = 0x40; /* loop */
2916                 if (debug & DEBUG_HFCMULTI_MODE)
2917                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2918                             " %d flow %02x routing %02x conf %d (TX)\n",
2919                             __func__, ch, slot_tx, bank_tx,
2920                             flow_tx, routing, conf);
2921                 HFC_outb(hc, R_SLOT, slot_tx << 1);
2922                 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2923                 if (hc->ctype != HFC_TYPE_XHFC)
2924                         HFC_outb(hc, A_CONF,
2925                                 (conf < 0) ? 0 : (conf | V_CONF_SL));
2926                 hc->slot_owner[slot_tx << 1] = ch;
2927                 hc->chan[ch].slot_tx = slot_tx;
2928                 hc->chan[ch].bank_tx = bank_tx;
2929         }
2930         if (slot_rx < 0) {
2931                 /* disable pcm slot */
2932                 flow_rx = 0x80; /* ST->FIFO */
2933                 hc->chan[ch].slot_rx = -1;
2934                 hc->chan[ch].bank_rx = 0;
2935         } else {
2936                 /* set pcm slot */
2937                 if (hc->chan[ch].txpending)
2938                         flow_rx = 0x80; /* ST->FIFO */
2939                 else
2940                         flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2941                 /* put on slot */
2942                 routing = bank_rx ? 0x80 : 0xc0; /* reversed */
2943                 if (conf >= 0 || bank_rx > 1)
2944                         routing = 0x40; /* loop */
2945                 if (debug & DEBUG_HFCMULTI_MODE)
2946                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2947                             " %d flow %02x routing %02x conf %d (RX)\n",
2948                             __func__, ch, slot_rx, bank_rx,
2949                             flow_rx, routing, conf);
2950                 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2951                 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2952                 hc->slot_owner[(slot_rx<<1)|1] = ch;
2953                 hc->chan[ch].slot_rx = slot_rx;
2954                 hc->chan[ch].bank_rx = bank_rx;
2955         }
2956
2957         switch (protocol) {
2958         case (ISDN_P_NONE):
2959                 /* disable TX fifo */
2960                 HFC_outb(hc, R_FIFO, ch << 1);
2961                 HFC_wait(hc);
2962                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2963                 HFC_outb(hc, A_SUBCH_CFG, 0);
2964                 HFC_outb(hc, A_IRQ_MSK, 0);
2965                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2966                 HFC_wait(hc);
2967                 /* disable RX fifo */
2968                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2969                 HFC_wait(hc);
2970                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2971                 HFC_outb(hc, A_SUBCH_CFG, 0);
2972                 HFC_outb(hc, A_IRQ_MSK, 0);
2973                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2974                 HFC_wait(hc);
2975                 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
2976                         hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2977                             ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
2978                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2979                         /* undocumented: delay after R_ST_SEL */
2980                         udelay(1);
2981                         HFC_outb(hc, A_ST_CTRL0,
2982                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2983                 }
2984                 if (hc->chan[ch].bch) {
2985                         test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2986                         test_and_clear_bit(FLG_TRANSPARENT,
2987                             &hc->chan[ch].bch->Flags);
2988                 }
2989                 break;
2990         case (ISDN_P_B_RAW): /* B-channel */
2991
2992                 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2993                     (hc->chan[ch].slot_rx < 0) &&
2994                     (hc->chan[ch].slot_tx < 0)) {
2995
2996                         printk(KERN_DEBUG
2997                             "Setting B-channel %d to echo cancelable "
2998                             "state on PCM slot %d\n", ch,
2999                             ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
3000                         printk(KERN_DEBUG
3001                             "Enabling pass through for channel\n");
3002                         vpm_out(hc, ch, ((ch / 4) * 8) +
3003                             ((ch % 4) * 4) + 1, 0x01);
3004                         /* rx path */
3005                         /* S/T -> PCM */
3006                         HFC_outb(hc, R_FIFO, (ch << 1));
3007                         HFC_wait(hc);
3008                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3009                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3010                             ((ch % 4) * 4) + 1) << 1);
3011                         HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
3012
3013                         /* PCM -> FIFO */
3014                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3015                         HFC_wait(hc);
3016                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3017                         HFC_outb(hc, A_SUBCH_CFG, 0);
3018                         HFC_outb(hc, A_IRQ_MSK, 0);
3019                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3020                         HFC_wait(hc);
3021                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3022                             ((ch % 4) * 4) + 1) << 1) | 1);
3023                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3024
3025                         /* tx path */
3026                         /* PCM -> S/T */
3027                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3028                         HFC_wait(hc);
3029                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3030                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3031                             ((ch % 4) * 4)) << 1) | 1);
3032                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3033
3034                         /* FIFO -> PCM */
3035                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3036                         HFC_wait(hc);
3037                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3038                         HFC_outb(hc, A_SUBCH_CFG, 0);
3039                         HFC_outb(hc, A_IRQ_MSK, 0);
3040                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3041                         HFC_wait(hc);
3042                         /* tx silence */
3043                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3044                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3045                             ((ch % 4) * 4)) << 1);
3046                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3047                 } else {
3048                         /* enable TX fifo */
3049                         HFC_outb(hc, R_FIFO, ch << 1);
3050                         HFC_wait(hc);
3051                         if (hc->ctype == HFC_TYPE_XHFC)
3052                                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
3053                                         V_HDLC_TRP | V_IFF);
3054                                         /* Enable FIFO, no interrupt */
3055                         else
3056                                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3057                                         V_HDLC_TRP | V_IFF);
3058                         HFC_outb(hc, A_SUBCH_CFG, 0);
3059                         HFC_outb(hc, A_IRQ_MSK, 0);
3060                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3061                         HFC_wait(hc);
3062                         /* tx silence */
3063                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3064                         /* enable RX fifo */
3065                         HFC_outb(hc, R_FIFO, (ch<<1)|1);
3066                         HFC_wait(hc);
3067                         if (hc->ctype == HFC_TYPE_XHFC)
3068                                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
3069                                         V_HDLC_TRP);
3070                                         /* Enable FIFO, no interrupt*/
3071                         else
3072                                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
3073                                                 V_HDLC_TRP);
3074                         HFC_outb(hc, A_SUBCH_CFG, 0);
3075                         HFC_outb(hc, A_IRQ_MSK, 0);
3076                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3077                         HFC_wait(hc);
3078                 }
3079                 if (hc->ctype != HFC_TYPE_E1) {
3080                         hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3081                             ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3082                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3083                         /* undocumented: delay after R_ST_SEL */
3084                         udelay(1);
3085                         HFC_outb(hc, A_ST_CTRL0,
3086                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3087                 }
3088                 if (hc->chan[ch].bch)
3089                         test_and_set_bit(FLG_TRANSPARENT,
3090                             &hc->chan[ch].bch->Flags);
3091                 break;
3092         case (ISDN_P_B_HDLC): /* B-channel */
3093         case (ISDN_P_TE_S0): /* D-channel */
3094         case (ISDN_P_NT_S0):
3095         case (ISDN_P_TE_E1):
3096         case (ISDN_P_NT_E1):
3097                 /* enable TX fifo */
3098                 HFC_outb(hc, R_FIFO, ch<<1);
3099                 HFC_wait(hc);
3100                 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3101                         /* E1 or B-channel */
3102                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3103                         HFC_outb(hc, A_SUBCH_CFG, 0);
3104                 } else {
3105                         /* D-Channel without HDLC fill flags */
3106                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3107                         HFC_outb(hc, A_SUBCH_CFG, 2);
3108                 }
3109                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3110                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3111                 HFC_wait(hc);
3112                 /* enable RX fifo */
3113                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3114                 HFC_wait(hc);
3115                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3116                 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3117                         HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3118                 else
3119                         HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3120                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3121                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3122                 HFC_wait(hc);
3123                 if (hc->chan[ch].bch) {
3124                         test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3125                         if (hc->ctype != HFC_TYPE_E1) {
3126                                 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3127                                   ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3128                                 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3129                                 /* undocumented: delay after R_ST_SEL */
3130                                 udelay(1);
3131                                 HFC_outb(hc, A_ST_CTRL0,
3132                                   hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3133                         }
3134                 }
3135                 break;
3136         default:
3137                 printk(KERN_DEBUG "%s: protocol not known %x\n",
3138                     __func__, protocol);
3139                 hc->chan[ch].protocol = ISDN_P_NONE;
3140                 return -ENOPROTOOPT;
3141         }
3142         hc->chan[ch].protocol = protocol;
3143         return 0;
3144 }
3145
3146
3147 /*
3148  * connect/disconnect PCM
3149  */
3150
3151 static void
3152 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3153     int slot_rx, int bank_rx)
3154 {
3155         if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3156                 /* disable PCM */
3157                 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3158                 return;
3159         }
3160
3161         /* enable pcm */
3162         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3163                 slot_rx, bank_rx);
3164 }
3165
3166 /*
3167  * set/disable conference
3168  */
3169
3170 static void
3171 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3172 {
3173         if (num >= 0 && num <= 7)
3174                 hc->chan[ch].conf = num;
3175         else
3176                 hc->chan[ch].conf = -1;
3177         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3178             hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3179             hc->chan[ch].bank_rx);
3180 }
3181
3182
3183 /*
3184  * set/disable sample loop
3185  */
3186
3187 /* NOTE: this function is experimental and therefore disabled */
3188
3189 /*
3190  * Layer 1 callback function
3191  */
3192 static int
3193 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3194 {
3195         struct hfc_multi        *hc = dch->hw;
3196         u_long  flags;
3197
3198         switch (cmd) {
3199         case INFO3_P8:
3200         case INFO3_P10:
3201                 break;
3202         case HW_RESET_REQ:
3203                 /* start activation */
3204                 spin_lock_irqsave(&hc->lock, flags);
3205                 if (hc->ctype == HFC_TYPE_E1) {
3206                         if (debug & DEBUG_HFCMULTI_MSG)
3207                                 printk(KERN_DEBUG
3208                                     "%s: HW_RESET_REQ no BRI\n",
3209                                     __func__);
3210                 } else {
3211                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3212                         /* undocumented: delay after R_ST_SEL */
3213                         udelay(1);
3214                         HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3215                         udelay(6); /* wait at least 5,21us */
3216                         HFC_outb(hc, A_ST_WR_STATE, 3);
3217                         HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3218                                 /* activate */
3219                 }
3220                 spin_unlock_irqrestore(&hc->lock, flags);
3221                 l1_event(dch->l1, HW_POWERUP_IND);
3222                 break;
3223         case HW_DEACT_REQ:
3224                 /* start deactivation */
3225                 spin_lock_irqsave(&hc->lock, flags);
3226                 if (hc->ctype == HFC_TYPE_E1) {
3227                         if (debug & DEBUG_HFCMULTI_MSG)
3228                                 printk(KERN_DEBUG
3229                                     "%s: HW_DEACT_REQ no BRI\n",
3230                                     __func__);
3231                 } else {
3232                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3233                         /* undocumented: delay after R_ST_SEL */
3234                         udelay(1);
3235                         HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3236                                 /* deactivate */
3237                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3238                                 hc->syncronized &=
3239                                    ~(1 << hc->chan[dch->slot].port);
3240                                 plxsd_checksync(hc, 0);
3241                         }
3242                 }
3243                 skb_queue_purge(&dch->squeue);
3244                 if (dch->tx_skb) {
3245                         dev_kfree_skb(dch->tx_skb);
3246                         dch->tx_skb = NULL;
3247                 }
3248                 dch->tx_idx = 0;
3249                 if (dch->rx_skb) {
3250                         dev_kfree_skb(dch->rx_skb);
3251                         dch->rx_skb = NULL;
3252                 }
3253                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3254                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3255                         del_timer(&dch->timer);
3256                 spin_unlock_irqrestore(&hc->lock, flags);
3257                 break;
3258         case HW_POWERUP_REQ:
3259                 spin_lock_irqsave(&hc->lock, flags);
3260                 if (hc->ctype == HFC_TYPE_E1) {
3261                         if (debug & DEBUG_HFCMULTI_MSG)
3262                                 printk(KERN_DEBUG
3263                                     "%s: HW_POWERUP_REQ no BRI\n",
3264                                     __func__);
3265                 } else {
3266                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3267                         /* undocumented: delay after R_ST_SEL */
3268                         udelay(1);
3269                         HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3270                         udelay(6); /* wait at least 5,21us */
3271                         HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3272                 }
3273                 spin_unlock_irqrestore(&hc->lock, flags);
3274                 break;
3275         case PH_ACTIVATE_IND:
3276                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3277                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3278                         GFP_ATOMIC);
3279                 break;
3280         case PH_DEACTIVATE_IND:
3281                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3282                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3283                         GFP_ATOMIC);
3284                 break;
3285         default:
3286                 if (dch->debug & DEBUG_HW)
3287                         printk(KERN_DEBUG "%s: unknown command %x\n",
3288                             __func__, cmd);
3289                 return -1;
3290         }
3291         return 0;
3292 }
3293
3294 /*
3295  * Layer2 -> Layer 1 Transfer
3296  */
3297
3298 static int
3299 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3300 {
3301         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
3302         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
3303         struct hfc_multi        *hc = dch->hw;
3304         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3305         int                     ret = -EINVAL;
3306         unsigned int            id;
3307         u_long                  flags;
3308
3309         switch (hh->prim) {
3310         case PH_DATA_REQ:
3311                 if (skb->len < 1)
3312                         break;
3313                 spin_lock_irqsave(&hc->lock, flags);
3314                 ret = dchannel_senddata(dch, skb);
3315                 if (ret > 0) { /* direct TX */
3316                         id = hh->id; /* skb can be freed */
3317                         hfcmulti_tx(hc, dch->slot);
3318                         ret = 0;
3319                         /* start fifo */
3320                         HFC_outb(hc, R_FIFO, 0);
3321                         HFC_wait(hc);
3322                         spin_unlock_irqrestore(&hc->lock, flags);
3323                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3324                 } else
3325                         spin_unlock_irqrestore(&hc->lock, flags);
3326                 return ret;
3327         case PH_ACTIVATE_REQ:
3328                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3329                         spin_lock_irqsave(&hc->lock, flags);
3330                         ret = 0;
3331                         if (debug & DEBUG_HFCMULTI_MSG)
3332                                 printk(KERN_DEBUG
3333                                     "%s: PH_ACTIVATE port %d (0..%d)\n",
3334                                     __func__, hc->chan[dch->slot].port,
3335                                     hc->ports-1);
3336                         /* start activation */
3337                         if (hc->ctype == HFC_TYPE_E1) {
3338                                 ph_state_change(dch);
3339                                 if (debug & DEBUG_HFCMULTI_STATE)
3340                                         printk(KERN_DEBUG
3341                                             "%s: E1 report state %x \n",
3342                                             __func__, dch->state);
3343                         } else {
3344                                 HFC_outb(hc, R_ST_SEL,
3345                                     hc->chan[dch->slot].port);
3346                                 /* undocumented: delay after R_ST_SEL */
3347                                 udelay(1);
3348                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3349                                     /* G1 */
3350                                 udelay(6); /* wait at least 5,21us */
3351                                 HFC_outb(hc, A_ST_WR_STATE, 1);
3352                                 HFC_outb(hc, A_ST_WR_STATE, 1 |
3353                                     (V_ST_ACT*3)); /* activate */
3354                                 dch->state = 1;
3355                         }
3356                         spin_unlock_irqrestore(&hc->lock, flags);
3357                 } else
3358                         ret = l1_event(dch->l1, hh->prim);
3359                 break;
3360         case PH_DEACTIVATE_REQ:
3361                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3362                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3363                         spin_lock_irqsave(&hc->lock, flags);
3364                         if (debug & DEBUG_HFCMULTI_MSG)
3365                                 printk(KERN_DEBUG
3366                                     "%s: PH_DEACTIVATE port %d (0..%d)\n",
3367                                     __func__, hc->chan[dch->slot].port,
3368                                     hc->ports-1);
3369                         /* start deactivation */
3370                         if (hc->ctype == HFC_TYPE_E1) {
3371                                 if (debug & DEBUG_HFCMULTI_MSG)
3372                                         printk(KERN_DEBUG
3373                                             "%s: PH_DEACTIVATE no BRI\n",
3374                                             __func__);
3375                         } else {
3376                                 HFC_outb(hc, R_ST_SEL,
3377                                     hc->chan[dch->slot].port);
3378                                 /* undocumented: delay after R_ST_SEL */
3379                                 udelay(1);
3380                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3381                                     /* deactivate */
3382                                 dch->state = 1;
3383                         }
3384                         skb_queue_purge(&dch->squeue);
3385                         if (dch->tx_skb) {
3386                                 dev_kfree_skb(dch->tx_skb);
3387                                 dch->tx_skb = NULL;
3388                         }
3389                         dch->tx_idx = 0;
3390                         if (dch->rx_skb) {
3391                                 dev_kfree_skb(dch->rx_skb);
3392                                 dch->rx_skb = NULL;
3393                         }
3394                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3395                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3396                                 del_timer(&dch->timer);
3397 #ifdef FIXME
3398                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3399                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3400 #endif
3401                         ret = 0;
3402                         spin_unlock_irqrestore(&hc->lock, flags);
3403                 } else
3404                         ret = l1_event(dch->l1, hh->prim);
3405                 break;
3406         }
3407         if (!ret)
3408                 dev_kfree_skb(skb);
3409         return ret;
3410 }
3411
3412 static void
3413 deactivate_bchannel(struct bchannel *bch)
3414 {
3415         struct hfc_multi        *hc = bch->hw;
3416         u_long                  flags;
3417
3418         spin_lock_irqsave(&hc->lock, flags);
3419         if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
3420                 dev_kfree_skb(bch->next_skb);
3421                 bch->next_skb = NULL;
3422         }
3423         if (bch->tx_skb) {
3424                 dev_kfree_skb(bch->tx_skb);
3425                 bch->tx_skb = NULL;
3426         }
3427         bch->tx_idx = 0;
3428         if (bch->rx_skb) {
3429                 dev_kfree_skb(bch->rx_skb);
3430                 bch->rx_skb = NULL;
3431         }
3432         hc->chan[bch->slot].coeff_count = 0;
3433         test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
3434         test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
3435         hc->chan[bch->slot].rx_off = 0;
3436         hc->chan[bch->slot].conf = -1;
3437         mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3438         spin_unlock_irqrestore(&hc->lock, flags);
3439 }
3440
3441 static int
3442 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3443 {
3444         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3445         struct hfc_multi        *hc = bch->hw;
3446         int                     ret = -EINVAL;
3447         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3448         unsigned int            id;
3449         u_long                  flags;
3450
3451         switch (hh->prim) {
3452         case PH_DATA_REQ:
3453                 if (!skb->len)
3454                         break;
3455                 spin_lock_irqsave(&hc->lock, flags);
3456                 ret = bchannel_senddata(bch, skb);
3457                 if (ret > 0) { /* direct TX */
3458                         id = hh->id; /* skb can be freed */
3459                         hfcmulti_tx(hc, bch->slot);
3460                         ret = 0;
3461                         /* start fifo */
3462                         HFC_outb_nodebug(hc, R_FIFO, 0);
3463                         HFC_wait_nodebug(hc);
3464                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3465                                 spin_unlock_irqrestore(&hc->lock, flags);
3466                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3467                         } else
3468                                 spin_unlock_irqrestore(&hc->lock, flags);
3469                 } else
3470                         spin_unlock_irqrestore(&hc->lock, flags);
3471                 return ret;
3472         case PH_ACTIVATE_REQ:
3473                 if (debug & DEBUG_HFCMULTI_MSG)
3474                         printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3475                                 __func__, bch->slot);
3476                 spin_lock_irqsave(&hc->lock, flags);
3477                 /* activate B-channel if not already activated */
3478                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3479                         hc->chan[bch->slot].txpending = 0;
3480                         ret = mode_hfcmulti(hc, bch->slot,
3481                                 ch->protocol,
3482                                 hc->chan[bch->slot].slot_tx,
3483                                 hc->chan[bch->slot].bank_tx,
3484                                 hc->chan[bch->slot].slot_rx,
3485                                 hc->chan[bch->slot].bank_rx);
3486                         if (!ret) {
3487                                 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3488                                         && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3489                                         /* start decoder */
3490                                         hc->dtmf = 1;
3491                                         if (debug & DEBUG_HFCMULTI_DTMF)
3492                                                 printk(KERN_DEBUG
3493                                                     "%s: start dtmf decoder\n",
3494                                                         __func__);
3495                                         HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3496                                             V_RST_DTMF);
3497                                 }
3498                         }
3499                 } else
3500                         ret = 0;
3501                 spin_unlock_irqrestore(&hc->lock, flags);
3502                 if (!ret)
3503                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3504                                 GFP_KERNEL);
3505                 break;
3506         case PH_CONTROL_REQ:
3507                 spin_lock_irqsave(&hc->lock, flags);
3508                 switch (hh->id) {
3509                 case HFC_SPL_LOOP_ON: /* set sample loop */
3510                         if (debug & DEBUG_HFCMULTI_MSG)
3511                                 printk(KERN_DEBUG
3512                                     "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3513                                     __func__, skb->len);
3514                         ret = 0;
3515                         break;
3516                 case HFC_SPL_LOOP_OFF: /* set silence */
3517                         if (debug & DEBUG_HFCMULTI_MSG)
3518                                 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3519                                     __func__);
3520                         ret = 0;
3521                         break;
3522                 default:
3523                         printk(KERN_ERR
3524                              "%s: unknown PH_CONTROL_REQ info %x\n",
3525                              __func__, hh->id);
3526                         ret = -EINVAL;
3527                 }
3528                 spin_unlock_irqrestore(&hc->lock, flags);
3529                 break;
3530         case PH_DEACTIVATE_REQ:
3531                 deactivate_bchannel(bch); /* locked there */
3532                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3533                         GFP_KERNEL);
3534                 ret = 0;
3535                 break;
3536         }
3537         if (!ret)
3538                 dev_kfree_skb(skb);
3539         return ret;
3540 }
3541
3542 /*
3543  * bchannel control function
3544  */
3545 static int
3546 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3547 {
3548         int                     ret = 0;
3549         struct dsp_features     *features =
3550                 (struct dsp_features *)(*((u_long *)&cq->p1));
3551         struct hfc_multi        *hc = bch->hw;
3552         int                     slot_tx;
3553         int                     bank_tx;
3554         int                     slot_rx;
3555         int                     bank_rx;
3556         int                     num;
3557
3558         switch (cq->op) {
3559         case MISDN_CTRL_GETOP:
3560                 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3561                         | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY;
3562                 break;
3563         case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3564                 hc->chan[bch->slot].rx_off = !!cq->p1;
3565                 if (!hc->chan[bch->slot].rx_off) {
3566                         /* reset fifo on rx on */
3567                         HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3568                         HFC_wait_nodebug(hc);
3569                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3570                         HFC_wait_nodebug(hc);
3571                 }
3572                 if (debug & DEBUG_HFCMULTI_MSG)
3573                         printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3574                             __func__, bch->nr, hc->chan[bch->slot].rx_off);
3575                 break;
3576         case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
3577                 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
3578                 if (debug & DEBUG_HFCMULTI_MSG)
3579                         printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
3580                                 "off=%d)\n", __func__, bch->nr, !!cq->p1);
3581                 break;
3582         case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3583                 if (debug & DEBUG_HFCMULTI_MSG)
3584                         printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3585                             __func__);
3586                 /* create confirm */
3587                 features->hfc_id = hc->id;
3588                 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3589                         features->hfc_dtmf = 1;
3590                 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3591                         features->hfc_conf = 1;
3592                 features->hfc_loops = 0;
3593                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3594                         features->hfc_echocanhw = 1;
3595                 } else {
3596                         features->pcm_id = hc->pcm;
3597                         features->pcm_slots = hc->slots;
3598                         features->pcm_banks = 2;
3599                 }
3600                 break;
3601         case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3602                 slot_tx = cq->p1 & 0xff;
3603                 bank_tx = cq->p1 >> 8;
3604                 slot_rx = cq->p2 & 0xff;
3605                 bank_rx = cq->p2 >> 8;
3606                 if (debug & DEBUG_HFCMULTI_MSG)
3607                         printk(KERN_DEBUG
3608                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3609                             "slot %d bank %d (RX)\n",
3610                             __func__, slot_tx, bank_tx,
3611                             slot_rx, bank_rx);
3612                 if (slot_tx < hc->slots && bank_tx <= 2 &&
3613                     slot_rx < hc->slots && bank_rx <= 2)
3614                         hfcmulti_pcm(hc, bch->slot,
3615                             slot_tx, bank_tx, slot_rx, bank_rx);
3616                 else {
3617                         printk(KERN_WARNING
3618                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3619                             "slot %d bank %d (RX) out of range\n",
3620                             __func__, slot_tx, bank_tx,
3621                             slot_rx, bank_rx);
3622                         ret = -EINVAL;
3623                 }
3624                 break;
3625         case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3626                 if (debug & DEBUG_HFCMULTI_MSG)
3627                         printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3628                             __func__);
3629                 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3630                 break;
3631         case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3632                 num = cq->p1 & 0xff;
3633                 if (debug & DEBUG_HFCMULTI_MSG)
3634                         printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3635                             __func__, num);
3636                 if (num <= 7)
3637                         hfcmulti_conf(hc, bch->slot, num);
3638                 else {
3639                         printk(KERN_WARNING
3640                             "%s: HW_CONF_JOIN conf %d out of range\n",
3641                             __func__, num);
3642                         ret = -EINVAL;
3643                 }
3644                 break;
3645         case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3646                 if (debug & DEBUG_HFCMULTI_MSG)
3647                         printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3648                 hfcmulti_conf(hc, bch->slot, -1);
3649                 break;
3650         case MISDN_CTRL_HFC_ECHOCAN_ON:
3651                 if (debug & DEBUG_HFCMULTI_MSG)
3652                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3653                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3654                         vpm_echocan_on(hc, bch->slot, cq->p1);
3655                 else
3656                         ret = -EINVAL;
3657                 break;
3658
3659         case MISDN_CTRL_HFC_ECHOCAN_OFF:
3660                 if (debug & DEBUG_HFCMULTI_MSG)
3661                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3662                                 __func__);
3663                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3664                         vpm_echocan_off(hc, bch->slot);
3665                 else
3666                         ret = -EINVAL;
3667                 break;
3668         default:
3669                 printk(KERN_WARNING "%s: unknown Op %x\n",
3670                     __func__, cq->op);
3671                 ret = -EINVAL;
3672                 break;
3673         }
3674         return ret;
3675 }
3676
3677 static int
3678 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3679 {
3680         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3681         struct hfc_multi        *hc = bch->hw;
3682         int                     err = -EINVAL;
3683         u_long  flags;
3684
3685         if (bch->debug & DEBUG_HW)
3686                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3687                     __func__, cmd, arg);
3688         switch (cmd) {
3689         case CLOSE_CHANNEL:
3690                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3691                 if (test_bit(FLG_ACTIVE, &bch->Flags))
3692                         deactivate_bchannel(bch); /* locked there */
3693                 ch->protocol = ISDN_P_NONE;
3694                 ch->peer = NULL;
3695                 module_put(THIS_MODULE);
3696                 err = 0;
3697                 break;
3698         case CONTROL_CHANNEL:
3699                 spin_lock_irqsave(&hc->lock, flags);
3700                 err = channel_bctrl(bch, arg);
3701                 spin_unlock_irqrestore(&hc->lock, flags);
3702                 break;
3703         default:
3704                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3705                         __func__, cmd);
3706         }
3707         return err;
3708 }
3709
3710 /*
3711  * handle D-channel events
3712  *
3713  * handle state change event
3714  */
3715 static void
3716 ph_state_change(struct dchannel *dch)
3717 {
3718         struct hfc_multi *hc;
3719         int ch, i;
3720
3721         if (!dch) {
3722                 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
3723                 return;
3724         }
3725         hc = dch->hw;
3726         ch = dch->slot;
3727
3728         if (hc->ctype == HFC_TYPE_E1) {
3729                 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3730                         if (debug & DEBUG_HFCMULTI_STATE)
3731                                 printk(KERN_DEBUG
3732                                     "%s: E1 TE (id=%d) newstate %x\n",
3733                                     __func__, hc->id, dch->state);
3734                 } else {
3735                         if (debug & DEBUG_HFCMULTI_STATE)
3736                                 printk(KERN_DEBUG
3737                                     "%s: E1 NT (id=%d) newstate %x\n",
3738                                     __func__, hc->id, dch->state);
3739                 }
3740                 switch (dch->state) {
3741                 case (1):
3742                         if (hc->e1_state != 1) {
3743                                 for (i = 1; i <= 31; i++) {
3744                                         /* reset fifos on e1 activation */
3745                                         HFC_outb_nodebug(hc, R_FIFO,
3746                                                 (i << 1) | 1);
3747                                         HFC_wait_nodebug(hc);
3748                                         HFC_outb_nodebug(hc, R_INC_RES_FIFO,
3749                                                 V_RES_F);
3750                                         HFC_wait_nodebug(hc);
3751                                 }
3752                         }
3753                         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3754                         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3755                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3756                         break;
3757
3758                 default:
3759                         if (hc->e1_state != 1)
3760                                 return;
3761                         test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3762                         _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3763                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3764                 }
3765                 hc->e1_state = dch->state;
3766         } else {
3767                 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3768                         if (debug & DEBUG_HFCMULTI_STATE)
3769                                 printk(KERN_DEBUG
3770                                     "%s: S/T TE newstate %x\n",
3771                                     __func__, dch->state);
3772                         switch (dch->state) {
3773                         case (0):
3774                                 l1_event(dch->l1, HW_RESET_IND);
3775                                 break;
3776                         case (3):
3777                                 l1_event(dch->l1, HW_DEACT_IND);
3778                                 break;
3779                         case (5):
3780                         case (8):
3781                                 l1_event(dch->l1, ANYSIGNAL);
3782                                 break;
3783                         case (6):
3784                                 l1_event(dch->l1, INFO2);
3785                                 break;
3786                         case (7):
3787                                 l1_event(dch->l1, INFO4_P8);
3788                                 break;
3789                         }
3790                 } else {
3791                         if (debug & DEBUG_HFCMULTI_STATE)
3792                                 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3793                                     __func__, dch->state);
3794                         switch (dch->state) {
3795                         case (2):
3796                                 if (hc->chan[ch].nt_timer == 0) {
3797                                         hc->chan[ch].nt_timer = -1;
3798                                         HFC_outb(hc, R_ST_SEL,
3799                                             hc->chan[ch].port);
3800                                         /* undocumented: delay after R_ST_SEL */
3801                                         udelay(1);
3802                                         HFC_outb(hc, A_ST_WR_STATE, 4 |
3803                                             V_ST_LD_STA); /* G4 */
3804                                         udelay(6); /* wait at least 5,21us */
3805                                         HFC_outb(hc, A_ST_WR_STATE, 4);
3806                                         dch->state = 4;
3807                                 } else {
3808                                         /* one extra count for the next event */
3809                                         hc->chan[ch].nt_timer =
3810                                             nt_t1_count[poll_timer] + 1;
3811                                         HFC_outb(hc, R_ST_SEL,
3812                                             hc->chan[ch].port);
3813                                         /* undocumented: delay after R_ST_SEL */
3814                                         udelay(1);
3815                                         /* allow G2 -> G3 transition */
3816                                         HFC_outb(hc, A_ST_WR_STATE, 2 |
3817                                             V_SET_G2_G3);
3818                                 }
3819                                 break;
3820                         case (1):
3821                                 hc->chan[ch].nt_timer = -1;
3822                                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3823                                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3824                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3825                                 break;
3826                         case (4):
3827                                 hc->chan[ch].nt_timer = -1;
3828                                 break;
3829                         case (3):
3830                                 hc->chan[ch].nt_timer = -1;
3831                                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3832                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3833                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3834                                 break;
3835                         }
3836                 }
3837         }
3838 }
3839
3840 /*
3841  * called for card mode init message
3842  */
3843
3844 static void
3845 hfcmulti_initmode(struct dchannel *dch)
3846 {
3847         struct hfc_multi *hc = dch->hw;
3848         u_char          a_st_wr_state, r_e1_wr_sta;
3849         int             i, pt;
3850
3851         if (debug & DEBUG_HFCMULTI_INIT)
3852                 printk(KERN_DEBUG "%s: entered\n", __func__);
3853
3854         if (hc->ctype == HFC_TYPE_E1) {
3855                 hc->chan[hc->dslot].slot_tx = -1;
3856                 hc->chan[hc->dslot].slot_rx = -1;
3857                 hc->chan[hc->dslot].conf = -1;
3858                 if (hc->dslot) {
3859                         mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3860                                 -1, 0, -1, 0);
3861                         dch->timer.function = (void *) hfcmulti_dbusy_timer;
3862                         dch->timer.data = (long) dch;
3863                         init_timer(&dch->timer);
3864                 }
3865                 for (i = 1; i <= 31; i++) {
3866                         if (i == hc->dslot)
3867                                 continue;
3868                         hc->chan[i].slot_tx = -1;
3869                         hc->chan[i].slot_rx = -1;
3870                         hc->chan[i].conf = -1;
3871                         mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3872                 }
3873                 /* E1 */
3874                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3875                         HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3876                         HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3877                 }
3878                 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3879                         HFC_outb(hc, R_RX0, 0);
3880                         hc->hw.r_tx0 = 0 | V_OUT_EN;
3881                 } else {
3882                         HFC_outb(hc, R_RX0, 1);
3883                         hc->hw.r_tx0 = 1 | V_OUT_EN;
3884                 }
3885                 hc->hw.r_tx1 = V_ATX | V_NTRI;
3886                 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3887                 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3888                 HFC_outb(hc, R_TX_FR0, 0x00);
3889                 HFC_outb(hc, R_TX_FR1, 0xf8);
3890
3891                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3892                         HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3893
3894                 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3895
3896                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3897                         HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3898
3899                 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3900                         if (debug & DEBUG_HFCMULTI_INIT)
3901                                 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3902                                     __func__);
3903                         r_e1_wr_sta = 0; /* G0 */
3904                         hc->e1_getclock = 0;
3905                 } else {
3906                         if (debug & DEBUG_HFCMULTI_INIT)
3907                                 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3908                                     __func__);
3909                         r_e1_wr_sta = 0; /* F0 */
3910                         hc->e1_getclock = 1;
3911                 }
3912                 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3913                         HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3914                 else
3915                         HFC_outb(hc, R_SYNC_OUT, 0);
3916                 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3917                         hc->e1_getclock = 1;
3918                 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3919                         hc->e1_getclock = 0;
3920                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3921                         /* SLAVE (clock master) */
3922                         if (debug & DEBUG_HFCMULTI_INIT)
3923                                 printk(KERN_DEBUG
3924                                     "%s: E1 port is clock master "
3925                                     "(clock from PCM)\n", __func__);
3926                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3927                 } else {
3928                         if (hc->e1_getclock) {
3929                                 /* MASTER (clock slave) */
3930                                 if (debug & DEBUG_HFCMULTI_INIT)
3931                                         printk(KERN_DEBUG
3932                                             "%s: E1 port is clock slave "
3933                                             "(clock to PCM)\n", __func__);
3934                                 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3935                         } else {
3936                                 /* MASTER (clock master) */
3937                                 if (debug & DEBUG_HFCMULTI_INIT)
3938                                         printk(KERN_DEBUG "%s: E1 port is "
3939                                             "clock master "
3940                                             "(clock from QUARTZ)\n",
3941                                             __func__);
3942                                 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3943                                     V_PCM_SYNC | V_JATT_OFF);
3944                                 HFC_outb(hc, R_SYNC_OUT, 0);
3945                         }
3946                 }
3947                 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3948                 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3949                 HFC_outb(hc, R_PWM0, 0x50);
3950                 HFC_outb(hc, R_PWM1, 0xff);
3951                 /* state machine setup */
3952                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3953                 udelay(6); /* wait at least 5,21us */
3954                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3955                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3956                         hc->syncronized = 0;
3957                         plxsd_checksync(hc, 0);
3958                 }
3959         } else {
3960                 i = dch->slot;
3961                 hc->chan[i].slot_tx = -1;
3962                 hc->chan[i].slot_rx = -1;
3963                 hc->chan[i].conf = -1;
3964                 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3965                 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3966                 dch->timer.data = (long) dch;
3967                 init_timer(&dch->timer);
3968                 hc->chan[i - 2].slot_tx = -1;
3969                 hc->chan[i - 2].slot_rx = -1;
3970                 hc->chan[i - 2].conf = -1;
3971                 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3972                 hc->chan[i - 1].slot_tx = -1;
3973                 hc->chan[i - 1].slot_rx = -1;
3974                 hc->chan[i - 1].conf = -1;
3975                 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3976                 /* ST */
3977                 pt = hc->chan[i].port;
3978                 /* select interface */
3979                 HFC_outb(hc, R_ST_SEL, pt);
3980                 /* undocumented: delay after R_ST_SEL */
3981                 udelay(1);
3982                 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3983                         if (debug & DEBUG_HFCMULTI_INIT)
3984                                 printk(KERN_DEBUG
3985                                     "%s: ST port %d is NT-mode\n",
3986                                     __func__, pt);
3987                         /* clock delay */
3988                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3989                         a_st_wr_state = 1; /* G1 */
3990                         hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3991                 } else {
3992                         if (debug & DEBUG_HFCMULTI_INIT)
3993                                 printk(KERN_DEBUG
3994                                     "%s: ST port %d is TE-mode\n",
3995                                     __func__, pt);
3996                         /* clock delay */
3997                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3998                         a_st_wr_state = 2; /* F2 */
3999                         hc->hw.a_st_ctrl0[pt] = 0;
4000                 }
4001                 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
4002                         hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
4003                 if (hc->ctype == HFC_TYPE_XHFC) {
4004                         hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
4005                         HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
4006                                 0x7c << 1 /* V_ST_PULSE */);
4007                 }
4008                 /* line setup */
4009                 HFC_outb(hc, A_ST_CTRL0,  hc->hw.a_st_ctrl0[pt]);
4010                 /* disable E-channel */
4011                 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
4012                     test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
4013                         HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
4014                 else
4015                         HFC_outb(hc, A_ST_CTRL1, 0);
4016                 /* enable B-channel receive */
4017                 HFC_outb(hc, A_ST_CTRL2,  V_B1_RX_EN | V_B2_RX_EN);
4018                 /* state machine setup */
4019                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
4020                 udelay(6); /* wait at least 5,21us */
4021                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
4022                 hc->hw.r_sci_msk |= 1 << pt;
4023                 /* state machine interrupts */
4024                 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4025                 /* unset sync on port */
4026                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4027                         hc->syncronized &=
4028                            ~(1 << hc->chan[dch->slot].port);
4029                         plxsd_checksync(hc, 0);
4030                 }
4031         }
4032         if (debug & DEBUG_HFCMULTI_INIT)
4033                 printk("%s: done\n", __func__);
4034 }
4035
4036
4037 static int
4038 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
4039     struct channel_req *rq)
4040 {
4041         int     err = 0;
4042         u_long  flags;
4043
4044         if (debug & DEBUG_HW_OPEN)
4045                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
4046                     dch->dev.id, __builtin_return_address(0));
4047         if (rq->protocol == ISDN_P_NONE)
4048                 return -EINVAL;
4049         if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4050             (dch->dev.D.protocol != rq->protocol)) {
4051                 if (debug & DEBUG_HFCMULTI_MODE)
4052                         printk(KERN_DEBUG "%s: change protocol %x to %x\n",
4053                             __func__, dch->dev.D.protocol, rq->protocol);
4054         }
4055         if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4056             (rq->protocol != ISDN_P_TE_S0))
4057                 l1_event(dch->l1, CLOSE_CHANNEL);
4058         if (dch->dev.D.protocol != rq->protocol) {
4059                 if (rq->protocol == ISDN_P_TE_S0) {
4060                         err = create_l1(dch, hfcm_l1callback);
4061                         if (err)
4062                                 return err;
4063                 }
4064                 dch->dev.D.protocol = rq->protocol;
4065                 spin_lock_irqsave(&hc->lock, flags);
4066                 hfcmulti_initmode(dch);
4067                 spin_unlock_irqrestore(&hc->lock, flags);
4068         }
4069
4070         if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
4071             ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
4072             ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
4073             ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
4074                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4075                     0, NULL, GFP_KERNEL);
4076         }
4077         rq->ch = &dch->dev.D;
4078         if (!try_module_get(THIS_MODULE))
4079                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4080         return 0;
4081 }
4082
4083 static int
4084 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
4085     struct channel_req *rq)
4086 {
4087         struct bchannel *bch;
4088         int             ch;
4089
4090         if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
4091                 return -EINVAL;
4092         if (rq->protocol == ISDN_P_NONE)
4093                 return -EINVAL;
4094         if (hc->ctype == HFC_TYPE_E1)
4095                 ch = rq->adr.channel;
4096         else
4097                 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4098         bch = hc->chan[ch].bch;
4099         if (!bch) {
4100                 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4101                     __func__, ch);
4102                 return -EINVAL;
4103         }
4104         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4105                 return -EBUSY; /* b-channel can be only open once */
4106         test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
4107         bch->ch.protocol = rq->protocol;
4108         hc->chan[ch].rx_off = 0;
4109         rq->ch = &bch->ch;
4110         if (!try_module_get(THIS_MODULE))
4111                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4112         return 0;
4113 }
4114
4115 /*
4116  * device control function
4117  */
4118 static int
4119 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4120 {
4121         struct hfc_multi        *hc = dch->hw;
4122         int     ret = 0;
4123         int     wd_mode, wd_cnt;
4124
4125         switch (cq->op) {
4126         case MISDN_CTRL_GETOP:
4127                 cq->op = MISDN_CTRL_HFC_OP;
4128                 break;
4129         case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4130                 wd_cnt = cq->p1 & 0xf;
4131                 wd_mode = !!(cq->p1 >> 4);
4132                 if (debug & DEBUG_HFCMULTI_MSG)
4133                         printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
4134                             ", counter 0x%x\n", __func__,
4135                             wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4136                 /* set the watchdog timer */
4137                 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4138                 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4139                 if (hc->ctype == HFC_TYPE_XHFC)
4140                         hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4141                 /* init the watchdog register and reset the counter */
4142                 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4143                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4144                         /* enable the watchdog output for Speech-Design */
4145                         HFC_outb(hc, R_GPIO_SEL,  V_GPIO_SEL7);
4146                         HFC_outb(hc, R_GPIO_EN1,  V_GPIO_EN15);
4147                         HFC_outb(hc, R_GPIO_OUT1, 0);
4148                         HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4149                 }
4150                 break;
4151         case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4152                 if (debug & DEBUG_HFCMULTI_MSG)
4153                         printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4154                             __func__);
4155                 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4156                 break;
4157         default:
4158                 printk(KERN_WARNING "%s: unknown Op %x\n",
4159                     __func__, cq->op);
4160                 ret = -EINVAL;
4161                 break;
4162         }
4163         return ret;
4164 }
4165
4166 static int
4167 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4168 {
4169         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
4170         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
4171         struct hfc_multi        *hc = dch->hw;
4172         struct channel_req      *rq;
4173         int                     err = 0;
4174         u_long                  flags;
4175
4176         if (dch->debug & DEBUG_HW)
4177                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4178                     __func__, cmd, arg);
4179         switch (cmd) {
4180         case OPEN_CHANNEL:
4181                 rq = arg;
4182                 switch (rq->protocol) {
4183                 case ISDN_P_TE_S0:
4184                 case ISDN_P_NT_S0:
4185                         if (hc->ctype == HFC_TYPE_E1) {
4186                                 err = -EINVAL;
4187                                 break;
4188                         }
4189                         err = open_dchannel(hc, dch, rq); /* locked there */
4190                         break;
4191                 case ISDN_P_TE_E1:
4192                 case ISDN_P_NT_E1:
4193                         if (hc->ctype != HFC_TYPE_E1) {
4194                                 err = -EINVAL;
4195                                 break;
4196                         }
4197                         err = open_dchannel(hc, dch, rq); /* locked there */
4198                         break;
4199                 default:
4200                         spin_lock_irqsave(&hc->lock, flags);
4201                         err = open_bchannel(hc, dch, rq);
4202                         spin_unlock_irqrestore(&hc->lock, flags);
4203                 }
4204                 break;
4205         case CLOSE_CHANNEL:
4206                 if (debug & DEBUG_HW_OPEN)
4207                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4208                             __func__, dch->dev.id,
4209                             __builtin_return_address(0));
4210                 module_put(THIS_MODULE);
4211                 break;
4212         case CONTROL_CHANNEL:
4213                 spin_lock_irqsave(&hc->lock, flags);
4214                 err = channel_dctrl(dch, arg);
4215                 spin_unlock_irqrestore(&hc->lock, flags);
4216                 break;
4217         default:
4218                 if (dch->debug & DEBUG_HW)
4219                         printk(KERN_DEBUG "%s: unknown command %x\n",
4220                             __func__, cmd);
4221                 err = -EINVAL;
4222         }
4223         return err;
4224 }
4225
4226 static int
4227 clockctl(void *priv, int enable)
4228 {
4229         struct hfc_multi *hc = priv;
4230
4231         hc->iclock_on = enable;
4232         return 0;
4233 }
4234
4235 /*
4236  * initialize the card
4237  */
4238
4239 /*
4240  * start timer irq, wait some time and check if we have interrupts.
4241  * if not, reset chip and try again.
4242  */
4243 static int
4244 init_card(struct hfc_multi *hc)
4245 {
4246         int     err = -EIO;
4247         u_long  flags;
4248         void    __iomem *plx_acc;
4249         u_long  plx_flags;
4250
4251         if (debug & DEBUG_HFCMULTI_INIT)
4252                 printk(KERN_DEBUG "%s: entered\n", __func__);
4253
4254         spin_lock_irqsave(&hc->lock, flags);
4255         /* set interrupts but leave global interrupt disabled */
4256         hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4257         disable_hwirq(hc);
4258         spin_unlock_irqrestore(&hc->lock, flags);
4259
4260         if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4261             "HFC-multi", hc)) {
4262                 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4263                     hc->irq);
4264                 hc->irq = 0;
4265                 return -EIO;
4266         }
4267
4268         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4269                 spin_lock_irqsave(&plx_lock, plx_flags);
4270                 plx_acc = hc->plx_membase + PLX_INTCSR;
4271                 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4272                         plx_acc); /* enable PCI & LINT1 irq */
4273                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4274         }
4275
4276         if (debug & DEBUG_HFCMULTI_INIT)
4277                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4278                     __func__, hc->irq, hc->irqcnt);
4279         err = init_chip(hc);
4280         if (err)
4281                 goto error;
4282         /*
4283          * Finally enable IRQ output
4284          * this is only allowed, if an IRQ routine is allready
4285          * established for this HFC, so don't do that earlier
4286          */
4287         spin_lock_irqsave(&hc->lock, flags);
4288         enable_hwirq(hc);
4289         spin_unlock_irqrestore(&hc->lock, flags);
4290         /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4291         set_current_state(TASK_UNINTERRUPTIBLE);
4292         schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4293         /* turn IRQ off until chip is completely initialized */
4294         spin_lock_irqsave(&hc->lock, flags);
4295         disable_hwirq(hc);
4296         spin_unlock_irqrestore(&hc->lock, flags);
4297         if (debug & DEBUG_HFCMULTI_INIT)
4298                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4299                     __func__, hc->irq, hc->irqcnt);
4300         if (hc->irqcnt) {
4301                 if (debug & DEBUG_HFCMULTI_INIT)
4302                         printk(KERN_DEBUG "%s: done\n", __func__);
4303
4304                 return 0;
4305         }
4306         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4307                 printk(KERN_INFO "ignoring missing interrupts\n");
4308                 return 0;
4309         }
4310
4311         printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4312                 hc->irq);
4313
4314         err = -EIO;
4315
4316 error:
4317         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4318                 spin_lock_irqsave(&plx_lock, plx_flags);
4319                 plx_acc = hc->plx_membase + PLX_INTCSR;
4320                 writew(0x00, plx_acc); /*disable IRQs*/
4321                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4322         }
4323
4324         if (debug & DEBUG_HFCMULTI_INIT)
4325                 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4326         if (hc->irq) {
4327                 free_irq(hc->irq, hc);
4328                 hc->irq = 0;
4329         }
4330
4331         if (debug & DEBUG_HFCMULTI_INIT)
4332                 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4333         return err;
4334 }
4335
4336 /*
4337  * find pci device and set it up
4338  */
4339
4340 static int
4341 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4342                 const struct pci_device_id *ent)
4343 {
4344         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4345
4346         printk(KERN_INFO
4347             "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4348             m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4349
4350         hc->pci_dev = pdev;
4351         if (m->clock2)
4352                 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4353
4354         if (ent->device == 0xB410) {
4355                 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4356                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4357                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4358                 hc->slots = 32;
4359         }
4360
4361         if (hc->pci_dev->irq <= 0) {
4362                 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4363                 return -EIO;
4364         }
4365         if (pci_enable_device(hc->pci_dev)) {
4366                 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4367                 return -EIO;
4368         }
4369         hc->leds = m->leds;
4370         hc->ledstate = 0xAFFEAFFE;
4371         hc->opticalsupport = m->opticalsupport;
4372
4373         hc->pci_iobase = 0;
4374         hc->pci_membase = NULL;
4375         hc->plx_membase = NULL;
4376
4377         /* set memory access methods */
4378         if (m->io_mode) /* use mode from card config */
4379                 hc->io_mode = m->io_mode;
4380         switch (hc->io_mode) {
4381         case HFC_IO_MODE_PLXSD:
4382                 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4383                 hc->slots = 128; /* required */
4384                 hc->HFC_outb = HFC_outb_pcimem;
4385                 hc->HFC_inb = HFC_inb_pcimem;
4386                 hc->HFC_inw = HFC_inw_pcimem;
4387                 hc->HFC_wait = HFC_wait_pcimem;
4388                 hc->read_fifo = read_fifo_pcimem;
4389                 hc->write_fifo = write_fifo_pcimem;
4390                 hc->plx_origmembase =  hc->pci_dev->resource[0].start;
4391                 /* MEMBASE 1 is PLX PCI Bridge */
4392
4393                 if (!hc->plx_origmembase) {
4394                         printk(KERN_WARNING
4395                           "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4396                         pci_disable_device(hc->pci_dev);
4397                         return -EIO;
4398                 }
4399
4400                 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4401                 if (!hc->plx_membase) {
4402                         printk(KERN_WARNING
4403                             "HFC-multi: failed to remap plx address space. "
4404                             "(internal error)\n");
4405                         pci_disable_device(hc->pci_dev);
4406                         return -EIO;
4407                 }
4408                 printk(KERN_INFO
4409                     "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4410                     (u_long)hc->plx_membase, hc->plx_origmembase);
4411
4412                 hc->pci_origmembase =  hc->pci_dev->resource[2].start;
4413                     /* MEMBASE 1 is PLX PCI Bridge */
4414                 if (!hc->pci_origmembase) {
4415                         printk(KERN_WARNING
4416                             "HFC-multi: No IO-Memory for PCI card found\n");
4417                         pci_disable_device(hc->pci_dev);
4418                         return -EIO;
4419                 }
4420
4421                 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4422                 if (!hc->pci_membase) {
4423                         printk(KERN_WARNING "HFC-multi: failed to remap io "
4424                             "address space. (internal error)\n");
4425                         pci_disable_device(hc->pci_dev);
4426                         return -EIO;
4427                 }
4428
4429                 printk(KERN_INFO
4430                     "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4431                     "leds-type %d\n",
4432                     hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4433                     hc->pci_dev->irq, HZ, hc->leds);
4434                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4435                 break;
4436         case HFC_IO_MODE_PCIMEM:
4437                 hc->HFC_outb = HFC_outb_pcimem;
4438                 hc->HFC_inb = HFC_inb_pcimem;
4439                 hc->HFC_inw = HFC_inw_pcimem;
4440                 hc->HFC_wait = HFC_wait_pcimem;
4441                 hc->read_fifo = read_fifo_pcimem;
4442                 hc->write_fifo = write_fifo_pcimem;
4443                 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4444                 if (!hc->pci_origmembase) {
4445                         printk(KERN_WARNING
4446                             "HFC-multi: No IO-Memory for PCI card found\n");
4447                         pci_disable_device(hc->pci_dev);
4448                         return -EIO;
4449                 }
4450
4451                 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4452                 if (!hc->pci_membase) {
4453                         printk(KERN_WARNING
4454                             "HFC-multi: failed to remap io address space. "
4455                             "(internal error)\n");
4456                         pci_disable_device(hc->pci_dev);
4457                         return -EIO;
4458                 }
4459                 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4460                     "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4461                     hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4462                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4463                 break;
4464         case HFC_IO_MODE_REGIO:
4465                 hc->HFC_outb = HFC_outb_regio;
4466                 hc->HFC_inb = HFC_inb_regio;
4467                 hc->HFC_inw = HFC_inw_regio;
4468                 hc->HFC_wait = HFC_wait_regio;
4469                 hc->read_fifo = read_fifo_regio;
4470                 hc->write_fifo = write_fifo_regio;
4471                 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4472                 if (!hc->pci_iobase) {
4473                         printk(KERN_WARNING
4474                                 "HFC-multi: No IO for PCI card found\n");
4475                         pci_disable_device(hc->pci_dev);
4476                         return -EIO;
4477                 }
4478
4479                 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4480                         printk(KERN_WARNING "HFC-multi: failed to request "
4481                             "address space at 0x%08lx (internal error)\n",
4482                             hc->pci_iobase);
4483                         pci_disable_device(hc->pci_dev);
4484                         return -EIO;
4485                 }
4486
4487                 printk(KERN_INFO
4488                     "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4489                     m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4490                     hc->pci_dev->irq, HZ, hc->leds);
4491                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4492                 break;
4493         default:
4494                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4495                 pci_disable_device(hc->pci_dev);
4496                 return -EIO;
4497         }
4498
4499         pci_set_drvdata(hc->pci_dev, hc);
4500
4501         /* At this point the needed PCI config is done */
4502         /* fifos are still not enabled */
4503         return 0;
4504 }
4505
4506
4507 /*
4508  * remove port
4509  */
4510
4511 static void
4512 release_port(struct hfc_multi *hc, struct dchannel *dch)
4513 {
4514         int     pt, ci, i = 0;
4515         u_long  flags;
4516         struct bchannel *pb;
4517
4518         ci = dch->slot;
4519         pt = hc->chan[ci].port;
4520
4521         if (debug & DEBUG_HFCMULTI_INIT)
4522                 printk(KERN_DEBUG "%s: entered for port %d\n",
4523                         __func__, pt + 1);
4524
4525         if (pt >= hc->ports) {
4526                 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4527                      __func__, pt + 1);
4528                 return;
4529         }
4530
4531         if (debug & DEBUG_HFCMULTI_INIT)
4532                 printk(KERN_DEBUG "%s: releasing port=%d\n",
4533                     __func__, pt + 1);
4534
4535         if (dch->dev.D.protocol == ISDN_P_TE_S0)
4536                 l1_event(dch->l1, CLOSE_CHANNEL);
4537
4538         hc->chan[ci].dch = NULL;
4539
4540         if (hc->created[pt]) {
4541                 hc->created[pt] = 0;
4542                 mISDN_unregister_device(&dch->dev);
4543         }
4544
4545         spin_lock_irqsave(&hc->lock, flags);
4546
4547         if (dch->timer.function) {
4548                 del_timer(&dch->timer);
4549                 dch->timer.function = NULL;
4550         }
4551
4552         if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4553                 /* remove sync */
4554                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4555                         hc->syncronized = 0;
4556                         plxsd_checksync(hc, 1);
4557                 }
4558                 /* free channels */
4559                 for (i = 0; i <= 31; i++) {
4560                         if (hc->chan[i].bch) {
4561                                 if (debug & DEBUG_HFCMULTI_INIT)
4562                                         printk(KERN_DEBUG
4563                                             "%s: free port %d channel %d\n",
4564                                             __func__, hc->chan[i].port+1, i);
4565                                 pb = hc->chan[i].bch;
4566                                 hc->chan[i].bch = NULL;
4567                                 spin_unlock_irqrestore(&hc->lock, flags);
4568                                 mISDN_freebchannel(pb);
4569                                 kfree(pb);
4570                                 kfree(hc->chan[i].coeff);
4571                                 spin_lock_irqsave(&hc->lock, flags);
4572                         }
4573                 }
4574         } else {
4575                 /* remove sync */
4576                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4577                         hc->syncronized &=
4578                            ~(1 << hc->chan[ci].port);
4579                         plxsd_checksync(hc, 1);
4580                 }
4581                 /* free channels */
4582                 if (hc->chan[ci - 2].bch) {
4583                         if (debug & DEBUG_HFCMULTI_INIT)
4584                                 printk(KERN_DEBUG
4585                                     "%s: free port %d channel %d\n",
4586                                     __func__, hc->chan[ci - 2].port+1,
4587                                     ci - 2);
4588                         pb = hc->chan[ci - 2].bch;
4589                         hc->chan[ci - 2].bch = NULL;
4590                         spin_unlock_irqrestore(&hc->lock, flags);
4591                         mISDN_freebchannel(pb);
4592                         kfree(pb);
4593                         kfree(hc->chan[ci - 2].coeff);
4594                         spin_lock_irqsave(&hc->lock, flags);
4595                 }
4596                 if (hc->chan[ci - 1].bch) {
4597                         if (debug & DEBUG_HFCMULTI_INIT)
4598                                 printk(KERN_DEBUG
4599                                     "%s: free port %d channel %d\n",
4600                                     __func__, hc->chan[ci - 1].port+1,
4601                                     ci - 1);
4602                         pb = hc->chan[ci - 1].bch;
4603                         hc->chan[ci - 1].bch = NULL;
4604                         spin_unlock_irqrestore(&hc->lock, flags);
4605                         mISDN_freebchannel(pb);
4606                         kfree(pb);
4607                         kfree(hc->chan[ci - 1].coeff);
4608                         spin_lock_irqsave(&hc->lock, flags);
4609                 }
4610         }
4611
4612         spin_unlock_irqrestore(&hc->lock, flags);
4613
4614         if (debug & DEBUG_HFCMULTI_INIT)
4615                 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4616         mISDN_freedchannel(dch);
4617         kfree(dch);
4618
4619         if (debug & DEBUG_HFCMULTI_INIT)
4620                 printk(KERN_DEBUG "%s: done!\n", __func__);
4621 }
4622
4623 static void
4624 release_card(struct hfc_multi *hc)
4625 {
4626         u_long  flags;
4627         int     ch;
4628
4629         if (debug & DEBUG_HFCMULTI_INIT)
4630                 printk(KERN_DEBUG "%s: release card (%d) entered\n",
4631                     __func__, hc->id);
4632
4633         /* unregister clock source */
4634         if (hc->iclock)
4635                 mISDN_unregister_clock(hc->iclock);
4636
4637         /* disable irq */
4638         spin_lock_irqsave(&hc->lock, flags);
4639         disable_hwirq(hc);
4640         spin_unlock_irqrestore(&hc->lock, flags);
4641         udelay(1000);
4642
4643         /* dimm leds */
4644         if (hc->leds)
4645                 hfcmulti_leds(hc);
4646
4647         /* disable D-channels & B-channels */
4648         if (debug & DEBUG_HFCMULTI_INIT)
4649                 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4650                     __func__);
4651         for (ch = 0; ch <= 31; ch++) {
4652                 if (hc->chan[ch].dch)
4653                         release_port(hc, hc->chan[ch].dch);
4654         }
4655
4656         /* release hardware & irq */
4657         if (hc->irq) {
4658                 if (debug & DEBUG_HFCMULTI_INIT)
4659                         printk(KERN_DEBUG "%s: free irq %d\n",
4660                             __func__, hc->irq);
4661                 free_irq(hc->irq, hc);
4662                 hc->irq = 0;
4663
4664         }
4665         release_io_hfcmulti(hc);
4666
4667         if (debug & DEBUG_HFCMULTI_INIT)
4668                 printk(KERN_DEBUG "%s: remove instance from list\n",
4669                      __func__);
4670         list_del(&hc->list);
4671
4672         if (debug & DEBUG_HFCMULTI_INIT)
4673                 printk(KERN_DEBUG "%s: delete instance\n", __func__);
4674         if (hc == syncmaster)
4675                 syncmaster = NULL;
4676         kfree(hc);
4677         if (debug & DEBUG_HFCMULTI_INIT)
4678                 printk(KERN_DEBUG "%s: card successfully removed\n",
4679                     __func__);
4680 }
4681
4682 static int
4683 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4684 {
4685         struct dchannel *dch;
4686         struct bchannel *bch;
4687         int             ch, ret = 0;
4688         char            name[MISDN_MAX_IDLEN];
4689
4690         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4691         if (!dch)
4692                 return -ENOMEM;
4693         dch->debug = debug;
4694         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4695         dch->hw = hc;
4696         dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4697         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4698             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4699         dch->dev.D.send = handle_dmsg;
4700         dch->dev.D.ctrl = hfcm_dctrl;
4701         dch->dev.nrbchan = (hc->dslot) ? 30 : 31;
4702         dch->slot = hc->dslot;
4703         hc->chan[hc->dslot].dch = dch;
4704         hc->chan[hc->dslot].port = 0;
4705         hc->chan[hc->dslot].nt_timer = -1;
4706         for (ch = 1; ch <= 31; ch++) {
4707                 if (ch == hc->dslot) /* skip dchannel */
4708                         continue;
4709                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4710                 if (!bch) {
4711                         printk(KERN_ERR "%s: no memory for bchannel\n",
4712                             __func__);
4713                         ret = -ENOMEM;
4714                         goto free_chan;
4715                 }
4716                 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4717                 if (!hc->chan[ch].coeff) {
4718                         printk(KERN_ERR "%s: no memory for coeffs\n",
4719                             __func__);
4720                         ret = -ENOMEM;
4721                         kfree(bch);
4722                         goto free_chan;
4723                 }
4724                 bch->nr = ch;
4725                 bch->slot = ch;
4726                 bch->debug = debug;
4727                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4728                 bch->hw = hc;
4729                 bch->ch.send = handle_bmsg;
4730                 bch->ch.ctrl = hfcm_bctrl;
4731                 bch->ch.nr = ch;
4732                 list_add(&bch->ch.list, &dch->dev.bchannels);
4733                 hc->chan[ch].bch = bch;
4734                 hc->chan[ch].port = 0;
4735                 set_channelmap(bch->nr, dch->dev.channelmap);
4736         }
4737         /* set optical line type */
4738         if (port[Port_cnt] & 0x001) {
4739                 if (!m->opticalsupport)  {
4740                         printk(KERN_INFO
4741                             "This board has no optical "
4742                             "support\n");
4743                 } else {
4744                         if (debug & DEBUG_HFCMULTI_INIT)
4745                                 printk(KERN_DEBUG
4746                                     "%s: PORT set optical "
4747                                     "interfacs: card(%d) "
4748                                     "port(%d)\n",
4749                                     __func__,
4750                                     HFC_cnt + 1, 1);
4751                         test_and_set_bit(HFC_CFG_OPTICAL,
4752                             &hc->chan[hc->dslot].cfg);
4753                 }
4754         }
4755         /* set LOS report */
4756         if (port[Port_cnt] & 0x004) {
4757                 if (debug & DEBUG_HFCMULTI_INIT)
4758                         printk(KERN_DEBUG "%s: PORT set "
4759                             "LOS report: card(%d) port(%d)\n",
4760                             __func__, HFC_cnt + 1, 1);
4761                 test_and_set_bit(HFC_CFG_REPORT_LOS,
4762                     &hc->chan[hc->dslot].cfg);
4763         }
4764         /* set AIS report */
4765         if (port[Port_cnt] & 0x008) {
4766                 if (debug & DEBUG_HFCMULTI_INIT)
4767                         printk(KERN_DEBUG "%s: PORT set "
4768                             "AIS report: card(%d) port(%d)\n",
4769                             __func__, HFC_cnt + 1, 1);
4770                 test_and_set_bit(HFC_CFG_REPORT_AIS,
4771                     &hc->chan[hc->dslot].cfg);
4772         }
4773         /* set SLIP report */
4774         if (port[Port_cnt] & 0x010) {
4775                 if (debug & DEBUG_HFCMULTI_INIT)
4776                         printk(KERN_DEBUG
4777                             "%s: PORT set SLIP report: "
4778                             "card(%d) port(%d)\n",
4779                             __func__, HFC_cnt + 1, 1);
4780                 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4781                     &hc->chan[hc->dslot].cfg);
4782         }
4783         /* set RDI report */
4784         if (port[Port_cnt] & 0x020) {
4785                 if (debug & DEBUG_HFCMULTI_INIT)
4786                         printk(KERN_DEBUG
4787                             "%s: PORT set RDI report: "
4788                             "card(%d) port(%d)\n",
4789                             __func__, HFC_cnt + 1, 1);
4790                 test_and_set_bit(HFC_CFG_REPORT_RDI,
4791                     &hc->chan[hc->dslot].cfg);
4792         }
4793         /* set CRC-4 Mode */
4794         if (!(port[Port_cnt] & 0x100)) {
4795                 if (debug & DEBUG_HFCMULTI_INIT)
4796                         printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4797                                 " card(%d) port(%d)\n",
4798                                 __func__, HFC_cnt + 1, 1);
4799                 test_and_set_bit(HFC_CFG_CRC4,
4800                     &hc->chan[hc->dslot].cfg);
4801         } else {
4802                 if (debug & DEBUG_HFCMULTI_INIT)
4803                         printk(KERN_DEBUG "%s: PORT turn off CRC4"
4804                                 " report: card(%d) port(%d)\n",
4805                                 __func__, HFC_cnt + 1, 1);
4806         }
4807         /* set forced clock */
4808         if (port[Port_cnt] & 0x0200) {
4809                 if (debug & DEBUG_HFCMULTI_INIT)
4810                         printk(KERN_DEBUG "%s: PORT force getting clock from "
4811                                 "E1: card(%d) port(%d)\n",
4812                                 __func__, HFC_cnt + 1, 1);
4813                 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4814         } else
4815         if (port[Port_cnt] & 0x0400) {
4816                 if (debug & DEBUG_HFCMULTI_INIT)
4817                         printk(KERN_DEBUG "%s: PORT force putting clock to "
4818                                 "E1: card(%d) port(%d)\n",
4819                                 __func__, HFC_cnt + 1, 1);
4820                 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4821         }
4822         /* set JATT PLL */
4823         if (port[Port_cnt] & 0x0800) {
4824                 if (debug & DEBUG_HFCMULTI_INIT)
4825                         printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4826                                 "E1: card(%d) port(%d)\n",
4827                                 __func__, HFC_cnt + 1, 1);
4828                 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4829         }
4830         /* set elastic jitter buffer */
4831         if (port[Port_cnt] & 0x3000) {
4832                 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4833                 if (debug & DEBUG_HFCMULTI_INIT)
4834                         printk(KERN_DEBUG
4835                             "%s: PORT set elastic "
4836                             "buffer to %d: card(%d) port(%d)\n",
4837                             __func__, hc->chan[hc->dslot].jitter,
4838                             HFC_cnt + 1, 1);
4839         } else
4840                 hc->chan[hc->dslot].jitter = 2; /* default */
4841         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4842         ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4843         if (ret)
4844                 goto free_chan;
4845         hc->created[0] = 1;
4846         return ret;
4847 free_chan:
4848         release_port(hc, dch);
4849         return ret;
4850 }
4851
4852 static int
4853 init_multi_port(struct hfc_multi *hc, int pt)
4854 {
4855         struct dchannel *dch;
4856         struct bchannel *bch;
4857         int             ch, i, ret = 0;
4858         char            name[MISDN_MAX_IDLEN];
4859
4860         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4861         if (!dch)
4862                 return -ENOMEM;
4863         dch->debug = debug;
4864         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4865         dch->hw = hc;
4866         dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4867         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4868             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4869         dch->dev.D.send = handle_dmsg;
4870         dch->dev.D.ctrl = hfcm_dctrl;
4871         dch->dev.nrbchan = 2;
4872         i = pt << 2;
4873         dch->slot = i + 2;
4874         hc->chan[i + 2].dch = dch;
4875         hc->chan[i + 2].port = pt;
4876         hc->chan[i + 2].nt_timer = -1;
4877         for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4878                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4879                 if (!bch) {
4880                         printk(KERN_ERR "%s: no memory for bchannel\n",
4881                             __func__);
4882                         ret = -ENOMEM;
4883                         goto free_chan;
4884                 }
4885                 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4886                 if (!hc->chan[i + ch].coeff) {
4887                         printk(KERN_ERR "%s: no memory for coeffs\n",
4888                             __func__);
4889                         ret = -ENOMEM;
4890                         kfree(bch);
4891                         goto free_chan;
4892                 }
4893                 bch->nr = ch + 1;
4894                 bch->slot = i + ch;
4895                 bch->debug = debug;
4896                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4897                 bch->hw = hc;
4898                 bch->ch.send = handle_bmsg;
4899                 bch->ch.ctrl = hfcm_bctrl;
4900                 bch->ch.nr = ch + 1;
4901                 list_add(&bch->ch.list, &dch->dev.bchannels);
4902                 hc->chan[i + ch].bch = bch;
4903                 hc->chan[i + ch].port = pt;
4904                 set_channelmap(bch->nr, dch->dev.channelmap);
4905         }
4906         /* set master clock */
4907         if (port[Port_cnt] & 0x001) {
4908                 if (debug & DEBUG_HFCMULTI_INIT)
4909                         printk(KERN_DEBUG
4910                             "%s: PROTOCOL set master clock: "
4911                             "card(%d) port(%d)\n",
4912                             __func__, HFC_cnt + 1, pt + 1);
4913                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4914                         printk(KERN_ERR "Error: Master clock "
4915                             "for port(%d) of card(%d) is only"
4916                             " possible with TE-mode\n",
4917                             pt + 1, HFC_cnt + 1);
4918                         ret = -EINVAL;
4919                         goto free_chan;
4920                 }
4921                 if (hc->masterclk >= 0) {
4922                         printk(KERN_ERR "Error: Master clock "
4923                             "for port(%d) of card(%d) already "
4924                             "defined for port(%d)\n",
4925                             pt + 1, HFC_cnt + 1, hc->masterclk+1);
4926                         ret = -EINVAL;
4927                         goto free_chan;
4928                 }
4929                 hc->masterclk = pt;
4930         }
4931         /* set transmitter line to non capacitive */
4932         if (port[Port_cnt] & 0x002) {
4933                 if (debug & DEBUG_HFCMULTI_INIT)
4934                         printk(KERN_DEBUG
4935                             "%s: PROTOCOL set non capacitive "
4936                             "transmitter: card(%d) port(%d)\n",
4937                             __func__, HFC_cnt + 1, pt + 1);
4938                 test_and_set_bit(HFC_CFG_NONCAP_TX,
4939                     &hc->chan[i + 2].cfg);
4940         }
4941         /* disable E-channel */
4942         if (port[Port_cnt] & 0x004) {
4943                 if (debug & DEBUG_HFCMULTI_INIT)
4944                         printk(KERN_DEBUG
4945                             "%s: PROTOCOL disable E-channel: "
4946                             "card(%d) port(%d)\n",
4947                             __func__, HFC_cnt + 1, pt + 1);
4948                 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4949                     &hc->chan[i + 2].cfg);
4950         }
4951         if (hc->ctype == HFC_TYPE_XHFC) {
4952                 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4953                         HFC_cnt + 1, pt + 1);
4954                 ret = mISDN_register_device(&dch->dev, NULL, name);
4955         } else {
4956                 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4957                         hc->ctype, HFC_cnt + 1, pt + 1);
4958                 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4959         }
4960         if (ret)
4961                 goto free_chan;
4962         hc->created[pt] = 1;
4963         return ret;
4964 free_chan:
4965         release_port(hc, dch);
4966         return ret;
4967 }
4968
4969 static int
4970 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
4971     const struct pci_device_id *ent)
4972 {
4973         int             ret_err = 0;
4974         int             pt;
4975         struct hfc_multi        *hc;
4976         u_long          flags;
4977         u_char          dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4978         int             i;
4979
4980         if (HFC_cnt >= MAX_CARDS) {
4981                 printk(KERN_ERR "too many cards (max=%d).\n",
4982                         MAX_CARDS);
4983                 return -EINVAL;
4984         }
4985         if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4986                 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4987                     "type[%d] %d was supplied as module parameter\n",
4988                     m->vendor_name, m->card_name, m->type, HFC_cnt,
4989                     type[HFC_cnt] & 0xff);
4990                 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4991                         "first, to see cards and their types.");
4992                 return -EINVAL;
4993         }
4994         if (debug & DEBUG_HFCMULTI_INIT)
4995                 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4996                     __func__, m->vendor_name, m->card_name, m->type,
4997                     type[HFC_cnt]);
4998
4999         /* allocate card+fifo structure */
5000         hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
5001         if (!hc) {
5002                 printk(KERN_ERR "No kmem for HFC-Multi card\n");
5003                 return -ENOMEM;
5004         }
5005         spin_lock_init(&hc->lock);
5006         hc->mtyp = m;
5007         hc->ctype =  m->type;
5008         hc->ports = m->ports;
5009         hc->id = HFC_cnt;
5010         hc->pcm = pcm[HFC_cnt];
5011         hc->io_mode = iomode[HFC_cnt];
5012         if (dslot[HFC_cnt] < 0 && hc->ctype == HFC_TYPE_E1) {
5013                 hc->dslot = 0;
5014                 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
5015                         "31 B-channels\n");
5016         }
5017         if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32
5018             && hc->ctype == HFC_TYPE_E1) {
5019                 hc->dslot = dslot[HFC_cnt];
5020                 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
5021                         "time slot %d\n", dslot[HFC_cnt]);
5022         } else
5023                 hc->dslot = 16;
5024
5025         /* set chip specific features */
5026         hc->masterclk = -1;
5027         if (type[HFC_cnt] & 0x100) {
5028                 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
5029                 hc->silence = 0xff; /* ulaw silence */
5030         } else
5031                 hc->silence = 0x2a; /* alaw silence */
5032         if ((poll >> 1) > sizeof(hc->silence_data)) {
5033                 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
5034                         "please fix\n");
5035                 return -EINVAL;
5036         }
5037         for (i = 0; i < (poll >> 1); i++)
5038                 hc->silence_data[i] = hc->silence;
5039
5040         if (hc->ctype != HFC_TYPE_XHFC) {
5041                 if (!(type[HFC_cnt] & 0x200))
5042                         test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5043                 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5044         }
5045
5046         if (type[HFC_cnt] & 0x800)
5047                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5048         if (type[HFC_cnt] & 0x1000) {
5049                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5050                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5051         }
5052         if (type[HFC_cnt] & 0x4000)
5053                 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5054         if (type[HFC_cnt] & 0x8000)
5055                 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5056         hc->slots = 32;
5057         if (type[HFC_cnt] & 0x10000)
5058                 hc->slots = 64;
5059         if (type[HFC_cnt] & 0x20000)
5060                 hc->slots = 128;
5061         if (type[HFC_cnt] & 0x80000) {
5062                 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5063                 hc->wdcount = 0;
5064                 hc->wdbyte = V_GPIO_OUT2;
5065                 printk(KERN_NOTICE "Watchdog enabled\n");
5066         }
5067
5068         if (pdev && ent)
5069                 /* setup pci, hc->slots may change due to PLXSD */
5070                 ret_err = setup_pci(hc, pdev, ent);
5071         else
5072 #ifdef CONFIG_MISDN_HFCMULTI_8xx
5073                 ret_err = setup_embedded(hc, m);
5074 #else
5075         {
5076                 printk(KERN_WARNING "Embedded IO Mode not selected\n");
5077                 ret_err = -EIO;
5078         }
5079 #endif
5080         if (ret_err) {
5081                 if (hc == syncmaster)
5082                         syncmaster = NULL;
5083                 kfree(hc);
5084                 return ret_err;
5085         }
5086
5087         hc->HFC_outb_nodebug = hc->HFC_outb;
5088         hc->HFC_inb_nodebug = hc->HFC_inb;
5089         hc->HFC_inw_nodebug = hc->HFC_inw;
5090         hc->HFC_wait_nodebug = hc->HFC_wait;
5091 #ifdef HFC_REGISTER_DEBUG
5092         hc->HFC_outb = HFC_outb_debug;
5093         hc->HFC_inb = HFC_inb_debug;
5094         hc->HFC_inw = HFC_inw_debug;
5095         hc->HFC_wait = HFC_wait_debug;
5096 #endif
5097         /* create channels */
5098         for (pt = 0; pt < hc->ports; pt++) {
5099                 if (Port_cnt >= MAX_PORTS) {
5100                         printk(KERN_ERR "too many ports (max=%d).\n",
5101                                 MAX_PORTS);
5102                         ret_err = -EINVAL;
5103                         goto free_card;
5104                 }
5105                 if (hc->ctype == HFC_TYPE_E1)
5106                         ret_err = init_e1_port(hc, m);
5107                 else
5108                         ret_err = init_multi_port(hc, pt);
5109                 if (debug & DEBUG_HFCMULTI_INIT)
5110                         printk(KERN_DEBUG
5111                             "%s: Registering D-channel, card(%d) port(%d)"
5112                             "result %d\n",
5113                             __func__, HFC_cnt + 1, pt, ret_err);
5114
5115                 if (ret_err) {
5116                         while (pt) { /* release already registered ports */
5117                                 pt--;
5118                                 release_port(hc, hc->chan[(pt << 2) + 2].dch);
5119                         }
5120                         goto free_card;
5121                 }
5122                 Port_cnt++;
5123         }
5124
5125         /* disp switches */
5126         switch (m->dip_type) {
5127         case DIP_4S:
5128                 /*
5129                  * Get DIP setting for beroNet 1S/2S/4S cards
5130                  * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5131                  * GPI 19/23 (R_GPI_IN2))
5132                  */
5133                 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5134                         ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5135                         (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5136
5137                 /* Port mode (TE/NT) jumpers */
5138                 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4)  & 0xf);
5139
5140                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5141                         pmj = ~pmj & 0xf;
5142
5143                 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5144                         m->vendor_name, m->card_name, dips, pmj);
5145                 break;
5146         case DIP_8S:
5147                 /*
5148                  * Get DIP Setting for beroNet 8S0+ cards
5149                  * Enable PCI auxbridge function
5150                  */
5151                 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5152                 /* prepare access to auxport */
5153                 outw(0x4000, hc->pci_iobase + 4);
5154                 /*
5155                  * some dummy reads are required to
5156                  * read valid DIP switch data
5157                  */
5158                 dips = inb(hc->pci_iobase);
5159                 dips = inb(hc->pci_iobase);
5160                 dips = inb(hc->pci_iobase);
5161                 dips = ~inb(hc->pci_iobase) & 0x3F;
5162                 outw(0x0, hc->pci_iobase + 4);
5163                 /* disable PCI auxbridge function */
5164                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5165                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5166                     m->vendor_name, m->card_name, dips);
5167                 break;
5168         case DIP_E1:
5169                 /*
5170                  * get DIP Setting for beroNet E1 cards
5171                  * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5172                  */
5173                 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
5174                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5175                     m->vendor_name, m->card_name, dips);
5176                 break;
5177         }
5178
5179         /* add to list */
5180         spin_lock_irqsave(&HFClock, flags);
5181         list_add_tail(&hc->list, &HFClist);
5182         spin_unlock_irqrestore(&HFClock, flags);
5183
5184         /* use as clock source */
5185         if (clock == HFC_cnt + 1)
5186                 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5187
5188         /* initialize hardware */
5189         hc->irq = (m->irq) ? : hc->pci_dev->irq;
5190         ret_err = init_card(hc);
5191         if (ret_err) {
5192                 printk(KERN_ERR "init card returns %d\n", ret_err);
5193                 release_card(hc);
5194                 return ret_err;
5195         }
5196
5197         /* start IRQ and return */
5198         spin_lock_irqsave(&hc->lock, flags);
5199         enable_hwirq(hc);
5200         spin_unlock_irqrestore(&hc->lock, flags);
5201         return 0;
5202
5203 free_card:
5204         release_io_hfcmulti(hc);
5205         if (hc == syncmaster)
5206                 syncmaster = NULL;
5207         kfree(hc);
5208         return ret_err;
5209 }
5210
5211 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5212 {
5213         struct hfc_multi        *card = pci_get_drvdata(pdev);
5214         u_long                  flags;
5215
5216         if (debug)
5217                 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5218                     "device:%x subvendor:%x subdevice:%x\n",
5219                     pdev->vendor, pdev->device,
5220                     pdev->subsystem_vendor, pdev->subsystem_device);
5221
5222         if (card) {
5223                 spin_lock_irqsave(&HFClock, flags);
5224                 release_card(card);
5225                 spin_unlock_irqrestore(&HFClock, flags);
5226         }  else {
5227                 if (debug)
5228                         printk(KERN_DEBUG "%s: drvdata allready removed\n",
5229                             __func__);
5230         }
5231 }
5232
5233 #define VENDOR_CCD      "Cologne Chip AG"
5234 #define VENDOR_BN       "beroNet GmbH"
5235 #define VENDOR_DIG      "Digium Inc."
5236 #define VENDOR_JH       "Junghanns.NET GmbH"
5237 #define VENDOR_PRIM     "PrimuX"
5238
5239 static const struct hm_map hfcm_map[] = {
5240 /*0*/   {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5241 /*1*/   {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5242 /*2*/   {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5243 /*3*/   {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5244 /*4*/   {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5245 /*5*/   {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5246 /*6*/   {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5247 /*7*/   {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5248 /*8*/   {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5249 /*9*/   {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5250 /*10*/  {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5251 /*11*/  {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5252
5253 /*12*/  {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5254 /*13*/  {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5255                 HFC_IO_MODE_REGIO, 0},
5256 /*14*/  {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5257 /*15*/  {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5258
5259 /*16*/  {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5260 /*17*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5261 /*18*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5262
5263 /*19*/  {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5264 /*20*/  {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5265 /*21*/  {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5266 /*22*/  {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5267
5268 /*23*/  {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5269 /*24*/  {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5270 /*25*/  {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5271
5272 /*26*/  {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5273                 HFC_IO_MODE_PLXSD, 0},
5274 /*27*/  {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5275                 HFC_IO_MODE_PLXSD, 0},
5276 /*28*/  {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5277 /*29*/  {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5278 /*30*/  {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5279 /*31*/  {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5280                 HFC_IO_MODE_EMBSD, XHFC_IRQ},
5281 /*32*/  {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5282 };
5283
5284 #undef H
5285 #define H(x)    ((unsigned long)&hfcm_map[x])
5286 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5287
5288         /* Cards with HFC-4S Chip */
5289         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5290                 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5291         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5292                 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5293         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5294                 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5295         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5296                 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5297         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5298                 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5299         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5300                 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5301         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5302                 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5303         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5304                 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5305         { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5306                 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5307         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5308                 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5309         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5310                 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5311         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5312                 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5313         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5314                 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5315         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5316                 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5317
5318         /* Cards with HFC-8S Chip */
5319         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5320         PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5321         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5322         PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5323         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5324         PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5325         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5326         PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5327         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5328                 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST  */
5329         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5330                 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST  */
5331         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5332                 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5333         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5334                 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5335         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5336                 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S  */
5337
5338
5339         /* Cards with HFC-E1 Chip */
5340         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5341                 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5342         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5343                 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5344         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5345                 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5346         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5347                 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5348
5349         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5350                 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5351         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5352                 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5353         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5354                 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5355
5356         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5357                 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5358         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5359                 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5360
5361         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5362                 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
5363
5364         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5365                 0, 0, 0},
5366         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5367                 0, 0, 0},
5368         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5369                 0, 0, 0},
5370         {0, }
5371 };
5372 #undef H
5373
5374 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5375
5376 static int
5377 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5378 {
5379         struct hm_map   *m = (struct hm_map *)ent->driver_data;
5380         int             ret;
5381
5382         if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5383             ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5384             ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5385             ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5386                 printk(KERN_ERR
5387                     "Unknown HFC multiport controller (vendor:%x device:%x "
5388                     "subvendor:%x subdevice:%x)\n", ent->vendor, ent->device,
5389                     ent->subvendor, ent->subdevice);
5390                 printk(KERN_ERR
5391                     "Please contact the driver maintainer for support.\n");
5392                 return -ENODEV;
5393         }
5394         ret = hfcmulti_init(m, pdev, ent);
5395         if (ret)
5396                 return ret;
5397         HFC_cnt++;
5398         printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5399         return 0;
5400 }
5401
5402 static struct pci_driver hfcmultipci_driver = {
5403         .name           = "hfc_multi",
5404         .probe          = hfcmulti_probe,
5405         .remove         = __devexit_p(hfc_remove_pci),
5406         .id_table       = hfmultipci_ids,
5407 };
5408
5409 static void __exit
5410 HFCmulti_cleanup(void)
5411 {
5412         struct hfc_multi *card, *next;
5413
5414         /* get rid of all devices of this driver */
5415         list_for_each_entry_safe(card, next, &HFClist, list)
5416                 release_card(card);
5417         pci_unregister_driver(&hfcmultipci_driver);
5418 }
5419
5420 static int __init
5421 HFCmulti_init(void)
5422 {
5423         int err;
5424         int i, xhfc = 0;
5425         struct hm_map m;
5426
5427         printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5428
5429 #ifdef IRQ_DEBUG
5430         printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5431 #endif
5432
5433         spin_lock_init(&HFClock);
5434         spin_lock_init(&plx_lock);
5435
5436         if (debug & DEBUG_HFCMULTI_INIT)
5437                 printk(KERN_DEBUG "%s: init entered\n", __func__);
5438
5439         switch (poll) {
5440         case 0:
5441                 poll_timer = 6;
5442                 poll = 128;
5443                 break;
5444         case 8:
5445                 poll_timer = 2;
5446                 break;
5447         case 16:
5448                 poll_timer = 3;
5449                 break;
5450         case 32:
5451                 poll_timer = 4;
5452                 break;
5453         case 64:
5454                 poll_timer = 5;
5455                 break;
5456         case 128:
5457                 poll_timer = 6;
5458                 break;
5459         case 256:
5460                 poll_timer = 7;
5461                 break;
5462         default:
5463                 printk(KERN_ERR
5464                     "%s: Wrong poll value (%d).\n", __func__, poll);
5465                 err = -EINVAL;
5466                 return err;
5467
5468         }
5469
5470         if (!clock)
5471                 clock = 1;
5472
5473         /* Register the embedded devices.
5474          * This should be done before the PCI cards registration */
5475         switch (hwid) {
5476         case HWID_MINIP4:
5477                 xhfc = 1;
5478                 m = hfcm_map[31];
5479                 break;
5480         case HWID_MINIP8:
5481                 xhfc = 2;
5482                 m = hfcm_map[31];
5483                 break;
5484         case HWID_MINIP16:
5485                 xhfc = 4;
5486                 m = hfcm_map[31];
5487                 break;
5488         default:
5489                 xhfc = 0;
5490         }
5491
5492         for (i = 0; i < xhfc; ++i) {
5493                 err = hfcmulti_init(&m, NULL, NULL);
5494                 if (err) {
5495                         printk(KERN_ERR "error registering embedded driver: "
5496                                 "%x\n", err);
5497                         return -err;
5498                 }
5499                 HFC_cnt++;
5500                 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5501         }
5502
5503         /* Register the PCI cards */
5504         err = pci_register_driver(&hfcmultipci_driver);
5505         if (err < 0) {
5506                 printk(KERN_ERR "error registering pci driver: %x\n", err);
5507                 return err;
5508         }
5509
5510         return 0;
5511 }
5512
5513
5514 module_init(HFCmulti_init);
5515 module_exit(HFCmulti_cleanup);