SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/isdn/hardware/mISDN/hfcmulti.c

   1 /*
   2  * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
   3  *
   4  * Author       Andreas Eversberg (jolly@eversberg.eu)
   5  * ported to mqueue mechanism:
   6  *              Peter Sprenger (sprengermoving-bytes.de)
   7  *
   8  * inspired by existing hfc-pci driver:
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil (kkeil@suse.de)
  11  * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2, or (at your option)
  16  * any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  * Thanks to Cologne Chip AG for this great controller!
  29  */
  30
  31 /*
  32  * module parameters:
  33  * type:
  34  *      By default (0), the card is automatically detected.
  35  *      Or use the following combinations:
  36  *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
  37  * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
  38  * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
  39  *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
  40  *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
  41  *      Bit 10    = spare
  42  *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
  43  * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
  44  *      Bit 13    = spare
  45  *      Bit 14    = 0x04000 = Use external ram (128K)
  46  *      Bit 15    = 0x08000 = Use external ram (512K)
  47  *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
  48  * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
  49  *      Bit 18    = spare
  50  *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
  51  * (all other bits are reserved and shall be 0)
  52  *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
  53  *               bus (PCM master)
  54  *
  55  * port: (optional or required for all ports on all installed cards)
  56  *      HFC-4S/HFC-8S only bits:
  57  *      Bit 0     = 0x001 = Use master clock for this S/T interface
  58  *                          (ony once per chip).
  59  *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
  60  *                          Don't use this unless you know what you are doing!
  61  *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
  62  *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
  63  *               received from port 1
  64  *
  65  *      HFC-E1 only bits:
  66  *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
  67  *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
  68  *      Bit 2     = 0x0004 = Report LOS
  69  *      Bit 3     = 0x0008 = Report AIS
  70  *      Bit 4     = 0x0010 = Report SLIP
  71  *      Bit 5     = 0x0020 = Report RDI
  72  *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
  73  *                           mode instead.
  74  *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
  75  * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
  76  *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
  77  *                           (E1 only)
  78  *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
  79  *                           for default.
  80  * (all other bits are reserved and shall be 0)
  81  *
  82  * debug:
  83  *      NOTE: only one debug value must be given for all cards
  84  *      enable debugging (see hfc_multi.h for debug options)
  85  *
  86  * poll:
  87  *      NOTE: only one poll value must be given for all cards
  88  *      Give the number of samples for each fifo process.
  89  *      By default 128 is used. Decrease to reduce delay, increase to
  90  *      reduce cpu load. If unsure, don't mess with it!
  91  *      Valid is 8, 16, 32, 64, 128, 256.
  92  *
  93  * pcm:
  94  *      NOTE: only one pcm value must be given for every card.
  95  *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
  96  *      By default (0), the PCM bus id is 100 for the card that is PCM master.
  97  *      If multiple cards are PCM master (because they are not interconnected),
  98  *      each card with PCM master will have increasing PCM id.
  99  *      All PCM busses with the same ID are expected to be connected and have
 100  *      common time slots slots.
 101  *      Only one chip of the PCM bus must be master, the others slave.
 102  *      -1 means no support of PCM bus not even.
 103  *      Omit this value, if all cards are interconnected or none is connected.
 104  *      If unsure, don't give this parameter.
 105  *
 106  * dslot:
 107  *      NOTE: only one poll value must be given for every card.
 108  *      Also this value must be given for non-E1 cards. If omitted, the E1
 109  *      card has D-channel on time slot 16, which is default.
 110  *      If 1..15 or 17..31, an alternate time slot is used for D-channel.
 111  *      In this case, the application must be able to handle this.
 112  *      If -1 is given, the D-channel is disabled and all 31 slots can be used
 113  *      for B-channel. (only for specific applications)
 114  *      If you don't know how to use it, you don't need it!
 115  *
 116  * iomode:
 117  *      NOTE: only one mode value must be given for every card.
 118  *      -> See hfc_multi.h for HFC_IO_MODE_* values
 119  *      By default, the IO mode is pci memory IO (MEMIO).
 120  *      Some cards requre specific IO mode, so it cannot be changed.
 121  *      It may be usefull to set IO mode to register io (REGIO) to solve
 122  *      PCI bridge problems.
 123  *      If unsure, don't give this parameter.
 124  *
 125  * clockdelay_nt:
 126  *      NOTE: only one clockdelay_nt value must be given once for all cards.
 127  *      Give the value of the clock control register (A_ST_CLK_DLY)
 128  *      of the S/T interfaces in NT mode.
 129  *      This register is needed for the TBR3 certification, so don't change it.
 130  *
 131  * clockdelay_te:
 132  *      NOTE: only one clockdelay_te value must be given once
 133  *      Give the value of the clock control register (A_ST_CLK_DLY)
 134  *      of the S/T interfaces in TE mode.
 135  *      This register is needed for the TBR3 certification, so don't change it.
 136  */
 137
 138 /*
 139  * debug register access (never use this, it will flood your system log)
 140  * #define HFC_REGISTER_DEBUG
 141  */
 142
 143 #define HFC_MULTI_VERSION       "2.03"
 144
 145 #include <linux/module.h>
 146 #include <linux/pci.h>
 147 #include <linux/delay.h>
 148 #include <linux/mISDNhw.h>
 149 #include <linux/mISDNdsp.h>
 150
 151 /*
 152 #define IRQCOUNT_DEBUG
 153 #define IRQ_DEBUG
 154 */
 155
 156 #include "hfc_multi.h"
 157 #ifdef ECHOPREP
 158 #include "gaintab.h"
 159 #endif
 160
 161 #define MAX_CARDS       8
 162 #define MAX_PORTS       (8 * MAX_CARDS)
 163
 164 static LIST_HEAD(HFClist);
 165 static spinlock_t HFClock; /* global hfc list lock */
 166
 167 static void ph_state_change(struct dchannel *);
 168
 169 static struct hfc_multi *syncmaster;
 170 static int plxsd_master; /* if we have a master card (yet) */
 171 static spinlock_t plx_lock; /* may not acquire other lock inside */
 172
 173 #define TYP_E1          1
 174 #define TYP_4S          4
 175 #define TYP_8S          8
 176
 177 static int poll_timer = 6;      /* default = 128 samples = 16ms */
 178 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
 179 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
 180 #define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
 181 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
 182                                    (0x60 MUST be included!) */
 183
 184 #define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
 185 #define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
 186 #define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */
 187
 188 /*
 189  * module stuff
 190  */
 191
 192 static uint     type[MAX_CARDS];
 193 static uint     pcm[MAX_CARDS];
 194 static uint     dslot[MAX_CARDS];
 195 static uint     iomode[MAX_CARDS];
 196 static uint     port[MAX_PORTS];
 197 static uint     debug;
 198 static uint     poll;
 199 static uint     timer;
 200 static uint     clockdelay_te = CLKDEL_TE;
 201 static uint     clockdelay_nt = CLKDEL_NT;
 202
 203 static int      HFC_cnt, Port_cnt, PCM_cnt = 99;
 204
 205 MODULE_AUTHOR("Andreas Eversberg");
 206 MODULE_LICENSE("GPL");
 207 MODULE_VERSION(HFC_MULTI_VERSION);
 208 module_param(debug, uint, S_IRUGO | S_IWUSR);
 209 module_param(poll, uint, S_IRUGO | S_IWUSR);
 210 module_param(timer, uint, S_IRUGO | S_IWUSR);
 211 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
 212 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
 213 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
 214 module_param_array(pcm, uint, NULL, S_IRUGO | S_IWUSR);
 215 module_param_array(dslot, uint, NULL, S_IRUGO | S_IWUSR);
 216 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
 217 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
 218
 219 #ifdef HFC_REGISTER_DEBUG
 220 #define HFC_outb(hc, reg, val) \
 221         (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
 222 #define HFC_outb_nodebug(hc, reg, val) \
 223         (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
 224 #define HFC_inb(hc, reg) \
 225         (hc->HFC_inb(hc, reg, __func__, __LINE__))
 226 #define HFC_inb_nodebug(hc, reg) \
 227         (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
 228 #define HFC_inw(hc, reg) \
 229         (hc->HFC_inw(hc, reg, __func__, __LINE__))
 230 #define HFC_inw_nodebug(hc, reg) \
 231         (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
 232 #define HFC_wait(hc) \
 233         (hc->HFC_wait(hc, __func__, __LINE__))
 234 #define HFC_wait_nodebug(hc) \
 235         (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
 236 #else
 237 #define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
 238 #define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
 239 #define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
 240 #define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
 241 #define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
 242 #define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
 243 #define HFC_wait(hc)                    (hc->HFC_wait(hc))
 244 #define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
 245 #endif
 246
 247 /* HFC_IO_MODE_PCIMEM */
 248 static void
 249 #ifdef HFC_REGISTER_DEBUG
 250 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
 251                 const char *function, int line)
 252 #else
 253 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
 254 #endif
 255 {
 256         writeb(val, (hc->pci_membase)+reg);
 257 }
 258 static u_char
 259 #ifdef HFC_REGISTER_DEBUG
 260 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 261 #else
 262 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
 263 #endif
 264 {
 265         return readb((hc->pci_membase)+reg);
 266 }
 267 static u_short
 268 #ifdef HFC_REGISTER_DEBUG
 269 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 270 #else
 271 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
 272 #endif
 273 {
 274         return readw((hc->pci_membase)+reg);
 275 }
 276 static void
 277 #ifdef HFC_REGISTER_DEBUG
 278 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
 279 #else
 280 HFC_wait_pcimem(struct hfc_multi *hc)
 281 #endif
 282 {
 283         while (readb((hc->pci_membase)+R_STATUS) & V_BUSY);
 284 }
 285
 286 /* HFC_IO_MODE_REGIO */
 287 static void
 288 #ifdef HFC_REGISTER_DEBUG
 289 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
 290         const char *function, int line)
 291 #else
 292 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
 293 #endif
 294 {
 295         outb(reg, (hc->pci_iobase)+4);
 296         outb(val, hc->pci_iobase);
 297 }
 298 static u_char
 299 #ifdef HFC_REGISTER_DEBUG
 300 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 301 #else
 302 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
 303 #endif
 304 {
 305         outb(reg, (hc->pci_iobase)+4);
 306         return inb(hc->pci_iobase);
 307 }
 308 static u_short
 309 #ifdef HFC_REGISTER_DEBUG
 310 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 311 #else
 312 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
 313 #endif
 314 {
 315         outb(reg, (hc->pci_iobase)+4);
 316         return inw(hc->pci_iobase);
 317 }
 318 static void
 319 #ifdef HFC_REGISTER_DEBUG
 320 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
 321 #else
 322 HFC_wait_regio(struct hfc_multi *hc)
 323 #endif
 324 {
 325         outb(R_STATUS, (hc->pci_iobase)+4);
 326         while (inb(hc->pci_iobase) & V_BUSY);
 327 }
 328
 329 #ifdef HFC_REGISTER_DEBUG
 330 static void
 331 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
 332                 const char *function, int line)
 333 {
 334         char regname[256] = "", bits[9] = "xxxxxxxx";
 335         int i;
 336
 337         i = -1;
 338         while (hfc_register_names[++i].name) {
 339                 if (hfc_register_names[i].reg == reg)
 340                         strcat(regname, hfc_register_names[i].name);
 341         }
 342         if (regname[0] == '\0')
 343                 strcpy(regname, "register");
 344
 345         bits[7] = '0'+(!!(val&1));
 346         bits[6] = '0'+(!!(val&2));
 347         bits[5] = '0'+(!!(val&4));
 348         bits[4] = '0'+(!!(val&8));
 349         bits[3] = '0'+(!!(val&16));
 350         bits[2] = '0'+(!!(val&32));
 351         bits[1] = '0'+(!!(val&64));
 352         bits[0] = '0'+(!!(val&128));
 353         printk(KERN_DEBUG
 354             "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
 355             hc->id, reg, regname, val, bits, function, line);
 356         HFC_outb_nodebug(hc, reg, val);
 357 }
 358 static u_char
 359 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 360 {
 361         char regname[256] = "", bits[9] = "xxxxxxxx";
 362         u_char val = HFC_inb_nodebug(hc, reg);
 363         int i;
 364
 365         i = 0;
 366         while (hfc_register_names[i++].name)
 367                 ;
 368         while (hfc_register_names[++i].name) {
 369                 if (hfc_register_names[i].reg == reg)
 370                         strcat(regname, hfc_register_names[i].name);
 371         }
 372         if (regname[0] == '\0')
 373                 strcpy(regname, "register");
 374
 375         bits[7] = '0'+(!!(val&1));
 376         bits[6] = '0'+(!!(val&2));
 377         bits[5] = '0'+(!!(val&4));
 378         bits[4] = '0'+(!!(val&8));
 379         bits[3] = '0'+(!!(val&16));
 380         bits[2] = '0'+(!!(val&32));
 381         bits[1] = '0'+(!!(val&64));
 382         bits[0] = '0'+(!!(val&128));
 383         printk(KERN_DEBUG
 384             "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
 385             hc->id, reg, regname, val, bits, function, line);
 386         return val;
 387 }
 388 static u_short
 389 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 390 {
 391         char regname[256] = "";
 392         u_short val = HFC_inw_nodebug(hc, reg);
 393         int i;
 394
 395         i = 0;
 396         while (hfc_register_names[i++].name)
 397                 ;
 398         while (hfc_register_names[++i].name) {
 399                 if (hfc_register_names[i].reg == reg)
 400                         strcat(regname, hfc_register_names[i].name);
 401         }
 402         if (regname[0] == '\0')
 403                 strcpy(regname, "register");
 404
 405         printk(KERN_DEBUG
 406             "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
 407             hc->id, reg, regname, val, function, line);
 408         return val;
 409 }
 410 static void
 411 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
 412 {
 413         printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
 414             hc->id, function, line);
 415         HFC_wait_nodebug(hc);
 416 }
 417 #endif
 418
 419 /* write fifo data (REGIO) */
 420 static void
 421 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 422 {
 423         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 424         while (len>>2) {
 425                 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
 426                 data += 4;
 427                 len -= 4;
 428         }
 429         while (len>>1) {
 430                 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
 431                 data += 2;
 432                 len -= 2;
 433         }
 434         while (len) {
 435                 outb(*data, hc->pci_iobase);
 436                 data++;
 437                 len--;
 438         }
 439 }
 440 /* write fifo data (PCIMEM) */
 441 static void
 442 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 443 {
 444         while (len>>2) {
 445                 writel(cpu_to_le32(*(u32 *)data),
 446                         hc->pci_membase + A_FIFO_DATA0);
 447                 data += 4;
 448                 len -= 4;
 449         }
 450         while (len>>1) {
 451                 writew(cpu_to_le16(*(u16 *)data),
 452                         hc->pci_membase + A_FIFO_DATA0);
 453                 data += 2;
 454                 len -= 2;
 455         }
 456         while (len) {
 457                 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
 458                 data++;
 459                 len--;
 460         }
 461 }
 462 /* read fifo data (REGIO) */
 463 static void
 464 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 465 {
 466         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 467         while (len>>2) {
 468                 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
 469                 data += 4;
 470                 len -= 4;
 471         }
 472         while (len>>1) {
 473                 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
 474                 data += 2;
 475                 len -= 2;
 476         }
 477         while (len) {
 478                 *data = inb(hc->pci_iobase);
 479                 data++;
 480                 len--;
 481         }
 482 }
 483
 484 /* read fifo data (PCIMEM) */
 485 static void
 486 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 487 {
 488         while (len>>2) {
 489                 *(u32 *)data =
 490                         le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
 491                 data += 4;
 492                 len -= 4;
 493         }
 494         while (len>>1) {
 495                 *(u16 *)data =
 496                         le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
 497                 data += 2;
 498                 len -= 2;
 499         }
 500         while (len) {
 501                 *data = readb(hc->pci_membase + A_FIFO_DATA0);
 502                 data++;
 503                 len--;
 504         }
 505 }
 506
 507
 508 static void
 509 enable_hwirq(struct hfc_multi *hc)
 510 {
 511         hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
 512         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 513 }
 514
 515 static void
 516 disable_hwirq(struct hfc_multi *hc)
 517 {
 518         hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
 519         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 520 }
 521
 522 #define NUM_EC 2
 523 #define MAX_TDM_CHAN 32
 524
 525
 526 inline void
 527 enablepcibridge(struct hfc_multi *c)
 528 {
 529         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
 530 }
 531
 532 inline void
 533 disablepcibridge(struct hfc_multi *c)
 534 {
 535         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
 536 }
 537
 538 inline unsigned char
 539 readpcibridge(struct hfc_multi *hc, unsigned char address)
 540 {
 541         unsigned short cipv;
 542         unsigned char data;
 543
 544         if (!hc->pci_iobase)
 545                 return 0;
 546
 547         /* slow down a PCI read access by 1 PCI clock cycle */
 548         HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
 549
 550         if (address == 0)
 551                 cipv = 0x4000;
 552         else
 553                 cipv = 0x5800;
 554
 555         /* select local bridge port address by writing to CIP port */
 556         /* data = HFC_inb(c, cipv); * was _io before */
 557         outw(cipv, hc->pci_iobase + 4);
 558         data = inb(hc->pci_iobase);
 559
 560         /* restore R_CTRL for normal PCI read cycle speed */
 561         HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
 562
 563         return data;
 564 }
 565
 566 inline void
 567 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
 568 {
 569         unsigned short cipv;
 570         unsigned int datav;
 571
 572         if (!hc->pci_iobase)
 573                 return;
 574
 575         if (address == 0)
 576                 cipv = 0x4000;
 577         else
 578                 cipv = 0x5800;
 579
 580         /* select local bridge port address by writing to CIP port */
 581         outw(cipv, hc->pci_iobase + 4);
 582         /* define a 32 bit dword with 4 identical bytes for write sequence */
 583         datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
 584             ((__u32) data << 24);
 585
 586         /*
 587          * write this 32 bit dword to the bridge data port
 588          * this will initiate a write sequence of up to 4 writes to the same
 589          * address on the local bus interface the number of write accesses
 590          * is undefined but >=1 and depends on the next PCI transaction
 591          * during write sequence on the local bus
 592          */
 593         outl(datav, hc->pci_iobase);
 594 }
 595
 596 inline void
 597 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
 598 {
 599         /* Do data pin read low byte */
 600         HFC_outb(hc, R_GPIO_OUT1, reg);
 601 }
 602
 603 inline void
 604 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
 605 {
 606         cpld_set_reg(hc, reg);
 607
 608         enablepcibridge(hc);
 609         writepcibridge(hc, 1, val);
 610         disablepcibridge(hc);
 611
 612         return;
 613 }
 614
 615 inline unsigned char
 616 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
 617 {
 618         unsigned char bytein;
 619
 620         cpld_set_reg(hc, reg);
 621
 622         /* Do data pin read low byte */
 623         HFC_outb(hc, R_GPIO_OUT1, reg);
 624
 625         enablepcibridge(hc);
 626         bytein = readpcibridge(hc, 1);
 627         disablepcibridge(hc);
 628
 629         return bytein;
 630 }
 631
 632 inline void
 633 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
 634 {
 635         cpld_write_reg(hc, 0, 0xff & addr);
 636         cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
 637 }
 638
 639 inline unsigned short
 640 vpm_read_address(struct hfc_multi *c)
 641 {
 642         unsigned short addr;
 643         unsigned short highbit;
 644
 645         addr = cpld_read_reg(c, 0);
 646         highbit = cpld_read_reg(c, 1);
 647
 648         addr = addr | (highbit << 8);
 649
 650         return addr & 0x1ff;
 651 }
 652
 653 inline unsigned char
 654 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
 655 {
 656         unsigned char res;
 657
 658         vpm_write_address(c, addr);
 659
 660         if (!which)
 661                 cpld_set_reg(c, 2);
 662         else
 663                 cpld_set_reg(c, 3);
 664
 665         enablepcibridge(c);
 666         res = readpcibridge(c, 1);
 667         disablepcibridge(c);
 668
 669         cpld_set_reg(c, 0);
 670
 671         return res;
 672 }
 673
 674 inline void
 675 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
 676     unsigned char data)
 677 {
 678         vpm_write_address(c, addr);
 679
 680         enablepcibridge(c);
 681
 682         if (!which)
 683                 cpld_set_reg(c, 2);
 684         else
 685                 cpld_set_reg(c, 3);
 686
 687         writepcibridge(c, 1, data);
 688
 689         cpld_set_reg(c, 0);
 690
 691         disablepcibridge(c);
 692
 693         {
 694         unsigned char regin;
 695         regin = vpm_in(c, which, addr);
 696         if (regin != data)
 697                 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
 698                         "0x%x\n", data, addr, regin);
 699         }
 700
 701 }
 702
 703
 704 static void
 705 vpm_init(struct hfc_multi *wc)
 706 {
 707         unsigned char reg;
 708         unsigned int mask;
 709         unsigned int i, x, y;
 710         unsigned int ver;
 711
 712         for (x = 0; x < NUM_EC; x++) {
 713                 /* Setup GPIO's */
 714                 if (!x) {
 715                         ver = vpm_in(wc, x, 0x1a0);
 716                         printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
 717                 }
 718
 719                 for (y = 0; y < 4; y++) {
 720                         vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
 721                         vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
 722                         vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
 723                 }
 724
 725                 /* Setup TDM path - sets fsync and tdm_clk as inputs */
 726                 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
 727                 vpm_out(wc, x, 0x1a3, reg & ~2);
 728
 729                 /* Setup Echo length (256 taps) */
 730                 vpm_out(wc, x, 0x022, 1);
 731                 vpm_out(wc, x, 0x023, 0xff);
 732
 733                 /* Setup timeslots */
 734                 vpm_out(wc, x, 0x02f, 0x00);
 735                 mask = 0x02020202 << (x * 4);
 736
 737                 /* Setup the tdm channel masks for all chips */
 738                 for (i = 0; i < 4; i++)
 739                         vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
 740
 741                 /* Setup convergence rate */
 742                 printk(KERN_DEBUG "VPM: A-law mode\n");
 743                 reg = 0x00 | 0x10 | 0x01;
 744                 vpm_out(wc, x, 0x20, reg);
 745                 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
 746                 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
 747
 748                 vpm_out(wc, x, 0x24, 0x02);
 749                 reg = vpm_in(wc, x, 0x24);
 750                 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
 751
 752                 /* Initialize echo cans */
 753                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 754                         if (mask & (0x00000001 << i))
 755                                 vpm_out(wc, x, i, 0x00);
 756                 }
 757
 758                 /*
 759                  * ARM arch at least disallows a udelay of
 760                  * more than 2ms... it gives a fake "__bad_udelay"
 761                  * reference at link-time.
 762                  * long delays in kernel code are pretty sucky anyway
 763                  * for now work around it using 5 x 2ms instead of 1 x 10ms
 764                  */
 765
 766                 udelay(2000);
 767                 udelay(2000);
 768                 udelay(2000);
 769                 udelay(2000);
 770                 udelay(2000);
 771
 772                 /* Put in bypass mode */
 773                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 774                         if (mask & (0x00000001 << i))
 775                                 vpm_out(wc, x, i, 0x01);
 776                 }
 777
 778                 /* Enable bypass */
 779                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 780                         if (mask & (0x00000001 << i))
 781                                 vpm_out(wc, x, 0x78 + i, 0x01);
 782                 }
 783
 784         }
 785 }
 786
 787 #ifdef UNUSED
 788 static void
 789 vpm_check(struct hfc_multi *hctmp)
 790 {
 791         unsigned char gpi2;
 792
 793         gpi2 = HFC_inb(hctmp, R_GPI_IN2);
 794
 795         if ((gpi2 & 0x3) != 0x3)
 796                 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
 797 }
 798 #endif /* UNUSED */
 799
 800
 801 /*
 802  * Interface to enable/disable the HW Echocan
 803  *
 804  * these functions are called within a spin_lock_irqsave on
 805  * the channel instance lock, so we are not disturbed by irqs
 806  *
 807  * we can later easily change the interface to make  other
 808  * things configurable, for now we configure the taps
 809  *
 810  */
 811
 812 static void
 813 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
 814 {
 815         unsigned int timeslot;
 816         unsigned int unit;
 817         struct bchannel *bch = hc->chan[ch].bch;
 818 #ifdef TXADJ
 819         int txadj = -4;
 820         struct sk_buff *skb;
 821 #endif
 822         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 823                 return;
 824
 825         if (!bch)
 826                 return;
 827
 828 #ifdef TXADJ
 829         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 830                 sizeof(int), &txadj, GFP_ATOMIC);
 831         if (skb)
 832                 recv_Bchannel_skb(bch, skb);
 833 #endif
 834
 835         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 836         unit = ch % 4;
 837
 838         printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
 839             taps, timeslot);
 840
 841         vpm_out(hc, unit, timeslot, 0x7e);
 842 }
 843
 844 static void
 845 vpm_echocan_off(struct hfc_multi *hc, int ch)
 846 {
 847         unsigned int timeslot;
 848         unsigned int unit;
 849         struct bchannel *bch = hc->chan[ch].bch;
 850 #ifdef TXADJ
 851         int txadj = 0;
 852         struct sk_buff *skb;
 853 #endif
 854
 855         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 856                 return;
 857
 858         if (!bch)
 859                 return;
 860
 861 #ifdef TXADJ
 862         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 863                 sizeof(int), &txadj, GFP_ATOMIC);
 864         if (skb)
 865                 recv_Bchannel_skb(bch, skb);
 866 #endif
 867
 868         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 869         unit = ch % 4;
 870
 871         printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
 872             timeslot);
 873         /* FILLME */
 874         vpm_out(hc, unit, timeslot, 0x01);
 875 }
 876
 877
 878 /*
 879  * Speech Design resync feature
 880  * NOTE: This is called sometimes outside interrupt handler.
 881  * We must lock irqsave, so no other interrupt (other card) will occurr!
 882  * Also multiple interrupts may nest, so must lock each access (lists, card)!
 883  */
 884 static inline void
 885 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
 886 {
 887         struct hfc_multi *hc, *next, *pcmmaster = NULL;
 888         void __iomem *plx_acc_32;
 889         u_int pv;
 890         u_long flags;
 891
 892         spin_lock_irqsave(&HFClock, flags);
 893         spin_lock(&plx_lock); /* must be locked inside other locks */
 894
 895         if (debug & DEBUG_HFCMULTI_PLXSD)
 896                 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
 897                         __func__, syncmaster);
 898
 899         /* select new master */
 900         if (newmaster) {
 901                 if (debug & DEBUG_HFCMULTI_PLXSD)
 902                         printk(KERN_DEBUG "using provided controller\n");
 903         } else {
 904                 list_for_each_entry_safe(hc, next, &HFClist, list) {
 905                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 906                                 if (hc->syncronized) {
 907                                         newmaster = hc;
 908                                         break;
 909                                 }
 910                         }
 911                 }
 912         }
 913
 914         /* Disable sync of all cards */
 915         list_for_each_entry_safe(hc, next, &HFClist, list) {
 916                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 917                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 918                         pv = readl(plx_acc_32);
 919                         pv &= ~PLX_SYNC_O_EN;
 920                         writel(pv, plx_acc_32);
 921                         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
 922                                 pcmmaster = hc;
 923                                 if (hc->type == 1) {
 924                                         if (debug & DEBUG_HFCMULTI_PLXSD)
 925                                                 printk(KERN_DEBUG
 926                                                         "Schedule SYNC_I\n");
 927                                         hc->e1_resync |= 1; /* get SYNC_I */
 928                                 }
 929                         }
 930                 }
 931         }
 932
 933         if (newmaster) {
 934                 hc = newmaster;
 935                 if (debug & DEBUG_HFCMULTI_PLXSD)
 936                         printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
 937                                 "interface.\n", hc->id, hc);
 938                 /* Enable new sync master */
 939                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 940                 pv = readl(plx_acc_32);
 941                 pv |= PLX_SYNC_O_EN;
 942                 writel(pv, plx_acc_32);
 943                 /* switch to jatt PLL, if not disabled by RX_SYNC */
 944                 if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
 945                         if (debug & DEBUG_HFCMULTI_PLXSD)
 946                                 printk(KERN_DEBUG "Schedule jatt PLL\n");
 947                         hc->e1_resync |= 2; /* switch to jatt */
 948                 }
 949         } else {
 950                 if (pcmmaster) {
 951                         hc = pcmmaster;
 952                         if (debug & DEBUG_HFCMULTI_PLXSD)
 953                                 printk(KERN_DEBUG
 954                                         "id=%d (0x%p) = PCM master syncronized "
 955                                         "with QUARTZ\n", hc->id, hc);
 956                         if (hc->type == 1) {
 957                                 /* Use the crystal clock for the PCM
 958                                    master card */
 959                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 960                                         printk(KERN_DEBUG
 961                                             "Schedule QUARTZ for HFC-E1\n");
 962                                 hc->e1_resync |= 4; /* switch quartz */
 963                         } else {
 964                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 965                                         printk(KERN_DEBUG
 966                                             "QUARTZ is automatically "
 967                                             "enabled by HFC-%dS\n", hc->type);
 968                         }
 969                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 970                         pv = readl(plx_acc_32);
 971                         pv |= PLX_SYNC_O_EN;
 972                         writel(pv, plx_acc_32);
 973                 } else
 974                         if (!rm)
 975                                 printk(KERN_ERR "%s no pcm master, this MUST "
 976                                         "not happen!\n", __func__);
 977         }
 978         syncmaster = newmaster;
 979
 980         spin_unlock(&plx_lock);
 981         spin_unlock_irqrestore(&HFClock, flags);
 982 }
 983
 984 /* This must be called AND hc must be locked irqsave!!! */
 985 inline void
 986 plxsd_checksync(struct hfc_multi *hc, int rm)
 987 {
 988         if (hc->syncronized) {
 989                 if (syncmaster == NULL) {
 990                         if (debug & DEBUG_HFCMULTI_PLXSD)
 991                                 printk(KERN_WARNING "%s: GOT sync on card %d"
 992                                         " (id=%d)\n", __func__, hc->id + 1,
 993                                         hc->id);
 994                         hfcmulti_resync(hc, hc, rm);
 995                 }
 996         } else {
 997                 if (syncmaster == hc) {
 998                         if (debug & DEBUG_HFCMULTI_PLXSD)
 999                                 printk(KERN_WARNING "%s: LOST sync on card %d"
1000                                         " (id=%d)\n", __func__, hc->id + 1,
1001                                         hc->id);
1002                         hfcmulti_resync(hc, NULL, rm);
1003                 }
1004         }
1005 }
1006
1007
1008 /*
1009  * free hardware resources used by driver
1010  */
1011 static void
1012 release_io_hfcmulti(struct hfc_multi *hc)
1013 {
1014         void __iomem *plx_acc_32;
1015         u_int   pv;
1016         u_long  plx_flags;
1017
1018         if (debug & DEBUG_HFCMULTI_INIT)
1019                 printk(KERN_DEBUG "%s: entered\n", __func__);
1020
1021         /* soft reset also masks all interrupts */
1022         hc->hw.r_cirm |= V_SRES;
1023         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1024         udelay(1000);
1025         hc->hw.r_cirm &= ~V_SRES;
1026         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1027         udelay(1000); /* instead of 'wait' that may cause locking */
1028
1029         /* release Speech Design card, if PLX was initialized */
1030         if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1031                 if (debug & DEBUG_HFCMULTI_PLXSD)
1032                         printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1033                             __func__, hc->id + 1);
1034                 spin_lock_irqsave(&plx_lock, plx_flags);
1035                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1036                 writel(PLX_GPIOC_INIT, plx_acc_32);
1037                 pv = readl(plx_acc_32);
1038                 /* Termination off */
1039                 pv &= ~PLX_TERM_ON;
1040                 /* Disconnect the PCM */
1041                 pv |= PLX_SLAVE_EN_N;
1042                 pv &= ~PLX_MASTER_EN;
1043                 pv &= ~PLX_SYNC_O_EN;
1044                 /* Put the DSP in Reset */
1045                 pv &= ~PLX_DSP_RES_N;
1046                 writel(pv, plx_acc_32);
1047                 if (debug & DEBUG_HFCMULTI_INIT)
1048                         printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n",
1049                                 __func__, pv);
1050                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1051         }
1052
1053         /* disable memory mapped ports / io ports */
1054         test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1055         pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1056         if (hc->pci_membase)
1057                 iounmap(hc->pci_membase);
1058         if (hc->plx_membase)
1059                 iounmap(hc->plx_membase);
1060         if (hc->pci_iobase)
1061                 release_region(hc->pci_iobase, 8);
1062
1063         if (hc->pci_dev) {
1064                 pci_disable_device(hc->pci_dev);
1065                 pci_set_drvdata(hc->pci_dev, NULL);
1066         }
1067         if (debug & DEBUG_HFCMULTI_INIT)
1068                 printk(KERN_DEBUG "%s: done\n", __func__);
1069 }
1070
1071 /*
1072  * function called to reset the HFC chip. A complete software reset of chip
1073  * and fifos is done. All configuration of the chip is done.
1074  */
1075
1076 static int
1077 init_chip(struct hfc_multi *hc)
1078 {
1079         u_long                  flags, val, val2 = 0, rev;
1080         int                     i, err = 0;
1081         u_char                  r_conf_en, rval;
1082         void __iomem            *plx_acc_32;
1083         u_int                   pv;
1084         u_long                  plx_flags, hfc_flags;
1085         int                     plx_count;
1086         struct hfc_multi        *pos, *next, *plx_last_hc;
1087
1088         spin_lock_irqsave(&hc->lock, flags);
1089         /* reset all registers */
1090         memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1091
1092         /* revision check */
1093         if (debug & DEBUG_HFCMULTI_INIT)
1094                 printk(KERN_DEBUG "%s: entered\n", __func__);
1095         val = HFC_inb(hc, R_CHIP_ID)>>4;
1096         if (val != 0x8 && val != 0xc && val != 0xe) {
1097                 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1098                 err = -EIO;
1099                 goto out;
1100         }
1101         rev = HFC_inb(hc, R_CHIP_RV);
1102         printk(KERN_INFO
1103             "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1104             val, rev, (rev == 0) ? " (old FIFO handling)" : "");
1105         if (rev == 0) {
1106                 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1107                 printk(KERN_WARNING
1108                     "HFC_multi: NOTE: Your chip is revision 0, "
1109                     "ask Cologne Chip for update. Newer chips "
1110                     "have a better FIFO handling. Old chips "
1111                     "still work but may have slightly lower "
1112                     "HDLC transmit performance.\n");
1113         }
1114         if (rev > 1) {
1115                 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1116                     "consider chip revision = %ld. The chip / "
1117                     "bridge may not work.\n", rev);
1118         }
1119
1120         /* set s-ram size */
1121         hc->Flen = 0x10;
1122         hc->Zmin = 0x80;
1123         hc->Zlen = 384;
1124         hc->DTMFbase = 0x1000;
1125         if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1126                 if (debug & DEBUG_HFCMULTI_INIT)
1127                         printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1128                             __func__);
1129                 hc->hw.r_ctrl |= V_EXT_RAM;
1130                 hc->hw.r_ram_sz = 1;
1131                 hc->Flen = 0x20;
1132                 hc->Zmin = 0xc0;
1133                 hc->Zlen = 1856;
1134                 hc->DTMFbase = 0x2000;
1135         }
1136         if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1137                 if (debug & DEBUG_HFCMULTI_INIT)
1138                         printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1139                             __func__);
1140                 hc->hw.r_ctrl |= V_EXT_RAM;
1141                 hc->hw.r_ram_sz = 2;
1142                 hc->Flen = 0x20;
1143                 hc->Zmin = 0xc0;
1144                 hc->Zlen = 8000;
1145                 hc->DTMFbase = 0x2000;
1146         }
1147         hc->max_trans = poll << 1;
1148         if (hc->max_trans > hc->Zlen)
1149                 hc->max_trans = hc->Zlen;
1150
1151         /* Speech Design PLX bridge */
1152         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1153                 if (debug & DEBUG_HFCMULTI_PLXSD)
1154                         printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1155                             __func__, hc->id + 1);
1156                 spin_lock_irqsave(&plx_lock, plx_flags);
1157                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1158                 writel(PLX_GPIOC_INIT, plx_acc_32);
1159                 pv = readl(plx_acc_32);
1160                 /* The first and the last cards are terminating the PCM bus */
1161                 pv |= PLX_TERM_ON; /* hc is currently the last */
1162                 /* Disconnect the PCM */
1163                 pv |= PLX_SLAVE_EN_N;
1164                 pv &= ~PLX_MASTER_EN;
1165                 pv &= ~PLX_SYNC_O_EN;
1166                 /* Put the DSP in Reset */
1167                 pv &= ~PLX_DSP_RES_N;
1168                 writel(pv, plx_acc_32);
1169                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1170                 if (debug & DEBUG_HFCMULTI_INIT)
1171                         printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n",
1172                                 __func__, pv);
1173                 /*
1174                  * If we are the 3rd PLXSD card or higher, we must turn
1175                  * termination of last PLXSD card off.
1176                  */
1177                 spin_lock_irqsave(&HFClock, hfc_flags);
1178                 plx_count = 0;
1179                 plx_last_hc = NULL;
1180                 list_for_each_entry_safe(pos, next, &HFClist, list) {
1181                         if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1182                                 plx_count++;
1183                                 if (pos != hc)
1184                                         plx_last_hc = pos;
1185                         }
1186                 }
1187                 if (plx_count >= 3) {
1188                         if (debug & DEBUG_HFCMULTI_PLXSD)
1189                                 printk(KERN_DEBUG "%s: card %d is between, so "
1190                                         "we disable termination\n",
1191                                     __func__, plx_last_hc->id + 1);
1192                         spin_lock_irqsave(&plx_lock, plx_flags);
1193                         plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1194                         pv = readl(plx_acc_32);
1195                         pv &= ~PLX_TERM_ON;
1196                         writel(pv, plx_acc_32);
1197                         spin_unlock_irqrestore(&plx_lock, plx_flags);
1198                         if (debug & DEBUG_HFCMULTI_INIT)
1199                             printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n",
1200                                         __func__, pv);
1201                 }
1202                 spin_unlock_irqrestore(&HFClock, hfc_flags);
1203                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1204         }
1205
1206         /* we only want the real Z2 read-pointer for revision > 0 */
1207         if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1208                 hc->hw.r_ram_sz |= V_FZ_MD;
1209
1210         /* select pcm mode */
1211         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1212                 if (debug & DEBUG_HFCMULTI_INIT)
1213                         printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1214                             __func__);
1215         } else
1216         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1217                 if (debug & DEBUG_HFCMULTI_INIT)
1218                         printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1219                             __func__);
1220                 hc->hw.r_pcm_md0 |= V_PCM_MD;
1221         } else {
1222                 if (debug & DEBUG_HFCMULTI_INIT)
1223                         printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1224                             __func__);
1225         }
1226
1227         /* soft reset */
1228         HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1229         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1230         HFC_outb(hc, R_FIFO_MD, 0);
1231         hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
1232         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1233         udelay(100);
1234         hc->hw.r_cirm = 0;
1235         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1236         udelay(100);
1237         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1238
1239         /* Speech Design PLX bridge pcm and sync mode */
1240         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1241                 spin_lock_irqsave(&plx_lock, plx_flags);
1242                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1243                 pv = readl(plx_acc_32);
1244                 /* Connect PCM */
1245                 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1246                         pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1247                         pv |= PLX_SYNC_O_EN;
1248                         if (debug & DEBUG_HFCMULTI_INIT)
1249                                 printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n",
1250                                         __func__, pv);
1251                 } else {
1252                         pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1253                         pv &= ~PLX_SYNC_O_EN;
1254                         if (debug & DEBUG_HFCMULTI_INIT)
1255                                 printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n",
1256                                         __func__, pv);
1257                 }
1258                 writel(pv, plx_acc_32);
1259                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1260         }
1261
1262         /* PCM setup */
1263         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1264         if (hc->slots == 32)
1265                 HFC_outb(hc, R_PCM_MD1, 0x00);
1266         if (hc->slots == 64)
1267                 HFC_outb(hc, R_PCM_MD1, 0x10);
1268         if (hc->slots == 128)
1269                 HFC_outb(hc, R_PCM_MD1, 0x20);
1270         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1271         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1272                 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1273         else
1274                 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1275         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1276         for (i = 0; i < 256; i++) {
1277                 HFC_outb_nodebug(hc, R_SLOT, i);
1278                 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1279                 HFC_outb_nodebug(hc, A_CONF, 0);
1280                 hc->slot_owner[i] = -1;
1281         }
1282
1283         /* set clock speed */
1284         if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1285                 if (debug & DEBUG_HFCMULTI_INIT)
1286                         printk(KERN_DEBUG
1287                             "%s: setting double clock\n", __func__);
1288                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1289         }
1290
1291         /* B410P GPIO */
1292         if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1293                 printk(KERN_NOTICE "Setting GPIOs\n");
1294                 HFC_outb(hc, R_GPIO_SEL, 0x30);
1295                 HFC_outb(hc, R_GPIO_EN1, 0x3);
1296                 udelay(1000);
1297                 printk(KERN_NOTICE "calling vpm_init\n");
1298                 vpm_init(hc);
1299         }
1300
1301         /* check if R_F0_CNT counts (8 kHz frame count) */
1302         val = HFC_inb(hc, R_F0_CNTL);
1303         val += HFC_inb(hc, R_F0_CNTH) << 8;
1304         if (debug & DEBUG_HFCMULTI_INIT)
1305                 printk(KERN_DEBUG
1306                     "HFC_multi F0_CNT %ld after reset\n", val);
1307         spin_unlock_irqrestore(&hc->lock, flags);
1308         set_current_state(TASK_UNINTERRUPTIBLE);
1309         schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1310         spin_lock_irqsave(&hc->lock, flags);
1311         val2 = HFC_inb(hc, R_F0_CNTL);
1312         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1313         if (debug & DEBUG_HFCMULTI_INIT)
1314                 printk(KERN_DEBUG
1315                         "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1316                     val2);
1317         if (val2 >= val+8) { /* 1 ms */
1318                 /* it counts, so we keep the pcm mode */
1319                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1320                         printk(KERN_INFO "controller is PCM bus MASTER\n");
1321                 else
1322                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1323                         printk(KERN_INFO "controller is PCM bus SLAVE\n");
1324                 else {
1325                         test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1326                         printk(KERN_INFO "controller is PCM bus SLAVE "
1327                                 "(auto detected)\n");
1328                 }
1329         } else {
1330                 /* does not count */
1331                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1332 controller_fail:
1333                         printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1334                             "pulse. Seems that controller fails.\n");
1335                         err = -EIO;
1336                         goto out;
1337                 }
1338                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1339                         printk(KERN_INFO "controller is PCM bus SLAVE "
1340                                 "(ignoring missing PCM clock)\n");
1341                 } else {
1342                         /* only one pcm master */
1343                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1344                                 && plxsd_master) {
1345                                 printk(KERN_ERR "HFC_multi ERROR, no clock "
1346                                     "on another Speech Design card found. "
1347                                     "Please be sure to connect PCM cable.\n");
1348                                 err = -EIO;
1349                                 goto out;
1350                         }
1351                         /* retry with master clock */
1352                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1353                                 spin_lock_irqsave(&plx_lock, plx_flags);
1354                                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1355                                 pv = readl(plx_acc_32);
1356                                 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1357                                 pv |= PLX_SYNC_O_EN;
1358                                 writel(pv, plx_acc_32);
1359                                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1360                                 if (debug & DEBUG_HFCMULTI_INIT)
1361                                     printk(KERN_WARNING "%s: master: PLX_GPIO"
1362                                         "=%x\n", __func__, pv);
1363                         }
1364                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1365                         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1366                         spin_unlock_irqrestore(&hc->lock, flags);
1367                         set_current_state(TASK_UNINTERRUPTIBLE);
1368                         schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1369                         spin_lock_irqsave(&hc->lock, flags);
1370                         val2 = HFC_inb(hc, R_F0_CNTL);
1371                         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1372                         if (debug & DEBUG_HFCMULTI_INIT)
1373                                 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1374                                         "10 ms (2nd try)\n", val2);
1375                         if (val2 >= val+8) { /* 1 ms */
1376                                 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1377                                         &hc->chip);
1378                                 printk(KERN_INFO "controller is PCM bus MASTER "
1379                                         "(auto detected)\n");
1380                         } else
1381                                 goto controller_fail;
1382                 }
1383         }
1384
1385         /* Release the DSP Reset */
1386         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1387                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1388                         plxsd_master = 1;
1389                 spin_lock_irqsave(&plx_lock, plx_flags);
1390                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1391                 pv = readl(plx_acc_32);
1392                 pv |=  PLX_DSP_RES_N;
1393                 writel(pv, plx_acc_32);
1394                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1395                 if (debug & DEBUG_HFCMULTI_INIT)
1396                         printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n",
1397                                 __func__, pv);
1398         }
1399
1400         /* pcm id */
1401         if (hc->pcm)
1402                 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1403                         hc->pcm);
1404         else {
1405                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1406                  || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1407                         PCM_cnt++; /* SD has proprietary bridging */
1408                 }
1409                 hc->pcm = PCM_cnt;
1410                 printk(KERN_INFO "controller has PCM BUS ID %d "
1411                         "(auto selected)\n", hc->pcm);
1412         }
1413
1414         /* set up timer */
1415         HFC_outb(hc, R_TI_WD, poll_timer);
1416         hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1417
1418         /* set E1 state machine IRQ */
1419         if (hc->type == 1)
1420                 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1421
1422         /* set DTMF detection */
1423         if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1424                 if (debug & DEBUG_HFCMULTI_INIT)
1425                         printk(KERN_DEBUG "%s: enabling DTMF detection "
1426                             "for all B-channel\n", __func__);
1427                 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1428                 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1429                         hc->hw.r_dtmf |= V_ULAW_SEL;
1430                 HFC_outb(hc, R_DTMF_N, 102 - 1);
1431                 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1432         }
1433
1434         /* conference engine */
1435         if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1436                 r_conf_en = V_CONF_EN | V_ULAW;
1437         else
1438                 r_conf_en = V_CONF_EN;
1439         HFC_outb(hc, R_CONF_EN, r_conf_en);
1440
1441         /* setting leds */
1442         switch (hc->leds) {
1443         case 1: /* HFC-E1 OEM */
1444                 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1445                         HFC_outb(hc, R_GPIO_SEL, 0x32);
1446                 else
1447                         HFC_outb(hc, R_GPIO_SEL, 0x30);
1448
1449                 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1450                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1451
1452                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1453                 break;
1454
1455         case 2: /* HFC-4S OEM */
1456         case 3:
1457                 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1458                 HFC_outb(hc, R_GPIO_EN1, 0xff);
1459                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1460                 break;
1461         }
1462
1463         /* set master clock */
1464         if (hc->masterclk >= 0) {
1465                 if (debug & DEBUG_HFCMULTI_INIT)
1466                         printk(KERN_DEBUG "%s: setting ST master clock "
1467                             "to port %d (0..%d)\n",
1468                             __func__, hc->masterclk, hc->ports-1);
1469                 hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
1470                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1471         }
1472
1473         /* setting misc irq */
1474         HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1475         if (debug & DEBUG_HFCMULTI_INIT)
1476                 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1477                     hc->hw.r_irqmsk_misc);
1478
1479         /* RAM access test */
1480         HFC_outb(hc, R_RAM_ADDR0, 0);
1481         HFC_outb(hc, R_RAM_ADDR1, 0);
1482         HFC_outb(hc, R_RAM_ADDR2, 0);
1483         for (i = 0; i < 256; i++) {
1484                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1485                 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1486         }
1487         for (i = 0; i < 256; i++) {
1488                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1489                 HFC_inb_nodebug(hc, R_RAM_DATA);
1490                 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1491                 if (rval != ((i * 3) & 0xff)) {
1492                         printk(KERN_DEBUG
1493                             "addr:%x val:%x should:%x\n", i, rval,
1494                             (i * 3) & 0xff);
1495                         err++;
1496                 }
1497         }
1498         if (err) {
1499                 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1500                 err = -EIO;
1501                 goto out;
1502         }
1503
1504         if (debug & DEBUG_HFCMULTI_INIT)
1505                 printk(KERN_DEBUG "%s: done\n", __func__);
1506 out:
1507         spin_unlock_irqrestore(&hc->lock, flags);
1508         return err;
1509 }
1510
1511
1512 /*
1513  * control the watchdog
1514  */
1515 static void
1516 hfcmulti_watchdog(struct hfc_multi *hc)
1517 {
1518         hc->wdcount++;
1519
1520         if (hc->wdcount > 10) {
1521                 hc->wdcount = 0;
1522                 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1523                     V_GPIO_OUT3 : V_GPIO_OUT2;
1524
1525         /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1526                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1527                 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1528         }
1529 }
1530
1531
1532
1533 /*
1534  * output leds
1535  */
1536 static void
1537 hfcmulti_leds(struct hfc_multi *hc)
1538 {
1539         unsigned long lled;
1540         unsigned long leddw;
1541         int i, state, active, leds;
1542         struct dchannel *dch;
1543         int led[4];
1544
1545         hc->ledcount += poll;
1546         if (hc->ledcount > 4096) {
1547                 hc->ledcount -= 4096;
1548                 hc->ledstate = 0xAFFEAFFE;
1549         }
1550
1551         switch (hc->leds) {
1552         case 1: /* HFC-E1 OEM */
1553                 /* 2 red blinking: NT mode deactivate
1554                  * 2 red steady:   TE mode deactivate
1555                  * left green:     L1 active
1556                  * left red:       frame sync, but no L1
1557                  * right green:    L2 active
1558                  */
1559                 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1560                         if (hc->chan[hc->dslot].dch->dev.D.protocol
1561                                 != ISDN_P_NT_E1) {
1562                                 led[0] = 1;
1563                                 led[1] = 1;
1564                         } else if (hc->ledcount>>11) {
1565                                 led[0] = 1;
1566                                 led[1] = 1;
1567                         } else {
1568                                 led[0] = 0;
1569                                 led[1] = 0;
1570                         }
1571                         led[2] = 0;
1572                         led[3] = 0;
1573                 } else { /* with frame sync */
1574                         /* TODO make it work */
1575                         led[0] = 0;
1576                         led[1] = 0;
1577                         led[2] = 0;
1578                         led[3] = 1;
1579                 }
1580                 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1581                         /* leds are inverted */
1582                 if (leds != (int)hc->ledstate) {
1583                         HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1584                         hc->ledstate = leds;
1585                 }
1586                 break;
1587
1588         case 2: /* HFC-4S OEM */
1589                 /* red blinking = PH_DEACTIVATE NT Mode
1590                  * red steady   = PH_DEACTIVATE TE Mode
1591                  * green steady = PH_ACTIVATE
1592                  */
1593                 for (i = 0; i < 4; i++) {
1594                         state = 0;
1595                         active = -1;
1596                         dch = hc->chan[(i << 2) | 2].dch;
1597                         if (dch) {
1598                                 state = dch->state;
1599                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1600                                         active = 3;
1601                                 else
1602                                         active = 7;
1603                         }
1604                         if (state) {
1605                                 if (state == active) {
1606                                         led[i] = 1; /* led green */
1607                                 } else
1608                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1609                                                 /* TE mode: led red */
1610                                                 led[i] = 2;
1611                                         else
1612                                                 if (hc->ledcount>>11)
1613                                                         /* led red */
1614                                                         led[i] = 2;
1615                                                 else
1616                                                         /* led off */
1617                                                         led[i] = 0;
1618                         } else
1619                                 led[i] = 0; /* led off */
1620                 }
1621                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1622                         leds = 0;
1623                         for (i = 0; i < 4; i++) {
1624                                 if (led[i] == 1) {
1625                                         /*green*/
1626                                         leds |= (0x2 << (i * 2));
1627                                 } else if (led[i] == 2) {
1628                                         /*red*/
1629                                         leds |= (0x1 << (i * 2));
1630                                 }
1631                         }
1632                         if (leds != (int)hc->ledstate) {
1633                                 vpm_out(hc, 0, 0x1a8 + 3, leds);
1634                                 hc->ledstate = leds;
1635                         }
1636                 } else {
1637                         leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1638                             ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1639                             ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1640                             ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1641                         if (leds != (int)hc->ledstate) {
1642                                 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1643                                 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1644                                 hc->ledstate = leds;
1645                         }
1646                 }
1647                 break;
1648
1649         case 3: /* HFC 1S/2S Beronet */
1650                 /* red blinking = PH_DEACTIVATE NT Mode
1651                  * red steady   = PH_DEACTIVATE TE Mode
1652                  * green steady = PH_ACTIVATE
1653                  */
1654                 for (i = 0; i < 2; i++) {
1655                         state = 0;
1656                         active = -1;
1657                         dch = hc->chan[(i << 2) | 2].dch;
1658                         if (dch) {
1659                                 state = dch->state;
1660                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1661                                         active = 3;
1662                                 else
1663                                         active = 7;
1664                         }
1665                         if (state) {
1666                                 if (state == active) {
1667                                         led[i] = 1; /* led green */
1668                                 } else
1669                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1670                                                 /* TE mode: led red */
1671                                                 led[i] = 2;
1672                                         else
1673                                                 if (hc->ledcount >> 11)
1674                                                         /* led red */
1675                                                         led[i] = 2;
1676                                                 else
1677                                                         /* led off */
1678                                                         led[i] = 0;
1679                         } else
1680                                 led[i] = 0; /* led off */
1681                 }
1682
1683
1684                 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1685                         | ((led[1]&1)<<3);
1686                 if (leds != (int)hc->ledstate) {
1687                         HFC_outb_nodebug(hc, R_GPIO_EN1,
1688                             ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1689                         HFC_outb_nodebug(hc, R_GPIO_OUT1,
1690                             ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1691                         hc->ledstate = leds;
1692                 }
1693                 break;
1694         case 8: /* HFC 8S+ Beronet */
1695                 lled = 0;
1696
1697                 for (i = 0; i < 8; i++) {
1698                         state = 0;
1699                         active = -1;
1700                         dch = hc->chan[(i << 2) | 2].dch;
1701                         if (dch) {
1702                                 state = dch->state;
1703                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1704                                         active = 3;
1705                                 else
1706                                         active = 7;
1707                         }
1708                         if (state) {
1709                                 if (state == active) {
1710                                         lled |= 0 << i;
1711                                 } else
1712                                         if (hc->ledcount >> 11)
1713                                                 lled |= 0 << i;
1714                                         else
1715                                                 lled |= 1 << i;
1716                         } else
1717                                 lled |= 1 << i;
1718                 }
1719                 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1720                 if (leddw != hc->ledstate) {
1721                         /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1722                         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1723                         /* was _io before */
1724                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1725                         outw(0x4000, hc->pci_iobase + 4);
1726                         outl(leddw, hc->pci_iobase);
1727                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1728                         hc->ledstate = leddw;
1729                 }
1730                 break;
1731         }
1732 }
1733 /*
1734  * read dtmf coefficients
1735  */
1736
1737 static void
1738 hfcmulti_dtmf(struct hfc_multi *hc)
1739 {
1740         s32             *coeff;
1741         u_int           mantissa;
1742         int             co, ch;
1743         struct bchannel *bch = NULL;
1744         u8              exponent;
1745         int             dtmf = 0;
1746         int             addr;
1747         u16             w_float;
1748         struct sk_buff  *skb;
1749         struct mISDNhead *hh;
1750
1751         if (debug & DEBUG_HFCMULTI_DTMF)
1752                 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1753         for (ch = 0; ch <= 31; ch++) {
1754                 /* only process enabled B-channels */
1755                 bch = hc->chan[ch].bch;
1756                 if (!bch)
1757                         continue;
1758                 if (!hc->created[hc->chan[ch].port])
1759                         continue;
1760                 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1761                         continue;
1762                 if (debug & DEBUG_HFCMULTI_DTMF)
1763                         printk(KERN_DEBUG "%s: dtmf channel %d:",
1764                                 __func__, ch);
1765                 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1766                 dtmf = 1;
1767                 for (co = 0; co < 8; co++) {
1768                         /* read W(n-1) coefficient */
1769                         addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1770                         HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1771                         HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1772                         HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1773                                 | V_ADDR_INC);
1774                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1775                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1776                         if (debug & DEBUG_HFCMULTI_DTMF)
1777                                 printk(" %04x", w_float);
1778
1779                         /* decode float (see chip doc) */
1780                         mantissa = w_float & 0x0fff;
1781                         if (w_float & 0x8000)
1782                                 mantissa |= 0xfffff000;
1783                         exponent = (w_float>>12) & 0x7;
1784                         if (exponent) {
1785                                 mantissa ^= 0x1000;
1786                                 mantissa <<= (exponent-1);
1787                         }
1788
1789                         /* store coefficient */
1790                         coeff[co<<1] = mantissa;
1791
1792                         /* read W(n) coefficient */
1793                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1794                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1795                         if (debug & DEBUG_HFCMULTI_DTMF)
1796                                 printk(" %04x", w_float);
1797
1798                         /* decode float (see chip doc) */
1799                         mantissa = w_float & 0x0fff;
1800                         if (w_float & 0x8000)
1801                                 mantissa |= 0xfffff000;
1802                         exponent = (w_float>>12) & 0x7;
1803                         if (exponent) {
1804                                 mantissa ^= 0x1000;
1805                                 mantissa <<= (exponent-1);
1806                         }
1807
1808                         /* store coefficient */
1809                         coeff[(co<<1)|1] = mantissa;
1810                 }
1811                 if (debug & DEBUG_HFCMULTI_DTMF)
1812                         printk("%s: DTMF ready %08x %08x %08x %08x "
1813                             "%08x %08x %08x %08x\n", __func__,
1814                             coeff[0], coeff[1], coeff[2], coeff[3],
1815                             coeff[4], coeff[5], coeff[6], coeff[7]);
1816                 hc->chan[ch].coeff_count++;
1817                 if (hc->chan[ch].coeff_count == 8) {
1818                         hc->chan[ch].coeff_count = 0;
1819                         skb = mI_alloc_skb(512, GFP_ATOMIC);
1820                         if (!skb) {
1821                                 printk(KERN_WARNING "%s: No memory for skb\n",
1822                                     __func__);
1823                                 continue;
1824                         }
1825                         hh = mISDN_HEAD_P(skb);
1826                         hh->prim = PH_CONTROL_IND;
1827                         hh->id = DTMF_HFC_COEF;
1828                         memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1829                         recv_Bchannel_skb(bch, skb);
1830                 }
1831         }
1832
1833         /* restart DTMF processing */
1834         hc->dtmf = dtmf;
1835         if (dtmf)
1836                 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1837 }
1838
1839
1840 /*
1841  * fill fifo as much as possible
1842  */
1843
1844 static void
1845 hfcmulti_tx(struct hfc_multi *hc, int ch)
1846 {
1847         int i, ii, temp, len = 0;
1848         int Zspace, z1, z2; /* must be int for calculation */
1849         int Fspace, f1, f2;
1850         u_char *d;
1851         int *txpending, slot_tx;
1852         struct  bchannel *bch;
1853         struct  dchannel *dch;
1854         struct  sk_buff **sp = NULL;
1855         int *idxp;
1856
1857         bch = hc->chan[ch].bch;
1858         dch = hc->chan[ch].dch;
1859         if ((!dch) && (!bch))
1860                 return;
1861
1862         txpending = &hc->chan[ch].txpending;
1863         slot_tx = hc->chan[ch].slot_tx;
1864         if (dch) {
1865                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1866                         return;
1867                 sp = &dch->tx_skb;
1868                 idxp = &dch->tx_idx;
1869         } else {
1870                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1871                         return;
1872                 sp = &bch->tx_skb;
1873                 idxp = &bch->tx_idx;
1874         }
1875         if (*sp)
1876                 len = (*sp)->len;
1877
1878         if ((!len) && *txpending != 1)
1879                 return; /* no data */
1880
1881         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1882             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1883             (hc->chan[ch].slot_rx < 0) &&
1884             (hc->chan[ch].slot_tx < 0))
1885                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1886         else
1887                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1888         HFC_wait_nodebug(hc);
1889
1890         if (*txpending == 2) {
1891                 /* reset fifo */
1892                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1893                 HFC_wait_nodebug(hc);
1894                 HFC_outb(hc, A_SUBCH_CFG, 0);
1895                 *txpending = 1;
1896         }
1897 next_frame:
1898         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1899                 f1 = HFC_inb_nodebug(hc, A_F1);
1900                 f2 = HFC_inb_nodebug(hc, A_F2);
1901                 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1902                         if (debug & DEBUG_HFCMULTI_FIFO)
1903                                 printk(KERN_DEBUG
1904                                     "%s(card %d): reread f2 because %d!=%d\n",
1905                                     __func__, hc->id + 1, temp, f2);
1906                         f2 = temp; /* repeat until F2 is equal */
1907                 }
1908                 Fspace = f2 - f1 - 1;
1909                 if (Fspace < 0)
1910                         Fspace += hc->Flen;
1911                 /*
1912                  * Old FIFO handling doesn't give us the current Z2 read
1913                  * pointer, so we cannot send the next frame before the fifo
1914                  * is empty. It makes no difference except for a slightly
1915                  * lower performance.
1916                  */
1917                 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1918                         if (f1 != f2)
1919                                 Fspace = 0;
1920                         else
1921                                 Fspace = 1;
1922                 }
1923                 /* one frame only for ST D-channels, to allow resending */
1924                 if (hc->type != 1 && dch) {
1925                         if (f1 != f2)
1926                                 Fspace = 0;
1927                 }
1928                 /* F-counter full condition */
1929                 if (Fspace == 0)
1930                         return;
1931         }
1932         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1933         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1934         while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1935                 if (debug & DEBUG_HFCMULTI_FIFO)
1936                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
1937                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1938                 z2 = temp; /* repeat unti Z2 is equal */
1939         }
1940         Zspace = z2 - z1;
1941         if (Zspace <= 0)
1942                 Zspace += hc->Zlen;
1943         Zspace -= 4; /* keep not too full, so pointers will not overrun */
1944         /* fill transparent data only to maxinum transparent load (minus 4) */
1945         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
1946                 Zspace = Zspace - hc->Zlen + hc->max_trans;
1947         if (Zspace <= 0) /* no space of 4 bytes */
1948                 return;
1949
1950         /* if no data */
1951         if (!len) {
1952                 if (z1 == z2) { /* empty */
1953                         /* if done with FIFO audio data during PCM connection */
1954                         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
1955                             *txpending && slot_tx >= 0) {
1956                                 if (debug & DEBUG_HFCMULTI_MODE)
1957                                         printk(KERN_DEBUG
1958                                             "%s: reconnecting PCM due to no "
1959                                             "more FIFO data: channel %d "
1960                                             "slot_tx %d\n",
1961                                             __func__, ch, slot_tx);
1962                                 /* connect slot */
1963                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1964                                     V_HDLC_TRP | V_IFF);
1965                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1966                                 HFC_wait_nodebug(hc);
1967                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1968                                     V_HDLC_TRP | V_IFF);
1969                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
1970                                 HFC_wait_nodebug(hc);
1971                         }
1972                         *txpending = 0;
1973                 }
1974                 return; /* no data */
1975         }
1976
1977         /* "fill fifo if empty" feature */
1978         if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
1979                 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
1980                 if (debug & DEBUG_HFCMULTI_FILL)
1981                         printk(KERN_DEBUG "%s: buffer empty, so we have "
1982                                 "underrun\n", __func__);
1983                 /* fill buffer, to prevent future underrun */
1984                 hc->write_fifo(hc, hc->silence_data, poll >> 1);
1985                 Zspace -= (poll >> 1);
1986         }
1987
1988         /* if audio data and connected slot */
1989         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
1990                 && slot_tx >= 0) {
1991                 if (debug & DEBUG_HFCMULTI_MODE)
1992                         printk(KERN_DEBUG "%s: disconnecting PCM due to "
1993                             "FIFO data: channel %d slot_tx %d\n",
1994                             __func__, ch, slot_tx);
1995                 /* disconnect slot */
1996                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
1997                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1998                 HFC_wait_nodebug(hc);
1999                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2000                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2001                 HFC_wait_nodebug(hc);
2002         }
2003         *txpending = 1;
2004
2005         /* show activity */
2006         hc->activity[hc->chan[ch].port] = 1;
2007
2008         /* fill fifo to what we have left */
2009         ii = len;
2010         if (dch || test_bit(FLG_HDLC, &bch->Flags))
2011                 temp = 1;
2012         else
2013                 temp = 0;
2014         i = *idxp;
2015         d = (*sp)->data + i;
2016         if (ii - i > Zspace)
2017                 ii = Zspace + i;
2018         if (debug & DEBUG_HFCMULTI_FIFO)
2019                 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2020                     "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2021                         __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2022                         temp ? "HDLC":"TRANS");
2023
2024         /* Have to prep the audio data */
2025         hc->write_fifo(hc, d, ii - i);
2026         *idxp = ii;
2027
2028         /* if not all data has been written */
2029         if (ii != len) {
2030                 /* NOTE: fifo is started by the calling function */
2031                 return;
2032         }
2033
2034         /* if all data has been written, terminate frame */
2035         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2036                 /* increment f-counter */
2037                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2038                 HFC_wait_nodebug(hc);
2039         }
2040
2041         /* send confirm, since get_net_bframe will not do it with trans */
2042         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2043                 confirm_Bsend(bch);
2044
2045         /* check for next frame */
2046         dev_kfree_skb(*sp);
2047         if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2048                 len = (*sp)->len;
2049                 goto next_frame;
2050         }
2051         if (dch && get_next_dframe(dch)) {
2052                 len = (*sp)->len;
2053                 goto next_frame;
2054         }
2055
2056         /*
2057          * now we have no more data, so in case of transparent,
2058          * we set the last byte in fifo to 'silence' in case we will get
2059          * no more data at all. this prevents sending an undefined value.
2060          */
2061         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2062                 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2063 }
2064
2065
2066 /* NOTE: only called if E1 card is in active state */
2067 static void
2068 hfcmulti_rx(struct hfc_multi *hc, int ch)
2069 {
2070         int temp;
2071         int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2072         int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2073         int again = 0;
2074         struct  bchannel *bch;
2075         struct  dchannel *dch;
2076         struct sk_buff  *skb, **sp = NULL;
2077         int     maxlen;
2078
2079         bch = hc->chan[ch].bch;
2080         dch = hc->chan[ch].dch;
2081         if ((!dch) && (!bch))
2082                 return;
2083         if (dch) {
2084                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2085                         return;
2086                 sp = &dch->rx_skb;
2087                 maxlen = dch->maxlen;
2088         } else {
2089                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2090                         return;
2091                 sp = &bch->rx_skb;
2092                 maxlen = bch->maxlen;
2093         }
2094 next_frame:
2095         /* on first AND before getting next valid frame, R_FIFO must be written
2096            to. */
2097         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2098             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2099             (hc->chan[ch].slot_rx < 0) &&
2100             (hc->chan[ch].slot_tx < 0))
2101                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2102         else
2103                 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2104         HFC_wait_nodebug(hc);
2105
2106         /* ignore if rx is off BUT change fifo (above) to start pending TX */
2107         if (hc->chan[ch].rx_off)
2108                 return;
2109
2110         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2111                 f1 = HFC_inb_nodebug(hc, A_F1);
2112                 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2113                         if (debug & DEBUG_HFCMULTI_FIFO)
2114                                 printk(KERN_DEBUG
2115                                     "%s(card %d): reread f1 because %d!=%d\n",
2116                                     __func__, hc->id + 1, temp, f1);
2117                         f1 = temp; /* repeat until F1 is equal */
2118                 }
2119                 f2 = HFC_inb_nodebug(hc, A_F2);
2120         }
2121         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2122         while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2123                 if (debug & DEBUG_HFCMULTI_FIFO)
2124                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2125                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2126                 z1 = temp; /* repeat until Z1 is equal */
2127         }
2128         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2129         Zsize = z1 - z2;
2130         if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2131                 /* complete hdlc frame */
2132                 Zsize++;
2133         if (Zsize < 0)
2134                 Zsize += hc->Zlen;
2135         /* if buffer is empty */
2136         if (Zsize <= 0)
2137                 return;
2138
2139         if (*sp == NULL) {
2140                 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2141                 if (*sp == NULL) {
2142                         printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2143                             __func__);
2144                         return;
2145                 }
2146         }
2147         /* show activity */
2148         hc->activity[hc->chan[ch].port] = 1;
2149
2150         /* empty fifo with what we have */
2151         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2152                 if (debug & DEBUG_HFCMULTI_FIFO)
2153                         printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2154                             "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2155                             "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2156                             Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2157                             f1, f2, Zsize + (*sp)->len, again);
2158                 /* HDLC */
2159                 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2160                         if (debug & DEBUG_HFCMULTI_FIFO)
2161                                 printk(KERN_DEBUG
2162                                     "%s(card %d): hdlc-frame too large.\n",
2163                                     __func__, hc->id + 1);
2164                         skb_trim(*sp, 0);
2165                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2166                         HFC_wait_nodebug(hc);
2167                         return;
2168                 }
2169
2170                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2171
2172                 if (f1 != f2) {
2173                         /* increment Z2,F2-counter */
2174                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2175                         HFC_wait_nodebug(hc);
2176                         /* check size */
2177                         if ((*sp)->len < 4) {
2178                                 if (debug & DEBUG_HFCMULTI_FIFO)
2179                                         printk(KERN_DEBUG
2180                                             "%s(card %d): Frame below minimum "
2181                                             "size\n", __func__, hc->id + 1);
2182                                 skb_trim(*sp, 0);
2183                                 goto next_frame;
2184                         }
2185                         /* there is at least one complete frame, check crc */
2186                         if ((*sp)->data[(*sp)->len - 1]) {
2187                                 if (debug & DEBUG_HFCMULTI_CRC)
2188                                         printk(KERN_DEBUG
2189                                             "%s: CRC-error\n", __func__);
2190                                 skb_trim(*sp, 0);
2191                                 goto next_frame;
2192                         }
2193                         skb_trim(*sp, (*sp)->len - 3);
2194                         if ((*sp)->len < MISDN_COPY_SIZE) {
2195                                 skb = *sp;
2196                                 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2197                                 if (*sp) {
2198                                         memcpy(skb_put(*sp, skb->len),
2199                                             skb->data, skb->len);
2200                                         skb_trim(skb, 0);
2201                                 } else {
2202                                         printk(KERN_DEBUG "%s: No mem\n",
2203                                             __func__);
2204                                         *sp = skb;
2205                                         skb = NULL;
2206                                 }
2207                         } else {
2208                                 skb = NULL;
2209                         }
2210                         if (debug & DEBUG_HFCMULTI_FIFO) {
2211                                 printk(KERN_DEBUG "%s(card %d):",
2212                                         __func__, hc->id + 1);
2213                                 temp = 0;
2214                                 while (temp < (*sp)->len)
2215                                         printk(" %02x", (*sp)->data[temp++]);
2216                                 printk("\n");
2217                         }
2218                         if (dch)
2219                                 recv_Dchannel(dch);
2220                         else
2221                                 recv_Bchannel(bch);
2222                         *sp = skb;
2223                         again++;
2224                         goto next_frame;
2225                 }
2226                 /* there is an incomplete frame */
2227         } else {
2228                 /* transparent */
2229                 if (Zsize > skb_tailroom(*sp))
2230                         Zsize = skb_tailroom(*sp);
2231                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2232                 if (((*sp)->len) < MISDN_COPY_SIZE) {
2233                         skb = *sp;
2234                         *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2235                         if (*sp) {
2236                                 memcpy(skb_put(*sp, skb->len),
2237                                     skb->data, skb->len);
2238                                 skb_trim(skb, 0);
2239                         } else {
2240                                 printk(KERN_DEBUG "%s: No mem\n", __func__);
2241                                 *sp = skb;
2242                                 skb = NULL;
2243                         }
2244                 } else {
2245                         skb = NULL;
2246                 }
2247                 if (debug & DEBUG_HFCMULTI_FIFO)
2248                         printk(KERN_DEBUG
2249                             "%s(card %d): fifo(%d) reading %d bytes "
2250                             "(z1=%04x, z2=%04x) TRANS\n",
2251                                 __func__, hc->id + 1, ch, Zsize, z1, z2);
2252                 /* only bch is transparent */
2253                 recv_Bchannel(bch);
2254                 *sp = skb;
2255         }
2256 }
2257
2258
2259 /*
2260  * Interrupt handler
2261  */
2262 static void
2263 signal_state_up(struct dchannel *dch, int info, char *msg)
2264 {
2265         struct sk_buff  *skb;
2266         int             id, data = info;
2267
2268         if (debug & DEBUG_HFCMULTI_STATE)
2269                 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2270
2271         id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2272
2273         skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2274                 GFP_ATOMIC);
2275         if (!skb)
2276                 return;
2277         recv_Dchannel_skb(dch, skb);
2278 }
2279
2280 static inline void
2281 handle_timer_irq(struct hfc_multi *hc)
2282 {
2283         int             ch, temp;
2284         struct dchannel *dch;
2285         u_long          flags;
2286
2287         /* process queued resync jobs */
2288         if (hc->e1_resync) {
2289                 /* lock, so e1_resync gets not changed */
2290                 spin_lock_irqsave(&HFClock, flags);
2291                 if (hc->e1_resync & 1) {
2292                         if (debug & DEBUG_HFCMULTI_PLXSD)
2293                                 printk(KERN_DEBUG "Enable SYNC_I\n");
2294                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2295                         /* disable JATT, if RX_SYNC is set */
2296                         if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2297                                 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2298                 }
2299                 if (hc->e1_resync & 2) {
2300                         if (debug & DEBUG_HFCMULTI_PLXSD)
2301                                 printk(KERN_DEBUG "Enable jatt PLL\n");
2302                         HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2303                 }
2304                 if (hc->e1_resync & 4) {
2305                         if (debug & DEBUG_HFCMULTI_PLXSD)
2306                                 printk(KERN_DEBUG
2307                                     "Enable QUARTZ for HFC-E1\n");
2308                         /* set jatt to quartz */
2309                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2310                                 | V_JATT_OFF);
2311                         /* switch to JATT, in case it is not already */
2312                         HFC_outb(hc, R_SYNC_OUT, 0);
2313                 }
2314                 hc->e1_resync = 0;
2315                 spin_unlock_irqrestore(&HFClock, flags);
2316         }
2317
2318         if (hc->type != 1 || hc->e1_state == 1)
2319                 for (ch = 0; ch <= 31; ch++) {
2320                         if (hc->created[hc->chan[ch].port]) {
2321                                 hfcmulti_tx(hc, ch);
2322                                 /* fifo is started when switching to rx-fifo */
2323                                 hfcmulti_rx(hc, ch);
2324                                 if (hc->chan[ch].dch &&
2325                                     hc->chan[ch].nt_timer > -1) {
2326                                         dch = hc->chan[ch].dch;
2327                                         if (!(--hc->chan[ch].nt_timer)) {
2328                                                 schedule_event(dch,
2329                                                     FLG_PHCHANGE);
2330                                                 if (debug &
2331                                                     DEBUG_HFCMULTI_STATE)
2332                                                         printk(KERN_DEBUG
2333                                                             "%s: nt_timer at "
2334                                                             "state %x\n",
2335                                                             __func__,
2336                                                             dch->state);
2337                                         }
2338                                 }
2339                         }
2340                 }
2341         if (hc->type == 1 && hc->created[0]) {
2342                 dch = hc->chan[hc->dslot].dch;
2343                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2344                         /* LOS */
2345                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2346                         if (!temp && hc->chan[hc->dslot].los)
2347                                 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2348                                     "LOS detected");
2349                         if (temp && !hc->chan[hc->dslot].los)
2350                                 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2351                                     "LOS gone");
2352                         hc->chan[hc->dslot].los = temp;
2353                 }
2354                 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2355                         /* AIS */
2356                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2357                         if (!temp && hc->chan[hc->dslot].ais)
2358                                 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2359                                     "AIS detected");
2360                         if (temp && !hc->chan[hc->dslot].ais)
2361                                 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2362                                     "AIS gone");
2363                         hc->chan[hc->dslot].ais = temp;
2364                 }
2365                 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2366                         /* SLIP */
2367                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2368                         if (!temp && hc->chan[hc->dslot].slip_rx)
2369                                 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2370                                     " bit SLIP detected RX");
2371                         hc->chan[hc->dslot].slip_rx = temp;
2372                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2373                         if (!temp && hc->chan[hc->dslot].slip_tx)
2374                                 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2375                                     " bit SLIP detected TX");
2376                         hc->chan[hc->dslot].slip_tx = temp;
2377                 }
2378                 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2379                         /* RDI */
2380                         temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2381                         if (!temp && hc->chan[hc->dslot].rdi)
2382                                 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2383                                     "RDI detected");
2384                         if (temp && !hc->chan[hc->dslot].rdi)
2385                                 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2386                                     "RDI gone");
2387                         hc->chan[hc->dslot].rdi = temp;
2388                 }
2389                 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2390                 switch (hc->chan[hc->dslot].sync) {
2391                 case 0:
2392                         if ((temp & 0x60) == 0x60) {
2393                                 if (debug & DEBUG_HFCMULTI_SYNC)
2394                                         printk(KERN_DEBUG
2395                                             "%s: (id=%d) E1 now "
2396                                             "in clock sync\n",
2397                                             __func__, hc->id);
2398                                 HFC_outb(hc, R_RX_OFF,
2399                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2400                                 HFC_outb(hc, R_TX_OFF,
2401                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2402                                 hc->chan[hc->dslot].sync = 1;
2403                                 goto check_framesync;
2404                         }
2405                         break;
2406                 case 1:
2407                         if ((temp & 0x60) != 0x60) {
2408                                 if (debug & DEBUG_HFCMULTI_SYNC)
2409                                         printk(KERN_DEBUG
2410                                             "%s: (id=%d) E1 "
2411                                             "lost clock sync\n",
2412                                             __func__, hc->id);
2413                                 hc->chan[hc->dslot].sync = 0;
2414                                 break;
2415                         }
2416 check_framesync:
2417                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2418                         if (temp == 0x27) {
2419                                 if (debug & DEBUG_HFCMULTI_SYNC)
2420                                         printk(KERN_DEBUG
2421                                             "%s: (id=%d) E1 "
2422                                             "now in frame sync\n",
2423                                             __func__, hc->id);
2424                                 hc->chan[hc->dslot].sync = 2;
2425                         }
2426                         break;
2427                 case 2:
2428                         if ((temp & 0x60) != 0x60) {
2429                                 if (debug & DEBUG_HFCMULTI_SYNC)
2430                                         printk(KERN_DEBUG
2431                                             "%s: (id=%d) E1 lost "
2432                                             "clock & frame sync\n",
2433                                             __func__, hc->id);
2434                                 hc->chan[hc->dslot].sync = 0;
2435                                 break;
2436                         }
2437                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2438                         if (temp != 0x27) {
2439                                 if (debug & DEBUG_HFCMULTI_SYNC)
2440                                         printk(KERN_DEBUG
2441                                             "%s: (id=%d) E1 "
2442                                             "lost frame sync\n",
2443                                             __func__, hc->id);
2444                                 hc->chan[hc->dslot].sync = 1;
2445                         }
2446                         break;
2447                 }
2448         }
2449
2450         if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2451                 hfcmulti_watchdog(hc);
2452
2453         if (hc->leds)
2454                 hfcmulti_leds(hc);
2455 }
2456
2457 static void
2458 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2459 {
2460         struct dchannel *dch;
2461         int             ch;
2462         int             active;
2463         u_char          st_status, temp;
2464
2465         /* state machine */
2466         for (ch = 0; ch <= 31; ch++) {
2467                 if (hc->chan[ch].dch) {
2468                         dch = hc->chan[ch].dch;
2469                         if (r_irq_statech & 1) {
2470                                 HFC_outb_nodebug(hc, R_ST_SEL,
2471                                         hc->chan[ch].port);
2472                                 /* undocumented: delay after R_ST_SEL */
2473                                 udelay(1);
2474                                 /* undocumented: status changes during read */
2475                                 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2476                                 while (st_status != (temp =
2477                                         HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2478                                         if (debug & DEBUG_HFCMULTI_STATE)
2479                                                 printk(KERN_DEBUG "%s: reread "
2480                                                     "STATE because %d!=%d\n",
2481                                                     __func__, temp,
2482                                                     st_status);
2483                                         st_status = temp; /* repeat */
2484                                 }
2485
2486                                 /* Speech Design TE-sync indication */
2487                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2488                                         dch->dev.D.protocol == ISDN_P_TE_S0) {
2489                                         if (st_status & V_FR_SYNC_ST)
2490                                                 hc->syncronized |=
2491                                                     (1 << hc->chan[ch].port);
2492                                         else
2493                                                 hc->syncronized &=
2494                                                    ~(1 << hc->chan[ch].port);
2495                                 }
2496                                 dch->state = st_status & 0x0f;
2497                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2498                                         active = 3;
2499                                 else
2500                                         active = 7;
2501                                 if (dch->state == active) {
2502                                         HFC_outb_nodebug(hc, R_FIFO,
2503                                                 (ch << 1) | 1);
2504                                         HFC_wait_nodebug(hc);
2505                                         HFC_outb_nodebug(hc,
2506                                                 R_INC_RES_FIFO, V_RES_F);
2507                                         HFC_wait_nodebug(hc);
2508                                         dch->tx_idx = 0;
2509                                 }
2510                                 schedule_event(dch, FLG_PHCHANGE);
2511                                 if (debug & DEBUG_HFCMULTI_STATE)
2512                                         printk(KERN_DEBUG
2513                                             "%s: S/T newstate %x port %d\n",
2514                                             __func__, dch->state,
2515                                             hc->chan[ch].port);
2516                         }
2517                         r_irq_statech >>= 1;
2518                 }
2519         }
2520         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2521                 plxsd_checksync(hc, 0);
2522 }
2523
2524 static void
2525 fifo_irq(struct hfc_multi *hc, int block)
2526 {
2527         int     ch, j;
2528         struct dchannel *dch;
2529         struct bchannel *bch;
2530         u_char r_irq_fifo_bl;
2531
2532         r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2533         j = 0;
2534         while (j < 8) {
2535                 ch = (block << 2) + (j >> 1);
2536                 dch = hc->chan[ch].dch;
2537                 bch = hc->chan[ch].bch;
2538                 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2539                         j += 2;
2540                         continue;
2541                 }
2542                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2543                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2544                         hfcmulti_tx(hc, ch);
2545                         /* start fifo */
2546                         HFC_outb_nodebug(hc, R_FIFO, 0);
2547                         HFC_wait_nodebug(hc);
2548                 }
2549                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2550                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2551                         hfcmulti_tx(hc, ch);
2552                         /* start fifo */
2553                         HFC_outb_nodebug(hc, R_FIFO, 0);
2554                         HFC_wait_nodebug(hc);
2555                 }
2556                 j++;
2557                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2558                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2559                         hfcmulti_rx(hc, ch);
2560                 }
2561                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2562                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2563                         hfcmulti_rx(hc, ch);
2564                 }
2565                 j++;
2566         }
2567 }
2568
2569 #ifdef IRQ_DEBUG
2570 int irqsem;
2571 #endif
2572 static irqreturn_t
2573 hfcmulti_interrupt(int intno, void *dev_id)
2574 {
2575 #ifdef IRQCOUNT_DEBUG
2576         static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2577             iq5 = 0, iq6 = 0, iqcnt = 0;
2578 #endif
2579         struct hfc_multi        *hc = dev_id;
2580         struct dchannel         *dch;
2581         u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
2582         int                     i;
2583         void __iomem            *plx_acc;
2584         u_short                 wval;
2585         u_char                  e1_syncsta, temp;
2586         u_long                  flags;
2587
2588         if (!hc) {
2589                 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2590                 return IRQ_NONE;
2591         }
2592
2593         spin_lock(&hc->lock);
2594
2595 #ifdef IRQ_DEBUG
2596         if (irqsem)
2597                 printk(KERN_ERR "irq for card %d during irq from "
2598                 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2599         irqsem = hc->id + 1;
2600 #endif
2601
2602         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2603                 spin_lock_irqsave(&plx_lock, flags);
2604                 plx_acc = hc->plx_membase + PLX_INTCSR;
2605                 wval = readw(plx_acc);
2606                 spin_unlock_irqrestore(&plx_lock, flags);
2607                 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2608                         goto irq_notforus;
2609         }
2610
2611         status = HFC_inb_nodebug(hc, R_STATUS);
2612         r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2613 #ifdef IRQCOUNT_DEBUG
2614         if (r_irq_statech)
2615                 iq1++;
2616         if (status & V_DTMF_STA)
2617                 iq2++;
2618         if (status & V_LOST_STA)
2619                 iq3++;
2620         if (status & V_EXT_IRQSTA)
2621                 iq4++;
2622         if (status & V_MISC_IRQSTA)
2623                 iq5++;
2624         if (status & V_FR_IRQSTA)
2625                 iq6++;
2626         if (iqcnt++ > 5000) {
2627                 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2628                     iq1, iq2, iq3, iq4, iq5, iq6);
2629                 iqcnt = 0;
2630         }
2631 #endif
2632         if (!r_irq_statech &&
2633             !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2634             V_MISC_IRQSTA | V_FR_IRQSTA))) {
2635                 /* irq is not for us */
2636                 goto irq_notforus;
2637         }
2638         hc->irqcnt++;
2639         if (r_irq_statech) {
2640                 if (hc->type != 1)
2641                         ph_state_irq(hc, r_irq_statech);
2642         }
2643         if (status & V_EXT_IRQSTA)
2644                 ; /* external IRQ */
2645         if (status & V_LOST_STA) {
2646                 /* LOST IRQ */
2647                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2648         }
2649         if (status & V_MISC_IRQSTA) {
2650                 /* misc IRQ */
2651                 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2652                 if (r_irq_misc & V_STA_IRQ) {
2653                         if (hc->type == 1) {
2654                                 /* state machine */
2655                                 dch = hc->chan[hc->dslot].dch;
2656                                 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2657                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2658                                  && hc->e1_getclock) {
2659                                         if (e1_syncsta & V_FR_SYNC_E1)
2660                                                 hc->syncronized = 1;
2661                                         else
2662                                                 hc->syncronized = 0;
2663                                 }
2664                                 /* undocumented: status changes during read */
2665                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2666                                 while (dch->state != (temp =
2667                                         HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2668                                         if (debug & DEBUG_HFCMULTI_STATE)
2669                                                 printk(KERN_DEBUG "%s: reread "
2670                                                     "STATE because %d!=%d\n",
2671                                                     __func__, temp,
2672                                                     dch->state);
2673                                         dch->state = temp; /* repeat */
2674                                 }
2675                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2676                                         & 0x7;
2677                                 schedule_event(dch, FLG_PHCHANGE);
2678                                 if (debug & DEBUG_HFCMULTI_STATE)
2679                                         printk(KERN_DEBUG
2680                                             "%s: E1 (id=%d) newstate %x\n",
2681                                             __func__, hc->id, dch->state);
2682                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2683                                         plxsd_checksync(hc, 0);
2684                         }
2685                 }
2686                 if (r_irq_misc & V_TI_IRQ)
2687                         handle_timer_irq(hc);
2688
2689                 if (r_irq_misc & V_DTMF_IRQ) {
2690                         /* -> DTMF IRQ */
2691                         hfcmulti_dtmf(hc);
2692                 }
2693                 if (r_irq_misc & V_IRQ_PROC) {
2694                         static int irq_proc_cnt;
2695                         if (!irq_proc_cnt++)
2696                                 printk(KERN_WARNING "%s: got V_IRQ_PROC -"
2697                                     " this should not happen\n", __func__);
2698                 }
2699
2700         }
2701         if (status & V_FR_IRQSTA) {
2702                 /* FIFO IRQ */
2703                 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2704                 for (i = 0; i < 8; i++) {
2705                         if (r_irq_oview & (1 << i))
2706                                 fifo_irq(hc, i);
2707                 }
2708         }
2709
2710 #ifdef IRQ_DEBUG
2711         irqsem = 0;
2712 #endif
2713         spin_unlock(&hc->lock);
2714         return IRQ_HANDLED;
2715
2716 irq_notforus:
2717 #ifdef IRQ_DEBUG
2718         irqsem = 0;
2719 #endif
2720         spin_unlock(&hc->lock);
2721         return IRQ_NONE;
2722 }
2723
2724
2725 /*
2726  * timer callback for D-chan busy resolution. Currently no function
2727  */
2728
2729 static void
2730 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2731 {
2732 }
2733
2734
2735 /*
2736  * activate/deactivate hardware for selected channels and mode
2737  *
2738  * configure B-channel with the given protocol
2739  * ch eqals to the HFC-channel (0-31)
2740  * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2741  * for S/T, 1-31 for E1)
2742  * the hdlc interrupts will be set/unset
2743  */
2744 static int
2745 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2746     int bank_tx, int slot_rx, int bank_rx)
2747 {
2748         int flow_tx = 0, flow_rx = 0, routing = 0;
2749         int oslot_tx, oslot_rx;
2750         int conf;
2751
2752         if (ch < 0 || ch > 31)
2753                 return EINVAL;
2754         oslot_tx = hc->chan[ch].slot_tx;
2755         oslot_rx = hc->chan[ch].slot_rx;
2756         conf = hc->chan[ch].conf;
2757
2758         if (debug & DEBUG_HFCMULTI_MODE)
2759                 printk(KERN_DEBUG
2760                     "%s: card %d channel %d protocol %x slot old=%d new=%d "
2761                     "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2762                     __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2763                     bank_tx, oslot_rx, slot_rx, bank_rx);
2764
2765         if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2766                 /* remove from slot */
2767                 if (debug & DEBUG_HFCMULTI_MODE)
2768                         printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2769                             __func__, oslot_tx);
2770                 if (hc->slot_owner[oslot_tx<<1] == ch) {
2771                         HFC_outb(hc, R_SLOT, oslot_tx << 1);
2772                         HFC_outb(hc, A_SL_CFG, 0);
2773                         HFC_outb(hc, A_CONF, 0);
2774                         hc->slot_owner[oslot_tx<<1] = -1;
2775                 } else {
2776                         if (debug & DEBUG_HFCMULTI_MODE)
2777                                 printk(KERN_DEBUG
2778                                     "%s: we are not owner of this tx slot "
2779                                     "anymore, channel %d is.\n",
2780                                     __func__, hc->slot_owner[oslot_tx<<1]);
2781                 }
2782         }
2783
2784         if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2785                 /* remove from slot */
2786                 if (debug & DEBUG_HFCMULTI_MODE)
2787                         printk(KERN_DEBUG
2788                             "%s: remove from slot %d (RX)\n",
2789                             __func__, oslot_rx);
2790                 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2791                         HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2792                         HFC_outb(hc, A_SL_CFG, 0);
2793                         hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2794                 } else {
2795                         if (debug & DEBUG_HFCMULTI_MODE)
2796                                 printk(KERN_DEBUG
2797                                     "%s: we are not owner of this rx slot "
2798                                     "anymore, channel %d is.\n",
2799                                     __func__,
2800                                     hc->slot_owner[(oslot_rx << 1) | 1]);
2801                 }
2802         }
2803
2804         if (slot_tx < 0) {
2805                 flow_tx = 0x80; /* FIFO->ST */
2806                 /* disable pcm slot */
2807                 hc->chan[ch].slot_tx = -1;
2808                 hc->chan[ch].bank_tx = 0;
2809         } else {
2810                 /* set pcm slot */
2811                 if (hc->chan[ch].txpending)
2812                         flow_tx = 0x80; /* FIFO->ST */
2813                 else
2814                         flow_tx = 0xc0; /* PCM->ST */
2815                 /* put on slot */
2816                 routing = bank_tx ? 0xc0 : 0x80;
2817                 if (conf >= 0 || bank_tx > 1)
2818                         routing = 0x40; /* loop */
2819                 if (debug & DEBUG_HFCMULTI_MODE)
2820                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2821                             " %d flow %02x routing %02x conf %d (TX)\n",
2822                             __func__, ch, slot_tx, bank_tx,
2823                             flow_tx, routing, conf);
2824                 HFC_outb(hc, R_SLOT, slot_tx << 1);
2825                 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2826                 HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
2827                 hc->slot_owner[slot_tx << 1] = ch;
2828                 hc->chan[ch].slot_tx = slot_tx;
2829                 hc->chan[ch].bank_tx = bank_tx;
2830         }
2831         if (slot_rx < 0) {
2832                 /* disable pcm slot */
2833                 flow_rx = 0x80; /* ST->FIFO */
2834                 hc->chan[ch].slot_rx = -1;
2835                 hc->chan[ch].bank_rx = 0;
2836         } else {
2837                 /* set pcm slot */
2838                 if (hc->chan[ch].txpending)
2839                         flow_rx = 0x80; /* ST->FIFO */
2840                 else
2841                         flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2842                 /* put on slot */
2843                 routing = bank_rx?0x80:0xc0; /* reversed */
2844                 if (conf >= 0 || bank_rx > 1)
2845                         routing = 0x40; /* loop */
2846                 if (debug & DEBUG_HFCMULTI_MODE)
2847                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2848                             " %d flow %02x routing %02x conf %d (RX)\n",
2849                             __func__, ch, slot_rx, bank_rx,
2850                             flow_rx, routing, conf);
2851                 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2852                 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2853                 hc->slot_owner[(slot_rx<<1)|1] = ch;
2854                 hc->chan[ch].slot_rx = slot_rx;
2855                 hc->chan[ch].bank_rx = bank_rx;
2856         }
2857
2858         switch (protocol) {
2859         case (ISDN_P_NONE):
2860                 /* disable TX fifo */
2861                 HFC_outb(hc, R_FIFO, ch << 1);
2862                 HFC_wait(hc);
2863                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2864                 HFC_outb(hc, A_SUBCH_CFG, 0);
2865                 HFC_outb(hc, A_IRQ_MSK, 0);
2866                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2867                 HFC_wait(hc);
2868                 /* disable RX fifo */
2869                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2870                 HFC_wait(hc);
2871                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2872                 HFC_outb(hc, A_SUBCH_CFG, 0);
2873                 HFC_outb(hc, A_IRQ_MSK, 0);
2874                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2875                 HFC_wait(hc);
2876                 if (hc->chan[ch].bch && hc->type != 1) {
2877                         hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2878                             ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
2879                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2880                         /* undocumented: delay after R_ST_SEL */
2881                         udelay(1);
2882                         HFC_outb(hc, A_ST_CTRL0,
2883                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2884                 }
2885                 if (hc->chan[ch].bch) {
2886                         test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2887                         test_and_clear_bit(FLG_TRANSPARENT,
2888                             &hc->chan[ch].bch->Flags);
2889                 }
2890                 break;
2891         case (ISDN_P_B_RAW): /* B-channel */
2892
2893                 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2894                     (hc->chan[ch].slot_rx < 0) &&
2895                     (hc->chan[ch].slot_tx < 0)) {
2896
2897                         printk(KERN_DEBUG
2898                             "Setting B-channel %d to echo cancelable "
2899                             "state on PCM slot %d\n", ch,
2900                             ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2901                         printk(KERN_DEBUG
2902                             "Enabling pass through for channel\n");
2903                         vpm_out(hc, ch, ((ch / 4) * 8) +
2904                             ((ch % 4) * 4) + 1, 0x01);
2905                         /* rx path */
2906                         /* S/T -> PCM */
2907                         HFC_outb(hc, R_FIFO, (ch << 1));
2908                         HFC_wait(hc);
2909                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2910                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2911                             ((ch % 4) * 4) + 1) << 1);
2912                         HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2913
2914                         /* PCM -> FIFO */
2915                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2916                         HFC_wait(hc);
2917                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2918                         HFC_outb(hc, A_SUBCH_CFG, 0);
2919                         HFC_outb(hc, A_IRQ_MSK, 0);
2920                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2921                         HFC_wait(hc);
2922                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2923                             ((ch % 4) * 4) + 1) << 1) | 1);
2924                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
2925
2926                         /* tx path */
2927                         /* PCM -> S/T */
2928                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2929                         HFC_wait(hc);
2930                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2931                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2932                             ((ch % 4) * 4)) << 1) | 1);
2933                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
2934
2935                         /* FIFO -> PCM */
2936                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
2937                         HFC_wait(hc);
2938                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2939                         HFC_outb(hc, A_SUBCH_CFG, 0);
2940                         HFC_outb(hc, A_IRQ_MSK, 0);
2941                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2942                         HFC_wait(hc);
2943                         /* tx silence */
2944                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2945                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2946                             ((ch % 4) * 4)) << 1);
2947                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
2948                 } else {
2949                         /* enable TX fifo */
2950                         HFC_outb(hc, R_FIFO, ch << 1);
2951                         HFC_wait(hc);
2952                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
2953                             V_HDLC_TRP | V_IFF);
2954                         HFC_outb(hc, A_SUBCH_CFG, 0);
2955                         HFC_outb(hc, A_IRQ_MSK, 0);
2956                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2957                         HFC_wait(hc);
2958                         /* tx silence */
2959                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2960                         /* enable RX fifo */
2961                         HFC_outb(hc, R_FIFO, (ch<<1)|1);
2962                         HFC_wait(hc);
2963                         HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
2964                         HFC_outb(hc, A_SUBCH_CFG, 0);
2965                         HFC_outb(hc, A_IRQ_MSK, 0);
2966                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2967                         HFC_wait(hc);
2968                 }
2969                 if (hc->type != 1) {
2970                         hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
2971                             ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
2972                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2973                         /* undocumented: delay after R_ST_SEL */
2974                         udelay(1);
2975                         HFC_outb(hc, A_ST_CTRL0,
2976                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2977                 }
2978                 if (hc->chan[ch].bch)
2979                         test_and_set_bit(FLG_TRANSPARENT,
2980                             &hc->chan[ch].bch->Flags);
2981                 break;
2982         case (ISDN_P_B_HDLC): /* B-channel */
2983         case (ISDN_P_TE_S0): /* D-channel */
2984         case (ISDN_P_NT_S0):
2985         case (ISDN_P_TE_E1):
2986         case (ISDN_P_NT_E1):
2987                 /* enable TX fifo */
2988                 HFC_outb(hc, R_FIFO, ch<<1);
2989                 HFC_wait(hc);
2990                 if (hc->type == 1 || hc->chan[ch].bch) {
2991                         /* E1 or B-channel */
2992                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
2993                         HFC_outb(hc, A_SUBCH_CFG, 0);
2994                 } else {
2995                         /* D-Channel without HDLC fill flags */
2996                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
2997                         HFC_outb(hc, A_SUBCH_CFG, 2);
2998                 }
2999                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3000                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3001                 HFC_wait(hc);
3002                 /* enable RX fifo */
3003                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3004                 HFC_wait(hc);
3005                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3006                 if (hc->type == 1 || hc->chan[ch].bch)
3007                         HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3008                 else
3009                         HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3010                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3011                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3012                 HFC_wait(hc);
3013                 if (hc->chan[ch].bch) {
3014                         test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3015                         if (hc->type != 1) {
3016                                 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3017                                   ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3018                                 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3019                                 /* undocumented: delay after R_ST_SEL */
3020                                 udelay(1);
3021                                 HFC_outb(hc, A_ST_CTRL0,
3022                                   hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3023                         }
3024                 }
3025                 break;
3026         default:
3027                 printk(KERN_DEBUG "%s: protocol not known %x\n",
3028                     __func__, protocol);
3029                 hc->chan[ch].protocol = ISDN_P_NONE;
3030                 return -ENOPROTOOPT;
3031         }
3032         hc->chan[ch].protocol = protocol;
3033         return 0;
3034 }
3035
3036
3037 /*
3038  * connect/disconnect PCM
3039  */
3040
3041 static void
3042 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3043     int slot_rx, int bank_rx)
3044 {
3045         if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3046                 /* disable PCM */
3047                 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3048                 return;
3049         }
3050
3051         /* enable pcm */
3052         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3053                 slot_rx, bank_rx);
3054 }
3055
3056 /*
3057  * set/disable conference
3058  */
3059
3060 static void
3061 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3062 {
3063         if (num >= 0 && num <= 7)
3064                 hc->chan[ch].conf = num;
3065         else
3066                 hc->chan[ch].conf = -1;
3067         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3068             hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3069             hc->chan[ch].bank_rx);
3070 }
3071
3072
3073 /*
3074  * set/disable sample loop
3075  */
3076
3077 /* NOTE: this function is experimental and therefore disabled */
3078
3079 /*
3080  * Layer 1 callback function
3081  */
3082 static int
3083 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3084 {
3085         struct hfc_multi        *hc = dch->hw;
3086         u_long  flags;
3087
3088         switch (cmd) {
3089         case INFO3_P8:
3090         case INFO3_P10:
3091                 break;
3092         case HW_RESET_REQ:
3093                 /* start activation */
3094                 spin_lock_irqsave(&hc->lock, flags);
3095                 if (hc->type == 1) {
3096                         if (debug & DEBUG_HFCMULTI_MSG)
3097                                 printk(KERN_DEBUG
3098                                     "%s: HW_RESET_REQ no BRI\n",
3099                                     __func__);
3100                 } else {
3101                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3102                         /* undocumented: delay after R_ST_SEL */
3103                         udelay(1);
3104                         HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3105                         udelay(6); /* wait at least 5,21us */
3106                         HFC_outb(hc, A_ST_WR_STATE, 3);
3107                         HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3108                                 /* activate */
3109                 }
3110                 spin_unlock_irqrestore(&hc->lock, flags);
3111                 l1_event(dch->l1, HW_POWERUP_IND);
3112                 break;
3113         case HW_DEACT_REQ:
3114                 /* start deactivation */
3115                 spin_lock_irqsave(&hc->lock, flags);
3116                 if (hc->type == 1) {
3117                         if (debug & DEBUG_HFCMULTI_MSG)
3118                                 printk(KERN_DEBUG
3119                                     "%s: HW_DEACT_REQ no BRI\n",
3120                                     __func__);
3121                 } else {
3122                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3123                         /* undocumented: delay after R_ST_SEL */
3124                         udelay(1);
3125                         HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3126                                 /* deactivate */
3127                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3128                                 hc->syncronized &=
3129                                    ~(1 << hc->chan[dch->slot].port);
3130                                 plxsd_checksync(hc, 0);
3131                         }
3132                 }
3133                 skb_queue_purge(&dch->squeue);
3134                 if (dch->tx_skb) {
3135                         dev_kfree_skb(dch->tx_skb);
3136                         dch->tx_skb = NULL;
3137                 }
3138                 dch->tx_idx = 0;
3139                 if (dch->rx_skb) {
3140                         dev_kfree_skb(dch->rx_skb);
3141                         dch->rx_skb = NULL;
3142                 }
3143                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3144                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3145                         del_timer(&dch->timer);
3146                 spin_unlock_irqrestore(&hc->lock, flags);
3147                 break;
3148         case HW_POWERUP_REQ:
3149                 spin_lock_irqsave(&hc->lock, flags);
3150                 if (hc->type == 1) {
3151                         if (debug & DEBUG_HFCMULTI_MSG)
3152                                 printk(KERN_DEBUG
3153                                     "%s: HW_POWERUP_REQ no BRI\n",
3154                                     __func__);
3155                 } else {
3156                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3157                         /* undocumented: delay after R_ST_SEL */
3158                         udelay(1);
3159                         HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3160                         udelay(6); /* wait at least 5,21us */
3161                         HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3162                 }
3163                 spin_unlock_irqrestore(&hc->lock, flags);
3164                 break;
3165         case PH_ACTIVATE_IND:
3166                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3167                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3168                         GFP_ATOMIC);
3169                 break;
3170         case PH_DEACTIVATE_IND:
3171                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3172                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3173                         GFP_ATOMIC);
3174                 break;
3175         default:
3176                 if (dch->debug & DEBUG_HW)
3177                         printk(KERN_DEBUG "%s: unknown command %x\n",
3178                             __func__, cmd);
3179                 return -1;
3180         }
3181         return 0;
3182 }
3183
3184 /*
3185  * Layer2 -> Layer 1 Transfer
3186  */
3187
3188 static int
3189 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3190 {
3191         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
3192         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
3193         struct hfc_multi        *hc = dch->hw;
3194         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3195         int                     ret = -EINVAL;
3196         unsigned int            id;
3197         u_long                  flags;
3198
3199         switch (hh->prim) {
3200         case PH_DATA_REQ:
3201                 if (skb->len < 1)
3202                         break;
3203                 spin_lock_irqsave(&hc->lock, flags);
3204                 ret = dchannel_senddata(dch, skb);
3205                 if (ret > 0) { /* direct TX */
3206                         id = hh->id; /* skb can be freed */
3207                         hfcmulti_tx(hc, dch->slot);
3208                         ret = 0;
3209                         /* start fifo */
3210                         HFC_outb(hc, R_FIFO, 0);
3211                         HFC_wait(hc);
3212                         spin_unlock_irqrestore(&hc->lock, flags);
3213                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3214                 } else
3215                         spin_unlock_irqrestore(&hc->lock, flags);
3216                 return ret;
3217         case PH_ACTIVATE_REQ:
3218                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3219                         spin_lock_irqsave(&hc->lock, flags);
3220                         ret = 0;
3221                         if (debug & DEBUG_HFCMULTI_MSG)
3222                                 printk(KERN_DEBUG
3223                                     "%s: PH_ACTIVATE port %d (0..%d)\n",
3224                                     __func__, hc->chan[dch->slot].port,
3225                                     hc->ports-1);
3226                         /* start activation */
3227                         if (hc->type == 1) {
3228                                 ph_state_change(dch);
3229                                 if (debug & DEBUG_HFCMULTI_STATE)
3230                                         printk(KERN_DEBUG
3231                                             "%s: E1 report state %x \n",
3232                                             __func__, dch->state);
3233                         } else {
3234                                 HFC_outb(hc, R_ST_SEL,
3235                                     hc->chan[dch->slot].port);
3236                                 /* undocumented: delay after R_ST_SEL */
3237                                 udelay(1);
3238                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3239                                     /* G1 */
3240                                 udelay(6); /* wait at least 5,21us */
3241                                 HFC_outb(hc, A_ST_WR_STATE, 1);
3242                                 HFC_outb(hc, A_ST_WR_STATE, 1 |
3243                                     (V_ST_ACT*3)); /* activate */
3244                                 dch->state = 1;
3245                         }
3246                         spin_unlock_irqrestore(&hc->lock, flags);
3247                 } else
3248                         ret = l1_event(dch->l1, hh->prim);
3249                 break;
3250         case PH_DEACTIVATE_REQ:
3251                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3252                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3253                         spin_lock_irqsave(&hc->lock, flags);
3254                         if (debug & DEBUG_HFCMULTI_MSG)
3255                                 printk(KERN_DEBUG
3256                                     "%s: PH_DEACTIVATE port %d (0..%d)\n",
3257                                     __func__, hc->chan[dch->slot].port,
3258                                     hc->ports-1);
3259                         /* start deactivation */
3260                         if (hc->type == 1) {
3261                                 if (debug & DEBUG_HFCMULTI_MSG)
3262                                         printk(KERN_DEBUG
3263                                             "%s: PH_DEACTIVATE no BRI\n",
3264                                             __func__);
3265                         } else {
3266                                 HFC_outb(hc, R_ST_SEL,
3267                                     hc->chan[dch->slot].port);
3268                                 /* undocumented: delay after R_ST_SEL */
3269                                 udelay(1);
3270                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3271                                     /* deactivate */
3272                                 dch->state = 1;
3273                         }
3274                         skb_queue_purge(&dch->squeue);
3275                         if (dch->tx_skb) {
3276                                 dev_kfree_skb(dch->tx_skb);
3277                                 dch->tx_skb = NULL;
3278                         }
3279                         dch->tx_idx = 0;
3280                         if (dch->rx_skb) {
3281                                 dev_kfree_skb(dch->rx_skb);
3282                                 dch->rx_skb = NULL;
3283                         }
3284                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3285                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3286                                 del_timer(&dch->timer);
3287 #ifdef FIXME
3288                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3289                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3290 #endif
3291                         ret = 0;
3292                         spin_unlock_irqrestore(&hc->lock, flags);
3293                 } else
3294                         ret = l1_event(dch->l1, hh->prim);
3295                 break;
3296         }
3297         if (!ret)
3298                 dev_kfree_skb(skb);
3299         return ret;
3300 }
3301
3302 static void
3303 deactivate_bchannel(struct bchannel *bch)
3304 {
3305         struct hfc_multi        *hc = bch->hw;
3306         u_long                  flags;
3307
3308         spin_lock_irqsave(&hc->lock, flags);
3309         if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
3310                 dev_kfree_skb(bch->next_skb);
3311                 bch->next_skb = NULL;
3312         }
3313         if (bch->tx_skb) {
3314                 dev_kfree_skb(bch->tx_skb);
3315                 bch->tx_skb = NULL;
3316         }
3317         bch->tx_idx = 0;
3318         if (bch->rx_skb) {
3319                 dev_kfree_skb(bch->rx_skb);
3320                 bch->rx_skb = NULL;
3321         }
3322         hc->chan[bch->slot].coeff_count = 0;
3323         test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
3324         test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
3325         hc->chan[bch->slot].rx_off = 0;
3326         hc->chan[bch->slot].conf = -1;
3327         mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3328         spin_unlock_irqrestore(&hc->lock, flags);
3329 }
3330
3331 static int
3332 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3333 {
3334         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3335         struct hfc_multi        *hc = bch->hw;
3336         int                     ret = -EINVAL;
3337         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3338         unsigned int            id;
3339         u_long                  flags;
3340
3341         switch (hh->prim) {
3342         case PH_DATA_REQ:
3343                 if (!skb->len)
3344                         break;
3345                 spin_lock_irqsave(&hc->lock, flags);
3346                 ret = bchannel_senddata(bch, skb);
3347                 if (ret > 0) { /* direct TX */
3348                         id = hh->id; /* skb can be freed */
3349                         hfcmulti_tx(hc, bch->slot);
3350                         ret = 0;
3351                         /* start fifo */
3352                         HFC_outb_nodebug(hc, R_FIFO, 0);
3353                         HFC_wait_nodebug(hc);
3354                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3355                                 spin_unlock_irqrestore(&hc->lock, flags);
3356                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3357                         } else
3358                                 spin_unlock_irqrestore(&hc->lock, flags);
3359                 } else
3360                         spin_unlock_irqrestore(&hc->lock, flags);
3361                 return ret;
3362         case PH_ACTIVATE_REQ:
3363                 if (debug & DEBUG_HFCMULTI_MSG)
3364                         printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3365                                 __func__, bch->slot);
3366                 spin_lock_irqsave(&hc->lock, flags);
3367                 /* activate B-channel if not already activated */
3368                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3369                         hc->chan[bch->slot].txpending = 0;
3370                         ret = mode_hfcmulti(hc, bch->slot,
3371                                 ch->protocol,
3372                                 hc->chan[bch->slot].slot_tx,
3373                                 hc->chan[bch->slot].bank_tx,
3374                                 hc->chan[bch->slot].slot_rx,
3375                                 hc->chan[bch->slot].bank_rx);
3376                         if (!ret) {
3377                                 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3378                                         && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3379                                         /* start decoder */
3380                                         hc->dtmf = 1;
3381                                         if (debug & DEBUG_HFCMULTI_DTMF)
3382                                                 printk(KERN_DEBUG
3383                                                     "%s: start dtmf decoder\n",
3384                                                         __func__);
3385                                         HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3386                                             V_RST_DTMF);
3387                                 }
3388                         }
3389                 } else
3390                         ret = 0;
3391                 spin_unlock_irqrestore(&hc->lock, flags);
3392                 if (!ret)
3393                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3394                                 GFP_KERNEL);
3395                 break;
3396         case PH_CONTROL_REQ:
3397                 spin_lock_irqsave(&hc->lock, flags);
3398                 switch (hh->id) {
3399                 case HFC_SPL_LOOP_ON: /* set sample loop */
3400                         if (debug & DEBUG_HFCMULTI_MSG)
3401                         printk(KERN_DEBUG
3402                             "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3403                             __func__, skb->len);
3404                         ret = 0;
3405                         break;
3406                 case HFC_SPL_LOOP_OFF: /* set silence */
3407                         if (debug & DEBUG_HFCMULTI_MSG)
3408                                 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3409                                     __func__);
3410                         ret = 0;
3411                         break;
3412                 default:
3413                         printk(KERN_ERR
3414                              "%s: unknown PH_CONTROL_REQ info %x\n",
3415                              __func__, hh->id);
3416                         ret = -EINVAL;
3417                 }
3418                 spin_unlock_irqrestore(&hc->lock, flags);
3419                 break;
3420         case PH_DEACTIVATE_REQ:
3421                 deactivate_bchannel(bch); /* locked there */
3422                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3423                         GFP_KERNEL);
3424                 ret = 0;
3425                 break;
3426         }
3427         if (!ret)
3428                 dev_kfree_skb(skb);
3429         return ret;
3430 }
3431
3432 /*
3433  * bchannel control function
3434  */
3435 static int
3436 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3437 {
3438         int                     ret = 0;
3439         struct dsp_features     *features =
3440                 (struct dsp_features *)(*((u_long *)&cq->p1));
3441         struct hfc_multi        *hc = bch->hw;
3442         int                     slot_tx;
3443         int                     bank_tx;
3444         int                     slot_rx;
3445         int                     bank_rx;
3446         int                     num;
3447
3448         switch (cq->op) {
3449         case MISDN_CTRL_GETOP:
3450                 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3451                         | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY;
3452                 break;
3453         case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3454                 hc->chan[bch->slot].rx_off = !!cq->p1;
3455                 if (!hc->chan[bch->slot].rx_off) {
3456                         /* reset fifo on rx on */
3457                         HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3458                         HFC_wait_nodebug(hc);
3459                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3460                         HFC_wait_nodebug(hc);
3461                 }
3462                 if (debug & DEBUG_HFCMULTI_MSG)
3463                         printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3464                             __func__, bch->nr, hc->chan[bch->slot].rx_off);
3465                 break;
3466         case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
3467                 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
3468                 if (debug & DEBUG_HFCMULTI_MSG)
3469                         printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
3470                                 "off=%d)\n", __func__, bch->nr, !!cq->p1);
3471                 break;
3472         case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3473                 if (debug & DEBUG_HFCMULTI_MSG)
3474                         printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3475                             __func__);
3476                 /* create confirm */
3477                 features->hfc_id = hc->id;
3478                 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3479                         features->hfc_dtmf = 1;
3480                 features->hfc_loops = 0;
3481                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3482                         features->hfc_echocanhw = 1;
3483                 } else {
3484                         features->pcm_id = hc->pcm;
3485                         features->pcm_slots = hc->slots;
3486                         features->pcm_banks = 2;
3487                 }
3488                 break;
3489         case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3490                 slot_tx = cq->p1 & 0xff;
3491                 bank_tx = cq->p1 >> 8;
3492                 slot_rx = cq->p2 & 0xff;
3493                 bank_rx = cq->p2 >> 8;
3494                 if (debug & DEBUG_HFCMULTI_MSG)
3495                         printk(KERN_DEBUG
3496                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3497                             "slot %d bank %d (RX)\n",
3498                             __func__, slot_tx, bank_tx,
3499                             slot_rx, bank_rx);
3500                 if (slot_tx < hc->slots && bank_tx <= 2 &&
3501                     slot_rx < hc->slots && bank_rx <= 2)
3502                         hfcmulti_pcm(hc, bch->slot,
3503                             slot_tx, bank_tx, slot_rx, bank_rx);
3504                 else {
3505                         printk(KERN_WARNING
3506                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3507                             "slot %d bank %d (RX) out of range\n",
3508                             __func__, slot_tx, bank_tx,
3509                             slot_rx, bank_rx);
3510                         ret = -EINVAL;
3511                 }
3512                 break;
3513         case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3514                 if (debug & DEBUG_HFCMULTI_MSG)
3515                         printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3516                             __func__);
3517                 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3518                 break;
3519         case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3520                 num = cq->p1 & 0xff;
3521                 if (debug & DEBUG_HFCMULTI_MSG)
3522                         printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3523                             __func__, num);
3524                 if (num <= 7)
3525                         hfcmulti_conf(hc, bch->slot, num);
3526                 else {
3527                         printk(KERN_WARNING
3528                             "%s: HW_CONF_JOIN conf %d out of range\n",
3529                             __func__, num);
3530                         ret = -EINVAL;
3531                 }
3532                 break;
3533         case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3534                 if (debug & DEBUG_HFCMULTI_MSG)
3535                         printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3536                 hfcmulti_conf(hc, bch->slot, -1);
3537                 break;
3538         case MISDN_CTRL_HFC_ECHOCAN_ON:
3539                 if (debug & DEBUG_HFCMULTI_MSG)
3540                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3541                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3542                         vpm_echocan_on(hc, bch->slot, cq->p1);
3543                 else
3544                         ret = -EINVAL;
3545                 break;
3546
3547         case MISDN_CTRL_HFC_ECHOCAN_OFF:
3548                 if (debug & DEBUG_HFCMULTI_MSG)
3549                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3550                                 __func__);
3551                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3552                         vpm_echocan_off(hc, bch->slot);
3553                 else
3554                         ret = -EINVAL;
3555                 break;
3556         default:
3557                 printk(KERN_WARNING "%s: unknown Op %x\n",
3558                     __func__, cq->op);
3559                 ret = -EINVAL;
3560                 break;
3561         }
3562         return ret;
3563 }
3564
3565 static int
3566 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3567 {
3568         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3569         struct hfc_multi        *hc = bch->hw;
3570         int                     err = -EINVAL;
3571         u_long  flags;
3572
3573         if (bch->debug & DEBUG_HW)
3574                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3575                     __func__, cmd, arg);
3576         switch (cmd) {
3577         case CLOSE_CHANNEL:
3578                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3579                 if (test_bit(FLG_ACTIVE, &bch->Flags))
3580                         deactivate_bchannel(bch); /* locked there */
3581                 ch->protocol = ISDN_P_NONE;
3582                 ch->peer = NULL;
3583                 module_put(THIS_MODULE);
3584                 err = 0;
3585                 break;
3586         case CONTROL_CHANNEL:
3587                 spin_lock_irqsave(&hc->lock, flags);
3588                 err = channel_bctrl(bch, arg);
3589                 spin_unlock_irqrestore(&hc->lock, flags);
3590                 break;
3591         default:
3592                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3593                         __func__, cmd);
3594         }
3595         return err;
3596 }
3597
3598 /*
3599  * handle D-channel events
3600  *
3601  * handle state change event
3602  */
3603 static void
3604 ph_state_change(struct dchannel *dch)
3605 {
3606         struct hfc_multi *hc = dch->hw;
3607         int ch, i;
3608
3609         if (!dch) {
3610                 printk(KERN_WARNING "%s: ERROR given dch is NULL\n",
3611                     __func__);
3612                 return;
3613         }
3614         ch = dch->slot;
3615
3616         if (hc->type == 1) {
3617                 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3618                         if (debug & DEBUG_HFCMULTI_STATE)
3619                                 printk(KERN_DEBUG
3620                                     "%s: E1 TE (id=%d) newstate %x\n",
3621                                     __func__, hc->id, dch->state);
3622                 } else {
3623                         if (debug & DEBUG_HFCMULTI_STATE)
3624                                 printk(KERN_DEBUG
3625                                     "%s: E1 NT (id=%d) newstate %x\n",
3626                                     __func__, hc->id, dch->state);
3627                 }
3628                 switch (dch->state) {
3629                 case (1):
3630                         if (hc->e1_state != 1) {
3631                             for (i = 1; i <= 31; i++) {
3632                                 /* reset fifos on e1 activation */
3633                                 HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1);
3634                                 HFC_wait_nodebug(hc);
3635                                 HFC_outb_nodebug(hc,
3636                                         R_INC_RES_FIFO, V_RES_F);
3637                                 HFC_wait_nodebug(hc);
3638                             }
3639                         }
3640                         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3641                         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3642                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3643                         break;
3644
3645                 default:
3646                         if (hc->e1_state != 1)
3647                                 return;
3648                         test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3649                         _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3650                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3651                 }
3652                 hc->e1_state = dch->state;
3653         } else {
3654                 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3655                         if (debug & DEBUG_HFCMULTI_STATE)
3656                                 printk(KERN_DEBUG
3657                                     "%s: S/T TE newstate %x\n",
3658                                     __func__, dch->state);
3659                         switch (dch->state) {
3660                         case (0):
3661                                 l1_event(dch->l1, HW_RESET_IND);
3662                                 break;
3663                         case (3):
3664                                 l1_event(dch->l1, HW_DEACT_IND);
3665                                 break;
3666                         case (5):
3667                         case (8):
3668                                 l1_event(dch->l1, ANYSIGNAL);
3669                                 break;
3670                         case (6):
3671                                 l1_event(dch->l1, INFO2);
3672                                 break;
3673                         case (7):
3674                                 l1_event(dch->l1, INFO4_P8);
3675                                 break;
3676                         }
3677                 } else {
3678                         if (debug & DEBUG_HFCMULTI_STATE)
3679                                 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3680                                     __func__, dch->state);
3681                         switch (dch->state) {
3682                         case (2):
3683                                 if (hc->chan[ch].nt_timer == 0) {
3684                                         hc->chan[ch].nt_timer = -1;
3685                                         HFC_outb(hc, R_ST_SEL,
3686                                             hc->chan[ch].port);
3687                                         /* undocumented: delay after R_ST_SEL */
3688                                         udelay(1);
3689                                         HFC_outb(hc, A_ST_WR_STATE, 4 |
3690                                             V_ST_LD_STA); /* G4 */
3691                                         udelay(6); /* wait at least 5,21us */
3692                                         HFC_outb(hc, A_ST_WR_STATE, 4);
3693                                         dch->state = 4;
3694                                 } else {
3695                                         /* one extra count for the next event */
3696                                         hc->chan[ch].nt_timer =
3697                                             nt_t1_count[poll_timer] + 1;
3698                                         HFC_outb(hc, R_ST_SEL,
3699                                             hc->chan[ch].port);
3700                                         /* undocumented: delay after R_ST_SEL */
3701                                         udelay(1);
3702                                         /* allow G2 -> G3 transition */
3703                                         HFC_outb(hc, A_ST_WR_STATE, 2 |
3704                                             V_SET_G2_G3);
3705                                 }
3706                                 break;
3707                         case (1):
3708                                 hc->chan[ch].nt_timer = -1;
3709                                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3710                                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3711                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3712                                 break;
3713                         case (4):
3714                                 hc->chan[ch].nt_timer = -1;
3715                                 break;
3716                         case (3):
3717                                 hc->chan[ch].nt_timer = -1;
3718                                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3719                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3720                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3721                                 break;
3722                         }
3723                 }
3724         }
3725 }
3726
3727 /*
3728  * called for card mode init message
3729  */
3730
3731 static void
3732 hfcmulti_initmode(struct dchannel *dch)
3733 {
3734         struct hfc_multi *hc = dch->hw;
3735         u_char          a_st_wr_state, r_e1_wr_sta;
3736         int             i, pt;
3737
3738         if (debug & DEBUG_HFCMULTI_INIT)
3739                 printk(KERN_DEBUG "%s: entered\n", __func__);
3740
3741         if (hc->type == 1) {
3742                 hc->chan[hc->dslot].slot_tx = -1;
3743                 hc->chan[hc->dslot].slot_rx = -1;
3744                 hc->chan[hc->dslot].conf = -1;
3745                 if (hc->dslot) {
3746                         mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3747                                 -1, 0, -1, 0);
3748                         dch->timer.function = (void *) hfcmulti_dbusy_timer;
3749                         dch->timer.data = (long) dch;
3750                         init_timer(&dch->timer);
3751                 }
3752                 for (i = 1; i <= 31; i++) {
3753                         if (i == hc->dslot)
3754                                 continue;
3755                         hc->chan[i].slot_tx = -1;
3756                         hc->chan[i].slot_rx = -1;
3757                         hc->chan[i].conf = -1;
3758                         mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3759                 }
3760                 /* E1 */
3761                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3762                         HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3763                         HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3764                 }
3765                 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3766                         HFC_outb(hc, R_RX0, 0);
3767                         hc->hw.r_tx0 = 0 | V_OUT_EN;
3768                 } else {
3769                         HFC_outb(hc, R_RX0, 1);
3770                         hc->hw.r_tx0 = 1 | V_OUT_EN;
3771                 }
3772                 hc->hw.r_tx1 = V_ATX | V_NTRI;
3773                 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3774                 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3775                 HFC_outb(hc, R_TX_FR0, 0x00);
3776                 HFC_outb(hc, R_TX_FR1, 0xf8);
3777
3778                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3779                         HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3780
3781                 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3782
3783                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3784                         HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3785
3786                 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3787                         if (debug & DEBUG_HFCMULTI_INIT)
3788                                 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3789                                     __func__);
3790                         r_e1_wr_sta = 0; /* G0 */
3791                         hc->e1_getclock = 0;
3792                 } else {
3793                         if (debug & DEBUG_HFCMULTI_INIT)
3794                                 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3795                                     __func__);
3796                         r_e1_wr_sta = 0; /* F0 */
3797                         hc->e1_getclock = 1;
3798                 }
3799                 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3800                         HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3801                 else
3802                         HFC_outb(hc, R_SYNC_OUT, 0);
3803                 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3804                         hc->e1_getclock = 1;
3805                 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3806                         hc->e1_getclock = 0;
3807                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3808                         /* SLAVE (clock master) */
3809                         if (debug & DEBUG_HFCMULTI_INIT)
3810                                 printk(KERN_DEBUG
3811                                     "%s: E1 port is clock master "
3812                                     "(clock from PCM)\n", __func__);
3813                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3814                 } else {
3815                         if (hc->e1_getclock) {
3816                                 /* MASTER (clock slave) */
3817                                 if (debug & DEBUG_HFCMULTI_INIT)
3818                                         printk(KERN_DEBUG
3819                                             "%s: E1 port is clock slave "
3820                                             "(clock to PCM)\n", __func__);
3821                                 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3822                         } else {
3823                                 /* MASTER (clock master) */
3824                                 if (debug & DEBUG_HFCMULTI_INIT)
3825                                         printk(KERN_DEBUG "%s: E1 port is "
3826                                             "clock master "
3827                                             "(clock from QUARTZ)\n",
3828                                             __func__);
3829                                 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3830                                     V_PCM_SYNC | V_JATT_OFF);
3831                                 HFC_outb(hc, R_SYNC_OUT, 0);
3832                         }
3833                 }
3834                 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3835                 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3836                 HFC_outb(hc, R_PWM0, 0x50);
3837                 HFC_outb(hc, R_PWM1, 0xff);
3838                 /* state machine setup */
3839                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3840                 udelay(6); /* wait at least 5,21us */
3841                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3842                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3843                         hc->syncronized = 0;
3844                         plxsd_checksync(hc, 0);
3845                 }
3846         } else {
3847                 i = dch->slot;
3848                 hc->chan[i].slot_tx = -1;
3849                 hc->chan[i].slot_rx = -1;
3850                 hc->chan[i].conf = -1;
3851                 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3852                 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3853                 dch->timer.data = (long) dch;
3854                 init_timer(&dch->timer);
3855                 hc->chan[i - 2].slot_tx = -1;
3856                 hc->chan[i - 2].slot_rx = -1;
3857                 hc->chan[i - 2].conf = -1;
3858                 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3859                 hc->chan[i - 1].slot_tx = -1;
3860                 hc->chan[i - 1].slot_rx = -1;
3861                 hc->chan[i - 1].conf = -1;
3862                 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3863                 /* ST */
3864                 pt = hc->chan[i].port;
3865                 /* select interface */
3866                 HFC_outb(hc, R_ST_SEL, pt);
3867                 /* undocumented: delay after R_ST_SEL */
3868                 udelay(1);
3869                 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3870                         if (debug & DEBUG_HFCMULTI_INIT)
3871                                 printk(KERN_DEBUG
3872                                     "%s: ST port %d is NT-mode\n",
3873                                     __func__, pt);
3874                         /* clock delay */
3875                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3876                         a_st_wr_state = 1; /* G1 */
3877                         hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3878                 } else {
3879                         if (debug & DEBUG_HFCMULTI_INIT)
3880                                 printk(KERN_DEBUG
3881                                     "%s: ST port %d is TE-mode\n",
3882                                     __func__, pt);
3883                         /* clock delay */
3884                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3885                         a_st_wr_state = 2; /* F2 */
3886                         hc->hw.a_st_ctrl0[pt] = 0;
3887                 }
3888                 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3889                         hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3890                 /* line setup */
3891                 HFC_outb(hc, A_ST_CTRL0,  hc->hw.a_st_ctrl0[pt]);
3892                 /* disable E-channel */
3893                 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3894                     test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3895                         HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3896                 else
3897                         HFC_outb(hc, A_ST_CTRL1, 0);
3898                 /* enable B-channel receive */
3899                 HFC_outb(hc, A_ST_CTRL2,  V_B1_RX_EN | V_B2_RX_EN);
3900                 /* state machine setup */
3901                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3902                 udelay(6); /* wait at least 5,21us */
3903                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
3904                 hc->hw.r_sci_msk |= 1 << pt;
3905                 /* state machine interrupts */
3906                 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
3907                 /* unset sync on port */
3908                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3909                         hc->syncronized &=
3910                            ~(1 << hc->chan[dch->slot].port);
3911                         plxsd_checksync(hc, 0);
3912                 }
3913         }
3914         if (debug & DEBUG_HFCMULTI_INIT)
3915                 printk("%s: done\n", __func__);
3916 }
3917
3918
3919 static int
3920 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
3921     struct channel_req *rq)
3922 {
3923         int     err = 0;
3924         u_long  flags;
3925
3926         if (debug & DEBUG_HW_OPEN)
3927                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
3928                     dch->dev.id, __builtin_return_address(0));
3929         if (rq->protocol == ISDN_P_NONE)
3930                 return -EINVAL;
3931         if ((dch->dev.D.protocol != ISDN_P_NONE) &&
3932             (dch->dev.D.protocol != rq->protocol)) {
3933             if (debug & DEBUG_HFCMULTI_MODE)
3934                 printk(KERN_WARNING "%s: change protocol %x to %x\n",
3935                     __func__, dch->dev.D.protocol, rq->protocol);
3936         }
3937         if ((dch->dev.D.protocol == ISDN_P_TE_S0)
3938          && (rq->protocol != ISDN_P_TE_S0))
3939                 l1_event(dch->l1, CLOSE_CHANNEL);
3940         if (dch->dev.D.protocol != rq->protocol) {
3941                 if (rq->protocol == ISDN_P_TE_S0) {
3942                         err = create_l1(dch, hfcm_l1callback);
3943                         if (err)
3944                                 return err;
3945                 }
3946                 dch->dev.D.protocol = rq->protocol;
3947                 spin_lock_irqsave(&hc->lock, flags);
3948                 hfcmulti_initmode(dch);
3949                 spin_unlock_irqrestore(&hc->lock, flags);
3950         }
3951
3952         if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
3953             ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
3954             ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
3955             ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
3956                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
3957                     0, NULL, GFP_KERNEL);
3958         }
3959         rq->ch = &dch->dev.D;
3960         if (!try_module_get(THIS_MODULE))
3961                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3962         return 0;
3963 }
3964
3965 static int
3966 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
3967     struct channel_req *rq)
3968 {
3969         struct bchannel *bch;
3970         int             ch;
3971
3972         if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
3973                 return -EINVAL;
3974         if (rq->protocol == ISDN_P_NONE)
3975                 return -EINVAL;
3976         if (hc->type == 1)
3977                 ch = rq->adr.channel;
3978         else
3979                 ch = (rq->adr.channel - 1) + (dch->slot - 2);
3980         bch = hc->chan[ch].bch;
3981         if (!bch) {
3982                 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
3983                     __func__, ch);
3984                 return -EINVAL;
3985         }
3986         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
3987                 return -EBUSY; /* b-channel can be only open once */
3988         test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
3989         bch->ch.protocol = rq->protocol;
3990         hc->chan[ch].rx_off = 0;
3991         rq->ch = &bch->ch;
3992         if (!try_module_get(THIS_MODULE))
3993                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3994         return 0;
3995 }
3996
3997 /*
3998  * device control function
3999  */
4000 static int
4001 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4002 {
4003         int     ret = 0;
4004
4005         switch (cq->op) {
4006         case MISDN_CTRL_GETOP:
4007                 cq->op = 0;
4008                 break;
4009         default:
4010                 printk(KERN_WARNING "%s: unknown Op %x\n",
4011                     __func__, cq->op);
4012                 ret = -EINVAL;
4013                 break;
4014         }
4015         return ret;
4016 }
4017
4018 static int
4019 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4020 {
4021         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
4022         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
4023         struct hfc_multi        *hc = dch->hw;
4024         struct channel_req      *rq;
4025         int                     err = 0;
4026         u_long                  flags;
4027
4028         if (dch->debug & DEBUG_HW)
4029                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4030                     __func__, cmd, arg);
4031         switch (cmd) {
4032         case OPEN_CHANNEL:
4033                 rq = arg;
4034                 switch (rq->protocol) {
4035                 case ISDN_P_TE_S0:
4036                 case ISDN_P_NT_S0:
4037                         if (hc->type == 1) {
4038                                 err = -EINVAL;
4039                                 break;
4040                         }
4041                         err = open_dchannel(hc, dch, rq); /* locked there */
4042                         break;
4043                 case ISDN_P_TE_E1:
4044                 case ISDN_P_NT_E1:
4045                         if (hc->type != 1) {
4046                                 err = -EINVAL;
4047                                 break;
4048                         }
4049                         err = open_dchannel(hc, dch, rq); /* locked there */
4050                         break;
4051                 default:
4052                         spin_lock_irqsave(&hc->lock, flags);
4053                         err = open_bchannel(hc, dch, rq);
4054                         spin_unlock_irqrestore(&hc->lock, flags);
4055                 }
4056                 break;
4057         case CLOSE_CHANNEL:
4058                 if (debug & DEBUG_HW_OPEN)
4059                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4060                             __func__, dch->dev.id,
4061                             __builtin_return_address(0));
4062                 module_put(THIS_MODULE);
4063                 break;
4064         case CONTROL_CHANNEL:
4065                 spin_lock_irqsave(&hc->lock, flags);
4066                 err = channel_dctrl(dch, arg);
4067                 spin_unlock_irqrestore(&hc->lock, flags);
4068                 break;
4069         default:
4070                 if (dch->debug & DEBUG_HW)
4071                         printk(KERN_DEBUG "%s: unknown command %x\n",
4072                             __func__, cmd);
4073                 err = -EINVAL;
4074         }
4075         return err;
4076 }
4077
4078 /*
4079  * initialize the card
4080  */
4081
4082 /*
4083  * start timer irq, wait some time and check if we have interrupts.
4084  * if not, reset chip and try again.
4085  */
4086 static int
4087 init_card(struct hfc_multi *hc)
4088 {
4089         int     err = -EIO;
4090         u_long  flags;
4091         void    __iomem *plx_acc;
4092         u_long  plx_flags;
4093
4094         if (debug & DEBUG_HFCMULTI_INIT)
4095                 printk(KERN_DEBUG "%s: entered\n", __func__);
4096
4097         spin_lock_irqsave(&hc->lock, flags);
4098         /* set interrupts but leave global interrupt disabled */
4099         hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4100         disable_hwirq(hc);
4101         spin_unlock_irqrestore(&hc->lock, flags);
4102
4103         if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
4104             "HFC-multi", hc)) {
4105                 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4106                     hc->pci_dev->irq);
4107                 return -EIO;
4108         }
4109         hc->irq = hc->pci_dev->irq;
4110
4111         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4112                 spin_lock_irqsave(&plx_lock, plx_flags);
4113                 plx_acc = hc->plx_membase + PLX_INTCSR;
4114                 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4115                         plx_acc); /* enable PCI & LINT1 irq */
4116                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4117         }
4118
4119         if (debug & DEBUG_HFCMULTI_INIT)
4120                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4121                     __func__, hc->irq, hc->irqcnt);
4122         err = init_chip(hc);
4123         if (err)
4124                 goto error;
4125         /*
4126          * Finally enable IRQ output
4127          * this is only allowed, if an IRQ routine is allready
4128          * established for this HFC, so don't do that earlier
4129          */
4130         spin_lock_irqsave(&hc->lock, flags);
4131         enable_hwirq(hc);
4132         spin_unlock_irqrestore(&hc->lock, flags);
4133         /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4134         set_current_state(TASK_UNINTERRUPTIBLE);
4135         schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4136         /* turn IRQ off until chip is completely initialized */
4137         spin_lock_irqsave(&hc->lock, flags);
4138         disable_hwirq(hc);
4139         spin_unlock_irqrestore(&hc->lock, flags);
4140         if (debug & DEBUG_HFCMULTI_INIT)
4141                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4142                     __func__, hc->irq, hc->irqcnt);
4143         if (hc->irqcnt) {
4144                 if (debug & DEBUG_HFCMULTI_INIT)
4145                         printk(KERN_DEBUG "%s: done\n", __func__);
4146
4147                 return 0;
4148         }
4149         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4150                 printk(KERN_INFO "ignoring missing interrupts\n");
4151                 return 0;
4152         }
4153
4154         printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4155                 hc->irq);
4156
4157         err = -EIO;
4158
4159 error:
4160         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4161                 spin_lock_irqsave(&plx_lock, plx_flags);
4162                 plx_acc = hc->plx_membase + PLX_INTCSR;
4163                 writew(0x00, plx_acc); /*disable IRQs*/
4164                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4165         }
4166
4167         if (debug & DEBUG_HFCMULTI_INIT)
4168                 printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq);
4169         if (hc->irq) {
4170                 free_irq(hc->irq, hc);
4171                 hc->irq = 0;
4172         }
4173
4174         if (debug & DEBUG_HFCMULTI_INIT)
4175                 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4176         return err;
4177 }
4178
4179 /*
4180  * find pci device and set it up
4181  */
4182
4183 static int
4184 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4185                 const struct pci_device_id *ent)
4186 {
4187         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4188
4189         printk(KERN_INFO
4190             "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4191             m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4192
4193         hc->pci_dev = pdev;
4194         if (m->clock2)
4195                 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4196
4197         if (ent->device == 0xB410) {
4198                 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4199                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4200                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4201                 hc->slots = 32;
4202         }
4203
4204         if (hc->pci_dev->irq <= 0) {
4205                 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4206                 return -EIO;
4207         }
4208         if (pci_enable_device(hc->pci_dev)) {
4209                 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4210                 return -EIO;
4211         }
4212         hc->leds = m->leds;
4213         hc->ledstate = 0xAFFEAFFE;
4214         hc->opticalsupport = m->opticalsupport;
4215
4216         /* set memory access methods */
4217         if (m->io_mode) /* use mode from card config */
4218                 hc->io_mode = m->io_mode;
4219         switch (hc->io_mode) {
4220         case HFC_IO_MODE_PLXSD:
4221                 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4222                 hc->slots = 128; /* required */
4223                 /* fall through */
4224         case HFC_IO_MODE_PCIMEM:
4225                 hc->HFC_outb = HFC_outb_pcimem;
4226                 hc->HFC_inb = HFC_inb_pcimem;
4227                 hc->HFC_inw = HFC_inw_pcimem;
4228                 hc->HFC_wait = HFC_wait_pcimem;
4229                 hc->read_fifo = read_fifo_pcimem;
4230                 hc->write_fifo = write_fifo_pcimem;
4231                 break;
4232         case HFC_IO_MODE_REGIO:
4233                 hc->HFC_outb = HFC_outb_regio;
4234                 hc->HFC_inb = HFC_inb_regio;
4235                 hc->HFC_inw = HFC_inw_regio;
4236                 hc->HFC_wait = HFC_wait_regio;
4237                 hc->read_fifo = read_fifo_regio;
4238                 hc->write_fifo = write_fifo_regio;
4239                 break;
4240         default:
4241                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4242                 pci_disable_device(hc->pci_dev);
4243                 return -EIO;
4244         }
4245         hc->HFC_outb_nodebug = hc->HFC_outb;
4246         hc->HFC_inb_nodebug = hc->HFC_inb;
4247         hc->HFC_inw_nodebug = hc->HFC_inw;
4248         hc->HFC_wait_nodebug = hc->HFC_wait;
4249 #ifdef HFC_REGISTER_DEBUG
4250         hc->HFC_outb = HFC_outb_debug;
4251         hc->HFC_inb = HFC_inb_debug;
4252         hc->HFC_inw = HFC_inw_debug;
4253         hc->HFC_wait = HFC_wait_debug;
4254 #endif
4255         hc->pci_iobase = 0;
4256         hc->pci_membase = NULL;
4257         hc->plx_membase = NULL;
4258
4259         switch (hc->io_mode) {
4260         case HFC_IO_MODE_PLXSD:
4261                 hc->plx_origmembase =  hc->pci_dev->resource[0].start;
4262                 /* MEMBASE 1 is PLX PCI Bridge */
4263
4264                 if (!hc->plx_origmembase) {
4265                         printk(KERN_WARNING
4266                           "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4267                         pci_disable_device(hc->pci_dev);
4268                         return -EIO;
4269                 }
4270
4271                 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4272                 if (!hc->plx_membase) {
4273                         printk(KERN_WARNING
4274                             "HFC-multi: failed to remap plx address space. "
4275                             "(internal error)\n");
4276                         pci_disable_device(hc->pci_dev);
4277                         return -EIO;
4278                 }
4279                 printk(KERN_INFO
4280                     "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4281                     (u_long)hc->plx_membase, hc->plx_origmembase);
4282
4283                 hc->pci_origmembase =  hc->pci_dev->resource[2].start;
4284                     /* MEMBASE 1 is PLX PCI Bridge */
4285                 if (!hc->pci_origmembase) {
4286                         printk(KERN_WARNING
4287                             "HFC-multi: No IO-Memory for PCI card found\n");
4288                         pci_disable_device(hc->pci_dev);
4289                         return -EIO;
4290                 }
4291
4292                 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4293                 if (!hc->pci_membase) {
4294                         printk(KERN_WARNING "HFC-multi: failed to remap io "
4295                             "address space. (internal error)\n");
4296                         pci_disable_device(hc->pci_dev);
4297                         return -EIO;
4298                 }
4299
4300                 printk(KERN_INFO
4301                     "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4302                     "leds-type %d\n",
4303                     hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4304                     hc->pci_dev->irq, HZ, hc->leds);
4305                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4306                 break;
4307         case HFC_IO_MODE_PCIMEM:
4308                 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4309                 if (!hc->pci_origmembase) {
4310                         printk(KERN_WARNING
4311                             "HFC-multi: No IO-Memory for PCI card found\n");
4312                         pci_disable_device(hc->pci_dev);
4313                         return -EIO;
4314                 }
4315
4316                 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4317                 if (!hc->pci_membase) {
4318                         printk(KERN_WARNING
4319                             "HFC-multi: failed to remap io address space. "
4320                             "(internal error)\n");
4321                         pci_disable_device(hc->pci_dev);
4322                         return -EIO;
4323                 }
4324                 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
4325                     "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4326                     hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4327                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4328                 break;
4329         case HFC_IO_MODE_REGIO:
4330                 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4331                 if (!hc->pci_iobase) {
4332                         printk(KERN_WARNING
4333                                 "HFC-multi: No IO for PCI card found\n");
4334                         pci_disable_device(hc->pci_dev);
4335                         return -EIO;
4336                 }
4337
4338                 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4339                         printk(KERN_WARNING "HFC-multi: failed to request "
4340                             "address space at 0x%08lx (internal error)\n",
4341                             hc->pci_iobase);
4342                         pci_disable_device(hc->pci_dev);
4343                         return -EIO;
4344                 }
4345
4346                 printk(KERN_INFO
4347                     "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4348                     m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4349                     hc->pci_dev->irq, HZ, hc->leds);
4350                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4351                 break;
4352         default:
4353                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4354                 pci_disable_device(hc->pci_dev);
4355                 return -EIO;
4356         }
4357
4358         pci_set_drvdata(hc->pci_dev, hc);
4359
4360         /* At this point the needed PCI config is done */
4361         /* fifos are still not enabled */
4362         return 0;
4363 }
4364
4365
4366 /*
4367  * remove port
4368  */
4369
4370 static void
4371 release_port(struct hfc_multi *hc, struct dchannel *dch)
4372 {
4373         int     pt, ci, i = 0;
4374         u_long  flags;
4375         struct bchannel *pb;
4376
4377         ci = dch->slot;
4378         pt = hc->chan[ci].port;
4379
4380         if (debug & DEBUG_HFCMULTI_INIT)
4381                 printk(KERN_DEBUG "%s: entered for port %d\n",
4382                         __func__, pt + 1);
4383
4384         if (pt >= hc->ports) {
4385                 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4386                      __func__, pt + 1);
4387                 return;
4388         }
4389
4390         if (debug & DEBUG_HFCMULTI_INIT)
4391                 printk(KERN_DEBUG "%s: releasing port=%d\n",
4392                     __func__, pt + 1);
4393
4394         if (dch->dev.D.protocol == ISDN_P_TE_S0)
4395                 l1_event(dch->l1, CLOSE_CHANNEL);
4396
4397         hc->chan[ci].dch = NULL;
4398
4399         if (hc->created[pt]) {
4400                 hc->created[pt] = 0;
4401                 mISDN_unregister_device(&dch->dev);
4402         }
4403
4404         spin_lock_irqsave(&hc->lock, flags);
4405
4406         if (dch->timer.function) {
4407                 del_timer(&dch->timer);
4408                 dch->timer.function = NULL;
4409         }
4410
4411         if (hc->type == 1) { /* E1 */
4412                 /* remove sync */
4413                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4414                         hc->syncronized = 0;
4415                         plxsd_checksync(hc, 1);
4416                 }
4417                 /* free channels */
4418                 for (i = 0; i <= 31; i++) {
4419                         if (hc->chan[i].bch) {
4420                                 if (debug & DEBUG_HFCMULTI_INIT)
4421                                         printk(KERN_DEBUG
4422                                             "%s: free port %d channel %d\n",
4423                                             __func__, hc->chan[i].port+1, i);
4424                                 pb = hc->chan[i].bch;
4425                                 hc->chan[i].bch = NULL;
4426                                 spin_unlock_irqrestore(&hc->lock, flags);
4427                                 mISDN_freebchannel(pb);
4428                                 kfree(pb);
4429                                 kfree(hc->chan[i].coeff);
4430                                 spin_lock_irqsave(&hc->lock, flags);
4431                         }
4432                 }
4433         } else {
4434                 /* remove sync */
4435                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4436                         hc->syncronized &=
4437                            ~(1 << hc->chan[ci].port);
4438                         plxsd_checksync(hc, 1);
4439                 }
4440                 /* free channels */
4441                 if (hc->chan[ci - 2].bch) {
4442                         if (debug & DEBUG_HFCMULTI_INIT)
4443                                 printk(KERN_DEBUG
4444                                     "%s: free port %d channel %d\n",
4445                                     __func__, hc->chan[ci - 2].port+1,
4446                                     ci - 2);
4447                         pb = hc->chan[ci - 2].bch;
4448                         hc->chan[ci - 2].bch = NULL;
4449                         spin_unlock_irqrestore(&hc->lock, flags);
4450                         mISDN_freebchannel(pb);
4451                         kfree(pb);
4452                         kfree(hc->chan[ci - 2].coeff);
4453                         spin_lock_irqsave(&hc->lock, flags);
4454                 }
4455                 if (hc->chan[ci - 1].bch) {
4456                         if (debug & DEBUG_HFCMULTI_INIT)
4457                                 printk(KERN_DEBUG
4458                                     "%s: free port %d channel %d\n",
4459                                     __func__, hc->chan[ci - 1].port+1,
4460                                     ci - 1);
4461                         pb = hc->chan[ci - 1].bch;
4462                         hc->chan[ci - 1].bch = NULL;
4463                         spin_unlock_irqrestore(&hc->lock, flags);
4464                         mISDN_freebchannel(pb);
4465                         kfree(pb);
4466                         kfree(hc->chan[ci - 1].coeff);
4467                         spin_lock_irqsave(&hc->lock, flags);
4468                 }
4469         }
4470
4471         spin_unlock_irqrestore(&hc->lock, flags);
4472
4473         if (debug & DEBUG_HFCMULTI_INIT)
4474                 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4475         mISDN_freedchannel(dch);
4476         kfree(dch);
4477
4478         if (debug & DEBUG_HFCMULTI_INIT)
4479                 printk(KERN_DEBUG "%s: done!\n", __func__);
4480 }
4481
4482 static void
4483 release_card(struct hfc_multi *hc)
4484 {
4485         u_long  flags;
4486         int     ch;
4487
4488         if (debug & DEBUG_HFCMULTI_INIT)
4489                 printk(KERN_WARNING "%s: release card (%d) entered\n",
4490                     __func__, hc->id);
4491
4492         spin_lock_irqsave(&hc->lock, flags);
4493         disable_hwirq(hc);
4494         spin_unlock_irqrestore(&hc->lock, flags);
4495
4496         udelay(1000);
4497
4498         /* dimm leds */
4499         if (hc->leds)
4500                 hfcmulti_leds(hc);
4501
4502         /* disable D-channels & B-channels */
4503         if (debug & DEBUG_HFCMULTI_INIT)
4504                 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4505                     __func__);
4506         for (ch = 0; ch <= 31; ch++) {
4507                 if (hc->chan[ch].dch)
4508                         release_port(hc, hc->chan[ch].dch);
4509         }
4510
4511         /* release hardware & irq */
4512         if (hc->irq) {
4513                 if (debug & DEBUG_HFCMULTI_INIT)
4514                         printk(KERN_WARNING "%s: free irq %d\n",
4515                             __func__, hc->irq);
4516                 free_irq(hc->irq, hc);
4517                 hc->irq = 0;
4518
4519         }
4520         release_io_hfcmulti(hc);
4521
4522         if (debug & DEBUG_HFCMULTI_INIT)
4523                 printk(KERN_WARNING "%s: remove instance from list\n",
4524                      __func__);
4525         list_del(&hc->list);
4526
4527         if (debug & DEBUG_HFCMULTI_INIT)
4528                 printk(KERN_WARNING "%s: delete instance\n", __func__);
4529         if (hc == syncmaster)
4530                 syncmaster = NULL;
4531         kfree(hc);
4532         if (debug & DEBUG_HFCMULTI_INIT)
4533                 printk(KERN_WARNING "%s: card successfully removed\n",
4534                     __func__);
4535 }
4536
4537 static int
4538 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4539 {
4540         struct dchannel *dch;
4541         struct bchannel *bch;
4542         int             ch, ret = 0;
4543         char            name[MISDN_MAX_IDLEN];
4544
4545         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4546         if (!dch)
4547                 return -ENOMEM;
4548         dch->debug = debug;
4549         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4550         dch->hw = hc;
4551         dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4552         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4553             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4554         dch->dev.D.send = handle_dmsg;
4555         dch->dev.D.ctrl = hfcm_dctrl;
4556         dch->dev.nrbchan = (hc->dslot)?30:31;
4557         dch->slot = hc->dslot;
4558         hc->chan[hc->dslot].dch = dch;
4559         hc->chan[hc->dslot].port = 0;
4560         hc->chan[hc->dslot].nt_timer = -1;
4561         for (ch = 1; ch <= 31; ch++) {
4562                 if (ch == hc->dslot) /* skip dchannel */
4563                         continue;
4564                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4565                 if (!bch) {
4566                         printk(KERN_ERR "%s: no memory for bchannel\n",
4567                             __func__);
4568                         ret = -ENOMEM;
4569                         goto free_chan;
4570                 }
4571                 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4572                 if (!hc->chan[ch].coeff) {
4573                         printk(KERN_ERR "%s: no memory for coeffs\n",
4574                             __func__);
4575                         ret = -ENOMEM;
4576                         goto free_chan;
4577                 }
4578                 bch->nr = ch;
4579                 bch->slot = ch;
4580                 bch->debug = debug;
4581                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4582                 bch->hw = hc;
4583                 bch->ch.send = handle_bmsg;
4584                 bch->ch.ctrl = hfcm_bctrl;
4585                 bch->ch.nr = ch;
4586                 list_add(&bch->ch.list, &dch->dev.bchannels);
4587                 hc->chan[ch].bch = bch;
4588                 hc->chan[ch].port = 0;
4589                 set_channelmap(bch->nr, dch->dev.channelmap);
4590         }
4591         /* set optical line type */
4592         if (port[Port_cnt] & 0x001) {
4593                 if (!m->opticalsupport)  {
4594                         printk(KERN_INFO
4595                             "This board has no optical "
4596                             "support\n");
4597                 } else {
4598                         if (debug & DEBUG_HFCMULTI_INIT)
4599                                 printk(KERN_DEBUG
4600                                     "%s: PORT set optical "
4601                                     "interfacs: card(%d) "
4602                                     "port(%d)\n",
4603                                     __func__,
4604                                     HFC_cnt + 1, 1);
4605                         test_and_set_bit(HFC_CFG_OPTICAL,
4606                             &hc->chan[hc->dslot].cfg);
4607                 }
4608         }
4609         /* set LOS report */
4610         if (port[Port_cnt] & 0x004) {
4611                 if (debug & DEBUG_HFCMULTI_INIT)
4612                         printk(KERN_DEBUG "%s: PORT set "
4613                             "LOS report: card(%d) port(%d)\n",
4614                             __func__, HFC_cnt + 1, 1);
4615                 test_and_set_bit(HFC_CFG_REPORT_LOS,
4616                     &hc->chan[hc->dslot].cfg);
4617         }
4618         /* set AIS report */
4619         if (port[Port_cnt] & 0x008) {
4620                 if (debug & DEBUG_HFCMULTI_INIT)
4621                         printk(KERN_DEBUG "%s: PORT set "
4622                             "AIS report: card(%d) port(%d)\n",
4623                             __func__, HFC_cnt + 1, 1);
4624                 test_and_set_bit(HFC_CFG_REPORT_AIS,
4625                     &hc->chan[hc->dslot].cfg);
4626         }
4627         /* set SLIP report */
4628         if (port[Port_cnt] & 0x010) {
4629                 if (debug & DEBUG_HFCMULTI_INIT)
4630                         printk(KERN_DEBUG
4631                             "%s: PORT set SLIP report: "
4632                             "card(%d) port(%d)\n",
4633                             __func__, HFC_cnt + 1, 1);
4634                 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4635                     &hc->chan[hc->dslot].cfg);
4636         }
4637         /* set RDI report */
4638         if (port[Port_cnt] & 0x020) {
4639                 if (debug & DEBUG_HFCMULTI_INIT)
4640                         printk(KERN_DEBUG
4641                             "%s: PORT set RDI report: "
4642                             "card(%d) port(%d)\n",
4643                             __func__, HFC_cnt + 1, 1);
4644                 test_and_set_bit(HFC_CFG_REPORT_RDI,
4645                     &hc->chan[hc->dslot].cfg);
4646         }
4647         /* set CRC-4 Mode */
4648         if (!(port[Port_cnt] & 0x100)) {
4649                 if (debug & DEBUG_HFCMULTI_INIT)
4650                         printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4651                                 " card(%d) port(%d)\n",
4652                                 __func__, HFC_cnt + 1, 1);
4653                 test_and_set_bit(HFC_CFG_CRC4,
4654                     &hc->chan[hc->dslot].cfg);
4655         } else {
4656                 if (debug & DEBUG_HFCMULTI_INIT)
4657                         printk(KERN_DEBUG "%s: PORT turn off CRC4"
4658                                 " report: card(%d) port(%d)\n",
4659                                 __func__, HFC_cnt + 1, 1);
4660         }
4661         /* set forced clock */
4662         if (port[Port_cnt] & 0x0200) {
4663                 if (debug & DEBUG_HFCMULTI_INIT)
4664                         printk(KERN_DEBUG "%s: PORT force getting clock from "
4665                                 "E1: card(%d) port(%d)\n",
4666                                 __func__, HFC_cnt + 1, 1);
4667                 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4668         } else
4669         if (port[Port_cnt] & 0x0400) {
4670                 if (debug & DEBUG_HFCMULTI_INIT)
4671                         printk(KERN_DEBUG "%s: PORT force putting clock to "
4672                                 "E1: card(%d) port(%d)\n",
4673                                 __func__, HFC_cnt + 1, 1);
4674                 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4675         }
4676         /* set JATT PLL */
4677         if (port[Port_cnt] & 0x0800) {
4678                 if (debug & DEBUG_HFCMULTI_INIT)
4679                         printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4680                                 "E1: card(%d) port(%d)\n",
4681                                 __func__, HFC_cnt + 1, 1);
4682                 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4683         }
4684         /* set elastic jitter buffer */
4685         if (port[Port_cnt] & 0x3000) {
4686                 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4687                 if (debug & DEBUG_HFCMULTI_INIT)
4688                         printk(KERN_DEBUG
4689                             "%s: PORT set elastic "
4690                             "buffer to %d: card(%d) port(%d)\n",
4691                             __func__, hc->chan[hc->dslot].jitter,
4692                             HFC_cnt + 1, 1);
4693         } else
4694                 hc->chan[hc->dslot].jitter = 2; /* default */
4695         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4696         ret = mISDN_register_device(&dch->dev, name);
4697         if (ret)
4698                 goto free_chan;
4699         hc->created[0] = 1;
4700         return ret;
4701 free_chan:
4702         release_port(hc, dch);
4703         return ret;
4704 }
4705
4706 static int
4707 init_multi_port(struct hfc_multi *hc, int pt)
4708 {
4709         struct dchannel *dch;
4710         struct bchannel *bch;
4711         int             ch, i, ret = 0;
4712         char            name[MISDN_MAX_IDLEN];
4713
4714         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4715         if (!dch)
4716                 return -ENOMEM;
4717         dch->debug = debug;
4718         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4719         dch->hw = hc;
4720         dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4721         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4722             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4723         dch->dev.D.send = handle_dmsg;
4724         dch->dev.D.ctrl = hfcm_dctrl;
4725         dch->dev.nrbchan = 2;
4726         i = pt << 2;
4727         dch->slot = i + 2;
4728         hc->chan[i + 2].dch = dch;
4729         hc->chan[i + 2].port = pt;
4730         hc->chan[i + 2].nt_timer = -1;
4731         for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4732                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4733                 if (!bch) {
4734                         printk(KERN_ERR "%s: no memory for bchannel\n",
4735                             __func__);
4736                         ret = -ENOMEM;
4737                         goto free_chan;
4738                 }
4739                 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4740                 if (!hc->chan[i + ch].coeff) {
4741                         printk(KERN_ERR "%s: no memory for coeffs\n",
4742                             __func__);
4743                         ret = -ENOMEM;
4744                         goto free_chan;
4745                 }
4746                 bch->nr = ch + 1;
4747                 bch->slot = i + ch;
4748                 bch->debug = debug;
4749                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4750                 bch->hw = hc;
4751                 bch->ch.send = handle_bmsg;
4752                 bch->ch.ctrl = hfcm_bctrl;
4753                 bch->ch.nr = ch + 1;
4754                 list_add(&bch->ch.list, &dch->dev.bchannels);
4755                 hc->chan[i + ch].bch = bch;
4756                 hc->chan[i + ch].port = pt;
4757                 set_channelmap(bch->nr, dch->dev.channelmap);
4758         }
4759         /* set master clock */
4760         if (port[Port_cnt] & 0x001) {
4761                 if (debug & DEBUG_HFCMULTI_INIT)
4762                         printk(KERN_DEBUG
4763                             "%s: PROTOCOL set master clock: "
4764                             "card(%d) port(%d)\n",
4765                             __func__, HFC_cnt + 1, pt + 1);
4766                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4767                         printk(KERN_ERR "Error: Master clock "
4768                             "for port(%d) of card(%d) is only"
4769                             " possible with TE-mode\n",
4770                             pt + 1, HFC_cnt + 1);
4771                         ret = -EINVAL;
4772                         goto free_chan;
4773                 }
4774                 if (hc->masterclk >= 0) {
4775                         printk(KERN_ERR "Error: Master clock "
4776                             "for port(%d) of card(%d) already "
4777                             "defined for port(%d)\n",
4778                             pt + 1, HFC_cnt + 1, hc->masterclk+1);
4779                         ret = -EINVAL;
4780                         goto free_chan;
4781                 }
4782                 hc->masterclk = pt;
4783         }
4784         /* set transmitter line to non capacitive */
4785         if (port[Port_cnt] & 0x002) {
4786                 if (debug & DEBUG_HFCMULTI_INIT)
4787                         printk(KERN_DEBUG
4788                             "%s: PROTOCOL set non capacitive "
4789                             "transmitter: card(%d) port(%d)\n",
4790                             __func__, HFC_cnt + 1, pt + 1);
4791                 test_and_set_bit(HFC_CFG_NONCAP_TX,
4792                     &hc->chan[i + 2].cfg);
4793         }
4794         /* disable E-channel */
4795         if (port[Port_cnt] & 0x004) {
4796         if (debug & DEBUG_HFCMULTI_INIT)
4797                         printk(KERN_DEBUG
4798                             "%s: PROTOCOL disable E-channel: "
4799                             "card(%d) port(%d)\n",
4800                             __func__, HFC_cnt + 1, pt + 1);
4801                 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4802                     &hc->chan[i + 2].cfg);
4803         }
4804         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d/%d",
4805                 hc->type, HFC_cnt + 1, pt + 1);
4806         ret = mISDN_register_device(&dch->dev, name);
4807         if (ret)
4808                 goto free_chan;
4809         hc->created[pt] = 1;
4810         return ret;
4811 free_chan:
4812         release_port(hc, dch);
4813         return ret;
4814 }
4815
4816 static int
4817 hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
4818 {
4819         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4820         int             ret_err = 0;
4821         int             pt;
4822         struct hfc_multi        *hc;
4823         u_long          flags;
4824         u_char          dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4825         int             i;
4826
4827         if (HFC_cnt >= MAX_CARDS) {
4828                 printk(KERN_ERR "too many cards (max=%d).\n",
4829                         MAX_CARDS);
4830                 return -EINVAL;
4831         }
4832         if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4833                 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4834                     "type[%d] %d was supplied as module parameter\n",
4835                     m->vendor_name, m->card_name, m->type, HFC_cnt,
4836                     type[HFC_cnt] & 0xff);
4837                 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4838                         "first, to see cards and their types.");
4839                 return -EINVAL;
4840         }
4841         if (debug & DEBUG_HFCMULTI_INIT)
4842                 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4843                     __func__, m->vendor_name, m->card_name, m->type,
4844                     type[HFC_cnt]);
4845
4846         /* allocate card+fifo structure */
4847         hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4848         if (!hc) {
4849                 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4850                 return -ENOMEM;
4851         }
4852         spin_lock_init(&hc->lock);
4853         hc->mtyp = m;
4854         hc->type =  m->type;
4855         hc->ports = m->ports;
4856         hc->id = HFC_cnt;
4857         hc->pcm = pcm[HFC_cnt];
4858         hc->io_mode = iomode[HFC_cnt];
4859         if (dslot[HFC_cnt] < 0 && hc->type == 1) {
4860                 hc->dslot = 0;
4861                 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
4862                         "31 B-channels\n");
4863         } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32 && hc->type == 1) {
4864                 hc->dslot = dslot[HFC_cnt];
4865                 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
4866                         "time slot %d\n", dslot[HFC_cnt]);
4867         } else
4868                 hc->dslot = 16;
4869
4870         /* set chip specific features */
4871         hc->masterclk = -1;
4872         if (type[HFC_cnt] & 0x100) {
4873                 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
4874                 hc->silence = 0xff; /* ulaw silence */
4875         } else
4876                 hc->silence = 0x2a; /* alaw silence */
4877         if ((poll >> 1) > sizeof(hc->silence_data)) {
4878                 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
4879                         "please fix\n");
4880                 return -EINVAL;
4881         }
4882         for (i = 0; i < (poll >> 1); i++)
4883                 hc->silence_data[i] = hc->silence;
4884
4885         if (!(type[HFC_cnt] & 0x200))
4886                 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4887
4888         if (type[HFC_cnt] & 0x800)
4889                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4890         if (type[HFC_cnt] & 0x1000) {
4891                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4892                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4893         }
4894         if (type[HFC_cnt] & 0x4000)
4895                 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
4896         if (type[HFC_cnt] & 0x8000)
4897                 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
4898         hc->slots = 32;
4899         if (type[HFC_cnt] & 0x10000)
4900                 hc->slots = 64;
4901         if (type[HFC_cnt] & 0x20000)
4902                 hc->slots = 128;
4903         if (type[HFC_cnt] & 0x80000) {
4904                 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
4905                 hc->wdcount = 0;
4906                 hc->wdbyte = V_GPIO_OUT2;
4907                 printk(KERN_NOTICE "Watchdog enabled\n");
4908         }
4909
4910         /* setup pci, hc->slots may change due to PLXSD */
4911         ret_err = setup_pci(hc, pdev, ent);
4912         if (ret_err) {
4913                 if (hc == syncmaster)
4914                         syncmaster = NULL;
4915                 kfree(hc);
4916                 return ret_err;
4917         }
4918
4919         /* crate channels */
4920         for (pt = 0; pt < hc->ports; pt++) {
4921                 if (Port_cnt >= MAX_PORTS) {
4922                         printk(KERN_ERR "too many ports (max=%d).\n",
4923                                 MAX_PORTS);
4924                         ret_err = -EINVAL;
4925                         goto free_card;
4926                 }
4927                 if (hc->type == 1)
4928                         ret_err = init_e1_port(hc, m);
4929                 else
4930                         ret_err = init_multi_port(hc, pt);
4931                 if (debug & DEBUG_HFCMULTI_INIT)
4932                         printk(KERN_DEBUG
4933                             "%s: Registering D-channel, card(%d) port(%d)"
4934                             "result %d\n",
4935                             __func__, HFC_cnt + 1, pt, ret_err);
4936
4937                 if (ret_err) {
4938                         while (pt) { /* release already registered ports */
4939                                 pt--;
4940                                 release_port(hc, hc->chan[(pt << 2) + 2].dch);
4941                         }
4942                         goto free_card;
4943                 }
4944                 Port_cnt++;
4945         }
4946
4947         /* disp switches */
4948         switch (m->dip_type) {
4949         case DIP_4S:
4950                 /*
4951                  * Get DIP setting for beroNet 1S/2S/4S cards
4952                  * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
4953                  * GPI 19/23 (R_GPI_IN2))
4954                  */
4955                 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
4956                         ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
4957                         (~HFC_inb(hc, R_GPI_IN2) & 0x08);
4958
4959                 /* Port mode (TE/NT) jumpers */
4960                 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4)  & 0xf);
4961
4962                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
4963                         pmj = ~pmj & 0xf;
4964
4965                 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
4966                         m->vendor_name, m->card_name, dips, pmj);
4967                 break;
4968         case DIP_8S:
4969                 /*
4970                  * Get DIP Setting for beroNet 8S0+ cards
4971                  * Enable PCI auxbridge function
4972                  */
4973                 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
4974                 /* prepare access to auxport */
4975                 outw(0x4000, hc->pci_iobase + 4);
4976                 /*
4977                  * some dummy reads are required to
4978                  * read valid DIP switch data
4979                  */
4980                 dips = inb(hc->pci_iobase);
4981                 dips = inb(hc->pci_iobase);
4982                 dips = inb(hc->pci_iobase);
4983                 dips = ~inb(hc->pci_iobase) & 0x3F;
4984                 outw(0x0, hc->pci_iobase + 4);
4985                 /* disable PCI auxbridge function */
4986                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
4987                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4988                     m->vendor_name, m->card_name, dips);
4989                 break;
4990         case DIP_E1:
4991                 /*
4992                  * get DIP Setting for beroNet E1 cards
4993                  * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
4994                  */
4995                 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
4996                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4997                     m->vendor_name, m->card_name, dips);
4998                 break;
4999         }
5000
5001         /* add to list */
5002         spin_lock_irqsave(&HFClock, flags);
5003         list_add_tail(&hc->list, &HFClist);
5004         spin_unlock_irqrestore(&HFClock, flags);
5005
5006         /* initialize hardware */
5007         ret_err = init_card(hc);
5008         if (ret_err) {
5009                 printk(KERN_ERR "init card returns %d\n", ret_err);
5010                 release_card(hc);
5011                 return ret_err;
5012         }
5013
5014         /* start IRQ and return */
5015         spin_lock_irqsave(&hc->lock, flags);
5016         enable_hwirq(hc);
5017         spin_unlock_irqrestore(&hc->lock, flags);
5018         return 0;
5019
5020 free_card:
5021         release_io_hfcmulti(hc);
5022         if (hc == syncmaster)
5023                 syncmaster = NULL;
5024         kfree(hc);
5025         return ret_err;
5026 }
5027
5028 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5029 {
5030         struct hfc_multi        *card = pci_get_drvdata(pdev);
5031         u_long                  flags;
5032
5033         if (debug)
5034                 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5035                     "device:%x subvendor:%x subdevice:%x\n",
5036                     pdev->vendor, pdev->device,
5037                     pdev->subsystem_vendor, pdev->subsystem_device);
5038
5039         if (card) {
5040                 spin_lock_irqsave(&HFClock, flags);
5041                 release_card(card);
5042                 spin_unlock_irqrestore(&HFClock, flags);
5043         }  else {
5044                 if (debug)
5045                         printk(KERN_WARNING "%s: drvdata allready removed\n",
5046                             __func__);
5047         }
5048 }
5049
5050 #define VENDOR_CCD      "Cologne Chip AG"
5051 #define VENDOR_BN       "beroNet GmbH"
5052 #define VENDOR_DIG      "Digium Inc."
5053 #define VENDOR_JH       "Junghanns.NET GmbH"
5054 #define VENDOR_PRIM     "PrimuX"
5055
5056 static const struct hm_map hfcm_map[] = {
5057 /*0*/   {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
5058 /*1*/   {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0},
5059 /*2*/   {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
5060 /*3*/   {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
5061 /*4*/   {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
5062 /*5*/   {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
5063 /*6*/   {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0},
5064 /*7*/   {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
5065 /*8*/   {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
5066 /*9*/   {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
5067 /*10*/  {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
5068 /*11*/  {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
5069
5070 /*12*/  {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
5071 /*13*/  {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5072                 HFC_IO_MODE_REGIO},
5073 /*14*/  {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
5074 /*15*/  {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
5075
5076 /*16*/  {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
5077 /*17*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5078 /*18*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5079
5080 /*19*/  {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
5081 /*20*/  {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
5082 /*21*/  {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5083 /*22*/  {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5084
5085 /*23*/  {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
5086 /*24*/  {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
5087 /*25*/  {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
5088
5089 /*26*/  {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5090                 HFC_IO_MODE_PLXSD},
5091 /*27*/  {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5092                 HFC_IO_MODE_PLXSD},
5093 /*28*/  {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
5094 /*29*/  {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
5095 /*30*/  {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
5096 };
5097
5098 #undef H
5099 #define H(x)    ((unsigned long)&hfcm_map[x])
5100 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5101
5102         /* Cards with HFC-4S Chip */
5103         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5104                 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5105         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5106                 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5107         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5108                 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5109         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5110                 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5111         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5112                 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5113         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5114                 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5115         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5116                 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5117         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5118                 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5119         { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5120                 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5121         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5122                 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5123         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5124                 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5125         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5126                 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5127         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5128                 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5129         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5130                 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5131
5132         /* Cards with HFC-8S Chip */
5133         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5134         PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5135         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5136         PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5137         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5138         PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5139         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5140         PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5141         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5142                 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST  */
5143         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5144                 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST  */
5145         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5146                 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5147         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5148                 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5149
5150
5151         /* Cards with HFC-E1 Chip */
5152         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5153                 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5154         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5155                 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5156         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5157                 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5158         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5159                 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5160
5161         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5162                 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5163         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5164                 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5165         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5166                 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5167
5168         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5169                 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5170         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5171                 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5172         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5173                 0, 0, 0},
5174         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5175                 0, 0, 0},
5176         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5177                 0, 0, 0},
5178         {0, }
5179 };
5180 #undef H
5181
5182 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5183
5184 static int
5185 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5186 {
5187         struct hm_map   *m = (struct hm_map *)ent->driver_data;
5188         int             ret;
5189
5190         if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5191             ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5192             ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5193             ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5194                 printk(KERN_ERR
5195                     "Unknown HFC multiport controller (vendor:%x device:%x "
5196                     "subvendor:%x subdevice:%x)\n", ent->vendor, ent->device,
5197                     ent->subvendor, ent->subdevice);
5198                 printk(KERN_ERR
5199                     "Please contact the driver maintainer for support.\n");
5200                 return -ENODEV;
5201         }
5202         ret = hfcmulti_init(pdev, ent);
5203         if (ret)
5204                 return ret;
5205         HFC_cnt++;
5206         printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5207         return 0;
5208 }
5209
5210 static struct pci_driver hfcmultipci_driver = {
5211         .name           = "hfc_multi",
5212         .probe          = hfcmulti_probe,
5213         .remove         = __devexit_p(hfc_remove_pci),
5214         .id_table       = hfmultipci_ids,
5215 };
5216
5217 static void __exit
5218 HFCmulti_cleanup(void)
5219 {
5220         struct hfc_multi *card, *next;
5221
5222         /* get rid of all devices of this driver */
5223         list_for_each_entry_safe(card, next, &HFClist, list)
5224                 release_card(card);
5225         pci_unregister_driver(&hfcmultipci_driver);
5226 }
5227
5228 static int __init
5229 HFCmulti_init(void)
5230 {
5231         int err;
5232
5233         printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5234
5235 #ifdef IRQ_DEBUG
5236         printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5237 #endif
5238
5239         spin_lock_init(&HFClock);
5240         spin_lock_init(&plx_lock);
5241
5242         if (debug & DEBUG_HFCMULTI_INIT)
5243                 printk(KERN_DEBUG "%s: init entered\n", __func__);
5244
5245         switch (poll) {
5246         case 0:
5247                 poll_timer = 6;
5248                 poll = 128;
5249                 break;
5250         case 8:
5251                 poll_timer = 2;
5252                 break;
5253         case 16:
5254                 poll_timer = 3;
5255                 break;
5256         case 32:
5257                 poll_timer = 4;
5258                 break;
5259         case 64:
5260                 poll_timer = 5;
5261                 break;
5262         case 128:
5263                 poll_timer = 6;
5264                 break;
5265         case 256:
5266                 poll_timer = 7;
5267                 break;
5268         default:
5269                 printk(KERN_ERR
5270                     "%s: Wrong poll value (%d).\n", __func__, poll);
5271                 err = -EINVAL;
5272                 return err;
5273
5274         }
5275
5276         err = pci_register_driver(&hfcmultipci_driver);
5277         if (err < 0) {
5278                 printk(KERN_ERR "error registering pci driver: %x\n", err);
5279                 return err;
5280         }
5281         return 0;
5282 }
5283
5284
5285 module_init(HFCmulti_init);
5286 module_exit(HFCmulti_cleanup);