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   1 /*
   2  * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
   3  *
   4  * Author       Andreas Eversberg (jolly@eversberg.eu)
   5  * ported to mqueue mechanism:
   6  *              Peter Sprenger (sprengermoving-bytes.de)
   7  *
   8  * inspired by existing hfc-pci driver:
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil (kkeil@suse.de)
  11  * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2, or (at your option)
  16  * any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  * Thanks to Cologne Chip AG for this great controller!
  29  */
  30
  31 /*
  32  * module parameters:
  33  * type:
  34  *      By default (0), the card is automatically detected.
  35  *      Or use the following combinations:
  36  *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
  37  * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
  38  * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
  39  *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
  40  *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
  41  *      Bit 10    = spare
  42  *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
  43  * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
  44  *      Bit 13    = spare
  45  *      Bit 14    = 0x04000 = Use external ram (128K)
  46  *      Bit 15    = 0x08000 = Use external ram (512K)
  47  *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
  48  * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
  49  *      Bit 18    = spare
  50  *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
  51  * (all other bits are reserved and shall be 0)
  52  *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
  53  *               bus (PCM master)
  54  *
  55  * port: (optional or required for all ports on all installed cards)
  56  *      HFC-4S/HFC-8S only bits:
  57  *      Bit 0     = 0x001 = Use master clock for this S/T interface
  58  *                          (ony once per chip).
  59  *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
  60  *                          Don't use this unless you know what you are doing!
  61  *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
  62  *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
  63  *               received from port 1
  64  *
  65  *      HFC-E1 only bits:
  66  *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
  67  *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
  68  *      Bit 2     = 0x0004 = Report LOS
  69  *      Bit 3     = 0x0008 = Report AIS
  70  *      Bit 4     = 0x0010 = Report SLIP
  71  *      Bit 5     = 0x0020 = Report RDI
  72  *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
  73  *                           mode instead.
  74  *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
  75  * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
  76  *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
  77  *                           (E1 only)
  78  *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
  79  *                           for default.
  80  * (all other bits are reserved and shall be 0)
  81  *
  82  * debug:
  83  *      NOTE: only one debug value must be given for all cards
  84  *      enable debugging (see hfc_multi.h for debug options)
  85  *
  86  * poll:
  87  *      NOTE: only one poll value must be given for all cards
  88  *      Give the number of samples for each fifo process.
  89  *      By default 128 is used. Decrease to reduce delay, increase to
  90  *      reduce cpu load. If unsure, don't mess with it!
  91  *      Valid is 8, 16, 32, 64, 128, 256.
  92  *
  93  * pcm:
  94  *      NOTE: only one pcm value must be given for every card.
  95  *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
  96  *      By default (0), the PCM bus id is 100 for the card that is PCM master.
  97  *      If multiple cards are PCM master (because they are not interconnected),
  98  *      each card with PCM master will have increasing PCM id.
  99  *      All PCM busses with the same ID are expected to be connected and have
 100  *      common time slots slots.
 101  *      Only one chip of the PCM bus must be master, the others slave.
 102  *      -1 means no support of PCM bus not even.
 103  *      Omit this value, if all cards are interconnected or none is connected.
 104  *      If unsure, don't give this parameter.
 105  *
 106  * dslot:
 107  *      NOTE: only one poll value must be given for every card.
 108  *      Also this value must be given for non-E1 cards. If omitted, the E1
 109  *      card has D-channel on time slot 16, which is default.
 110  *      If 1..15 or 17..31, an alternate time slot is used for D-channel.
 111  *      In this case, the application must be able to handle this.
 112  *      If -1 is given, the D-channel is disabled and all 31 slots can be used
 113  *      for B-channel. (only for specific applications)
 114  *      If you don't know how to use it, you don't need it!
 115  *
 116  * iomode:
 117  *      NOTE: only one mode value must be given for every card.
 118  *      -> See hfc_multi.h for HFC_IO_MODE_* values
 119  *      By default, the IO mode is pci memory IO (MEMIO).
 120  *      Some cards requre specific IO mode, so it cannot be changed.
 121  *      It may be usefull to set IO mode to register io (REGIO) to solve
 122  *      PCI bridge problems.
 123  *      If unsure, don't give this parameter.
 124  *
 125  * clockdelay_nt:
 126  *      NOTE: only one clockdelay_nt value must be given once for all cards.
 127  *      Give the value of the clock control register (A_ST_CLK_DLY)
 128  *      of the S/T interfaces in NT mode.
 129  *      This register is needed for the TBR3 certification, so don't change it.
 130  *
 131  * clockdelay_te:
 132  *      NOTE: only one clockdelay_te value must be given once
 133  *      Give the value of the clock control register (A_ST_CLK_DLY)
 134  *      of the S/T interfaces in TE mode.
 135  *      This register is needed for the TBR3 certification, so don't change it.
 136  */
 137
 138 /*
 139  * debug register access (never use this, it will flood your system log)
 140  * #define HFC_REGISTER_DEBUG
 141  */
 142
 143 #define HFC_MULTI_VERSION       "2.03"
 144
 145 #include <linux/module.h>
 146 #include <linux/pci.h>
 147 #include <linux/delay.h>
 148 #include <linux/mISDNhw.h>
 149 #include <linux/mISDNdsp.h>
 150
 151 /*
 152 #define IRQCOUNT_DEBUG
 153 #define IRQ_DEBUG
 154 */
 155
 156 #include "hfc_multi.h"
 157 #ifdef ECHOPREP
 158 #include "gaintab.h"
 159 #endif
 160
 161 #define MAX_CARDS       8
 162 #define MAX_PORTS       (8 * MAX_CARDS)
 163
 164 static LIST_HEAD(HFClist);
 165 static spinlock_t HFClock; /* global hfc list lock */
 166
 167 static void ph_state_change(struct dchannel *);
 168
 169 static struct hfc_multi *syncmaster;
 170 static int plxsd_master; /* if we have a master card (yet) */
 171 static spinlock_t plx_lock; /* may not acquire other lock inside */
 172
 173 #define TYP_E1          1
 174 #define TYP_4S          4
 175 #define TYP_8S          8
 176
 177 static int poll_timer = 6;      /* default = 128 samples = 16ms */
 178 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
 179 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
 180 #define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
 181 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
 182                                    (0x60 MUST be included!) */
 183 static u_char silence = 0xff;   /* silence by LAW */
 184
 185 #define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
 186 #define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
 187 #define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */
 188
 189 /*
 190  * module stuff
 191  */
 192
 193 static uint     type[MAX_CARDS];
 194 static uint     pcm[MAX_CARDS];
 195 static uint     dslot[MAX_CARDS];
 196 static uint     iomode[MAX_CARDS];
 197 static uint     port[MAX_PORTS];
 198 static uint     debug;
 199 static uint     poll;
 200 static uint     timer;
 201 static uint     clockdelay_te = CLKDEL_TE;
 202 static uint     clockdelay_nt = CLKDEL_NT;
 203
 204 static int      HFC_cnt, Port_cnt, PCM_cnt = 99;
 205
 206 MODULE_AUTHOR("Andreas Eversberg");
 207 MODULE_LICENSE("GPL");
 208 MODULE_VERSION(HFC_MULTI_VERSION);
 209 module_param(debug, uint, S_IRUGO | S_IWUSR);
 210 module_param(poll, uint, S_IRUGO | S_IWUSR);
 211 module_param(timer, uint, S_IRUGO | S_IWUSR);
 212 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
 213 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
 214 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
 215 module_param_array(pcm, uint, NULL, S_IRUGO | S_IWUSR);
 216 module_param_array(dslot, uint, NULL, S_IRUGO | S_IWUSR);
 217 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
 218 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
 219
 220 #ifdef HFC_REGISTER_DEBUG
 221 #define HFC_outb(hc, reg, val) \
 222         (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
 223 #define HFC_outb_nodebug(hc, reg, val) \
 224         (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
 225 #define HFC_inb(hc, reg) \
 226         (hc->HFC_inb(hc, reg, __func__, __LINE__))
 227 #define HFC_inb_nodebug(hc, reg) \
 228         (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
 229 #define HFC_inw(hc, reg) \
 230         (hc->HFC_inw(hc, reg, __func__, __LINE__))
 231 #define HFC_inw_nodebug(hc, reg) \
 232         (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
 233 #define HFC_wait(hc) \
 234         (hc->HFC_wait(hc, __func__, __LINE__))
 235 #define HFC_wait_nodebug(hc) \
 236         (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
 237 #else
 238 #define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
 239 #define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
 240 #define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
 241 #define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
 242 #define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
 243 #define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
 244 #define HFC_wait(hc)                    (hc->HFC_wait(hc))
 245 #define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
 246 #endif
 247
 248 /* HFC_IO_MODE_PCIMEM */
 249 static void
 250 #ifdef HFC_REGISTER_DEBUG
 251 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
 252                 const char *function, int line)
 253 #else
 254 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
 255 #endif
 256 {
 257         writeb(val, (hc->pci_membase)+reg);
 258 }
 259 static u_char
 260 #ifdef HFC_REGISTER_DEBUG
 261 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 262 #else
 263 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
 264 #endif
 265 {
 266         return readb((hc->pci_membase)+reg);
 267 }
 268 static u_short
 269 #ifdef HFC_REGISTER_DEBUG
 270 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 271 #else
 272 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
 273 #endif
 274 {
 275         return readw((hc->pci_membase)+reg);
 276 }
 277 static void
 278 #ifdef HFC_REGISTER_DEBUG
 279 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
 280 #else
 281 HFC_wait_pcimem(struct hfc_multi *hc)
 282 #endif
 283 {
 284         while (readb((hc->pci_membase)+R_STATUS) & V_BUSY);
 285 }
 286
 287 /* HFC_IO_MODE_REGIO */
 288 static void
 289 #ifdef HFC_REGISTER_DEBUG
 290 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
 291         const char *function, int line)
 292 #else
 293 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
 294 #endif
 295 {
 296         outb(reg, (hc->pci_iobase)+4);
 297         outb(val, hc->pci_iobase);
 298 }
 299 static u_char
 300 #ifdef HFC_REGISTER_DEBUG
 301 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 302 #else
 303 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
 304 #endif
 305 {
 306         outb(reg, (hc->pci_iobase)+4);
 307         return inb(hc->pci_iobase);
 308 }
 309 static u_short
 310 #ifdef HFC_REGISTER_DEBUG
 311 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 312 #else
 313 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
 314 #endif
 315 {
 316         outb(reg, (hc->pci_iobase)+4);
 317         return inw(hc->pci_iobase);
 318 }
 319 static void
 320 #ifdef HFC_REGISTER_DEBUG
 321 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
 322 #else
 323 HFC_wait_regio(struct hfc_multi *hc)
 324 #endif
 325 {
 326         outb(R_STATUS, (hc->pci_iobase)+4);
 327         while (inb(hc->pci_iobase) & V_BUSY);
 328 }
 329
 330 #ifdef HFC_REGISTER_DEBUG
 331 static void
 332 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
 333                 const char *function, int line)
 334 {
 335         char regname[256] = "", bits[9] = "xxxxxxxx";
 336         int i;
 337
 338         i = -1;
 339         while (hfc_register_names[++i].name) {
 340                 if (hfc_register_names[i].reg == reg)
 341                         strcat(regname, hfc_register_names[i].name);
 342         }
 343         if (regname[0] == '\0')
 344                 strcpy(regname, "register");
 345
 346         bits[7] = '0'+(!!(val&1));
 347         bits[6] = '0'+(!!(val&2));
 348         bits[5] = '0'+(!!(val&4));
 349         bits[4] = '0'+(!!(val&8));
 350         bits[3] = '0'+(!!(val&16));
 351         bits[2] = '0'+(!!(val&32));
 352         bits[1] = '0'+(!!(val&64));
 353         bits[0] = '0'+(!!(val&128));
 354         printk(KERN_DEBUG
 355             "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
 356             hc->id, reg, regname, val, bits, function, line);
 357         HFC_outb_nodebug(hc, reg, val);
 358 }
 359 static u_char
 360 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 361 {
 362         char regname[256] = "", bits[9] = "xxxxxxxx";
 363         u_char val = HFC_inb_nodebug(hc, reg);
 364         int i;
 365
 366         i = 0;
 367         while (hfc_register_names[i++].name)
 368                 ;
 369         while (hfc_register_names[++i].name) {
 370                 if (hfc_register_names[i].reg == reg)
 371                         strcat(regname, hfc_register_names[i].name);
 372         }
 373         if (regname[0] == '\0')
 374                 strcpy(regname, "register");
 375
 376         bits[7] = '0'+(!!(val&1));
 377         bits[6] = '0'+(!!(val&2));
 378         bits[5] = '0'+(!!(val&4));
 379         bits[4] = '0'+(!!(val&8));
 380         bits[3] = '0'+(!!(val&16));
 381         bits[2] = '0'+(!!(val&32));
 382         bits[1] = '0'+(!!(val&64));
 383         bits[0] = '0'+(!!(val&128));
 384         printk(KERN_DEBUG
 385             "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
 386             hc->id, reg, regname, val, bits, function, line);
 387         return val;
 388 }
 389 static u_short
 390 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 391 {
 392         char regname[256] = "";
 393         u_short val = HFC_inw_nodebug(hc, reg);
 394         int i;
 395
 396         i = 0;
 397         while (hfc_register_names[i++].name)
 398                 ;
 399         while (hfc_register_names[++i].name) {
 400                 if (hfc_register_names[i].reg == reg)
 401                         strcat(regname, hfc_register_names[i].name);
 402         }
 403         if (regname[0] == '\0')
 404                 strcpy(regname, "register");
 405
 406         printk(KERN_DEBUG
 407             "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
 408             hc->id, reg, regname, val, function, line);
 409         return val;
 410 }
 411 static void
 412 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
 413 {
 414         printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
 415             hc->id, function, line);
 416         HFC_wait_nodebug(hc);
 417 }
 418 #endif
 419
 420 /* write fifo data (REGIO) */
 421 static void
 422 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 423 {
 424         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 425         while (len>>2) {
 426                 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
 427                 data += 4;
 428                 len -= 4;
 429         }
 430         while (len>>1) {
 431                 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
 432                 data += 2;
 433                 len -= 2;
 434         }
 435         while (len) {
 436                 outb(*data, hc->pci_iobase);
 437                 data++;
 438                 len--;
 439         }
 440 }
 441 /* write fifo data (PCIMEM) */
 442 static void
 443 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 444 {
 445         while (len>>2) {
 446                 writel(cpu_to_le32(*(u32 *)data),
 447                         hc->pci_membase + A_FIFO_DATA0);
 448                 data += 4;
 449                 len -= 4;
 450         }
 451         while (len>>1) {
 452                 writew(cpu_to_le16(*(u16 *)data),
 453                         hc->pci_membase + A_FIFO_DATA0);
 454                 data += 2;
 455                 len -= 2;
 456         }
 457         while (len) {
 458                 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
 459                 data++;
 460                 len--;
 461         }
 462 }
 463 /* read fifo data (REGIO) */
 464 static void
 465 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 466 {
 467         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 468         while (len>>2) {
 469                 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
 470                 data += 4;
 471                 len -= 4;
 472         }
 473         while (len>>1) {
 474                 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
 475                 data += 2;
 476                 len -= 2;
 477         }
 478         while (len) {
 479                 *data = inb(hc->pci_iobase);
 480                 data++;
 481                 len--;
 482         }
 483 }
 484
 485 /* read fifo data (PCIMEM) */
 486 static void
 487 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 488 {
 489         while (len>>2) {
 490                 *(u32 *)data =
 491                         le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
 492                 data += 4;
 493                 len -= 4;
 494         }
 495         while (len>>1) {
 496                 *(u16 *)data =
 497                         le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
 498                 data += 2;
 499                 len -= 2;
 500         }
 501         while (len) {
 502                 *data = readb(hc->pci_membase + A_FIFO_DATA0);
 503                 data++;
 504                 len--;
 505         }
 506 }
 507
 508
 509 static void
 510 enable_hwirq(struct hfc_multi *hc)
 511 {
 512         hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
 513         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 514 }
 515
 516 static void
 517 disable_hwirq(struct hfc_multi *hc)
 518 {
 519         hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
 520         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 521 }
 522
 523 #define NUM_EC 2
 524 #define MAX_TDM_CHAN 32
 525
 526
 527 inline void
 528 enablepcibridge(struct hfc_multi *c)
 529 {
 530         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
 531 }
 532
 533 inline void
 534 disablepcibridge(struct hfc_multi *c)
 535 {
 536         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
 537 }
 538
 539 inline unsigned char
 540 readpcibridge(struct hfc_multi *hc, unsigned char address)
 541 {
 542         unsigned short cipv;
 543         unsigned char data;
 544
 545         if (!hc->pci_iobase)
 546                 return 0;
 547
 548         /* slow down a PCI read access by 1 PCI clock cycle */
 549         HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
 550
 551         if (address == 0)
 552                 cipv = 0x4000;
 553         else
 554                 cipv = 0x5800;
 555
 556         /* select local bridge port address by writing to CIP port */
 557         /* data = HFC_inb(c, cipv); * was _io before */
 558         outw(cipv, hc->pci_iobase + 4);
 559         data = inb(hc->pci_iobase);
 560
 561         /* restore R_CTRL for normal PCI read cycle speed */
 562         HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
 563
 564         return data;
 565 }
 566
 567 inline void
 568 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
 569 {
 570         unsigned short cipv;
 571         unsigned int datav;
 572
 573         if (!hc->pci_iobase)
 574                 return;
 575
 576         if (address == 0)
 577                 cipv = 0x4000;
 578         else
 579                 cipv = 0x5800;
 580
 581         /* select local bridge port address by writing to CIP port */
 582         outw(cipv, hc->pci_iobase + 4);
 583         /* define a 32 bit dword with 4 identical bytes for write sequence */
 584         datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
 585             ((__u32) data << 24);
 586
 587         /*
 588          * write this 32 bit dword to the bridge data port
 589          * this will initiate a write sequence of up to 4 writes to the same
 590          * address on the local bus interface the number of write accesses
 591          * is undefined but >=1 and depends on the next PCI transaction
 592          * during write sequence on the local bus
 593          */
 594         outl(datav, hc->pci_iobase);
 595 }
 596
 597 inline void
 598 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
 599 {
 600         /* Do data pin read low byte */
 601         HFC_outb(hc, R_GPIO_OUT1, reg);
 602 }
 603
 604 inline void
 605 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
 606 {
 607         cpld_set_reg(hc, reg);
 608
 609         enablepcibridge(hc);
 610         writepcibridge(hc, 1, val);
 611         disablepcibridge(hc);
 612
 613         return;
 614 }
 615
 616 inline unsigned char
 617 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
 618 {
 619         unsigned char bytein;
 620
 621         cpld_set_reg(hc, reg);
 622
 623         /* Do data pin read low byte */
 624         HFC_outb(hc, R_GPIO_OUT1, reg);
 625
 626         enablepcibridge(hc);
 627         bytein = readpcibridge(hc, 1);
 628         disablepcibridge(hc);
 629
 630         return bytein;
 631 }
 632
 633 inline void
 634 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
 635 {
 636         cpld_write_reg(hc, 0, 0xff & addr);
 637         cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
 638 }
 639
 640 inline unsigned short
 641 vpm_read_address(struct hfc_multi *c)
 642 {
 643         unsigned short addr;
 644         unsigned short highbit;
 645
 646         addr = cpld_read_reg(c, 0);
 647         highbit = cpld_read_reg(c, 1);
 648
 649         addr = addr | (highbit << 8);
 650
 651         return addr & 0x1ff;
 652 }
 653
 654 inline unsigned char
 655 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
 656 {
 657         unsigned char res;
 658
 659         vpm_write_address(c, addr);
 660
 661         if (!which)
 662                 cpld_set_reg(c, 2);
 663         else
 664                 cpld_set_reg(c, 3);
 665
 666         enablepcibridge(c);
 667         res = readpcibridge(c, 1);
 668         disablepcibridge(c);
 669
 670         cpld_set_reg(c, 0);
 671
 672         return res;
 673 }
 674
 675 inline void
 676 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
 677     unsigned char data)
 678 {
 679         vpm_write_address(c, addr);
 680
 681         enablepcibridge(c);
 682
 683         if (!which)
 684                 cpld_set_reg(c, 2);
 685         else
 686                 cpld_set_reg(c, 3);
 687
 688         writepcibridge(c, 1, data);
 689
 690         cpld_set_reg(c, 0);
 691
 692         disablepcibridge(c);
 693
 694         {
 695         unsigned char regin;
 696         regin = vpm_in(c, which, addr);
 697         if (regin != data)
 698                 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
 699                         "0x%x\n", data, addr, regin);
 700         }
 701
 702 }
 703
 704
 705 static void
 706 vpm_init(struct hfc_multi *wc)
 707 {
 708         unsigned char reg;
 709         unsigned int mask;
 710         unsigned int i, x, y;
 711         unsigned int ver;
 712
 713         for (x = 0; x < NUM_EC; x++) {
 714                 /* Setup GPIO's */
 715                 if (!x) {
 716                         ver = vpm_in(wc, x, 0x1a0);
 717                         printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
 718                 }
 719
 720                 for (y = 0; y < 4; y++) {
 721                         vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
 722                         vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
 723                         vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
 724                 }
 725
 726                 /* Setup TDM path - sets fsync and tdm_clk as inputs */
 727                 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
 728                 vpm_out(wc, x, 0x1a3, reg & ~2);
 729
 730                 /* Setup Echo length (256 taps) */
 731                 vpm_out(wc, x, 0x022, 1);
 732                 vpm_out(wc, x, 0x023, 0xff);
 733
 734                 /* Setup timeslots */
 735                 vpm_out(wc, x, 0x02f, 0x00);
 736                 mask = 0x02020202 << (x * 4);
 737
 738                 /* Setup the tdm channel masks for all chips */
 739                 for (i = 0; i < 4; i++)
 740                         vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
 741
 742                 /* Setup convergence rate */
 743                 printk(KERN_DEBUG "VPM: A-law mode\n");
 744                 reg = 0x00 | 0x10 | 0x01;
 745                 vpm_out(wc, x, 0x20, reg);
 746                 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
 747                 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
 748
 749                 vpm_out(wc, x, 0x24, 0x02);
 750                 reg = vpm_in(wc, x, 0x24);
 751                 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
 752
 753                 /* Initialize echo cans */
 754                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 755                         if (mask & (0x00000001 << i))
 756                                 vpm_out(wc, x, i, 0x00);
 757                 }
 758
 759                 /*
 760                  * ARM arch at least disallows a udelay of
 761                  * more than 2ms... it gives a fake "__bad_udelay"
 762                  * reference at link-time.
 763                  * long delays in kernel code are pretty sucky anyway
 764                  * for now work around it using 5 x 2ms instead of 1 x 10ms
 765                  */
 766
 767                 udelay(2000);
 768                 udelay(2000);
 769                 udelay(2000);
 770                 udelay(2000);
 771                 udelay(2000);
 772
 773                 /* Put in bypass mode */
 774                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 775                         if (mask & (0x00000001 << i))
 776                                 vpm_out(wc, x, i, 0x01);
 777                 }
 778
 779                 /* Enable bypass */
 780                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 781                         if (mask & (0x00000001 << i))
 782                                 vpm_out(wc, x, 0x78 + i, 0x01);
 783                 }
 784
 785         }
 786 }
 787
 788 #ifdef UNUSED
 789 static void
 790 vpm_check(struct hfc_multi *hctmp)
 791 {
 792         unsigned char gpi2;
 793
 794         gpi2 = HFC_inb(hctmp, R_GPI_IN2);
 795
 796         if ((gpi2 & 0x3) != 0x3)
 797                 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
 798 }
 799 #endif /* UNUSED */
 800
 801
 802 /*
 803  * Interface to enable/disable the HW Echocan
 804  *
 805  * these functions are called within a spin_lock_irqsave on
 806  * the channel instance lock, so we are not disturbed by irqs
 807  *
 808  * we can later easily change the interface to make  other
 809  * things configurable, for now we configure the taps
 810  *
 811  */
 812
 813 static void
 814 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
 815 {
 816         unsigned int timeslot;
 817         unsigned int unit;
 818         struct bchannel *bch = hc->chan[ch].bch;
 819 #ifdef TXADJ
 820         int txadj = -4;
 821         struct sk_buff *skb;
 822 #endif
 823         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 824                 return;
 825
 826         if (!bch)
 827                 return;
 828
 829 #ifdef TXADJ
 830         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 831                 sizeof(int), &txadj, GFP_ATOMIC);
 832         if (skb)
 833                 recv_Bchannel_skb(bch, skb);
 834 #endif
 835
 836         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 837         unit = ch % 4;
 838
 839         printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
 840             taps, timeslot);
 841
 842         vpm_out(hc, unit, timeslot, 0x7e);
 843 }
 844
 845 static void
 846 vpm_echocan_off(struct hfc_multi *hc, int ch)
 847 {
 848         unsigned int timeslot;
 849         unsigned int unit;
 850         struct bchannel *bch = hc->chan[ch].bch;
 851 #ifdef TXADJ
 852         int txadj = 0;
 853         struct sk_buff *skb;
 854 #endif
 855
 856         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 857                 return;
 858
 859         if (!bch)
 860                 return;
 861
 862 #ifdef TXADJ
 863         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 864                 sizeof(int), &txadj, GFP_ATOMIC);
 865         if (skb)
 866                 recv_Bchannel_skb(bch, skb);
 867 #endif
 868
 869         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 870         unit = ch % 4;
 871
 872         printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
 873             timeslot);
 874         /* FILLME */
 875         vpm_out(hc, unit, timeslot, 0x01);
 876 }
 877
 878
 879 /*
 880  * Speech Design resync feature
 881  * NOTE: This is called sometimes outside interrupt handler.
 882  * We must lock irqsave, so no other interrupt (other card) will occurr!
 883  * Also multiple interrupts may nest, so must lock each access (lists, card)!
 884  */
 885 static inline void
 886 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
 887 {
 888         struct hfc_multi *hc, *next, *pcmmaster = NULL;
 889         void __iomem *plx_acc_32;
 890         u_int pv;
 891         u_long flags;
 892
 893         spin_lock_irqsave(&HFClock, flags);
 894         spin_lock(&plx_lock); /* must be locked inside other locks */
 895
 896         if (debug & DEBUG_HFCMULTI_PLXSD)
 897                 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
 898                         __func__, syncmaster);
 899
 900         /* select new master */
 901         if (newmaster) {
 902                 if (debug & DEBUG_HFCMULTI_PLXSD)
 903                         printk(KERN_DEBUG "using provided controller\n");
 904         } else {
 905                 list_for_each_entry_safe(hc, next, &HFClist, list) {
 906                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 907                                 if (hc->syncronized) {
 908                                         newmaster = hc;
 909                                         break;
 910                                 }
 911                         }
 912                 }
 913         }
 914
 915         /* Disable sync of all cards */
 916         list_for_each_entry_safe(hc, next, &HFClist, list) {
 917                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 918                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 919                         pv = readl(plx_acc_32);
 920                         pv &= ~PLX_SYNC_O_EN;
 921                         writel(pv, plx_acc_32);
 922                         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
 923                                 pcmmaster = hc;
 924                                 if (hc->type == 1) {
 925                                         if (debug & DEBUG_HFCMULTI_PLXSD)
 926                                                 printk(KERN_DEBUG
 927                                                         "Schedule SYNC_I\n");
 928                                         hc->e1_resync |= 1; /* get SYNC_I */
 929                                 }
 930                         }
 931                 }
 932         }
 933
 934         if (newmaster) {
 935                 hc = newmaster;
 936                 if (debug & DEBUG_HFCMULTI_PLXSD)
 937                         printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
 938                                 "interface.\n", hc->id, hc);
 939                 /* Enable new sync master */
 940                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 941                 pv = readl(plx_acc_32);
 942                 pv |= PLX_SYNC_O_EN;
 943                 writel(pv, plx_acc_32);
 944                 /* switch to jatt PLL, if not disabled by RX_SYNC */
 945                 if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
 946                         if (debug & DEBUG_HFCMULTI_PLXSD)
 947                                 printk(KERN_DEBUG "Schedule jatt PLL\n");
 948                         hc->e1_resync |= 2; /* switch to jatt */
 949                 }
 950         } else {
 951                 if (pcmmaster) {
 952                         hc = pcmmaster;
 953                         if (debug & DEBUG_HFCMULTI_PLXSD)
 954                                 printk(KERN_DEBUG
 955                                         "id=%d (0x%p) = PCM master syncronized "
 956                                         "with QUARTZ\n", hc->id, hc);
 957                         if (hc->type == 1) {
 958                                 /* Use the crystal clock for the PCM
 959                                    master card */
 960                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 961                                         printk(KERN_DEBUG
 962                                             "Schedule QUARTZ for HFC-E1\n");
 963                                 hc->e1_resync |= 4; /* switch quartz */
 964                         } else {
 965                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 966                                         printk(KERN_DEBUG
 967                                             "QUARTZ is automatically "
 968                                             "enabled by HFC-%dS\n", hc->type);
 969                         }
 970                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 971                         pv = readl(plx_acc_32);
 972                         pv |= PLX_SYNC_O_EN;
 973                         writel(pv, plx_acc_32);
 974                 } else
 975                         if (!rm)
 976                                 printk(KERN_ERR "%s no pcm master, this MUST "
 977                                         "not happen!\n", __func__);
 978         }
 979         syncmaster = newmaster;
 980
 981         spin_unlock(&plx_lock);
 982         spin_unlock_irqrestore(&HFClock, flags);
 983 }
 984
 985 /* This must be called AND hc must be locked irqsave!!! */
 986 inline void
 987 plxsd_checksync(struct hfc_multi *hc, int rm)
 988 {
 989         if (hc->syncronized) {
 990                 if (syncmaster == NULL) {
 991                         if (debug & DEBUG_HFCMULTI_PLXSD)
 992                                 printk(KERN_WARNING "%s: GOT sync on card %d"
 993                                         " (id=%d)\n", __func__, hc->id + 1,
 994                                         hc->id);
 995                         hfcmulti_resync(hc, hc, rm);
 996                 }
 997         } else {
 998                 if (syncmaster == hc) {
 999                         if (debug & DEBUG_HFCMULTI_PLXSD)
1000                                 printk(KERN_WARNING "%s: LOST sync on card %d"
1001                                         " (id=%d)\n", __func__, hc->id + 1,
1002                                         hc->id);
1003                         hfcmulti_resync(hc, NULL, rm);
1004                 }
1005         }
1006 }
1007
1008
1009 /*
1010  * free hardware resources used by driver
1011  */
1012 static void
1013 release_io_hfcmulti(struct hfc_multi *hc)
1014 {
1015         void __iomem *plx_acc_32;
1016         u_int   pv;
1017         u_long  plx_flags;
1018
1019         if (debug & DEBUG_HFCMULTI_INIT)
1020                 printk(KERN_DEBUG "%s: entered\n", __func__);
1021
1022         /* soft reset also masks all interrupts */
1023         hc->hw.r_cirm |= V_SRES;
1024         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1025         udelay(1000);
1026         hc->hw.r_cirm &= ~V_SRES;
1027         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1028         udelay(1000); /* instead of 'wait' that may cause locking */
1029
1030         /* release Speech Design card, if PLX was initialized */
1031         if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1032                 if (debug & DEBUG_HFCMULTI_PLXSD)
1033                         printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1034                             __func__, hc->id + 1);
1035                 spin_lock_irqsave(&plx_lock, plx_flags);
1036                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1037                 writel(PLX_GPIOC_INIT, plx_acc_32);
1038                 pv = readl(plx_acc_32);
1039                 /* Termination off */
1040                 pv &= ~PLX_TERM_ON;
1041                 /* Disconnect the PCM */
1042                 pv |= PLX_SLAVE_EN_N;
1043                 pv &= ~PLX_MASTER_EN;
1044                 pv &= ~PLX_SYNC_O_EN;
1045                 /* Put the DSP in Reset */
1046                 pv &= ~PLX_DSP_RES_N;
1047                 writel(pv, plx_acc_32);
1048                 if (debug & DEBUG_HFCMULTI_INIT)
1049                         printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n",
1050                                 __func__, pv);
1051                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1052         }
1053
1054         /* disable memory mapped ports / io ports */
1055         test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1056         pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1057         if (hc->pci_membase)
1058                 iounmap(hc->pci_membase);
1059         if (hc->plx_membase)
1060                 iounmap(hc->plx_membase);
1061         if (hc->pci_iobase)
1062                 release_region(hc->pci_iobase, 8);
1063
1064         if (hc->pci_dev) {
1065                 pci_disable_device(hc->pci_dev);
1066                 pci_set_drvdata(hc->pci_dev, NULL);
1067         }
1068         if (debug & DEBUG_HFCMULTI_INIT)
1069                 printk(KERN_DEBUG "%s: done\n", __func__);
1070 }
1071
1072 /*
1073  * function called to reset the HFC chip. A complete software reset of chip
1074  * and fifos is done. All configuration of the chip is done.
1075  */
1076
1077 static int
1078 init_chip(struct hfc_multi *hc)
1079 {
1080         u_long                  flags, val, val2 = 0, rev;
1081         int                     i, err = 0;
1082         u_char                  r_conf_en, rval;
1083         void __iomem            *plx_acc_32;
1084         u_int                   pv;
1085         u_long                  plx_flags, hfc_flags;
1086         int                     plx_count;
1087         struct hfc_multi        *pos, *next, *plx_last_hc;
1088
1089         spin_lock_irqsave(&hc->lock, flags);
1090         /* reset all registers */
1091         memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1092
1093         /* revision check */
1094         if (debug & DEBUG_HFCMULTI_INIT)
1095                 printk(KERN_DEBUG "%s: entered\n", __func__);
1096         val = HFC_inb(hc, R_CHIP_ID)>>4;
1097         if (val != 0x8 && val != 0xc && val != 0xe) {
1098                 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1099                 err = -EIO;
1100                 goto out;
1101         }
1102         rev = HFC_inb(hc, R_CHIP_RV);
1103         printk(KERN_INFO
1104             "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1105             val, rev, (rev == 0) ? " (old FIFO handling)" : "");
1106         if (rev == 0) {
1107                 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1108                 printk(KERN_WARNING
1109                     "HFC_multi: NOTE: Your chip is revision 0, "
1110                     "ask Cologne Chip for update. Newer chips "
1111                     "have a better FIFO handling. Old chips "
1112                     "still work but may have slightly lower "
1113                     "HDLC transmit performance.\n");
1114         }
1115         if (rev > 1) {
1116                 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1117                     "consider chip revision = %ld. The chip / "
1118                     "bridge may not work.\n", rev);
1119         }
1120
1121         /* set s-ram size */
1122         hc->Flen = 0x10;
1123         hc->Zmin = 0x80;
1124         hc->Zlen = 384;
1125         hc->DTMFbase = 0x1000;
1126         if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1127                 if (debug & DEBUG_HFCMULTI_INIT)
1128                         printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1129                             __func__);
1130                 hc->hw.r_ctrl |= V_EXT_RAM;
1131                 hc->hw.r_ram_sz = 1;
1132                 hc->Flen = 0x20;
1133                 hc->Zmin = 0xc0;
1134                 hc->Zlen = 1856;
1135                 hc->DTMFbase = 0x2000;
1136         }
1137         if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1138                 if (debug & DEBUG_HFCMULTI_INIT)
1139                         printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1140                             __func__);
1141                 hc->hw.r_ctrl |= V_EXT_RAM;
1142                 hc->hw.r_ram_sz = 2;
1143                 hc->Flen = 0x20;
1144                 hc->Zmin = 0xc0;
1145                 hc->Zlen = 8000;
1146                 hc->DTMFbase = 0x2000;
1147         }
1148         hc->max_trans = poll << 1;
1149         if (hc->max_trans > hc->Zlen)
1150                 hc->max_trans = hc->Zlen;
1151
1152         /* Speech Design PLX bridge */
1153         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1154                 if (debug & DEBUG_HFCMULTI_PLXSD)
1155                         printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1156                             __func__, hc->id + 1);
1157                 spin_lock_irqsave(&plx_lock, plx_flags);
1158                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1159                 writel(PLX_GPIOC_INIT, plx_acc_32);
1160                 pv = readl(plx_acc_32);
1161                 /* The first and the last cards are terminating the PCM bus */
1162                 pv |= PLX_TERM_ON; /* hc is currently the last */
1163                 /* Disconnect the PCM */
1164                 pv |= PLX_SLAVE_EN_N;
1165                 pv &= ~PLX_MASTER_EN;
1166                 pv &= ~PLX_SYNC_O_EN;
1167                 /* Put the DSP in Reset */
1168                 pv &= ~PLX_DSP_RES_N;
1169                 writel(pv, plx_acc_32);
1170                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1171                 if (debug & DEBUG_HFCMULTI_INIT)
1172                         printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n",
1173                                 __func__, pv);
1174                 /*
1175                  * If we are the 3rd PLXSD card or higher, we must turn
1176                  * termination of last PLXSD card off.
1177                  */
1178                 spin_lock_irqsave(&HFClock, hfc_flags);
1179                 plx_count = 0;
1180                 plx_last_hc = NULL;
1181                 list_for_each_entry_safe(pos, next, &HFClist, list) {
1182                         if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1183                                 plx_count++;
1184                                 if (pos != hc)
1185                                         plx_last_hc = pos;
1186                         }
1187                 }
1188                 if (plx_count >= 3) {
1189                         if (debug & DEBUG_HFCMULTI_PLXSD)
1190                                 printk(KERN_DEBUG "%s: card %d is between, so "
1191                                         "we disable termination\n",
1192                                     __func__, plx_last_hc->id + 1);
1193                         spin_lock_irqsave(&plx_lock, plx_flags);
1194                         plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1195                         pv = readl(plx_acc_32);
1196                         pv &= ~PLX_TERM_ON;
1197                         writel(pv, plx_acc_32);
1198                         spin_unlock_irqrestore(&plx_lock, plx_flags);
1199                         if (debug & DEBUG_HFCMULTI_INIT)
1200                             printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n",
1201                                         __func__, pv);
1202                 }
1203                 spin_unlock_irqrestore(&HFClock, hfc_flags);
1204                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1205         }
1206
1207         /* we only want the real Z2 read-pointer for revision > 0 */
1208         if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1209                 hc->hw.r_ram_sz |= V_FZ_MD;
1210
1211         /* select pcm mode */
1212         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1213                 if (debug & DEBUG_HFCMULTI_INIT)
1214                         printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1215                             __func__);
1216         } else
1217         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1218                 if (debug & DEBUG_HFCMULTI_INIT)
1219                         printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1220                             __func__);
1221                 hc->hw.r_pcm_md0 |= V_PCM_MD;
1222         } else {
1223                 if (debug & DEBUG_HFCMULTI_INIT)
1224                         printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1225                             __func__);
1226         }
1227
1228         /* soft reset */
1229         HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1230         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1231         HFC_outb(hc, R_FIFO_MD, 0);
1232         hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
1233         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1234         udelay(100);
1235         hc->hw.r_cirm = 0;
1236         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1237         udelay(100);
1238         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1239
1240         /* Speech Design PLX bridge pcm and sync mode */
1241         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1242                 spin_lock_irqsave(&plx_lock, plx_flags);
1243                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1244                 pv = readl(plx_acc_32);
1245                 /* Connect PCM */
1246                 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1247                         pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1248                         pv |= PLX_SYNC_O_EN;
1249                         if (debug & DEBUG_HFCMULTI_INIT)
1250                                 printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n",
1251                                         __func__, pv);
1252                 } else {
1253                         pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1254                         pv &= ~PLX_SYNC_O_EN;
1255                         if (debug & DEBUG_HFCMULTI_INIT)
1256                                 printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n",
1257                                         __func__, pv);
1258                 }
1259                 writel(pv, plx_acc_32);
1260                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1261         }
1262
1263         /* PCM setup */
1264         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1265         if (hc->slots == 32)
1266                 HFC_outb(hc, R_PCM_MD1, 0x00);
1267         if (hc->slots == 64)
1268                 HFC_outb(hc, R_PCM_MD1, 0x10);
1269         if (hc->slots == 128)
1270                 HFC_outb(hc, R_PCM_MD1, 0x20);
1271         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1272         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1273                 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1274         else
1275                 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1276         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1277         for (i = 0; i < 256; i++) {
1278                 HFC_outb_nodebug(hc, R_SLOT, i);
1279                 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1280                 HFC_outb_nodebug(hc, A_CONF, 0);
1281                 hc->slot_owner[i] = -1;
1282         }
1283
1284         /* set clock speed */
1285         if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1286                 if (debug & DEBUG_HFCMULTI_INIT)
1287                         printk(KERN_DEBUG
1288                             "%s: setting double clock\n", __func__);
1289                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1290         }
1291
1292         /* B410P GPIO */
1293         if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1294                 printk(KERN_NOTICE "Setting GPIOs\n");
1295                 HFC_outb(hc, R_GPIO_SEL, 0x30);
1296                 HFC_outb(hc, R_GPIO_EN1, 0x3);
1297                 udelay(1000);
1298                 printk(KERN_NOTICE "calling vpm_init\n");
1299                 vpm_init(hc);
1300         }
1301
1302         /* check if R_F0_CNT counts (8 kHz frame count) */
1303         val = HFC_inb(hc, R_F0_CNTL);
1304         val += HFC_inb(hc, R_F0_CNTH) << 8;
1305         if (debug & DEBUG_HFCMULTI_INIT)
1306                 printk(KERN_DEBUG
1307                     "HFC_multi F0_CNT %ld after reset\n", val);
1308         spin_unlock_irqrestore(&hc->lock, flags);
1309         set_current_state(TASK_UNINTERRUPTIBLE);
1310         schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1311         spin_lock_irqsave(&hc->lock, flags);
1312         val2 = HFC_inb(hc, R_F0_CNTL);
1313         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1314         if (debug & DEBUG_HFCMULTI_INIT)
1315                 printk(KERN_DEBUG
1316                         "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1317                     val2);
1318         if (val2 >= val+8) { /* 1 ms */
1319                 /* it counts, so we keep the pcm mode */
1320                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1321                         printk(KERN_INFO "controller is PCM bus MASTER\n");
1322                 else
1323                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1324                         printk(KERN_INFO "controller is PCM bus SLAVE\n");
1325                 else {
1326                         test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1327                         printk(KERN_INFO "controller is PCM bus SLAVE "
1328                                 "(auto detected)\n");
1329                 }
1330         } else {
1331                 /* does not count */
1332                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1333 controller_fail:
1334                         printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1335                             "pulse. Seems that controller fails.\n");
1336                         err = -EIO;
1337                         goto out;
1338                 }
1339                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1340                         printk(KERN_INFO "controller is PCM bus SLAVE "
1341                                 "(ignoring missing PCM clock)\n");
1342                 } else {
1343                         /* only one pcm master */
1344                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1345                                 && plxsd_master) {
1346                                 printk(KERN_ERR "HFC_multi ERROR, no clock "
1347                                     "on another Speech Design card found. "
1348                                     "Please be sure to connect PCM cable.\n");
1349                                 err = -EIO;
1350                                 goto out;
1351                         }
1352                         /* retry with master clock */
1353                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1354                                 spin_lock_irqsave(&plx_lock, plx_flags);
1355                                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1356                                 pv = readl(plx_acc_32);
1357                                 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1358                                 pv |= PLX_SYNC_O_EN;
1359                                 writel(pv, plx_acc_32);
1360                                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1361                                 if (debug & DEBUG_HFCMULTI_INIT)
1362                                     printk(KERN_WARNING "%s: master: PLX_GPIO"
1363                                         "=%x\n", __func__, pv);
1364                         }
1365                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1366                         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1367                         spin_unlock_irqrestore(&hc->lock, flags);
1368                         set_current_state(TASK_UNINTERRUPTIBLE);
1369                         schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1370                         spin_lock_irqsave(&hc->lock, flags);
1371                         val2 = HFC_inb(hc, R_F0_CNTL);
1372                         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1373                         if (debug & DEBUG_HFCMULTI_INIT)
1374                                 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1375                                         "10 ms (2nd try)\n", val2);
1376                         if (val2 >= val+8) { /* 1 ms */
1377                                 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1378                                         &hc->chip);
1379                                 printk(KERN_INFO "controller is PCM bus MASTER "
1380                                         "(auto detected)\n");
1381                         } else
1382                                 goto controller_fail;
1383                 }
1384         }
1385
1386         /* Release the DSP Reset */
1387         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1388                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1389                         plxsd_master = 1;
1390                 spin_lock_irqsave(&plx_lock, plx_flags);
1391                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1392                 pv = readl(plx_acc_32);
1393                 pv |=  PLX_DSP_RES_N;
1394                 writel(pv, plx_acc_32);
1395                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1396                 if (debug & DEBUG_HFCMULTI_INIT)
1397                         printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n",
1398                                 __func__, pv);
1399         }
1400
1401         /* pcm id */
1402         if (hc->pcm)
1403                 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1404                         hc->pcm);
1405         else {
1406                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1407                  || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1408                         PCM_cnt++; /* SD has proprietary bridging */
1409                 }
1410                 hc->pcm = PCM_cnt;
1411                 printk(KERN_INFO "controller has PCM BUS ID %d "
1412                         "(auto selected)\n", hc->pcm);
1413         }
1414
1415         /* set up timer */
1416         HFC_outb(hc, R_TI_WD, poll_timer);
1417         hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1418
1419         /* set E1 state machine IRQ */
1420         if (hc->type == 1)
1421                 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1422
1423         /* set DTMF detection */
1424         if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1425                 if (debug & DEBUG_HFCMULTI_INIT)
1426                         printk(KERN_DEBUG "%s: enabling DTMF detection "
1427                             "for all B-channel\n", __func__);
1428                 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1429                 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1430                         hc->hw.r_dtmf |= V_ULAW_SEL;
1431                 HFC_outb(hc, R_DTMF_N, 102 - 1);
1432                 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1433         }
1434
1435         /* conference engine */
1436         if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1437                 r_conf_en = V_CONF_EN | V_ULAW;
1438         else
1439                 r_conf_en = V_CONF_EN;
1440         HFC_outb(hc, R_CONF_EN, r_conf_en);
1441
1442         /* setting leds */
1443         switch (hc->leds) {
1444         case 1: /* HFC-E1 OEM */
1445                 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1446                         HFC_outb(hc, R_GPIO_SEL, 0x32);
1447                 else
1448                         HFC_outb(hc, R_GPIO_SEL, 0x30);
1449
1450                 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1451                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1452
1453                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1454                 break;
1455
1456         case 2: /* HFC-4S OEM */
1457         case 3:
1458                 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1459                 HFC_outb(hc, R_GPIO_EN1, 0xff);
1460                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1461                 break;
1462         }
1463
1464         /* set master clock */
1465         if (hc->masterclk >= 0) {
1466                 if (debug & DEBUG_HFCMULTI_INIT)
1467                         printk(KERN_DEBUG "%s: setting ST master clock "
1468                             "to port %d (0..%d)\n",
1469                             __func__, hc->masterclk, hc->ports-1);
1470                 hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
1471                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1472         }
1473
1474         /* setting misc irq */
1475         HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1476         if (debug & DEBUG_HFCMULTI_INIT)
1477                 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1478                     hc->hw.r_irqmsk_misc);
1479
1480         /* RAM access test */
1481         HFC_outb(hc, R_RAM_ADDR0, 0);
1482         HFC_outb(hc, R_RAM_ADDR1, 0);
1483         HFC_outb(hc, R_RAM_ADDR2, 0);
1484         for (i = 0; i < 256; i++) {
1485                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1486                 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1487         }
1488         for (i = 0; i < 256; i++) {
1489                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1490                 HFC_inb_nodebug(hc, R_RAM_DATA);
1491                 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1492                 if (rval != ((i * 3) & 0xff)) {
1493                         printk(KERN_DEBUG
1494                             "addr:%x val:%x should:%x\n", i, rval,
1495                             (i * 3) & 0xff);
1496                         err++;
1497                 }
1498         }
1499         if (err) {
1500                 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1501                 err = -EIO;
1502                 goto out;
1503         }
1504
1505         if (debug & DEBUG_HFCMULTI_INIT)
1506                 printk(KERN_DEBUG "%s: done\n", __func__);
1507 out:
1508         spin_unlock_irqrestore(&hc->lock, flags);
1509         return err;
1510 }
1511
1512
1513 /*
1514  * control the watchdog
1515  */
1516 static void
1517 hfcmulti_watchdog(struct hfc_multi *hc)
1518 {
1519         hc->wdcount++;
1520
1521         if (hc->wdcount > 10) {
1522                 hc->wdcount = 0;
1523                 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1524                     V_GPIO_OUT3 : V_GPIO_OUT2;
1525
1526         /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1527                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1528                 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1529         }
1530 }
1531
1532
1533
1534 /*
1535  * output leds
1536  */
1537 static void
1538 hfcmulti_leds(struct hfc_multi *hc)
1539 {
1540         unsigned long lled;
1541         unsigned long leddw;
1542         int i, state, active, leds;
1543         struct dchannel *dch;
1544         int led[4];
1545
1546         hc->ledcount += poll;
1547         if (hc->ledcount > 4096) {
1548                 hc->ledcount -= 4096;
1549                 hc->ledstate = 0xAFFEAFFE;
1550         }
1551
1552         switch (hc->leds) {
1553         case 1: /* HFC-E1 OEM */
1554                 /* 2 red blinking: NT mode deactivate
1555                  * 2 red steady:   TE mode deactivate
1556                  * left green:     L1 active
1557                  * left red:       frame sync, but no L1
1558                  * right green:    L2 active
1559                  */
1560                 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1561                         if (hc->chan[hc->dslot].dch->dev.D.protocol
1562                                 != ISDN_P_NT_E1) {
1563                                 led[0] = 1;
1564                                 led[1] = 1;
1565                         } else if (hc->ledcount>>11) {
1566                                 led[0] = 1;
1567                                 led[1] = 1;
1568                         } else {
1569                                 led[0] = 0;
1570                                 led[1] = 0;
1571                         }
1572                         led[2] = 0;
1573                         led[3] = 0;
1574                 } else { /* with frame sync */
1575                         /* TODO make it work */
1576                         led[0] = 0;
1577                         led[1] = 0;
1578                         led[2] = 0;
1579                         led[3] = 1;
1580                 }
1581                 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1582                         /* leds are inverted */
1583                 if (leds != (int)hc->ledstate) {
1584                         HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1585                         hc->ledstate = leds;
1586                 }
1587                 break;
1588
1589         case 2: /* HFC-4S OEM */
1590                 /* red blinking = PH_DEACTIVATE NT Mode
1591                  * red steady   = PH_DEACTIVATE TE Mode
1592                  * green steady = PH_ACTIVATE
1593                  */
1594                 for (i = 0; i < 4; i++) {
1595                         state = 0;
1596                         active = -1;
1597                         dch = hc->chan[(i << 2) | 2].dch;
1598                         if (dch) {
1599                                 state = dch->state;
1600                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1601                                         active = 3;
1602                                 else
1603                                         active = 7;
1604                         }
1605                         if (state) {
1606                                 if (state == active) {
1607                                         led[i] = 1; /* led green */
1608                                 } else
1609                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1610                                                 /* TE mode: led red */
1611                                                 led[i] = 2;
1612                                         else
1613                                                 if (hc->ledcount>>11)
1614                                                         /* led red */
1615                                                         led[i] = 2;
1616                                                 else
1617                                                         /* led off */
1618                                                         led[i] = 0;
1619                         } else
1620                                 led[i] = 0; /* led off */
1621                 }
1622                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1623                         leds = 0;
1624                         for (i = 0; i < 4; i++) {
1625                                 if (led[i] == 1) {
1626                                         /*green*/
1627                                         leds |= (0x2 << (i * 2));
1628                                 } else if (led[i] == 2) {
1629                                         /*red*/
1630                                         leds |= (0x1 << (i * 2));
1631                                 }
1632                         }
1633                         if (leds != (int)hc->ledstate) {
1634                                 vpm_out(hc, 0, 0x1a8 + 3, leds);
1635                                 hc->ledstate = leds;
1636                         }
1637                 } else {
1638                         leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1639                             ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1640                             ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1641                             ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1642                         if (leds != (int)hc->ledstate) {
1643                                 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1644                                 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1645                                 hc->ledstate = leds;
1646                         }
1647                 }
1648                 break;
1649
1650         case 3: /* HFC 1S/2S Beronet */
1651                 /* red blinking = PH_DEACTIVATE NT Mode
1652                  * red steady   = PH_DEACTIVATE TE Mode
1653                  * green steady = PH_ACTIVATE
1654                  */
1655                 for (i = 0; i < 2; i++) {
1656                         state = 0;
1657                         active = -1;
1658                         dch = hc->chan[(i << 2) | 2].dch;
1659                         if (dch) {
1660                                 state = dch->state;
1661                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1662                                         active = 3;
1663                                 else
1664                                         active = 7;
1665                         }
1666                         if (state) {
1667                                 if (state == active) {
1668                                         led[i] = 1; /* led green */
1669                                 } else
1670                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1671                                                 /* TE mode: led red */
1672                                                 led[i] = 2;
1673                                         else
1674                                                 if (hc->ledcount >> 11)
1675                                                         /* led red */
1676                                                         led[i] = 2;
1677                                                 else
1678                                                         /* led off */
1679                                                         led[i] = 0;
1680                         } else
1681                                 led[i] = 0; /* led off */
1682                 }
1683
1684
1685                 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1686                         | ((led[1]&1)<<3);
1687                 if (leds != (int)hc->ledstate) {
1688                         HFC_outb_nodebug(hc, R_GPIO_EN1,
1689                             ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1690                         HFC_outb_nodebug(hc, R_GPIO_OUT1,
1691                             ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1692                         hc->ledstate = leds;
1693                 }
1694                 break;
1695         case 8: /* HFC 8S+ Beronet */
1696                 lled = 0;
1697
1698                 for (i = 0; i < 8; i++) {
1699                         state = 0;
1700                         active = -1;
1701                         dch = hc->chan[(i << 2) | 2].dch;
1702                         if (dch) {
1703                                 state = dch->state;
1704                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1705                                         active = 3;
1706                                 else
1707                                         active = 7;
1708                         }
1709                         if (state) {
1710                                 if (state == active) {
1711                                         lled |= 0 << i;
1712                                 } else
1713                                         if (hc->ledcount >> 11)
1714                                                 lled |= 0 << i;
1715                                         else
1716                                                 lled |= 1 << i;
1717                         } else
1718                                 lled |= 1 << i;
1719                 }
1720                 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1721                 if (leddw != hc->ledstate) {
1722                         /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1723                         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1724                         /* was _io before */
1725                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1726                         outw(0x4000, hc->pci_iobase + 4);
1727                         outl(leddw, hc->pci_iobase);
1728                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1729                         hc->ledstate = leddw;
1730                 }
1731                 break;
1732         }
1733 }
1734 /*
1735  * read dtmf coefficients
1736  */
1737
1738 static void
1739 hfcmulti_dtmf(struct hfc_multi *hc)
1740 {
1741         s32             *coeff;
1742         u_int           mantissa;
1743         int             co, ch;
1744         struct bchannel *bch = NULL;
1745         u8              exponent;
1746         int             dtmf = 0;
1747         int             addr;
1748         u16             w_float;
1749         struct sk_buff  *skb;
1750         struct mISDNhead *hh;
1751
1752         if (debug & DEBUG_HFCMULTI_DTMF)
1753                 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1754         for (ch = 0; ch <= 31; ch++) {
1755                 /* only process enabled B-channels */
1756                 bch = hc->chan[ch].bch;
1757                 if (!bch)
1758                         continue;
1759                 if (!hc->created[hc->chan[ch].port])
1760                         continue;
1761                 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1762                         continue;
1763                 if (debug & DEBUG_HFCMULTI_DTMF)
1764                         printk(KERN_DEBUG "%s: dtmf channel %d:",
1765                                 __func__, ch);
1766                 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1767                 dtmf = 1;
1768                 for (co = 0; co < 8; co++) {
1769                         /* read W(n-1) coefficient */
1770                         addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1771                         HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1772                         HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1773                         HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1774                                 | V_ADDR_INC);
1775                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1776                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1777                         if (debug & DEBUG_HFCMULTI_DTMF)
1778                                 printk(" %04x", w_float);
1779
1780                         /* decode float (see chip doc) */
1781                         mantissa = w_float & 0x0fff;
1782                         if (w_float & 0x8000)
1783                                 mantissa |= 0xfffff000;
1784                         exponent = (w_float>>12) & 0x7;
1785                         if (exponent) {
1786                                 mantissa ^= 0x1000;
1787                                 mantissa <<= (exponent-1);
1788                         }
1789
1790                         /* store coefficient */
1791                         coeff[co<<1] = mantissa;
1792
1793                         /* read W(n) coefficient */
1794                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1795                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1796                         if (debug & DEBUG_HFCMULTI_DTMF)
1797                                 printk(" %04x", w_float);
1798
1799                         /* decode float (see chip doc) */
1800                         mantissa = w_float & 0x0fff;
1801                         if (w_float & 0x8000)
1802                                 mantissa |= 0xfffff000;
1803                         exponent = (w_float>>12) & 0x7;
1804                         if (exponent) {
1805                                 mantissa ^= 0x1000;
1806                                 mantissa <<= (exponent-1);
1807                         }
1808
1809                         /* store coefficient */
1810                         coeff[(co<<1)|1] = mantissa;
1811                 }
1812                 if (debug & DEBUG_HFCMULTI_DTMF)
1813                         printk("%s: DTMF ready %08x %08x %08x %08x "
1814                             "%08x %08x %08x %08x\n", __func__,
1815                             coeff[0], coeff[1], coeff[2], coeff[3],
1816                             coeff[4], coeff[5], coeff[6], coeff[7]);
1817                 hc->chan[ch].coeff_count++;
1818                 if (hc->chan[ch].coeff_count == 8) {
1819                         hc->chan[ch].coeff_count = 0;
1820                         skb = mI_alloc_skb(512, GFP_ATOMIC);
1821                         if (!skb) {
1822                                 printk(KERN_WARNING "%s: No memory for skb\n",
1823                                     __func__);
1824                                 continue;
1825                         }
1826                         hh = mISDN_HEAD_P(skb);
1827                         hh->prim = PH_CONTROL_IND;
1828                         hh->id = DTMF_HFC_COEF;
1829                         memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1830                         recv_Bchannel_skb(bch, skb);
1831                 }
1832         }
1833
1834         /* restart DTMF processing */
1835         hc->dtmf = dtmf;
1836         if (dtmf)
1837                 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1838 }
1839
1840
1841 /*
1842  * fill fifo as much as possible
1843  */
1844
1845 static void
1846 hfcmulti_tx(struct hfc_multi *hc, int ch)
1847 {
1848         int i, ii, temp, len = 0;
1849         int Zspace, z1, z2; /* must be int for calculation */
1850         int Fspace, f1, f2;
1851         u_char *d;
1852         int *txpending, slot_tx;
1853         struct  bchannel *bch;
1854         struct  dchannel *dch;
1855         struct  sk_buff **sp = NULL;
1856         int *idxp;
1857
1858         bch = hc->chan[ch].bch;
1859         dch = hc->chan[ch].dch;
1860         if ((!dch) && (!bch))
1861                 return;
1862
1863         txpending = &hc->chan[ch].txpending;
1864         slot_tx = hc->chan[ch].slot_tx;
1865         if (dch) {
1866                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1867                         return;
1868                 sp = &dch->tx_skb;
1869                 idxp = &dch->tx_idx;
1870         } else {
1871                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1872                         return;
1873                 sp = &bch->tx_skb;
1874                 idxp = &bch->tx_idx;
1875         }
1876         if (*sp)
1877                 len = (*sp)->len;
1878
1879         if ((!len) && *txpending != 1)
1880                 return; /* no data */
1881
1882         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1883             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1884             (hc->chan[ch].slot_rx < 0) &&
1885             (hc->chan[ch].slot_tx < 0))
1886                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1887         else
1888                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1889         HFC_wait_nodebug(hc);
1890
1891         if (*txpending == 2) {
1892                 /* reset fifo */
1893                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1894                 HFC_wait_nodebug(hc);
1895                 HFC_outb(hc, A_SUBCH_CFG, 0);
1896                 *txpending = 1;
1897         }
1898 next_frame:
1899         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1900                 f1 = HFC_inb_nodebug(hc, A_F1);
1901                 f2 = HFC_inb_nodebug(hc, A_F2);
1902                 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1903                         if (debug & DEBUG_HFCMULTI_FIFO)
1904                                 printk(KERN_DEBUG
1905                                     "%s(card %d): reread f2 because %d!=%d\n",
1906                                     __func__, hc->id + 1, temp, f2);
1907                         f2 = temp; /* repeat until F2 is equal */
1908                 }
1909                 Fspace = f2 - f1 - 1;
1910                 if (Fspace < 0)
1911                         Fspace += hc->Flen;
1912                 /*
1913                  * Old FIFO handling doesn't give us the current Z2 read
1914                  * pointer, so we cannot send the next frame before the fifo
1915                  * is empty. It makes no difference except for a slightly
1916                  * lower performance.
1917                  */
1918                 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1919                         if (f1 != f2)
1920                                 Fspace = 0;
1921                         else
1922                                 Fspace = 1;
1923                 }
1924                 /* one frame only for ST D-channels, to allow resending */
1925                 if (hc->type != 1 && dch) {
1926                         if (f1 != f2)
1927                                 Fspace = 0;
1928                 }
1929                 /* F-counter full condition */
1930                 if (Fspace == 0)
1931                         return;
1932         }
1933         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1934         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1935         while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1936                 if (debug & DEBUG_HFCMULTI_FIFO)
1937                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
1938                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1939                 z2 = temp; /* repeat unti Z2 is equal */
1940         }
1941         Zspace = z2 - z1;
1942         if (Zspace <= 0)
1943                 Zspace += hc->Zlen;
1944         Zspace -= 4; /* keep not too full, so pointers will not overrun */
1945         /* fill transparent data only to maxinum transparent load (minus 4) */
1946         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
1947                 Zspace = Zspace - hc->Zlen + hc->max_trans;
1948         if (Zspace <= 0) /* no space of 4 bytes */
1949                 return;
1950
1951         /* if no data */
1952         if (!len) {
1953                 if (z1 == z2) { /* empty */
1954                         /* if done with FIFO audio data during PCM connection */
1955                         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
1956                             *txpending && slot_tx >= 0) {
1957                                 if (debug & DEBUG_HFCMULTI_MODE)
1958                                         printk(KERN_DEBUG
1959                                             "%s: reconnecting PCM due to no "
1960                                             "more FIFO data: channel %d "
1961                                             "slot_tx %d\n",
1962                                             __func__, ch, slot_tx);
1963                                 /* connect slot */
1964                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1965                                     V_HDLC_TRP | V_IFF);
1966                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1967                                 HFC_wait_nodebug(hc);
1968                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1969                                     V_HDLC_TRP | V_IFF);
1970                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
1971                                 HFC_wait_nodebug(hc);
1972                         }
1973                         *txpending = 0;
1974                 }
1975                 return; /* no data */
1976         }
1977
1978         /* if audio data and connected slot */
1979         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
1980                 && slot_tx >= 0) {
1981                 if (debug & DEBUG_HFCMULTI_MODE)
1982                         printk(KERN_DEBUG "%s: disconnecting PCM due to "
1983                             "FIFO data: channel %d slot_tx %d\n",
1984                             __func__, ch, slot_tx);
1985                 /* disconnect slot */
1986                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
1987                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1988                 HFC_wait_nodebug(hc);
1989                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
1990                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
1991                 HFC_wait_nodebug(hc);
1992         }
1993         *txpending = 1;
1994
1995         /* show activity */
1996         hc->activity[hc->chan[ch].port] = 1;
1997
1998         /* fill fifo to what we have left */
1999         ii = len;
2000         if (dch || test_bit(FLG_HDLC, &bch->Flags))
2001                 temp = 1;
2002         else
2003                 temp = 0;
2004         i = *idxp;
2005         d = (*sp)->data + i;
2006         if (ii - i > Zspace)
2007                 ii = Zspace + i;
2008         if (debug & DEBUG_HFCMULTI_FIFO)
2009                 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2010                     "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2011                         __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2012                         temp ? "HDLC":"TRANS");
2013
2014
2015         /* Have to prep the audio data */
2016         hc->write_fifo(hc, d, ii - i);
2017         *idxp = ii;
2018
2019         /* if not all data has been written */
2020         if (ii != len) {
2021                 /* NOTE: fifo is started by the calling function */
2022                 return;
2023         }
2024
2025         /* if all data has been written, terminate frame */
2026         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2027                 /* increment f-counter */
2028                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2029                 HFC_wait_nodebug(hc);
2030         }
2031
2032         /* send confirm, since get_net_bframe will not do it with trans */
2033         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2034                 confirm_Bsend(bch);
2035
2036         /* check for next frame */
2037         dev_kfree_skb(*sp);
2038         if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2039                 len = (*sp)->len;
2040                 goto next_frame;
2041         }
2042         if (dch && get_next_dframe(dch)) {
2043                 len = (*sp)->len;
2044                 goto next_frame;
2045         }
2046
2047         /*
2048          * now we have no more data, so in case of transparent,
2049          * we set the last byte in fifo to 'silence' in case we will get
2050          * no more data at all. this prevents sending an undefined value.
2051          */
2052         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2053                 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2054 }
2055
2056
2057 /* NOTE: only called if E1 card is in active state */
2058 static void
2059 hfcmulti_rx(struct hfc_multi *hc, int ch)
2060 {
2061         int temp;
2062         int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2063         int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2064         int again = 0;
2065         struct  bchannel *bch;
2066         struct  dchannel *dch;
2067         struct sk_buff  *skb, **sp = NULL;
2068         int     maxlen;
2069
2070         bch = hc->chan[ch].bch;
2071         dch = hc->chan[ch].dch;
2072         if ((!dch) && (!bch))
2073                 return;
2074         if (dch) {
2075                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2076                         return;
2077                 sp = &dch->rx_skb;
2078                 maxlen = dch->maxlen;
2079         } else {
2080                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2081                         return;
2082                 sp = &bch->rx_skb;
2083                 maxlen = bch->maxlen;
2084         }
2085 next_frame:
2086         /* on first AND before getting next valid frame, R_FIFO must be written
2087            to. */
2088         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2089             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2090             (hc->chan[ch].slot_rx < 0) &&
2091             (hc->chan[ch].slot_tx < 0))
2092                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2093         else
2094                 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2095         HFC_wait_nodebug(hc);
2096
2097         /* ignore if rx is off BUT change fifo (above) to start pending TX */
2098         if (hc->chan[ch].rx_off)
2099                 return;
2100
2101         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2102                 f1 = HFC_inb_nodebug(hc, A_F1);
2103                 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2104                         if (debug & DEBUG_HFCMULTI_FIFO)
2105                                 printk(KERN_DEBUG
2106                                     "%s(card %d): reread f1 because %d!=%d\n",
2107                                     __func__, hc->id + 1, temp, f1);
2108                         f1 = temp; /* repeat until F1 is equal */
2109                 }
2110                 f2 = HFC_inb_nodebug(hc, A_F2);
2111         }
2112         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2113         while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2114                 if (debug & DEBUG_HFCMULTI_FIFO)
2115                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2116                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2117                 z1 = temp; /* repeat until Z1 is equal */
2118         }
2119         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2120         Zsize = z1 - z2;
2121         if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2122                 /* complete hdlc frame */
2123                 Zsize++;
2124         if (Zsize < 0)
2125                 Zsize += hc->Zlen;
2126         /* if buffer is empty */
2127         if (Zsize <= 0)
2128                 return;
2129
2130         if (*sp == NULL) {
2131                 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2132                 if (*sp == NULL) {
2133                         printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2134                             __func__);
2135                         return;
2136                 }
2137         }
2138         /* show activity */
2139         hc->activity[hc->chan[ch].port] = 1;
2140
2141         /* empty fifo with what we have */
2142         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2143                 if (debug & DEBUG_HFCMULTI_FIFO)
2144                         printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2145                             "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2146                             "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2147                             Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2148                             f1, f2, Zsize + (*sp)->len, again);
2149                 /* HDLC */
2150                 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2151                         if (debug & DEBUG_HFCMULTI_FIFO)
2152                                 printk(KERN_DEBUG
2153                                     "%s(card %d): hdlc-frame too large.\n",
2154                                     __func__, hc->id + 1);
2155                         skb_trim(*sp, 0);
2156                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2157                         HFC_wait_nodebug(hc);
2158                         return;
2159                 }
2160
2161                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2162
2163                 if (f1 != f2) {
2164                         /* increment Z2,F2-counter */
2165                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2166                         HFC_wait_nodebug(hc);
2167                         /* check size */
2168                         if ((*sp)->len < 4) {
2169                                 if (debug & DEBUG_HFCMULTI_FIFO)
2170                                         printk(KERN_DEBUG
2171                                             "%s(card %d): Frame below minimum "
2172                                             "size\n", __func__, hc->id + 1);
2173                                 skb_trim(*sp, 0);
2174                                 goto next_frame;
2175                         }
2176                         /* there is at least one complete frame, check crc */
2177                         if ((*sp)->data[(*sp)->len - 1]) {
2178                                 if (debug & DEBUG_HFCMULTI_CRC)
2179                                         printk(KERN_DEBUG
2180                                             "%s: CRC-error\n", __func__);
2181                                 skb_trim(*sp, 0);
2182                                 goto next_frame;
2183                         }
2184                         skb_trim(*sp, (*sp)->len - 3);
2185                         if ((*sp)->len < MISDN_COPY_SIZE) {
2186                                 skb = *sp;
2187                                 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2188                                 if (*sp) {
2189                                         memcpy(skb_put(*sp, skb->len),
2190                                             skb->data, skb->len);
2191                                         skb_trim(skb, 0);
2192                                 } else {
2193                                         printk(KERN_DEBUG "%s: No mem\n",
2194                                             __func__);
2195                                         *sp = skb;
2196                                         skb = NULL;
2197                                 }
2198                         } else {
2199                                 skb = NULL;
2200                         }
2201                         if (debug & DEBUG_HFCMULTI_FIFO) {
2202                                 printk(KERN_DEBUG "%s(card %d):",
2203                                         __func__, hc->id + 1);
2204                                 temp = 0;
2205                                 while (temp < (*sp)->len)
2206                                         printk(" %02x", (*sp)->data[temp++]);
2207                                 printk("\n");
2208                         }
2209                         if (dch)
2210                                 recv_Dchannel(dch);
2211                         else
2212                                 recv_Bchannel(bch);
2213                         *sp = skb;
2214                         again++;
2215                         goto next_frame;
2216                 }
2217                 /* there is an incomplete frame */
2218         } else {
2219                 /* transparent */
2220                 if (Zsize > skb_tailroom(*sp))
2221                         Zsize = skb_tailroom(*sp);
2222                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2223                 if (((*sp)->len) < MISDN_COPY_SIZE) {
2224                         skb = *sp;
2225                         *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2226                         if (*sp) {
2227                                 memcpy(skb_put(*sp, skb->len),
2228                                     skb->data, skb->len);
2229                                 skb_trim(skb, 0);
2230                         } else {
2231                                 printk(KERN_DEBUG "%s: No mem\n", __func__);
2232                                 *sp = skb;
2233                                 skb = NULL;
2234                         }
2235                 } else {
2236                         skb = NULL;
2237                 }
2238                 if (debug & DEBUG_HFCMULTI_FIFO)
2239                         printk(KERN_DEBUG
2240                             "%s(card %d): fifo(%d) reading %d bytes "
2241                             "(z1=%04x, z2=%04x) TRANS\n",
2242                                 __func__, hc->id + 1, ch, Zsize, z1, z2);
2243                 /* only bch is transparent */
2244                 recv_Bchannel(bch);
2245                 *sp = skb;
2246         }
2247 }
2248
2249
2250 /*
2251  * Interrupt handler
2252  */
2253 static void
2254 signal_state_up(struct dchannel *dch, int info, char *msg)
2255 {
2256         struct sk_buff  *skb;
2257         int             id, data = info;
2258
2259         if (debug & DEBUG_HFCMULTI_STATE)
2260                 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2261
2262         id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2263
2264         skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2265                 GFP_ATOMIC);
2266         if (!skb)
2267                 return;
2268         recv_Dchannel_skb(dch, skb);
2269 }
2270
2271 static inline void
2272 handle_timer_irq(struct hfc_multi *hc)
2273 {
2274         int             ch, temp;
2275         struct dchannel *dch;
2276         u_long          flags;
2277
2278         /* process queued resync jobs */
2279         if (hc->e1_resync) {
2280                 /* lock, so e1_resync gets not changed */
2281                 spin_lock_irqsave(&HFClock, flags);
2282                 if (hc->e1_resync & 1) {
2283                         if (debug & DEBUG_HFCMULTI_PLXSD)
2284                                 printk(KERN_DEBUG "Enable SYNC_I\n");
2285                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2286                         /* disable JATT, if RX_SYNC is set */
2287                         if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2288                                 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2289                 }
2290                 if (hc->e1_resync & 2) {
2291                         if (debug & DEBUG_HFCMULTI_PLXSD)
2292                                 printk(KERN_DEBUG "Enable jatt PLL\n");
2293                         HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2294                 }
2295                 if (hc->e1_resync & 4) {
2296                         if (debug & DEBUG_HFCMULTI_PLXSD)
2297                                 printk(KERN_DEBUG
2298                                     "Enable QUARTZ for HFC-E1\n");
2299                         /* set jatt to quartz */
2300                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2301                                 | V_JATT_OFF);
2302                         /* switch to JATT, in case it is not already */
2303                         HFC_outb(hc, R_SYNC_OUT, 0);
2304                 }
2305                 hc->e1_resync = 0;
2306                 spin_unlock_irqrestore(&HFClock, flags);
2307         }
2308
2309         if (hc->type != 1 || hc->e1_state == 1)
2310                 for (ch = 0; ch <= 31; ch++) {
2311                         if (hc->created[hc->chan[ch].port]) {
2312                                 hfcmulti_tx(hc, ch);
2313                                 /* fifo is started when switching to rx-fifo */
2314                                 hfcmulti_rx(hc, ch);
2315                                 if (hc->chan[ch].dch &&
2316                                     hc->chan[ch].nt_timer > -1) {
2317                                         dch = hc->chan[ch].dch;
2318                                         if (!(--hc->chan[ch].nt_timer)) {
2319                                                 schedule_event(dch,
2320                                                     FLG_PHCHANGE);
2321                                                 if (debug &
2322                                                     DEBUG_HFCMULTI_STATE)
2323                                                         printk(KERN_DEBUG
2324                                                             "%s: nt_timer at "
2325                                                             "state %x\n",
2326                                                             __func__,
2327                                                             dch->state);
2328                                         }
2329                                 }
2330                         }
2331                 }
2332         if (hc->type == 1 && hc->created[0]) {
2333                 dch = hc->chan[hc->dslot].dch;
2334                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2335                         /* LOS */
2336                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2337                         if (!temp && hc->chan[hc->dslot].los)
2338                                 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2339                                     "LOS detected");
2340                         if (temp && !hc->chan[hc->dslot].los)
2341                                 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2342                                     "LOS gone");
2343                         hc->chan[hc->dslot].los = temp;
2344                 }
2345                 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2346                         /* AIS */
2347                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2348                         if (!temp && hc->chan[hc->dslot].ais)
2349                                 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2350                                     "AIS detected");
2351                         if (temp && !hc->chan[hc->dslot].ais)
2352                                 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2353                                     "AIS gone");
2354                         hc->chan[hc->dslot].ais = temp;
2355                 }
2356                 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2357                         /* SLIP */
2358                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2359                         if (!temp && hc->chan[hc->dslot].slip_rx)
2360                                 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2361                                     " bit SLIP detected RX");
2362                         hc->chan[hc->dslot].slip_rx = temp;
2363                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2364                         if (!temp && hc->chan[hc->dslot].slip_tx)
2365                                 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2366                                     " bit SLIP detected TX");
2367                         hc->chan[hc->dslot].slip_tx = temp;
2368                 }
2369                 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2370                         /* RDI */
2371                         temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2372                         if (!temp && hc->chan[hc->dslot].rdi)
2373                                 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2374                                     "RDI detected");
2375                         if (temp && !hc->chan[hc->dslot].rdi)
2376                                 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2377                                     "RDI gone");
2378                         hc->chan[hc->dslot].rdi = temp;
2379                 }
2380                 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2381                 switch (hc->chan[hc->dslot].sync) {
2382                 case 0:
2383                         if ((temp & 0x60) == 0x60) {
2384                                 if (debug & DEBUG_HFCMULTI_SYNC)
2385                                         printk(KERN_DEBUG
2386                                             "%s: (id=%d) E1 now "
2387                                             "in clock sync\n",
2388                                             __func__, hc->id);
2389                                 HFC_outb(hc, R_RX_OFF,
2390                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2391                                 HFC_outb(hc, R_TX_OFF,
2392                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2393                                 hc->chan[hc->dslot].sync = 1;
2394                                 goto check_framesync;
2395                         }
2396                         break;
2397                 case 1:
2398                         if ((temp & 0x60) != 0x60) {
2399                                 if (debug & DEBUG_HFCMULTI_SYNC)
2400                                         printk(KERN_DEBUG
2401                                             "%s: (id=%d) E1 "
2402                                             "lost clock sync\n",
2403                                             __func__, hc->id);
2404                                 hc->chan[hc->dslot].sync = 0;
2405                                 break;
2406                         }
2407 check_framesync:
2408                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2409                         if (temp == 0x27) {
2410                                 if (debug & DEBUG_HFCMULTI_SYNC)
2411                                         printk(KERN_DEBUG
2412                                             "%s: (id=%d) E1 "
2413                                             "now in frame sync\n",
2414                                             __func__, hc->id);
2415                                 hc->chan[hc->dslot].sync = 2;
2416                         }
2417                         break;
2418                 case 2:
2419                         if ((temp & 0x60) != 0x60) {
2420                                 if (debug & DEBUG_HFCMULTI_SYNC)
2421                                         printk(KERN_DEBUG
2422                                             "%s: (id=%d) E1 lost "
2423                                             "clock & frame sync\n",
2424                                             __func__, hc->id);
2425                                 hc->chan[hc->dslot].sync = 0;
2426                                 break;
2427                         }
2428                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2429                         if (temp != 0x27) {
2430                                 if (debug & DEBUG_HFCMULTI_SYNC)
2431                                         printk(KERN_DEBUG
2432                                             "%s: (id=%d) E1 "
2433                                             "lost frame sync\n",
2434                                             __func__, hc->id);
2435                                 hc->chan[hc->dslot].sync = 1;
2436                         }
2437                         break;
2438                 }
2439         }
2440
2441         if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2442                 hfcmulti_watchdog(hc);
2443
2444         if (hc->leds)
2445                 hfcmulti_leds(hc);
2446 }
2447
2448 static void
2449 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2450 {
2451         struct dchannel *dch;
2452         int             ch;
2453         int             active;
2454         u_char          st_status, temp;
2455
2456         /* state machine */
2457         for (ch = 0; ch <= 31; ch++) {
2458                 if (hc->chan[ch].dch) {
2459                         dch = hc->chan[ch].dch;
2460                         if (r_irq_statech & 1) {
2461                                 HFC_outb_nodebug(hc, R_ST_SEL,
2462                                         hc->chan[ch].port);
2463                                 /* undocumented: delay after R_ST_SEL */
2464                                 udelay(1);
2465                                 /* undocumented: status changes during read */
2466                                 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2467                                 while (st_status != (temp =
2468                                         HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2469                                         if (debug & DEBUG_HFCMULTI_STATE)
2470                                                 printk(KERN_DEBUG "%s: reread "
2471                                                     "STATE because %d!=%d\n",
2472                                                     __func__, temp,
2473                                                     st_status);
2474                                         st_status = temp; /* repeat */
2475                                 }
2476
2477                                 /* Speech Design TE-sync indication */
2478                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2479                                         dch->dev.D.protocol == ISDN_P_TE_S0) {
2480                                         if (st_status & V_FR_SYNC_ST)
2481                                                 hc->syncronized |=
2482                                                     (1 << hc->chan[ch].port);
2483                                         else
2484                                                 hc->syncronized &=
2485                                                    ~(1 << hc->chan[ch].port);
2486                                 }
2487                                 dch->state = st_status & 0x0f;
2488                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2489                                         active = 3;
2490                                 else
2491                                         active = 7;
2492                                 if (dch->state == active) {
2493                                         HFC_outb_nodebug(hc, R_FIFO,
2494                                                 (ch << 1) | 1);
2495                                         HFC_wait_nodebug(hc);
2496                                         HFC_outb_nodebug(hc,
2497                                                 R_INC_RES_FIFO, V_RES_F);
2498                                         HFC_wait_nodebug(hc);
2499                                         dch->tx_idx = 0;
2500                                 }
2501                                 schedule_event(dch, FLG_PHCHANGE);
2502                                 if (debug & DEBUG_HFCMULTI_STATE)
2503                                         printk(KERN_DEBUG
2504                                             "%s: S/T newstate %x port %d\n",
2505                                             __func__, dch->state,
2506                                             hc->chan[ch].port);
2507                         }
2508                         r_irq_statech >>= 1;
2509                 }
2510         }
2511         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2512                 plxsd_checksync(hc, 0);
2513 }
2514
2515 static void
2516 fifo_irq(struct hfc_multi *hc, int block)
2517 {
2518         int     ch, j;
2519         struct dchannel *dch;
2520         struct bchannel *bch;
2521         u_char r_irq_fifo_bl;
2522
2523         r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2524         j = 0;
2525         while (j < 8) {
2526                 ch = (block << 2) + (j >> 1);
2527                 dch = hc->chan[ch].dch;
2528                 bch = hc->chan[ch].bch;
2529                 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2530                         j += 2;
2531                         continue;
2532                 }
2533                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2534                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2535                         hfcmulti_tx(hc, ch);
2536                         /* start fifo */
2537                         HFC_outb_nodebug(hc, R_FIFO, 0);
2538                         HFC_wait_nodebug(hc);
2539                 }
2540                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2541                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2542                         hfcmulti_tx(hc, ch);
2543                         /* start fifo */
2544                         HFC_outb_nodebug(hc, R_FIFO, 0);
2545                         HFC_wait_nodebug(hc);
2546                 }
2547                 j++;
2548                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2549                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2550                         hfcmulti_rx(hc, ch);
2551                 }
2552                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2553                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2554                         hfcmulti_rx(hc, ch);
2555                 }
2556                 j++;
2557         }
2558 }
2559
2560 #ifdef IRQ_DEBUG
2561 int irqsem;
2562 #endif
2563 static irqreturn_t
2564 hfcmulti_interrupt(int intno, void *dev_id)
2565 {
2566 #ifdef IRQCOUNT_DEBUG
2567         static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2568             iq5 = 0, iq6 = 0, iqcnt = 0;
2569 #endif
2570         struct hfc_multi        *hc = dev_id;
2571         struct dchannel         *dch;
2572         u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
2573         int                     i;
2574         void __iomem            *plx_acc;
2575         u_short                 wval;
2576         u_char                  e1_syncsta, temp;
2577         u_long                  flags;
2578
2579         if (!hc) {
2580                 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2581                 return IRQ_NONE;
2582         }
2583
2584         spin_lock(&hc->lock);
2585
2586 #ifdef IRQ_DEBUG
2587         if (irqsem)
2588                 printk(KERN_ERR "irq for card %d during irq from "
2589                 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2590         irqsem = hc->id + 1;
2591 #endif
2592
2593         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2594                 spin_lock_irqsave(&plx_lock, flags);
2595                 plx_acc = hc->plx_membase + PLX_INTCSR;
2596                 wval = readw(plx_acc);
2597                 spin_unlock_irqrestore(&plx_lock, flags);
2598                 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2599                         goto irq_notforus;
2600         }
2601
2602         status = HFC_inb_nodebug(hc, R_STATUS);
2603         r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2604 #ifdef IRQCOUNT_DEBUG
2605         if (r_irq_statech)
2606                 iq1++;
2607         if (status & V_DTMF_STA)
2608                 iq2++;
2609         if (status & V_LOST_STA)
2610                 iq3++;
2611         if (status & V_EXT_IRQSTA)
2612                 iq4++;
2613         if (status & V_MISC_IRQSTA)
2614                 iq5++;
2615         if (status & V_FR_IRQSTA)
2616                 iq6++;
2617         if (iqcnt++ > 5000) {
2618                 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2619                     iq1, iq2, iq3, iq4, iq5, iq6);
2620                 iqcnt = 0;
2621         }
2622 #endif
2623         if (!r_irq_statech &&
2624             !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2625             V_MISC_IRQSTA | V_FR_IRQSTA))) {
2626                 /* irq is not for us */
2627                 goto irq_notforus;
2628         }
2629         hc->irqcnt++;
2630         if (r_irq_statech) {
2631                 if (hc->type != 1)
2632                         ph_state_irq(hc, r_irq_statech);
2633         }
2634         if (status & V_EXT_IRQSTA)
2635                 ; /* external IRQ */
2636         if (status & V_LOST_STA) {
2637                 /* LOST IRQ */
2638                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2639         }
2640         if (status & V_MISC_IRQSTA) {
2641                 /* misc IRQ */
2642                 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2643                 if (r_irq_misc & V_STA_IRQ) {
2644                         if (hc->type == 1) {
2645                                 /* state machine */
2646                                 dch = hc->chan[hc->dslot].dch;
2647                                 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2648                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2649                                  && hc->e1_getclock) {
2650                                         if (e1_syncsta & V_FR_SYNC_E1)
2651                                                 hc->syncronized = 1;
2652                                         else
2653                                                 hc->syncronized = 0;
2654                                 }
2655                                 /* undocumented: status changes during read */
2656                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2657                                 while (dch->state != (temp =
2658                                         HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2659                                         if (debug & DEBUG_HFCMULTI_STATE)
2660                                                 printk(KERN_DEBUG "%s: reread "
2661                                                     "STATE because %d!=%d\n",
2662                                                     __func__, temp,
2663                                                     dch->state);
2664                                         dch->state = temp; /* repeat */
2665                                 }
2666                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2667                                         & 0x7;
2668                                 schedule_event(dch, FLG_PHCHANGE);
2669                                 if (debug & DEBUG_HFCMULTI_STATE)
2670                                         printk(KERN_DEBUG
2671                                             "%s: E1 (id=%d) newstate %x\n",
2672                                             __func__, hc->id, dch->state);
2673                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2674                                         plxsd_checksync(hc, 0);
2675                         }
2676                 }
2677                 if (r_irq_misc & V_TI_IRQ)
2678                         handle_timer_irq(hc);
2679
2680                 if (r_irq_misc & V_DTMF_IRQ) {
2681                         /* -> DTMF IRQ */
2682                         hfcmulti_dtmf(hc);
2683                 }
2684                 if (r_irq_misc & V_IRQ_PROC) {
2685                         static int irq_proc_cnt;
2686                         if (!irq_proc_cnt++)
2687                                 printk(KERN_WARNING "%s: got V_IRQ_PROC -"
2688                                     " this should not happen\n", __func__);
2689                 }
2690
2691         }
2692         if (status & V_FR_IRQSTA) {
2693                 /* FIFO IRQ */
2694                 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2695                 for (i = 0; i < 8; i++) {
2696                         if (r_irq_oview & (1 << i))
2697                                 fifo_irq(hc, i);
2698                 }
2699         }
2700
2701 #ifdef IRQ_DEBUG
2702         irqsem = 0;
2703 #endif
2704         spin_unlock(&hc->lock);
2705         return IRQ_HANDLED;
2706
2707 irq_notforus:
2708 #ifdef IRQ_DEBUG
2709         irqsem = 0;
2710 #endif
2711         spin_unlock(&hc->lock);
2712         return IRQ_NONE;
2713 }
2714
2715
2716 /*
2717  * timer callback for D-chan busy resolution. Currently no function
2718  */
2719
2720 static void
2721 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2722 {
2723 }
2724
2725
2726 /*
2727  * activate/deactivate hardware for selected channels and mode
2728  *
2729  * configure B-channel with the given protocol
2730  * ch eqals to the HFC-channel (0-31)
2731  * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2732  * for S/T, 1-31 for E1)
2733  * the hdlc interrupts will be set/unset
2734  */
2735 static int
2736 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2737     int bank_tx, int slot_rx, int bank_rx)
2738 {
2739         int flow_tx = 0, flow_rx = 0, routing = 0;
2740         int oslot_tx, oslot_rx;
2741         int conf;
2742
2743         if (ch < 0 || ch > 31)
2744                 return EINVAL;
2745         oslot_tx = hc->chan[ch].slot_tx;
2746         oslot_rx = hc->chan[ch].slot_rx;
2747         conf = hc->chan[ch].conf;
2748
2749         if (debug & DEBUG_HFCMULTI_MODE)
2750                 printk(KERN_DEBUG
2751                     "%s: card %d channel %d protocol %x slot old=%d new=%d "
2752                     "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2753                     __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2754                     bank_tx, oslot_rx, slot_rx, bank_rx);
2755
2756         if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2757                 /* remove from slot */
2758                 if (debug & DEBUG_HFCMULTI_MODE)
2759                         printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2760                             __func__, oslot_tx);
2761                 if (hc->slot_owner[oslot_tx<<1] == ch) {
2762                         HFC_outb(hc, R_SLOT, oslot_tx << 1);
2763                         HFC_outb(hc, A_SL_CFG, 0);
2764                         HFC_outb(hc, A_CONF, 0);
2765                         hc->slot_owner[oslot_tx<<1] = -1;
2766                 } else {
2767                         if (debug & DEBUG_HFCMULTI_MODE)
2768                                 printk(KERN_DEBUG
2769                                     "%s: we are not owner of this tx slot "
2770                                     "anymore, channel %d is.\n",
2771                                     __func__, hc->slot_owner[oslot_tx<<1]);
2772                 }
2773         }
2774
2775         if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2776                 /* remove from slot */
2777                 if (debug & DEBUG_HFCMULTI_MODE)
2778                         printk(KERN_DEBUG
2779                             "%s: remove from slot %d (RX)\n",
2780                             __func__, oslot_rx);
2781                 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2782                         HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2783                         HFC_outb(hc, A_SL_CFG, 0);
2784                         hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2785                 } else {
2786                         if (debug & DEBUG_HFCMULTI_MODE)
2787                                 printk(KERN_DEBUG
2788                                     "%s: we are not owner of this rx slot "
2789                                     "anymore, channel %d is.\n",
2790                                     __func__,
2791                                     hc->slot_owner[(oslot_rx << 1) | 1]);
2792                 }
2793         }
2794
2795         if (slot_tx < 0) {
2796                 flow_tx = 0x80; /* FIFO->ST */
2797                 /* disable pcm slot */
2798                 hc->chan[ch].slot_tx = -1;
2799                 hc->chan[ch].bank_tx = 0;
2800         } else {
2801                 /* set pcm slot */
2802                 if (hc->chan[ch].txpending)
2803                         flow_tx = 0x80; /* FIFO->ST */
2804                 else
2805                         flow_tx = 0xc0; /* PCM->ST */
2806                 /* put on slot */
2807                 routing = bank_tx ? 0xc0 : 0x80;
2808                 if (conf >= 0 || bank_tx > 1)
2809                         routing = 0x40; /* loop */
2810                 if (debug & DEBUG_HFCMULTI_MODE)
2811                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2812                             " %d flow %02x routing %02x conf %d (TX)\n",
2813                             __func__, ch, slot_tx, bank_tx,
2814                             flow_tx, routing, conf);
2815                 HFC_outb(hc, R_SLOT, slot_tx << 1);
2816                 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2817                 HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
2818                 hc->slot_owner[slot_tx << 1] = ch;
2819                 hc->chan[ch].slot_tx = slot_tx;
2820                 hc->chan[ch].bank_tx = bank_tx;
2821         }
2822         if (slot_rx < 0) {
2823                 /* disable pcm slot */
2824                 flow_rx = 0x80; /* ST->FIFO */
2825                 hc->chan[ch].slot_rx = -1;
2826                 hc->chan[ch].bank_rx = 0;
2827         } else {
2828                 /* set pcm slot */
2829                 if (hc->chan[ch].txpending)
2830                         flow_rx = 0x80; /* ST->FIFO */
2831                 else
2832                         flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2833                 /* put on slot */
2834                 routing = bank_rx?0x80:0xc0; /* reversed */
2835                 if (conf >= 0 || bank_rx > 1)
2836                         routing = 0x40; /* loop */
2837                 if (debug & DEBUG_HFCMULTI_MODE)
2838                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2839                             " %d flow %02x routing %02x conf %d (RX)\n",
2840                             __func__, ch, slot_rx, bank_rx,
2841                             flow_rx, routing, conf);
2842                 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2843                 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2844                 hc->slot_owner[(slot_rx<<1)|1] = ch;
2845                 hc->chan[ch].slot_rx = slot_rx;
2846                 hc->chan[ch].bank_rx = bank_rx;
2847         }
2848
2849         switch (protocol) {
2850         case (ISDN_P_NONE):
2851                 /* disable TX fifo */
2852                 HFC_outb(hc, R_FIFO, ch << 1);
2853                 HFC_wait(hc);
2854                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2855                 HFC_outb(hc, A_SUBCH_CFG, 0);
2856                 HFC_outb(hc, A_IRQ_MSK, 0);
2857                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2858                 HFC_wait(hc);
2859                 /* disable RX fifo */
2860                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2861                 HFC_wait(hc);
2862                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2863                 HFC_outb(hc, A_SUBCH_CFG, 0);
2864                 HFC_outb(hc, A_IRQ_MSK, 0);
2865                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2866                 HFC_wait(hc);
2867                 if (hc->chan[ch].bch && hc->type != 1) {
2868                         hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2869                             ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
2870                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2871                         /* undocumented: delay after R_ST_SEL */
2872                         udelay(1);
2873                         HFC_outb(hc, A_ST_CTRL0,
2874                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2875                 }
2876                 if (hc->chan[ch].bch) {
2877                         test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2878                         test_and_clear_bit(FLG_TRANSPARENT,
2879                             &hc->chan[ch].bch->Flags);
2880                 }
2881                 break;
2882         case (ISDN_P_B_RAW): /* B-channel */
2883
2884                 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2885                     (hc->chan[ch].slot_rx < 0) &&
2886                     (hc->chan[ch].slot_tx < 0)) {
2887
2888                         printk(KERN_DEBUG
2889                             "Setting B-channel %d to echo cancelable "
2890                             "state on PCM slot %d\n", ch,
2891                             ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2892                         printk(KERN_DEBUG
2893                             "Enabling pass through for channel\n");
2894                         vpm_out(hc, ch, ((ch / 4) * 8) +
2895                             ((ch % 4) * 4) + 1, 0x01);
2896                         /* rx path */
2897                         /* S/T -> PCM */
2898                         HFC_outb(hc, R_FIFO, (ch << 1));
2899                         HFC_wait(hc);
2900                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2901                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2902                             ((ch % 4) * 4) + 1) << 1);
2903                         HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2904
2905                         /* PCM -> FIFO */
2906                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2907                         HFC_wait(hc);
2908                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2909                         HFC_outb(hc, A_SUBCH_CFG, 0);
2910                         HFC_outb(hc, A_IRQ_MSK, 0);
2911                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2912                         HFC_wait(hc);
2913                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2914                             ((ch % 4) * 4) + 1) << 1) | 1);
2915                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
2916
2917                         /* tx path */
2918                         /* PCM -> S/T */
2919                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2920                         HFC_wait(hc);
2921                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2922                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2923                             ((ch % 4) * 4)) << 1) | 1);
2924                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
2925
2926                         /* FIFO -> PCM */
2927                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
2928                         HFC_wait(hc);
2929                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2930                         HFC_outb(hc, A_SUBCH_CFG, 0);
2931                         HFC_outb(hc, A_IRQ_MSK, 0);
2932                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2933                         HFC_wait(hc);
2934                         /* tx silence */
2935                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2936                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2937                             ((ch % 4) * 4)) << 1);
2938                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
2939                 } else {
2940                         /* enable TX fifo */
2941                         HFC_outb(hc, R_FIFO, ch << 1);
2942                         HFC_wait(hc);
2943                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
2944                             V_HDLC_TRP | V_IFF);
2945                         HFC_outb(hc, A_SUBCH_CFG, 0);
2946                         HFC_outb(hc, A_IRQ_MSK, 0);
2947                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2948                         HFC_wait(hc);
2949                         /* tx silence */
2950                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2951                         /* enable RX fifo */
2952                         HFC_outb(hc, R_FIFO, (ch<<1)|1);
2953                         HFC_wait(hc);
2954                         HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
2955                         HFC_outb(hc, A_SUBCH_CFG, 0);
2956                         HFC_outb(hc, A_IRQ_MSK, 0);
2957                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2958                         HFC_wait(hc);
2959                 }
2960                 if (hc->type != 1) {
2961                         hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
2962                             ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
2963                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2964                         /* undocumented: delay after R_ST_SEL */
2965                         udelay(1);
2966                         HFC_outb(hc, A_ST_CTRL0,
2967                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2968                 }
2969                 if (hc->chan[ch].bch)
2970                         test_and_set_bit(FLG_TRANSPARENT,
2971                             &hc->chan[ch].bch->Flags);
2972                 break;
2973         case (ISDN_P_B_HDLC): /* B-channel */
2974         case (ISDN_P_TE_S0): /* D-channel */
2975         case (ISDN_P_NT_S0):
2976         case (ISDN_P_TE_E1):
2977         case (ISDN_P_NT_E1):
2978                 /* enable TX fifo */
2979                 HFC_outb(hc, R_FIFO, ch<<1);
2980                 HFC_wait(hc);
2981                 if (hc->type == 1 || hc->chan[ch].bch) {
2982                         /* E1 or B-channel */
2983                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
2984                         HFC_outb(hc, A_SUBCH_CFG, 0);
2985                 } else {
2986                         /* D-Channel without HDLC fill flags */
2987                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
2988                         HFC_outb(hc, A_SUBCH_CFG, 2);
2989                 }
2990                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
2991                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2992                 HFC_wait(hc);
2993                 /* enable RX fifo */
2994                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2995                 HFC_wait(hc);
2996                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
2997                 if (hc->type == 1 || hc->chan[ch].bch)
2998                         HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
2999                 else
3000                         HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3001                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3002                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3003                 HFC_wait(hc);
3004                 if (hc->chan[ch].bch) {
3005                         test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3006                         if (hc->type != 1) {
3007                                 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3008                                   ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3009                                 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3010                                 /* undocumented: delay after R_ST_SEL */
3011                                 udelay(1);
3012                                 HFC_outb(hc, A_ST_CTRL0,
3013                                   hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3014                         }
3015                 }
3016                 break;
3017         default:
3018                 printk(KERN_DEBUG "%s: protocol not known %x\n",
3019                     __func__, protocol);
3020                 hc->chan[ch].protocol = ISDN_P_NONE;
3021                 return -ENOPROTOOPT;
3022         }
3023         hc->chan[ch].protocol = protocol;
3024         return 0;
3025 }
3026
3027
3028 /*
3029  * connect/disconnect PCM
3030  */
3031
3032 static void
3033 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3034     int slot_rx, int bank_rx)
3035 {
3036         if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3037                 /* disable PCM */
3038                 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3039                 return;
3040         }
3041
3042         /* enable pcm */
3043         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3044                 slot_rx, bank_rx);
3045 }
3046
3047 /*
3048  * set/disable conference
3049  */
3050
3051 static void
3052 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3053 {
3054         if (num >= 0 && num <= 7)
3055                 hc->chan[ch].conf = num;
3056         else
3057                 hc->chan[ch].conf = -1;
3058         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3059             hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3060             hc->chan[ch].bank_rx);
3061 }
3062
3063
3064 /*
3065  * set/disable sample loop
3066  */
3067
3068 /* NOTE: this function is experimental and therefore disabled */
3069
3070 /*
3071  * Layer 1 callback function
3072  */
3073 static int
3074 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3075 {
3076         struct hfc_multi        *hc = dch->hw;
3077         u_long  flags;
3078
3079         switch (cmd) {
3080         case INFO3_P8:
3081         case INFO3_P10:
3082                 break;
3083         case HW_RESET_REQ:
3084                 /* start activation */
3085                 spin_lock_irqsave(&hc->lock, flags);
3086                 if (hc->type == 1) {
3087                         if (debug & DEBUG_HFCMULTI_MSG)
3088                                 printk(KERN_DEBUG
3089                                     "%s: HW_RESET_REQ no BRI\n",
3090                                     __func__);
3091                 } else {
3092                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3093                         /* undocumented: delay after R_ST_SEL */
3094                         udelay(1);
3095                         HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3096                         udelay(6); /* wait at least 5,21us */
3097                         HFC_outb(hc, A_ST_WR_STATE, 3);
3098                         HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3099                                 /* activate */
3100                 }
3101                 spin_unlock_irqrestore(&hc->lock, flags);
3102                 l1_event(dch->l1, HW_POWERUP_IND);
3103                 break;
3104         case HW_DEACT_REQ:
3105                 /* start deactivation */
3106                 spin_lock_irqsave(&hc->lock, flags);
3107                 if (hc->type == 1) {
3108                         if (debug & DEBUG_HFCMULTI_MSG)
3109                                 printk(KERN_DEBUG
3110                                     "%s: HW_DEACT_REQ no BRI\n",
3111                                     __func__);
3112                 } else {
3113                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3114                         /* undocumented: delay after R_ST_SEL */
3115                         udelay(1);
3116                         HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3117                                 /* deactivate */
3118                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3119                                 hc->syncronized &=
3120                                    ~(1 << hc->chan[dch->slot].port);
3121                                 plxsd_checksync(hc, 0);
3122                         }
3123                 }
3124                 skb_queue_purge(&dch->squeue);
3125                 if (dch->tx_skb) {
3126                         dev_kfree_skb(dch->tx_skb);
3127                         dch->tx_skb = NULL;
3128                 }
3129                 dch->tx_idx = 0;
3130                 if (dch->rx_skb) {
3131                         dev_kfree_skb(dch->rx_skb);
3132                         dch->rx_skb = NULL;
3133                 }
3134                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3135                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3136                         del_timer(&dch->timer);
3137                 spin_unlock_irqrestore(&hc->lock, flags);
3138                 break;
3139         case HW_POWERUP_REQ:
3140                 spin_lock_irqsave(&hc->lock, flags);
3141                 if (hc->type == 1) {
3142                         if (debug & DEBUG_HFCMULTI_MSG)
3143                                 printk(KERN_DEBUG
3144                                     "%s: HW_POWERUP_REQ no BRI\n",
3145                                     __func__);
3146                 } else {
3147                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3148                         /* undocumented: delay after R_ST_SEL */
3149                         udelay(1);
3150                         HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3151                         udelay(6); /* wait at least 5,21us */
3152                         HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3153                 }
3154                 spin_unlock_irqrestore(&hc->lock, flags);
3155                 break;
3156         case PH_ACTIVATE_IND:
3157                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3158                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3159                         GFP_ATOMIC);
3160                 break;
3161         case PH_DEACTIVATE_IND:
3162                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3163                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3164                         GFP_ATOMIC);
3165                 break;
3166         default:
3167                 if (dch->debug & DEBUG_HW)
3168                         printk(KERN_DEBUG "%s: unknown command %x\n",
3169                             __func__, cmd);
3170                 return -1;
3171         }
3172         return 0;
3173 }
3174
3175 /*
3176  * Layer2 -> Layer 1 Transfer
3177  */
3178
3179 static int
3180 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3181 {
3182         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
3183         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
3184         struct hfc_multi        *hc = dch->hw;
3185         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3186         int                     ret = -EINVAL;
3187         unsigned int            id;
3188         u_long                  flags;
3189
3190         switch (hh->prim) {
3191         case PH_DATA_REQ:
3192                 if (skb->len < 1)
3193                         break;
3194                 spin_lock_irqsave(&hc->lock, flags);
3195                 ret = dchannel_senddata(dch, skb);
3196                 if (ret > 0) { /* direct TX */
3197                         id = hh->id; /* skb can be freed */
3198                         hfcmulti_tx(hc, dch->slot);
3199                         ret = 0;
3200                         /* start fifo */
3201                         HFC_outb(hc, R_FIFO, 0);
3202                         HFC_wait(hc);
3203                         spin_unlock_irqrestore(&hc->lock, flags);
3204                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3205                 } else
3206                         spin_unlock_irqrestore(&hc->lock, flags);
3207                 return ret;
3208         case PH_ACTIVATE_REQ:
3209                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3210                         spin_lock_irqsave(&hc->lock, flags);
3211                         ret = 0;
3212                         if (debug & DEBUG_HFCMULTI_MSG)
3213                                 printk(KERN_DEBUG
3214                                     "%s: PH_ACTIVATE port %d (0..%d)\n",
3215                                     __func__, hc->chan[dch->slot].port,
3216                                     hc->ports-1);
3217                         /* start activation */
3218                         if (hc->type == 1) {
3219                                 ph_state_change(dch);
3220                                 if (debug & DEBUG_HFCMULTI_STATE)
3221                                         printk(KERN_DEBUG
3222                                             "%s: E1 report state %x \n",
3223                                             __func__, dch->state);
3224                         } else {
3225                                 HFC_outb(hc, R_ST_SEL,
3226                                     hc->chan[dch->slot].port);
3227                                 /* undocumented: delay after R_ST_SEL */
3228                                 udelay(1);
3229                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3230                                     /* G1 */
3231                                 udelay(6); /* wait at least 5,21us */
3232                                 HFC_outb(hc, A_ST_WR_STATE, 1);
3233                                 HFC_outb(hc, A_ST_WR_STATE, 1 |
3234                                     (V_ST_ACT*3)); /* activate */
3235                                 dch->state = 1;
3236                         }
3237                         spin_unlock_irqrestore(&hc->lock, flags);
3238                 } else
3239                         ret = l1_event(dch->l1, hh->prim);
3240                 break;
3241         case PH_DEACTIVATE_REQ:
3242                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3243                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3244                         spin_lock_irqsave(&hc->lock, flags);
3245                         if (debug & DEBUG_HFCMULTI_MSG)
3246                                 printk(KERN_DEBUG
3247                                     "%s: PH_DEACTIVATE port %d (0..%d)\n",
3248                                     __func__, hc->chan[dch->slot].port,
3249                                     hc->ports-1);
3250                         /* start deactivation */
3251                         if (hc->type == 1) {
3252                                 if (debug & DEBUG_HFCMULTI_MSG)
3253                                         printk(KERN_DEBUG
3254                                             "%s: PH_DEACTIVATE no BRI\n",
3255                                             __func__);
3256                         } else {
3257                                 HFC_outb(hc, R_ST_SEL,
3258                                     hc->chan[dch->slot].port);
3259                                 /* undocumented: delay after R_ST_SEL */
3260                                 udelay(1);
3261                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3262                                     /* deactivate */
3263                                 dch->state = 1;
3264                         }
3265                         skb_queue_purge(&dch->squeue);
3266                         if (dch->tx_skb) {
3267                                 dev_kfree_skb(dch->tx_skb);
3268                                 dch->tx_skb = NULL;
3269                         }
3270                         dch->tx_idx = 0;
3271                         if (dch->rx_skb) {
3272                                 dev_kfree_skb(dch->rx_skb);
3273                                 dch->rx_skb = NULL;
3274                         }
3275                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3276                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3277                                 del_timer(&dch->timer);
3278 #ifdef FIXME
3279                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3280                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3281 #endif
3282                         ret = 0;
3283                         spin_unlock_irqrestore(&hc->lock, flags);
3284                 } else
3285                         ret = l1_event(dch->l1, hh->prim);
3286                 break;
3287         }
3288         if (!ret)
3289                 dev_kfree_skb(skb);
3290         return ret;
3291 }
3292
3293 static void
3294 deactivate_bchannel(struct bchannel *bch)
3295 {
3296         struct hfc_multi        *hc = bch->hw;
3297         u_long                  flags;
3298
3299         spin_lock_irqsave(&hc->lock, flags);
3300         if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
3301                 dev_kfree_skb(bch->next_skb);
3302                 bch->next_skb = NULL;
3303         }
3304         if (bch->tx_skb) {
3305                 dev_kfree_skb(bch->tx_skb);
3306                 bch->tx_skb = NULL;
3307         }
3308         bch->tx_idx = 0;
3309         if (bch->rx_skb) {
3310                 dev_kfree_skb(bch->rx_skb);
3311                 bch->rx_skb = NULL;
3312         }
3313         hc->chan[bch->slot].coeff_count = 0;
3314         test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
3315         test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
3316         hc->chan[bch->slot].rx_off = 0;
3317         hc->chan[bch->slot].conf = -1;
3318         mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3319         spin_unlock_irqrestore(&hc->lock, flags);
3320 }
3321
3322 static int
3323 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3324 {
3325         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3326         struct hfc_multi        *hc = bch->hw;
3327         int                     ret = -EINVAL;
3328         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3329         unsigned int            id;
3330         u_long                  flags;
3331
3332         switch (hh->prim) {
3333         case PH_DATA_REQ:
3334                 if (!skb->len)
3335                         break;
3336                 spin_lock_irqsave(&hc->lock, flags);
3337                 ret = bchannel_senddata(bch, skb);
3338                 if (ret > 0) { /* direct TX */
3339                         id = hh->id; /* skb can be freed */
3340                         hfcmulti_tx(hc, bch->slot);
3341                         ret = 0;
3342                         /* start fifo */
3343                         HFC_outb_nodebug(hc, R_FIFO, 0);
3344                         HFC_wait_nodebug(hc);
3345                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3346                                 spin_unlock_irqrestore(&hc->lock, flags);
3347                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3348                         } else
3349                                 spin_unlock_irqrestore(&hc->lock, flags);
3350                 } else
3351                         spin_unlock_irqrestore(&hc->lock, flags);
3352                 return ret;
3353         case PH_ACTIVATE_REQ:
3354                 if (debug & DEBUG_HFCMULTI_MSG)
3355                         printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3356                                 __func__, bch->slot);
3357                 spin_lock_irqsave(&hc->lock, flags);
3358                 /* activate B-channel if not already activated */
3359                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3360                         hc->chan[bch->slot].txpending = 0;
3361                         ret = mode_hfcmulti(hc, bch->slot,
3362                                 ch->protocol,
3363                                 hc->chan[bch->slot].slot_tx,
3364                                 hc->chan[bch->slot].bank_tx,
3365                                 hc->chan[bch->slot].slot_rx,
3366                                 hc->chan[bch->slot].bank_rx);
3367                         if (!ret) {
3368                                 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3369                                         && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3370                                         /* start decoder */
3371                                         hc->dtmf = 1;
3372                                         if (debug & DEBUG_HFCMULTI_DTMF)
3373                                                 printk(KERN_DEBUG
3374                                                     "%s: start dtmf decoder\n",
3375                                                         __func__);
3376                                         HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3377                                             V_RST_DTMF);
3378                                 }
3379                         }
3380                 } else
3381                         ret = 0;
3382                 spin_unlock_irqrestore(&hc->lock, flags);
3383                 if (!ret)
3384                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3385                                 GFP_KERNEL);
3386                 break;
3387         case PH_CONTROL_REQ:
3388                 spin_lock_irqsave(&hc->lock, flags);
3389                 switch (hh->id) {
3390                 case HFC_SPL_LOOP_ON: /* set sample loop */
3391                         if (debug & DEBUG_HFCMULTI_MSG)
3392                         printk(KERN_DEBUG
3393                             "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3394                             __func__, skb->len);
3395                         ret = 0;
3396                         break;
3397                 case HFC_SPL_LOOP_OFF: /* set silence */
3398                         if (debug & DEBUG_HFCMULTI_MSG)
3399                                 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3400                                     __func__);
3401                         ret = 0;
3402                         break;
3403                 default:
3404                         printk(KERN_ERR
3405                              "%s: unknown PH_CONTROL_REQ info %x\n",
3406                              __func__, hh->id);
3407                         ret = -EINVAL;
3408                 }
3409                 spin_unlock_irqrestore(&hc->lock, flags);
3410                 break;
3411         case PH_DEACTIVATE_REQ:
3412                 deactivate_bchannel(bch); /* locked there */
3413                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3414                         GFP_KERNEL);
3415                 ret = 0;
3416                 break;
3417         }
3418         if (!ret)
3419                 dev_kfree_skb(skb);
3420         return ret;
3421 }
3422
3423 /*
3424  * bchannel control function
3425  */
3426 static int
3427 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3428 {
3429         int                     ret = 0;
3430         struct dsp_features     *features =
3431                 (struct dsp_features *)(*((u_long *)&cq->p1));
3432         struct hfc_multi        *hc = bch->hw;
3433         int                     slot_tx;
3434         int                     bank_tx;
3435         int                     slot_rx;
3436         int                     bank_rx;
3437         int                     num;
3438
3439         switch (cq->op) {
3440         case MISDN_CTRL_GETOP:
3441                 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3442                         | MISDN_CTRL_RX_OFF;
3443                 break;
3444         case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3445                 hc->chan[bch->slot].rx_off = !!cq->p1;
3446                 if (!hc->chan[bch->slot].rx_off) {
3447                         /* reset fifo on rx on */
3448                         HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3449                         HFC_wait_nodebug(hc);
3450                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3451                         HFC_wait_nodebug(hc);
3452                 }
3453                 if (debug & DEBUG_HFCMULTI_MSG)
3454                         printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3455                             __func__, bch->nr, hc->chan[bch->slot].rx_off);
3456                 break;
3457         case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3458                 if (debug & DEBUG_HFCMULTI_MSG)
3459                         printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3460                             __func__);
3461                 /* create confirm */
3462                 features->hfc_id = hc->id;
3463                 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3464                         features->hfc_dtmf = 1;
3465                 features->hfc_loops = 0;
3466                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3467                         features->hfc_echocanhw = 1;
3468                 } else {
3469                         features->pcm_id = hc->pcm;
3470                         features->pcm_slots = hc->slots;
3471                         features->pcm_banks = 2;
3472                 }
3473                 break;
3474         case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3475                 slot_tx = cq->p1 & 0xff;
3476                 bank_tx = cq->p1 >> 8;
3477                 slot_rx = cq->p2 & 0xff;
3478                 bank_rx = cq->p2 >> 8;
3479                 if (debug & DEBUG_HFCMULTI_MSG)
3480                         printk(KERN_DEBUG
3481                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3482                             "slot %d bank %d (RX)\n",
3483                             __func__, slot_tx, bank_tx,
3484                             slot_rx, bank_rx);
3485                 if (slot_tx < hc->slots && bank_tx <= 2 &&
3486                     slot_rx < hc->slots && bank_rx <= 2)
3487                         hfcmulti_pcm(hc, bch->slot,
3488                             slot_tx, bank_tx, slot_rx, bank_rx);
3489                 else {
3490                         printk(KERN_WARNING
3491                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3492                             "slot %d bank %d (RX) out of range\n",
3493                             __func__, slot_tx, bank_tx,
3494                             slot_rx, bank_rx);
3495                         ret = -EINVAL;
3496                 }
3497                 break;
3498         case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3499                 if (debug & DEBUG_HFCMULTI_MSG)
3500                         printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3501                             __func__);
3502                 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3503                 break;
3504         case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3505                 num = cq->p1 & 0xff;
3506                 if (debug & DEBUG_HFCMULTI_MSG)
3507                         printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3508                             __func__, num);
3509                 if (num <= 7)
3510                         hfcmulti_conf(hc, bch->slot, num);
3511                 else {
3512                         printk(KERN_WARNING
3513                             "%s: HW_CONF_JOIN conf %d out of range\n",
3514                             __func__, num);
3515                         ret = -EINVAL;
3516                 }
3517                 break;
3518         case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3519                 if (debug & DEBUG_HFCMULTI_MSG)
3520                         printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3521                 hfcmulti_conf(hc, bch->slot, -1);
3522                 break;
3523         case MISDN_CTRL_HFC_ECHOCAN_ON:
3524                 if (debug & DEBUG_HFCMULTI_MSG)
3525                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3526                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3527                         vpm_echocan_on(hc, bch->slot, cq->p1);
3528                 else
3529                         ret = -EINVAL;
3530                 break;
3531
3532         case MISDN_CTRL_HFC_ECHOCAN_OFF:
3533                 if (debug & DEBUG_HFCMULTI_MSG)
3534                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3535                                 __func__);
3536                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3537                         vpm_echocan_off(hc, bch->slot);
3538                 else
3539                         ret = -EINVAL;
3540                 break;
3541         default:
3542                 printk(KERN_WARNING "%s: unknown Op %x\n",
3543                     __func__, cq->op);
3544                 ret = -EINVAL;
3545                 break;
3546         }
3547         return ret;
3548 }
3549
3550 static int
3551 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3552 {
3553         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3554         struct hfc_multi        *hc = bch->hw;
3555         int                     err = -EINVAL;
3556         u_long  flags;
3557
3558         if (bch->debug & DEBUG_HW)
3559                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3560                     __func__, cmd, arg);
3561         switch (cmd) {
3562         case CLOSE_CHANNEL:
3563                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3564                 if (test_bit(FLG_ACTIVE, &bch->Flags))
3565                         deactivate_bchannel(bch); /* locked there */
3566                 ch->protocol = ISDN_P_NONE;
3567                 ch->peer = NULL;
3568                 module_put(THIS_MODULE);
3569                 err = 0;
3570                 break;
3571         case CONTROL_CHANNEL:
3572                 spin_lock_irqsave(&hc->lock, flags);
3573                 err = channel_bctrl(bch, arg);
3574                 spin_unlock_irqrestore(&hc->lock, flags);
3575                 break;
3576         default:
3577                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3578                         __func__, cmd);
3579         }
3580         return err;
3581 }
3582
3583 /*
3584  * handle D-channel events
3585  *
3586  * handle state change event
3587  */
3588 static void
3589 ph_state_change(struct dchannel *dch)
3590 {
3591         struct hfc_multi *hc = dch->hw;
3592         int ch, i;
3593
3594         if (!dch) {
3595                 printk(KERN_WARNING "%s: ERROR given dch is NULL\n",
3596                     __func__);
3597                 return;
3598         }
3599         ch = dch->slot;
3600
3601         if (hc->type == 1) {
3602                 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3603                         if (debug & DEBUG_HFCMULTI_STATE)
3604                                 printk(KERN_DEBUG
3605                                     "%s: E1 TE (id=%d) newstate %x\n",
3606                                     __func__, hc->id, dch->state);
3607                 } else {
3608                         if (debug & DEBUG_HFCMULTI_STATE)
3609                                 printk(KERN_DEBUG
3610                                     "%s: E1 NT (id=%d) newstate %x\n",
3611                                     __func__, hc->id, dch->state);
3612                 }
3613                 switch (dch->state) {
3614                 case (1):
3615                         if (hc->e1_state != 1) {
3616                             for (i = 1; i <= 31; i++) {
3617                                 /* reset fifos on e1 activation */
3618                                 HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1);
3619                                 HFC_wait_nodebug(hc);
3620                                 HFC_outb_nodebug(hc,
3621                                         R_INC_RES_FIFO, V_RES_F);
3622                                 HFC_wait_nodebug(hc);
3623                             }
3624                         }
3625                         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3626                         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3627                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3628                         break;
3629
3630                 default:
3631                         if (hc->e1_state != 1)
3632                                 return;
3633                         test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3634                         _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3635                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3636                 }
3637                 hc->e1_state = dch->state;
3638         } else {
3639                 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3640                         if (debug & DEBUG_HFCMULTI_STATE)
3641                                 printk(KERN_DEBUG
3642                                     "%s: S/T TE newstate %x\n",
3643                                     __func__, dch->state);
3644                         switch (dch->state) {
3645                         case (0):
3646                                 l1_event(dch->l1, HW_RESET_IND);
3647                                 break;
3648                         case (3):
3649                                 l1_event(dch->l1, HW_DEACT_IND);
3650                                 break;
3651                         case (5):
3652                         case (8):
3653                                 l1_event(dch->l1, ANYSIGNAL);
3654                                 break;
3655                         case (6):
3656                                 l1_event(dch->l1, INFO2);
3657                                 break;
3658                         case (7):
3659                                 l1_event(dch->l1, INFO4_P8);
3660                                 break;
3661                         }
3662                 } else {
3663                         if (debug & DEBUG_HFCMULTI_STATE)
3664                                 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3665                                     __func__, dch->state);
3666                         switch (dch->state) {
3667                         case (2):
3668                                 if (hc->chan[ch].nt_timer == 0) {
3669                                         hc->chan[ch].nt_timer = -1;
3670                                         HFC_outb(hc, R_ST_SEL,
3671                                             hc->chan[ch].port);
3672                                         /* undocumented: delay after R_ST_SEL */
3673                                         udelay(1);
3674                                         HFC_outb(hc, A_ST_WR_STATE, 4 |
3675                                             V_ST_LD_STA); /* G4 */
3676                                         udelay(6); /* wait at least 5,21us */
3677                                         HFC_outb(hc, A_ST_WR_STATE, 4);
3678                                         dch->state = 4;
3679                                 } else {
3680                                         /* one extra count for the next event */
3681                                         hc->chan[ch].nt_timer =
3682                                             nt_t1_count[poll_timer] + 1;
3683                                         HFC_outb(hc, R_ST_SEL,
3684                                             hc->chan[ch].port);
3685                                         /* undocumented: delay after R_ST_SEL */
3686                                         udelay(1);
3687                                         /* allow G2 -> G3 transition */
3688                                         HFC_outb(hc, A_ST_WR_STATE, 2 |
3689                                             V_SET_G2_G3);
3690                                 }
3691                                 break;
3692                         case (1):
3693                                 hc->chan[ch].nt_timer = -1;
3694                                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3695                                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3696                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3697                                 break;
3698                         case (4):
3699                                 hc->chan[ch].nt_timer = -1;
3700                                 break;
3701                         case (3):
3702                                 hc->chan[ch].nt_timer = -1;
3703                                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3704                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3705                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3706                                 break;
3707                         }
3708                 }
3709         }
3710 }
3711
3712 /*
3713  * called for card mode init message
3714  */
3715
3716 static void
3717 hfcmulti_initmode(struct dchannel *dch)
3718 {
3719         struct hfc_multi *hc = dch->hw;
3720         u_char          a_st_wr_state, r_e1_wr_sta;
3721         int             i, pt;
3722
3723         if (debug & DEBUG_HFCMULTI_INIT)
3724                 printk(KERN_DEBUG "%s: entered\n", __func__);
3725
3726         if (hc->type == 1) {
3727                 hc->chan[hc->dslot].slot_tx = -1;
3728                 hc->chan[hc->dslot].slot_rx = -1;
3729                 hc->chan[hc->dslot].conf = -1;
3730                 if (hc->dslot) {
3731                         mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3732                                 -1, 0, -1, 0);
3733                         dch->timer.function = (void *) hfcmulti_dbusy_timer;
3734                         dch->timer.data = (long) dch;
3735                         init_timer(&dch->timer);
3736                 }
3737                 for (i = 1; i <= 31; i++) {
3738                         if (i == hc->dslot)
3739                                 continue;
3740                         hc->chan[i].slot_tx = -1;
3741                         hc->chan[i].slot_rx = -1;
3742                         hc->chan[i].conf = -1;
3743                         mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3744                 }
3745                 /* E1 */
3746                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3747                         HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3748                         HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3749                 }
3750                 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3751                         HFC_outb(hc, R_RX0, 0);
3752                         hc->hw.r_tx0 = 0 | V_OUT_EN;
3753                 } else {
3754                         HFC_outb(hc, R_RX0, 1);
3755                         hc->hw.r_tx0 = 1 | V_OUT_EN;
3756                 }
3757                 hc->hw.r_tx1 = V_ATX | V_NTRI;
3758                 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3759                 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3760                 HFC_outb(hc, R_TX_FR0, 0x00);
3761                 HFC_outb(hc, R_TX_FR1, 0xf8);
3762
3763                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3764                         HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3765
3766                 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3767
3768                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3769                         HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3770
3771                 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3772                         if (debug & DEBUG_HFCMULTI_INIT)
3773                                 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3774                                     __func__);
3775                         r_e1_wr_sta = 0; /* G0 */
3776                         hc->e1_getclock = 0;
3777                 } else {
3778                         if (debug & DEBUG_HFCMULTI_INIT)
3779                                 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3780                                     __func__);
3781                         r_e1_wr_sta = 0; /* F0 */
3782                         hc->e1_getclock = 1;
3783                 }
3784                 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3785                         HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3786                 else
3787                         HFC_outb(hc, R_SYNC_OUT, 0);
3788                 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3789                         hc->e1_getclock = 1;
3790                 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3791                         hc->e1_getclock = 0;
3792                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3793                         /* SLAVE (clock master) */
3794                         if (debug & DEBUG_HFCMULTI_INIT)
3795                                 printk(KERN_DEBUG
3796                                     "%s: E1 port is clock master "
3797                                     "(clock from PCM)\n", __func__);
3798                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3799                 } else {
3800                         if (hc->e1_getclock) {
3801                                 /* MASTER (clock slave) */
3802                                 if (debug & DEBUG_HFCMULTI_INIT)
3803                                         printk(KERN_DEBUG
3804                                             "%s: E1 port is clock slave "
3805                                             "(clock to PCM)\n", __func__);
3806                                 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3807                         } else {
3808                                 /* MASTER (clock master) */
3809                                 if (debug & DEBUG_HFCMULTI_INIT)
3810                                         printk(KERN_DEBUG "%s: E1 port is "
3811                                             "clock master "
3812                                             "(clock from QUARTZ)\n",
3813                                             __func__);
3814                                 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3815                                     V_PCM_SYNC | V_JATT_OFF);
3816                                 HFC_outb(hc, R_SYNC_OUT, 0);
3817                         }
3818                 }
3819                 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3820                 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3821                 HFC_outb(hc, R_PWM0, 0x50);
3822                 HFC_outb(hc, R_PWM1, 0xff);
3823                 /* state machine setup */
3824                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3825                 udelay(6); /* wait at least 5,21us */
3826                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3827                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3828                         hc->syncronized = 0;
3829                         plxsd_checksync(hc, 0);
3830                 }
3831         } else {
3832                 i = dch->slot;
3833                 hc->chan[i].slot_tx = -1;
3834                 hc->chan[i].slot_rx = -1;
3835                 hc->chan[i].conf = -1;
3836                 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3837                 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3838                 dch->timer.data = (long) dch;
3839                 init_timer(&dch->timer);
3840                 hc->chan[i - 2].slot_tx = -1;
3841                 hc->chan[i - 2].slot_rx = -1;
3842                 hc->chan[i - 2].conf = -1;
3843                 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3844                 hc->chan[i - 1].slot_tx = -1;
3845                 hc->chan[i - 1].slot_rx = -1;
3846                 hc->chan[i - 1].conf = -1;
3847                 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3848                 /* ST */
3849                 pt = hc->chan[i].port;
3850                 /* select interface */
3851                 HFC_outb(hc, R_ST_SEL, pt);
3852                 /* undocumented: delay after R_ST_SEL */
3853                 udelay(1);
3854                 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3855                         if (debug & DEBUG_HFCMULTI_INIT)
3856                                 printk(KERN_DEBUG
3857                                     "%s: ST port %d is NT-mode\n",
3858                                     __func__, pt);
3859                         /* clock delay */
3860                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3861                         a_st_wr_state = 1; /* G1 */
3862                         hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3863                 } else {
3864                         if (debug & DEBUG_HFCMULTI_INIT)
3865                                 printk(KERN_DEBUG
3866                                     "%s: ST port %d is TE-mode\n",
3867                                     __func__, pt);
3868                         /* clock delay */
3869                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3870                         a_st_wr_state = 2; /* F2 */
3871                         hc->hw.a_st_ctrl0[pt] = 0;
3872                 }
3873                 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3874                         hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3875                 /* line setup */
3876                 HFC_outb(hc, A_ST_CTRL0,  hc->hw.a_st_ctrl0[pt]);
3877                 /* disable E-channel */
3878                 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3879                     test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3880                         HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3881                 else
3882                         HFC_outb(hc, A_ST_CTRL1, 0);
3883                 /* enable B-channel receive */
3884                 HFC_outb(hc, A_ST_CTRL2,  V_B1_RX_EN | V_B2_RX_EN);
3885                 /* state machine setup */
3886                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3887                 udelay(6); /* wait at least 5,21us */
3888                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
3889                 hc->hw.r_sci_msk |= 1 << pt;
3890                 /* state machine interrupts */
3891                 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
3892                 /* unset sync on port */
3893                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3894                         hc->syncronized &=
3895                            ~(1 << hc->chan[dch->slot].port);
3896                         plxsd_checksync(hc, 0);
3897                 }
3898         }
3899         if (debug & DEBUG_HFCMULTI_INIT)
3900                 printk("%s: done\n", __func__);
3901 }
3902
3903
3904 static int
3905 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
3906     struct channel_req *rq)
3907 {
3908         int     err = 0;
3909         u_long  flags;
3910
3911         if (debug & DEBUG_HW_OPEN)
3912                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
3913                     dch->dev.id, __builtin_return_address(0));
3914         if (rq->protocol == ISDN_P_NONE)
3915                 return -EINVAL;
3916         if ((dch->dev.D.protocol != ISDN_P_NONE) &&
3917             (dch->dev.D.protocol != rq->protocol)) {
3918             if (debug & DEBUG_HFCMULTI_MODE)
3919                 printk(KERN_WARNING "%s: change protocol %x to %x\n",
3920                     __func__, dch->dev.D.protocol, rq->protocol);
3921         }
3922         if ((dch->dev.D.protocol == ISDN_P_TE_S0)
3923          && (rq->protocol != ISDN_P_TE_S0))
3924                 l1_event(dch->l1, CLOSE_CHANNEL);
3925         if (dch->dev.D.protocol != rq->protocol) {
3926                 if (rq->protocol == ISDN_P_TE_S0) {
3927                         err = create_l1(dch, hfcm_l1callback);
3928                         if (err)
3929                                 return err;
3930                 }
3931                 dch->dev.D.protocol = rq->protocol;
3932                 spin_lock_irqsave(&hc->lock, flags);
3933                 hfcmulti_initmode(dch);
3934                 spin_unlock_irqrestore(&hc->lock, flags);
3935         }
3936
3937         if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
3938             ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
3939             ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
3940             ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
3941                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
3942                     0, NULL, GFP_KERNEL);
3943         }
3944         rq->ch = &dch->dev.D;
3945         if (!try_module_get(THIS_MODULE))
3946                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3947         return 0;
3948 }
3949
3950 static int
3951 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
3952     struct channel_req *rq)
3953 {
3954         struct bchannel *bch;
3955         int             ch;
3956
3957         if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
3958                 return -EINVAL;
3959         if (rq->protocol == ISDN_P_NONE)
3960                 return -EINVAL;
3961         if (hc->type == 1)
3962                 ch = rq->adr.channel;
3963         else
3964                 ch = (rq->adr.channel - 1) + (dch->slot - 2);
3965         bch = hc->chan[ch].bch;
3966         if (!bch) {
3967                 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
3968                     __func__, ch);
3969                 return -EINVAL;
3970         }
3971         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
3972                 return -EBUSY; /* b-channel can be only open once */
3973         bch->ch.protocol = rq->protocol;
3974         hc->chan[ch].rx_off = 0;
3975         rq->ch = &bch->ch;
3976         if (!try_module_get(THIS_MODULE))
3977                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3978         return 0;
3979 }
3980
3981 /*
3982  * device control function
3983  */
3984 static int
3985 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
3986 {
3987         int     ret = 0;
3988
3989         switch (cq->op) {
3990         case MISDN_CTRL_GETOP:
3991                 cq->op = 0;
3992                 break;
3993         default:
3994                 printk(KERN_WARNING "%s: unknown Op %x\n",
3995                     __func__, cq->op);
3996                 ret = -EINVAL;
3997                 break;
3998         }
3999         return ret;
4000 }
4001
4002 static int
4003 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4004 {
4005         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
4006         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
4007         struct hfc_multi        *hc = dch->hw;
4008         struct channel_req      *rq;
4009         int                     err = 0;
4010         u_long                  flags;
4011
4012         if (dch->debug & DEBUG_HW)
4013                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4014                     __func__, cmd, arg);
4015         switch (cmd) {
4016         case OPEN_CHANNEL:
4017                 rq = arg;
4018                 switch (rq->protocol) {
4019                 case ISDN_P_TE_S0:
4020                 case ISDN_P_NT_S0:
4021                         if (hc->type == 1) {
4022                                 err = -EINVAL;
4023                                 break;
4024                         }
4025                         err = open_dchannel(hc, dch, rq); /* locked there */
4026                         break;
4027                 case ISDN_P_TE_E1:
4028                 case ISDN_P_NT_E1:
4029                         if (hc->type != 1) {
4030                                 err = -EINVAL;
4031                                 break;
4032                         }
4033                         err = open_dchannel(hc, dch, rq); /* locked there */
4034                         break;
4035                 default:
4036                         spin_lock_irqsave(&hc->lock, flags);
4037                         err = open_bchannel(hc, dch, rq);
4038                         spin_unlock_irqrestore(&hc->lock, flags);
4039                 }
4040                 break;
4041         case CLOSE_CHANNEL:
4042                 if (debug & DEBUG_HW_OPEN)
4043                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4044                             __func__, dch->dev.id,
4045                             __builtin_return_address(0));
4046                 module_put(THIS_MODULE);
4047                 break;
4048         case CONTROL_CHANNEL:
4049                 spin_lock_irqsave(&hc->lock, flags);
4050                 err = channel_dctrl(dch, arg);
4051                 spin_unlock_irqrestore(&hc->lock, flags);
4052                 break;
4053         default:
4054                 if (dch->debug & DEBUG_HW)
4055                         printk(KERN_DEBUG "%s: unknown command %x\n",
4056                             __func__, cmd);
4057                 err = -EINVAL;
4058         }
4059         return err;
4060 }
4061
4062 /*
4063  * initialize the card
4064  */
4065
4066 /*
4067  * start timer irq, wait some time and check if we have interrupts.
4068  * if not, reset chip and try again.
4069  */
4070 static int
4071 init_card(struct hfc_multi *hc)
4072 {
4073         int     err = -EIO;
4074         u_long  flags;
4075         void    __iomem *plx_acc;
4076         u_long  plx_flags;
4077
4078         if (debug & DEBUG_HFCMULTI_INIT)
4079                 printk(KERN_DEBUG "%s: entered\n", __func__);
4080
4081         spin_lock_irqsave(&hc->lock, flags);
4082         /* set interrupts but leave global interrupt disabled */
4083         hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4084         disable_hwirq(hc);
4085         spin_unlock_irqrestore(&hc->lock, flags);
4086
4087         if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
4088             "HFC-multi", hc)) {
4089                 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4090                     hc->pci_dev->irq);
4091                 return -EIO;
4092         }
4093         hc->irq = hc->pci_dev->irq;
4094
4095         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4096                 spin_lock_irqsave(&plx_lock, plx_flags);
4097                 plx_acc = hc->plx_membase + PLX_INTCSR;
4098                 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4099                         plx_acc); /* enable PCI & LINT1 irq */
4100                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4101         }
4102
4103         if (debug & DEBUG_HFCMULTI_INIT)
4104                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4105                     __func__, hc->irq, hc->irqcnt);
4106         err = init_chip(hc);
4107         if (err)
4108                 goto error;
4109         /*
4110          * Finally enable IRQ output
4111          * this is only allowed, if an IRQ routine is allready
4112          * established for this HFC, so don't do that earlier
4113          */
4114         spin_lock_irqsave(&hc->lock, flags);
4115         enable_hwirq(hc);
4116         spin_unlock_irqrestore(&hc->lock, flags);
4117         /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4118         set_current_state(TASK_UNINTERRUPTIBLE);
4119         schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4120         /* turn IRQ off until chip is completely initialized */
4121         spin_lock_irqsave(&hc->lock, flags);
4122         disable_hwirq(hc);
4123         spin_unlock_irqrestore(&hc->lock, flags);
4124         if (debug & DEBUG_HFCMULTI_INIT)
4125                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4126                     __func__, hc->irq, hc->irqcnt);
4127         if (hc->irqcnt) {
4128                 if (debug & DEBUG_HFCMULTI_INIT)
4129                         printk(KERN_DEBUG "%s: done\n", __func__);
4130
4131                 return 0;
4132         }
4133         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4134                 printk(KERN_INFO "ignoring missing interrupts\n");
4135                 return 0;
4136         }
4137
4138         printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4139                 hc->irq);
4140
4141         err = -EIO;
4142
4143 error:
4144         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4145                 spin_lock_irqsave(&plx_lock, plx_flags);
4146                 plx_acc = hc->plx_membase + PLX_INTCSR;
4147                 writew(0x00, plx_acc); /*disable IRQs*/
4148                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4149         }
4150
4151         if (debug & DEBUG_HFCMULTI_INIT)
4152                 printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq);
4153         if (hc->irq) {
4154                 free_irq(hc->irq, hc);
4155                 hc->irq = 0;
4156         }
4157
4158         if (debug & DEBUG_HFCMULTI_INIT)
4159                 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4160         return err;
4161 }
4162
4163 /*
4164  * find pci device and set it up
4165  */
4166
4167 static int
4168 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4169                 const struct pci_device_id *ent)
4170 {
4171         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4172
4173         printk(KERN_INFO
4174             "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4175             m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4176
4177         hc->pci_dev = pdev;
4178         if (m->clock2)
4179                 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4180
4181         if (ent->device == 0xB410) {
4182                 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4183                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4184                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4185                 hc->slots = 32;
4186         }
4187
4188         if (hc->pci_dev->irq <= 0) {
4189                 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4190                 return -EIO;
4191         }
4192         if (pci_enable_device(hc->pci_dev)) {
4193                 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4194                 return -EIO;
4195         }
4196         hc->leds = m->leds;
4197         hc->ledstate = 0xAFFEAFFE;
4198         hc->opticalsupport = m->opticalsupport;
4199
4200         /* set memory access methods */
4201         if (m->io_mode) /* use mode from card config */
4202                 hc->io_mode = m->io_mode;
4203         switch (hc->io_mode) {
4204         case HFC_IO_MODE_PLXSD:
4205                 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4206                 hc->slots = 128; /* required */
4207                 /* fall through */
4208         case HFC_IO_MODE_PCIMEM:
4209                 hc->HFC_outb = HFC_outb_pcimem;
4210                 hc->HFC_inb = HFC_inb_pcimem;
4211                 hc->HFC_inw = HFC_inw_pcimem;
4212                 hc->HFC_wait = HFC_wait_pcimem;
4213                 hc->read_fifo = read_fifo_pcimem;
4214                 hc->write_fifo = write_fifo_pcimem;
4215                 break;
4216         case HFC_IO_MODE_REGIO:
4217                 hc->HFC_outb = HFC_outb_regio;
4218                 hc->HFC_inb = HFC_inb_regio;
4219                 hc->HFC_inw = HFC_inw_regio;
4220                 hc->HFC_wait = HFC_wait_regio;
4221                 hc->read_fifo = read_fifo_regio;
4222                 hc->write_fifo = write_fifo_regio;
4223                 break;
4224         default:
4225                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4226                 pci_disable_device(hc->pci_dev);
4227                 return -EIO;
4228         }
4229         hc->HFC_outb_nodebug = hc->HFC_outb;
4230         hc->HFC_inb_nodebug = hc->HFC_inb;
4231         hc->HFC_inw_nodebug = hc->HFC_inw;
4232         hc->HFC_wait_nodebug = hc->HFC_wait;
4233 #ifdef HFC_REGISTER_DEBUG
4234         hc->HFC_outb = HFC_outb_debug;
4235         hc->HFC_inb = HFC_inb_debug;
4236         hc->HFC_inw = HFC_inw_debug;
4237         hc->HFC_wait = HFC_wait_debug;
4238 #endif
4239         hc->pci_iobase = 0;
4240         hc->pci_membase = NULL;
4241         hc->plx_membase = NULL;
4242
4243         switch (hc->io_mode) {
4244         case HFC_IO_MODE_PLXSD:
4245                 hc->plx_origmembase =  hc->pci_dev->resource[0].start;
4246                 /* MEMBASE 1 is PLX PCI Bridge */
4247
4248                 if (!hc->plx_origmembase) {
4249                         printk(KERN_WARNING
4250                           "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4251                         pci_disable_device(hc->pci_dev);
4252                         return -EIO;
4253                 }
4254
4255                 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4256                 if (!hc->plx_membase) {
4257                         printk(KERN_WARNING
4258                             "HFC-multi: failed to remap plx address space. "
4259                             "(internal error)\n");
4260                         pci_disable_device(hc->pci_dev);
4261                         return -EIO;
4262                 }
4263                 printk(KERN_INFO
4264                     "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4265                     (u_long)hc->plx_membase, hc->plx_origmembase);
4266
4267                 hc->pci_origmembase =  hc->pci_dev->resource[2].start;
4268                     /* MEMBASE 1 is PLX PCI Bridge */
4269                 if (!hc->pci_origmembase) {
4270                         printk(KERN_WARNING
4271                             "HFC-multi: No IO-Memory for PCI card found\n");
4272                         pci_disable_device(hc->pci_dev);
4273                         return -EIO;
4274                 }
4275
4276                 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4277                 if (!hc->pci_membase) {
4278                         printk(KERN_WARNING "HFC-multi: failed to remap io "
4279                             "address space. (internal error)\n");
4280                         pci_disable_device(hc->pci_dev);
4281                         return -EIO;
4282                 }
4283
4284                 printk(KERN_INFO
4285                     "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4286                     "leds-type %d\n",
4287                     hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4288                     hc->pci_dev->irq, HZ, hc->leds);
4289                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4290                 break;
4291         case HFC_IO_MODE_PCIMEM:
4292                 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4293                 if (!hc->pci_origmembase) {
4294                         printk(KERN_WARNING
4295                             "HFC-multi: No IO-Memory for PCI card found\n");
4296                         pci_disable_device(hc->pci_dev);
4297                         return -EIO;
4298                 }
4299
4300                 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4301                 if (!hc->pci_membase) {
4302                         printk(KERN_WARNING
4303                             "HFC-multi: failed to remap io address space. "
4304                             "(internal error)\n");
4305                         pci_disable_device(hc->pci_dev);
4306                         return -EIO;
4307                 }
4308                 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
4309                     "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4310                     hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4311                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4312                 break;
4313         case HFC_IO_MODE_REGIO:
4314                 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4315                 if (!hc->pci_iobase) {
4316                         printk(KERN_WARNING
4317                                 "HFC-multi: No IO for PCI card found\n");
4318                         pci_disable_device(hc->pci_dev);
4319                         return -EIO;
4320                 }
4321
4322                 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4323                         printk(KERN_WARNING "HFC-multi: failed to request "
4324                             "address space at 0x%08lx (internal error)\n",
4325                             hc->pci_iobase);
4326                         pci_disable_device(hc->pci_dev);
4327                         return -EIO;
4328                 }
4329
4330                 printk(KERN_INFO
4331                     "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4332                     m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4333                     hc->pci_dev->irq, HZ, hc->leds);
4334                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4335                 break;
4336         default:
4337                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4338                 pci_disable_device(hc->pci_dev);
4339                 return -EIO;
4340         }
4341
4342         pci_set_drvdata(hc->pci_dev, hc);
4343
4344         /* At this point the needed PCI config is done */
4345         /* fifos are still not enabled */
4346         return 0;
4347 }
4348
4349
4350 /*
4351  * remove port
4352  */
4353
4354 static void
4355 release_port(struct hfc_multi *hc, struct dchannel *dch)
4356 {
4357         int     pt, ci, i = 0;
4358         u_long  flags;
4359         struct bchannel *pb;
4360
4361         ci = dch->slot;
4362         pt = hc->chan[ci].port;
4363
4364         if (debug & DEBUG_HFCMULTI_INIT)
4365                 printk(KERN_DEBUG "%s: entered for port %d\n",
4366                         __func__, pt + 1);
4367
4368         if (pt >= hc->ports) {
4369                 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4370                      __func__, pt + 1);
4371                 return;
4372         }
4373
4374         if (debug & DEBUG_HFCMULTI_INIT)
4375                 printk(KERN_DEBUG "%s: releasing port=%d\n",
4376                     __func__, pt + 1);
4377
4378         if (dch->dev.D.protocol == ISDN_P_TE_S0)
4379                 l1_event(dch->l1, CLOSE_CHANNEL);
4380
4381         hc->chan[ci].dch = NULL;
4382
4383         if (hc->created[pt]) {
4384                 hc->created[pt] = 0;
4385                 mISDN_unregister_device(&dch->dev);
4386         }
4387
4388         spin_lock_irqsave(&hc->lock, flags);
4389
4390         if (dch->timer.function) {
4391                 del_timer(&dch->timer);
4392                 dch->timer.function = NULL;
4393         }
4394
4395         if (hc->type == 1) { /* E1 */
4396                 /* remove sync */
4397                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4398                         hc->syncronized = 0;
4399                         plxsd_checksync(hc, 1);
4400                 }
4401                 /* free channels */
4402                 for (i = 0; i <= 31; i++) {
4403                         if (hc->chan[i].bch) {
4404                                 if (debug & DEBUG_HFCMULTI_INIT)
4405                                         printk(KERN_DEBUG
4406                                             "%s: free port %d channel %d\n",
4407                                             __func__, hc->chan[i].port+1, i);
4408                                 pb = hc->chan[i].bch;
4409                                 hc->chan[i].bch = NULL;
4410                                 spin_unlock_irqrestore(&hc->lock, flags);
4411                                 mISDN_freebchannel(pb);
4412                                 kfree(pb);
4413                                 kfree(hc->chan[i].coeff);
4414                                 spin_lock_irqsave(&hc->lock, flags);
4415                         }
4416                 }
4417         } else {
4418                 /* remove sync */
4419                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4420                         hc->syncronized &=
4421                            ~(1 << hc->chan[ci].port);
4422                         plxsd_checksync(hc, 1);
4423                 }
4424                 /* free channels */
4425                 if (hc->chan[ci - 2].bch) {
4426                         if (debug & DEBUG_HFCMULTI_INIT)
4427                                 printk(KERN_DEBUG
4428                                     "%s: free port %d channel %d\n",
4429                                     __func__, hc->chan[ci - 2].port+1,
4430                                     ci - 2);
4431                         pb = hc->chan[ci - 2].bch;
4432                         hc->chan[ci - 2].bch = NULL;
4433                         spin_unlock_irqrestore(&hc->lock, flags);
4434                         mISDN_freebchannel(pb);
4435                         kfree(pb);
4436                         kfree(hc->chan[ci - 2].coeff);
4437                         spin_lock_irqsave(&hc->lock, flags);
4438                 }
4439                 if (hc->chan[ci - 1].bch) {
4440                         if (debug & DEBUG_HFCMULTI_INIT)
4441                                 printk(KERN_DEBUG
4442                                     "%s: free port %d channel %d\n",
4443                                     __func__, hc->chan[ci - 1].port+1,
4444                                     ci - 1);
4445                         pb = hc->chan[ci - 1].bch;
4446                         hc->chan[ci - 1].bch = NULL;
4447                         spin_unlock_irqrestore(&hc->lock, flags);
4448                         mISDN_freebchannel(pb);
4449                         kfree(pb);
4450                         kfree(hc->chan[ci - 1].coeff);
4451                         spin_lock_irqsave(&hc->lock, flags);
4452                 }
4453         }
4454
4455         spin_unlock_irqrestore(&hc->lock, flags);
4456
4457         if (debug & DEBUG_HFCMULTI_INIT)
4458                 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4459         mISDN_freedchannel(dch);
4460         kfree(dch);
4461
4462         if (debug & DEBUG_HFCMULTI_INIT)
4463                 printk(KERN_DEBUG "%s: done!\n", __func__);
4464 }
4465
4466 static void
4467 release_card(struct hfc_multi *hc)
4468 {
4469         u_long  flags;
4470         int     ch;
4471
4472         if (debug & DEBUG_HFCMULTI_INIT)
4473                 printk(KERN_WARNING "%s: release card (%d) entered\n",
4474                     __func__, hc->id);
4475
4476         spin_lock_irqsave(&hc->lock, flags);
4477         disable_hwirq(hc);
4478         spin_unlock_irqrestore(&hc->lock, flags);
4479
4480         udelay(1000);
4481
4482         /* dimm leds */
4483         if (hc->leds)
4484                 hfcmulti_leds(hc);
4485
4486         /* disable D-channels & B-channels */
4487         if (debug & DEBUG_HFCMULTI_INIT)
4488                 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4489                     __func__);
4490         for (ch = 0; ch <= 31; ch++) {
4491                 if (hc->chan[ch].dch)
4492                         release_port(hc, hc->chan[ch].dch);
4493         }
4494
4495         /* release hardware & irq */
4496         if (hc->irq) {
4497                 if (debug & DEBUG_HFCMULTI_INIT)
4498                         printk(KERN_WARNING "%s: free irq %d\n",
4499                             __func__, hc->irq);
4500                 free_irq(hc->irq, hc);
4501                 hc->irq = 0;
4502
4503         }
4504         release_io_hfcmulti(hc);
4505
4506         if (debug & DEBUG_HFCMULTI_INIT)
4507                 printk(KERN_WARNING "%s: remove instance from list\n",
4508                      __func__);
4509         list_del(&hc->list);
4510
4511         if (debug & DEBUG_HFCMULTI_INIT)
4512                 printk(KERN_WARNING "%s: delete instance\n", __func__);
4513         if (hc == syncmaster)
4514                 syncmaster = NULL;
4515         kfree(hc);
4516         if (debug & DEBUG_HFCMULTI_INIT)
4517                 printk(KERN_WARNING "%s: card successfully removed\n",
4518                     __func__);
4519 }
4520
4521 static int
4522 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4523 {
4524         struct dchannel *dch;
4525         struct bchannel *bch;
4526         int             ch, ret = 0;
4527         char            name[MISDN_MAX_IDLEN];
4528
4529         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4530         if (!dch)
4531                 return -ENOMEM;
4532         dch->debug = debug;
4533         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4534         dch->hw = hc;
4535         dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4536         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4537             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4538         dch->dev.D.send = handle_dmsg;
4539         dch->dev.D.ctrl = hfcm_dctrl;
4540         dch->dev.nrbchan = (hc->dslot)?30:31;
4541         dch->slot = hc->dslot;
4542         hc->chan[hc->dslot].dch = dch;
4543         hc->chan[hc->dslot].port = 0;
4544         hc->chan[hc->dslot].nt_timer = -1;
4545         for (ch = 1; ch <= 31; ch++) {
4546                 if (ch == hc->dslot) /* skip dchannel */
4547                         continue;
4548                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4549                 if (!bch) {
4550                         printk(KERN_ERR "%s: no memory for bchannel\n",
4551                             __func__);
4552                         ret = -ENOMEM;
4553                         goto free_chan;
4554                 }
4555                 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4556                 if (!hc->chan[ch].coeff) {
4557                         printk(KERN_ERR "%s: no memory for coeffs\n",
4558                             __func__);
4559                         ret = -ENOMEM;
4560                         goto free_chan;
4561                 }
4562                 bch->nr = ch;
4563                 bch->slot = ch;
4564                 bch->debug = debug;
4565                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4566                 bch->hw = hc;
4567                 bch->ch.send = handle_bmsg;
4568                 bch->ch.ctrl = hfcm_bctrl;
4569                 bch->ch.nr = ch;
4570                 list_add(&bch->ch.list, &dch->dev.bchannels);
4571                 hc->chan[ch].bch = bch;
4572                 hc->chan[ch].port = 0;
4573                 set_channelmap(bch->nr, dch->dev.channelmap);
4574         }
4575         /* set optical line type */
4576         if (port[Port_cnt] & 0x001) {
4577                 if (!m->opticalsupport)  {
4578                         printk(KERN_INFO
4579                             "This board has no optical "
4580                             "support\n");
4581                 } else {
4582                         if (debug & DEBUG_HFCMULTI_INIT)
4583                                 printk(KERN_DEBUG
4584                                     "%s: PORT set optical "
4585                                     "interfacs: card(%d) "
4586                                     "port(%d)\n",
4587                                     __func__,
4588                                     HFC_cnt + 1, 1);
4589                         test_and_set_bit(HFC_CFG_OPTICAL,
4590                             &hc->chan[hc->dslot].cfg);
4591                 }
4592         }
4593         /* set LOS report */
4594         if (port[Port_cnt] & 0x004) {
4595                 if (debug & DEBUG_HFCMULTI_INIT)
4596                         printk(KERN_DEBUG "%s: PORT set "
4597                             "LOS report: card(%d) port(%d)\n",
4598                             __func__, HFC_cnt + 1, 1);
4599                 test_and_set_bit(HFC_CFG_REPORT_LOS,
4600                     &hc->chan[hc->dslot].cfg);
4601         }
4602         /* set AIS report */
4603         if (port[Port_cnt] & 0x008) {
4604                 if (debug & DEBUG_HFCMULTI_INIT)
4605                         printk(KERN_DEBUG "%s: PORT set "
4606                             "AIS report: card(%d) port(%d)\n",
4607                             __func__, HFC_cnt + 1, 1);
4608                 test_and_set_bit(HFC_CFG_REPORT_AIS,
4609                     &hc->chan[hc->dslot].cfg);
4610         }
4611         /* set SLIP report */
4612         if (port[Port_cnt] & 0x010) {
4613                 if (debug & DEBUG_HFCMULTI_INIT)
4614                         printk(KERN_DEBUG
4615                             "%s: PORT set SLIP report: "
4616                             "card(%d) port(%d)\n",
4617                             __func__, HFC_cnt + 1, 1);
4618                 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4619                     &hc->chan[hc->dslot].cfg);
4620         }
4621         /* set RDI report */
4622         if (port[Port_cnt] & 0x020) {
4623                 if (debug & DEBUG_HFCMULTI_INIT)
4624                         printk(KERN_DEBUG
4625                             "%s: PORT set RDI report: "
4626                             "card(%d) port(%d)\n",
4627                             __func__, HFC_cnt + 1, 1);
4628                 test_and_set_bit(HFC_CFG_REPORT_RDI,
4629                     &hc->chan[hc->dslot].cfg);
4630         }
4631         /* set CRC-4 Mode */
4632         if (!(port[Port_cnt] & 0x100)) {
4633                 if (debug & DEBUG_HFCMULTI_INIT)
4634                         printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4635                                 " card(%d) port(%d)\n",
4636                                 __func__, HFC_cnt + 1, 1);
4637                 test_and_set_bit(HFC_CFG_CRC4,
4638                     &hc->chan[hc->dslot].cfg);
4639         } else {
4640                 if (debug & DEBUG_HFCMULTI_INIT)
4641                         printk(KERN_DEBUG "%s: PORT turn off CRC4"
4642                                 " report: card(%d) port(%d)\n",
4643                                 __func__, HFC_cnt + 1, 1);
4644         }
4645         /* set forced clock */
4646         if (port[Port_cnt] & 0x0200) {
4647                 if (debug & DEBUG_HFCMULTI_INIT)
4648                         printk(KERN_DEBUG "%s: PORT force getting clock from "
4649                                 "E1: card(%d) port(%d)\n",
4650                                 __func__, HFC_cnt + 1, 1);
4651                 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4652         } else
4653         if (port[Port_cnt] & 0x0400) {
4654                 if (debug & DEBUG_HFCMULTI_INIT)
4655                         printk(KERN_DEBUG "%s: PORT force putting clock to "
4656                                 "E1: card(%d) port(%d)\n",
4657                                 __func__, HFC_cnt + 1, 1);
4658                 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4659         }
4660         /* set JATT PLL */
4661         if (port[Port_cnt] & 0x0800) {
4662                 if (debug & DEBUG_HFCMULTI_INIT)
4663                         printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4664                                 "E1: card(%d) port(%d)\n",
4665                                 __func__, HFC_cnt + 1, 1);
4666                 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4667         }
4668         /* set elastic jitter buffer */
4669         if (port[Port_cnt] & 0x3000) {
4670                 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4671                 if (debug & DEBUG_HFCMULTI_INIT)
4672                         printk(KERN_DEBUG
4673                             "%s: PORT set elastic "
4674                             "buffer to %d: card(%d) port(%d)\n",
4675                             __func__, hc->chan[hc->dslot].jitter,
4676                             HFC_cnt + 1, 1);
4677         } else
4678                 hc->chan[hc->dslot].jitter = 2; /* default */
4679         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4680         ret = mISDN_register_device(&dch->dev, name);
4681         if (ret)
4682                 goto free_chan;
4683         hc->created[0] = 1;
4684         return ret;
4685 free_chan:
4686         release_port(hc, dch);
4687         return ret;
4688 }
4689
4690 static int
4691 init_multi_port(struct hfc_multi *hc, int pt)
4692 {
4693         struct dchannel *dch;
4694         struct bchannel *bch;
4695         int             ch, i, ret = 0;
4696         char            name[MISDN_MAX_IDLEN];
4697
4698         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4699         if (!dch)
4700                 return -ENOMEM;
4701         dch->debug = debug;
4702         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4703         dch->hw = hc;
4704         dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4705         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4706             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4707         dch->dev.D.send = handle_dmsg;
4708         dch->dev.D.ctrl = hfcm_dctrl;
4709         dch->dev.nrbchan = 2;
4710         i = pt << 2;
4711         dch->slot = i + 2;
4712         hc->chan[i + 2].dch = dch;
4713         hc->chan[i + 2].port = pt;
4714         hc->chan[i + 2].nt_timer = -1;
4715         for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4716                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4717                 if (!bch) {
4718                         printk(KERN_ERR "%s: no memory for bchannel\n",
4719                             __func__);
4720                         ret = -ENOMEM;
4721                         goto free_chan;
4722                 }
4723                 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4724                 if (!hc->chan[i + ch].coeff) {
4725                         printk(KERN_ERR "%s: no memory for coeffs\n",
4726                             __func__);
4727                         ret = -ENOMEM;
4728                         goto free_chan;
4729                 }
4730                 bch->nr = ch + 1;
4731                 bch->slot = i + ch;
4732                 bch->debug = debug;
4733                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4734                 bch->hw = hc;
4735                 bch->ch.send = handle_bmsg;
4736                 bch->ch.ctrl = hfcm_bctrl;
4737                 bch->ch.nr = ch + 1;
4738                 list_add(&bch->ch.list, &dch->dev.bchannels);
4739                 hc->chan[i + ch].bch = bch;
4740                 hc->chan[i + ch].port = pt;
4741                 set_channelmap(bch->nr, dch->dev.channelmap);
4742         }
4743         /* set master clock */
4744         if (port[Port_cnt] & 0x001) {
4745                 if (debug & DEBUG_HFCMULTI_INIT)
4746                         printk(KERN_DEBUG
4747                             "%s: PROTOCOL set master clock: "
4748                             "card(%d) port(%d)\n",
4749                             __func__, HFC_cnt + 1, pt + 1);
4750                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4751                         printk(KERN_ERR "Error: Master clock "
4752                             "for port(%d) of card(%d) is only"
4753                             " possible with TE-mode\n",
4754                             pt + 1, HFC_cnt + 1);
4755                         ret = -EINVAL;
4756                         goto free_chan;
4757                 }
4758                 if (hc->masterclk >= 0) {
4759                         printk(KERN_ERR "Error: Master clock "
4760                             "for port(%d) of card(%d) already "
4761                             "defined for port(%d)\n",
4762                             pt + 1, HFC_cnt + 1, hc->masterclk+1);
4763                         ret = -EINVAL;
4764                         goto free_chan;
4765                 }
4766                 hc->masterclk = pt;
4767         }
4768         /* set transmitter line to non capacitive */
4769         if (port[Port_cnt] & 0x002) {
4770                 if (debug & DEBUG_HFCMULTI_INIT)
4771                         printk(KERN_DEBUG
4772                             "%s: PROTOCOL set non capacitive "
4773                             "transmitter: card(%d) port(%d)\n",
4774                             __func__, HFC_cnt + 1, pt + 1);
4775                 test_and_set_bit(HFC_CFG_NONCAP_TX,
4776                     &hc->chan[i + 2].cfg);
4777         }
4778         /* disable E-channel */
4779         if (port[Port_cnt] & 0x004) {
4780         if (debug & DEBUG_HFCMULTI_INIT)
4781                         printk(KERN_DEBUG
4782                             "%s: PROTOCOL disable E-channel: "
4783                             "card(%d) port(%d)\n",
4784                             __func__, HFC_cnt + 1, pt + 1);
4785                 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4786                     &hc->chan[i + 2].cfg);
4787         }
4788         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d/%d",
4789                 hc->type, HFC_cnt + 1, pt + 1);
4790         ret = mISDN_register_device(&dch->dev, name);
4791         if (ret)
4792                 goto free_chan;
4793         hc->created[pt] = 1;
4794         return ret;
4795 free_chan:
4796         release_port(hc, dch);
4797         return ret;
4798 }
4799
4800 static int
4801 hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
4802 {
4803         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4804         int             ret_err = 0;
4805         int             pt;
4806         struct hfc_multi        *hc;
4807         u_long          flags;
4808         u_char          dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4809
4810         if (HFC_cnt >= MAX_CARDS) {
4811                 printk(KERN_ERR "too many cards (max=%d).\n",
4812                         MAX_CARDS);
4813                 return -EINVAL;
4814         }
4815         if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4816                 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4817                     "type[%d] %d was supplied as module parameter\n",
4818                     m->vendor_name, m->card_name, m->type, HFC_cnt,
4819                     type[HFC_cnt] & 0xff);
4820                 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4821                         "first, to see cards and their types.");
4822                 return -EINVAL;
4823         }
4824         if (debug & DEBUG_HFCMULTI_INIT)
4825                 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4826                     __func__, m->vendor_name, m->card_name, m->type,
4827                     type[HFC_cnt]);
4828
4829         /* allocate card+fifo structure */
4830         hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4831         if (!hc) {
4832                 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4833                 return -ENOMEM;
4834         }
4835         spin_lock_init(&hc->lock);
4836         hc->mtyp = m;
4837         hc->type =  m->type;
4838         hc->ports = m->ports;
4839         hc->id = HFC_cnt;
4840         hc->pcm = pcm[HFC_cnt];
4841         hc->io_mode = iomode[HFC_cnt];
4842         if (dslot[HFC_cnt] < 0) {
4843                 hc->dslot = 0;
4844                 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
4845                         "31 B-channels\n");
4846         } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32) {
4847                 hc->dslot = dslot[HFC_cnt];
4848                 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
4849                         "time slot %d\n", dslot[HFC_cnt]);
4850         } else
4851                 hc->dslot = 16;
4852
4853         /* set chip specific features */
4854         hc->masterclk = -1;
4855         if (type[HFC_cnt] & 0x100) {
4856                 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
4857                 silence = 0xff; /* ulaw silence */
4858         } else
4859                 silence = 0x2a; /* alaw silence */
4860         if (!(type[HFC_cnt] & 0x200))
4861                 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4862
4863         if (type[HFC_cnt] & 0x800)
4864                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4865         if (type[HFC_cnt] & 0x1000) {
4866                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4867                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4868         }
4869         if (type[HFC_cnt] & 0x4000)
4870                 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
4871         if (type[HFC_cnt] & 0x8000)
4872                 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
4873         hc->slots = 32;
4874         if (type[HFC_cnt] & 0x10000)
4875                 hc->slots = 64;
4876         if (type[HFC_cnt] & 0x20000)
4877                 hc->slots = 128;
4878         if (type[HFC_cnt] & 0x80000) {
4879                 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
4880                 hc->wdcount = 0;
4881                 hc->wdbyte = V_GPIO_OUT2;
4882                 printk(KERN_NOTICE "Watchdog enabled\n");
4883         }
4884
4885         /* setup pci, hc->slots may change due to PLXSD */
4886         ret_err = setup_pci(hc, pdev, ent);
4887         if (ret_err) {
4888                 if (hc == syncmaster)
4889                         syncmaster = NULL;
4890                 kfree(hc);
4891                 return ret_err;
4892         }
4893
4894         /* crate channels */
4895         for (pt = 0; pt < hc->ports; pt++) {
4896                 if (Port_cnt >= MAX_PORTS) {
4897                         printk(KERN_ERR "too many ports (max=%d).\n",
4898                                 MAX_PORTS);
4899                         ret_err = -EINVAL;
4900                         goto free_card;
4901                 }
4902                 if (hc->type == 1)
4903                         ret_err = init_e1_port(hc, m);
4904                 else
4905                         ret_err = init_multi_port(hc, pt);
4906                 if (debug & DEBUG_HFCMULTI_INIT)
4907                         printk(KERN_DEBUG
4908                             "%s: Registering D-channel, card(%d) port(%d)"
4909                             "result %d\n",
4910                             __func__, HFC_cnt + 1, pt, ret_err);
4911
4912                 if (ret_err) {
4913                         while (pt) { /* release already registered ports */
4914                                 pt--;
4915                                 release_port(hc, hc->chan[(pt << 2) + 2].dch);
4916                         }
4917                         goto free_card;
4918                 }
4919                 Port_cnt++;
4920         }
4921
4922         /* disp switches */
4923         switch (m->dip_type) {
4924         case DIP_4S:
4925                 /*
4926                  * Get DIP setting for beroNet 1S/2S/4S cards
4927                  * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
4928                  * GPI 19/23 (R_GPI_IN2))
4929                  */
4930                 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
4931                         ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
4932                         (~HFC_inb(hc, R_GPI_IN2) & 0x08);
4933
4934                 /* Port mode (TE/NT) jumpers */
4935                 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4)  & 0xf);
4936
4937                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
4938                         pmj = ~pmj & 0xf;
4939
4940                 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
4941                         m->vendor_name, m->card_name, dips, pmj);
4942                 break;
4943         case DIP_8S:
4944                 /*
4945                  * Get DIP Setting for beroNet 8S0+ cards
4946                  * Enable PCI auxbridge function
4947                  */
4948                 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
4949                 /* prepare access to auxport */
4950                 outw(0x4000, hc->pci_iobase + 4);
4951                 /*
4952                  * some dummy reads are required to
4953                  * read valid DIP switch data
4954                  */
4955                 dips = inb(hc->pci_iobase);
4956                 dips = inb(hc->pci_iobase);
4957                 dips = inb(hc->pci_iobase);
4958                 dips = ~inb(hc->pci_iobase) & 0x3F;
4959                 outw(0x0, hc->pci_iobase + 4);
4960                 /* disable PCI auxbridge function */
4961                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
4962                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4963                     m->vendor_name, m->card_name, dips);
4964                 break;
4965         case DIP_E1:
4966                 /*
4967                  * get DIP Setting for beroNet E1 cards
4968                  * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
4969                  */
4970                 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
4971                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4972                     m->vendor_name, m->card_name, dips);
4973                 break;
4974         }
4975
4976         /* add to list */
4977         spin_lock_irqsave(&HFClock, flags);
4978         list_add_tail(&hc->list, &HFClist);
4979         spin_unlock_irqrestore(&HFClock, flags);
4980
4981         /* initialize hardware */
4982         ret_err = init_card(hc);
4983         if (ret_err) {
4984                 printk(KERN_ERR "init card returns %d\n", ret_err);
4985                 release_card(hc);
4986                 return ret_err;
4987         }
4988
4989         /* start IRQ and return */
4990         spin_lock_irqsave(&hc->lock, flags);
4991         enable_hwirq(hc);
4992         spin_unlock_irqrestore(&hc->lock, flags);
4993         return 0;
4994
4995 free_card:
4996         release_io_hfcmulti(hc);
4997         if (hc == syncmaster)
4998                 syncmaster = NULL;
4999         kfree(hc);
5000         return ret_err;
5001 }
5002
5003 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5004 {
5005         struct hfc_multi        *card = pci_get_drvdata(pdev);
5006         u_long                  flags;
5007
5008         if (debug)
5009                 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5010                     "device:%x subvendor:%x subdevice:%x\n",
5011                     pdev->vendor, pdev->device,
5012                     pdev->subsystem_vendor, pdev->subsystem_device);
5013
5014         if (card) {
5015                 spin_lock_irqsave(&HFClock, flags);
5016                 release_card(card);
5017                 spin_unlock_irqrestore(&HFClock, flags);
5018         }  else {
5019                 if (debug)
5020                         printk(KERN_WARNING "%s: drvdata allready removed\n",
5021                             __func__);
5022         }
5023 }
5024
5025 #define VENDOR_CCD      "Cologne Chip AG"
5026 #define VENDOR_BN       "beroNet GmbH"
5027 #define VENDOR_DIG      "Digium Inc."
5028 #define VENDOR_JH       "Junghanns.NET GmbH"
5029 #define VENDOR_PRIM     "PrimuX"
5030
5031 static const struct hm_map hfcm_map[] = {
5032 /*0*/   {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
5033 /*1*/   {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0},
5034 /*2*/   {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
5035 /*3*/   {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
5036 /*4*/   {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
5037 /*5*/   {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
5038 /*6*/   {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0},
5039 /*7*/   {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
5040 /*8*/   {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
5041 /*9*/   {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
5042 /*10*/  {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
5043 /*11*/  {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
5044
5045 /*12*/  {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
5046 /*13*/  {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5047                 HFC_IO_MODE_REGIO},
5048 /*14*/  {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
5049 /*15*/  {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
5050
5051 /*16*/  {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
5052 /*17*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5053 /*18*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5054
5055 /*19*/  {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
5056 /*20*/  {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
5057 /*21*/  {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5058 /*22*/  {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5059
5060 /*23*/  {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
5061 /*24*/  {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
5062 /*25*/  {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
5063
5064 /*26*/  {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5065                 HFC_IO_MODE_PLXSD},
5066 /*27*/  {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5067                 HFC_IO_MODE_PLXSD},
5068 /*28*/  {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
5069 /*29*/  {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
5070 /*30*/  {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
5071 };
5072
5073 #undef H
5074 #define H(x)    ((unsigned long)&hfcm_map[x])
5075 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5076
5077         /* Cards with HFC-4S Chip */
5078         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5079                 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5080         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5081                 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5082         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5083                 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5084         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5085                 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5086         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5087                 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5088         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5089                 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5090         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5091                 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5092         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5093                 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5094         { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5095                 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5096         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5097                 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5098         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5099                 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5100         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5101                 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5102         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5103                 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5104         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5105                 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5106
5107         /* Cards with HFC-8S Chip */
5108         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5109         PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5110         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5111         PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5112         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5113         PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5114         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5115         PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5116         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5117                 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST  */
5118         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5119                 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST  */
5120         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5121                 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5122         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5123                 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5124
5125
5126         /* Cards with HFC-E1 Chip */
5127         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5128                 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5129         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5130                 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5131         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5132                 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5133         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5134                 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5135
5136         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5137                 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5138         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5139                 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5140         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5141                 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5142
5143         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5144                 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5145         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5146                 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5147         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5148                 0, 0, 0},
5149         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5150                 0, 0, 0},
5151         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5152                 0, 0, 0},
5153         {0, }
5154 };
5155 #undef H
5156
5157 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5158
5159 static int
5160 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5161 {
5162         struct hm_map   *m = (struct hm_map *)ent->driver_data;
5163         int             ret;
5164
5165         if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5166             ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5167             ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5168             ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5169                 printk(KERN_ERR
5170                     "Unknown HFC multiport controller (vendor:%x device:%x "
5171                     "subvendor:%x subdevice:%x)\n", ent->vendor, ent->device,
5172                     ent->subvendor, ent->subdevice);
5173                 printk(KERN_ERR
5174                     "Please contact the driver maintainer for support.\n");
5175                 return -ENODEV;
5176         }
5177         ret = hfcmulti_init(pdev, ent);
5178         if (ret)
5179                 return ret;
5180         HFC_cnt++;
5181         printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5182         return 0;
5183 }
5184
5185 static struct pci_driver hfcmultipci_driver = {
5186         .name           = "hfc_multi",
5187         .probe          = hfcmulti_probe,
5188         .remove         = __devexit_p(hfc_remove_pci),
5189         .id_table       = hfmultipci_ids,
5190 };
5191
5192 static void __exit
5193 HFCmulti_cleanup(void)
5194 {
5195         struct hfc_multi *card, *next;
5196
5197         /* get rid of all devices of this driver */
5198         list_for_each_entry_safe(card, next, &HFClist, list)
5199                 release_card(card);
5200         pci_unregister_driver(&hfcmultipci_driver);
5201 }
5202
5203 static int __init
5204 HFCmulti_init(void)
5205 {
5206         int err;
5207
5208         printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5209
5210 #ifdef IRQ_DEBUG
5211         printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5212 #endif
5213
5214         spin_lock_init(&HFClock);
5215         spin_lock_init(&plx_lock);
5216
5217         if (debug & DEBUG_HFCMULTI_INIT)
5218                 printk(KERN_DEBUG "%s: init entered\n", __func__);
5219
5220         switch (poll) {
5221         case 0:
5222                 poll_timer = 6;
5223                 poll = 128;
5224                 break;
5225         case 8:
5226                 poll_timer = 2;
5227                 break;
5228         case 16:
5229                 poll_timer = 3;
5230                 break;
5231         case 32:
5232                 poll_timer = 4;
5233                 break;
5234         case 64:
5235                 poll_timer = 5;
5236                 break;
5237         case 128:
5238                 poll_timer = 6;
5239                 break;
5240         case 256:
5241                 poll_timer = 7;
5242                 break;
5243         default:
5244                 printk(KERN_ERR
5245                     "%s: Wrong poll value (%d).\n", __func__, poll);
5246                 err = -EINVAL;
5247                 return err;
5248
5249         }
5250
5251         err = pci_register_driver(&hfcmultipci_driver);
5252         if (err < 0) {
5253                 printk(KERN_ERR "error registering pci driver: %x\n", err);
5254                 return err;
5255         }
5256         return 0;
5257 }
5258
5259
5260 module_init(HFCmulti_init);
5261 module_exit(HFCmulti_cleanup);