SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/isdn/hardware/mISDN/hfcmulti.c

   1 /*
   2  * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
   3  *
   4  * Author       Andreas Eversberg (jolly@eversberg.eu)
   5  * ported to mqueue mechanism:
   6  *              Peter Sprenger (sprengermoving-bytes.de)
   7  *
   8  * inspired by existing hfc-pci driver:
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil (kkeil@suse.de)
  11  * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2, or (at your option)
  16  * any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  * Thanks to Cologne Chip AG for this great controller!
  29  */
  30
  31 /*
  32  * module parameters:
  33  * type:
  34  *      By default (0), the card is automatically detected.
  35  *      Or use the following combinations:
  36  *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
  37  * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
  38  * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
  39  *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
  40  *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
  41  *      Bit 10    = spare
  42  *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
  43  * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
  44  *      Bit 13    = spare
  45  *      Bit 14    = 0x04000 = Use external ram (128K)
  46  *      Bit 15    = 0x08000 = Use external ram (512K)
  47  *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
  48  * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
  49  *      Bit 18    = spare
  50  *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
  51  * (all other bits are reserved and shall be 0)
  52  *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
  53  *               bus (PCM master)
  54  *
  55  * port: (optional or required for all ports on all installed cards)
  56  *      HFC-4S/HFC-8S only bits:
  57  *      Bit 0     = 0x001 = Use master clock for this S/T interface
  58  *                          (ony once per chip).
  59  *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
  60  *                          Don't use this unless you know what you are doing!
  61  *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
  62  *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
  63  *               received from port 1
  64  *
  65  *      HFC-E1 only bits:
  66  *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
  67  *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
  68  *      Bit 2     = 0x0004 = Report LOS
  69  *      Bit 3     = 0x0008 = Report AIS
  70  *      Bit 4     = 0x0010 = Report SLIP
  71  *      Bit 5     = 0x0020 = Report RDI
  72  *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
  73  *                           mode instead.
  74  *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
  75  * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
  76  *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
  77  *                           (E1 only)
  78  *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
  79  *                           for default.
  80  * (all other bits are reserved and shall be 0)
  81  *
  82  * debug:
  83  *      NOTE: only one debug value must be given for all cards
  84  *      enable debugging (see hfc_multi.h for debug options)
  85  *
  86  * poll:
  87  *      NOTE: only one poll value must be given for all cards
  88  *      Give the number of samples for each fifo process.
  89  *      By default 128 is used. Decrease to reduce delay, increase to
  90  *      reduce cpu load. If unsure, don't mess with it!
  91  *      Valid is 8, 16, 32, 64, 128, 256.
  92  *
  93  * pcm:
  94  *      NOTE: only one pcm value must be given for every card.
  95  *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
  96  *      By default (0), the PCM bus id is 100 for the card that is PCM master.
  97  *      If multiple cards are PCM master (because they are not interconnected),
  98  *      each card with PCM master will have increasing PCM id.
  99  *      All PCM busses with the same ID are expected to be connected and have
 100  *      common time slots slots.
 101  *      Only one chip of the PCM bus must be master, the others slave.
 102  *      -1 means no support of PCM bus not even.
 103  *      Omit this value, if all cards are interconnected or none is connected.
 104  *      If unsure, don't give this parameter.
 105  *
 106  * dslot:
 107  *      NOTE: only one poll value must be given for every card.
 108  *      Also this value must be given for non-E1 cards. If omitted, the E1
 109  *      card has D-channel on time slot 16, which is default.
 110  *      If 1..15 or 17..31, an alternate time slot is used for D-channel.
 111  *      In this case, the application must be able to handle this.
 112  *      If -1 is given, the D-channel is disabled and all 31 slots can be used
 113  *      for B-channel. (only for specific applications)
 114  *      If you don't know how to use it, you don't need it!
 115  *
 116  * iomode:
 117  *      NOTE: only one mode value must be given for every card.
 118  *      -> See hfc_multi.h for HFC_IO_MODE_* values
 119  *      By default, the IO mode is pci memory IO (MEMIO).
 120  *      Some cards requre specific IO mode, so it cannot be changed.
 121  *      It may be usefull to set IO mode to register io (REGIO) to solve
 122  *      PCI bridge problems.
 123  *      If unsure, don't give this parameter.
 124  *
 125  * clockdelay_nt:
 126  *      NOTE: only one clockdelay_nt value must be given once for all cards.
 127  *      Give the value of the clock control register (A_ST_CLK_DLY)
 128  *      of the S/T interfaces in NT mode.
 129  *      This register is needed for the TBR3 certification, so don't change it.
 130  *
 131  * clockdelay_te:
 132  *      NOTE: only one clockdelay_te value must be given once
 133  *      Give the value of the clock control register (A_ST_CLK_DLY)
 134  *      of the S/T interfaces in TE mode.
 135  *      This register is needed for the TBR3 certification, so don't change it.
 136  *
 137  * clock:
 138  *      NOTE: only one clockdelay_te value must be given once
 139  *      Selects interface with clock source for mISDN and applications.
 140  *      Set to card number starting with 1. Set to -1 to disable.
 141  *      By default, the first card is used as clock source.
 142  */
 143
 144 /*
 145  * debug register access (never use this, it will flood your system log)
 146  * #define HFC_REGISTER_DEBUG
 147  */
 148
 149 #define HFC_MULTI_VERSION       "2.03"
 150
 151 #include <linux/module.h>
 152 #include <linux/pci.h>
 153 #include <linux/delay.h>
 154 #include <linux/mISDNhw.h>
 155 #include <linux/mISDNdsp.h>
 156
 157 /*
 158 #define IRQCOUNT_DEBUG
 159 #define IRQ_DEBUG
 160 */
 161
 162 #include "hfc_multi.h"
 163 #ifdef ECHOPREP
 164 #include "gaintab.h"
 165 #endif
 166
 167 #define MAX_CARDS       8
 168 #define MAX_PORTS       (8 * MAX_CARDS)
 169
 170 static LIST_HEAD(HFClist);
 171 static spinlock_t HFClock; /* global hfc list lock */
 172
 173 static void ph_state_change(struct dchannel *);
 174
 175 static struct hfc_multi *syncmaster;
 176 static int plxsd_master; /* if we have a master card (yet) */
 177 static spinlock_t plx_lock; /* may not acquire other lock inside */
 178
 179 #define TYP_E1          1
 180 #define TYP_4S          4
 181 #define TYP_8S          8
 182
 183 static int poll_timer = 6;      /* default = 128 samples = 16ms */
 184 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
 185 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
 186 #define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
 187 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
 188                                    (0x60 MUST be included!) */
 189
 190 #define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
 191 #define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
 192 #define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */
 193
 194 /*
 195  * module stuff
 196  */
 197
 198 static uint     type[MAX_CARDS];
 199 static int      pcm[MAX_CARDS];
 200 static int      dslot[MAX_CARDS];
 201 static uint     iomode[MAX_CARDS];
 202 static uint     port[MAX_PORTS];
 203 static uint     debug;
 204 static uint     poll;
 205 static int      clock;
 206 static uint     timer;
 207 static uint     clockdelay_te = CLKDEL_TE;
 208 static uint     clockdelay_nt = CLKDEL_NT;
 209
 210 static int      HFC_cnt, Port_cnt, PCM_cnt = 99;
 211
 212 MODULE_AUTHOR("Andreas Eversberg");
 213 MODULE_LICENSE("GPL");
 214 MODULE_VERSION(HFC_MULTI_VERSION);
 215 module_param(debug, uint, S_IRUGO | S_IWUSR);
 216 module_param(poll, uint, S_IRUGO | S_IWUSR);
 217 module_param(clock, int, S_IRUGO | S_IWUSR);
 218 module_param(timer, uint, S_IRUGO | S_IWUSR);
 219 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
 220 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
 221 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
 222 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
 223 module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
 224 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
 225 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
 226
 227 #ifdef HFC_REGISTER_DEBUG
 228 #define HFC_outb(hc, reg, val) \
 229         (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
 230 #define HFC_outb_nodebug(hc, reg, val) \
 231         (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
 232 #define HFC_inb(hc, reg) \
 233         (hc->HFC_inb(hc, reg, __func__, __LINE__))
 234 #define HFC_inb_nodebug(hc, reg) \
 235         (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
 236 #define HFC_inw(hc, reg) \
 237         (hc->HFC_inw(hc, reg, __func__, __LINE__))
 238 #define HFC_inw_nodebug(hc, reg) \
 239         (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
 240 #define HFC_wait(hc) \
 241         (hc->HFC_wait(hc, __func__, __LINE__))
 242 #define HFC_wait_nodebug(hc) \
 243         (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
 244 #else
 245 #define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
 246 #define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
 247 #define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
 248 #define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
 249 #define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
 250 #define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
 251 #define HFC_wait(hc)                    (hc->HFC_wait(hc))
 252 #define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
 253 #endif
 254
 255 /* HFC_IO_MODE_PCIMEM */
 256 static void
 257 #ifdef HFC_REGISTER_DEBUG
 258 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
 259                 const char *function, int line)
 260 #else
 261 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
 262 #endif
 263 {
 264         writeb(val, (hc->pci_membase)+reg);
 265 }
 266 static u_char
 267 #ifdef HFC_REGISTER_DEBUG
 268 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 269 #else
 270 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
 271 #endif
 272 {
 273         return readb((hc->pci_membase)+reg);
 274 }
 275 static u_short
 276 #ifdef HFC_REGISTER_DEBUG
 277 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 278 #else
 279 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
 280 #endif
 281 {
 282         return readw((hc->pci_membase)+reg);
 283 }
 284 static void
 285 #ifdef HFC_REGISTER_DEBUG
 286 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
 287 #else
 288 HFC_wait_pcimem(struct hfc_multi *hc)
 289 #endif
 290 {
 291         while (readb((hc->pci_membase)+R_STATUS) & V_BUSY);
 292 }
 293
 294 /* HFC_IO_MODE_REGIO */
 295 static void
 296 #ifdef HFC_REGISTER_DEBUG
 297 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
 298         const char *function, int line)
 299 #else
 300 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
 301 #endif
 302 {
 303         outb(reg, (hc->pci_iobase)+4);
 304         outb(val, hc->pci_iobase);
 305 }
 306 static u_char
 307 #ifdef HFC_REGISTER_DEBUG
 308 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 309 #else
 310 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
 311 #endif
 312 {
 313         outb(reg, (hc->pci_iobase)+4);
 314         return inb(hc->pci_iobase);
 315 }
 316 static u_short
 317 #ifdef HFC_REGISTER_DEBUG
 318 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 319 #else
 320 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
 321 #endif
 322 {
 323         outb(reg, (hc->pci_iobase)+4);
 324         return inw(hc->pci_iobase);
 325 }
 326 static void
 327 #ifdef HFC_REGISTER_DEBUG
 328 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
 329 #else
 330 HFC_wait_regio(struct hfc_multi *hc)
 331 #endif
 332 {
 333         outb(R_STATUS, (hc->pci_iobase)+4);
 334         while (inb(hc->pci_iobase) & V_BUSY);
 335 }
 336
 337 #ifdef HFC_REGISTER_DEBUG
 338 static void
 339 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
 340                 const char *function, int line)
 341 {
 342         char regname[256] = "", bits[9] = "xxxxxxxx";
 343         int i;
 344
 345         i = -1;
 346         while (hfc_register_names[++i].name) {
 347                 if (hfc_register_names[i].reg == reg)
 348                         strcat(regname, hfc_register_names[i].name);
 349         }
 350         if (regname[0] == '\0')
 351                 strcpy(regname, "register");
 352
 353         bits[7] = '0'+(!!(val&1));
 354         bits[6] = '0'+(!!(val&2));
 355         bits[5] = '0'+(!!(val&4));
 356         bits[4] = '0'+(!!(val&8));
 357         bits[3] = '0'+(!!(val&16));
 358         bits[2] = '0'+(!!(val&32));
 359         bits[1] = '0'+(!!(val&64));
 360         bits[0] = '0'+(!!(val&128));
 361         printk(KERN_DEBUG
 362             "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
 363             hc->id, reg, regname, val, bits, function, line);
 364         HFC_outb_nodebug(hc, reg, val);
 365 }
 366 static u_char
 367 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 368 {
 369         char regname[256] = "", bits[9] = "xxxxxxxx";
 370         u_char val = HFC_inb_nodebug(hc, reg);
 371         int i;
 372
 373         i = 0;
 374         while (hfc_register_names[i++].name)
 375                 ;
 376         while (hfc_register_names[++i].name) {
 377                 if (hfc_register_names[i].reg == reg)
 378                         strcat(regname, hfc_register_names[i].name);
 379         }
 380         if (regname[0] == '\0')
 381                 strcpy(regname, "register");
 382
 383         bits[7] = '0'+(!!(val&1));
 384         bits[6] = '0'+(!!(val&2));
 385         bits[5] = '0'+(!!(val&4));
 386         bits[4] = '0'+(!!(val&8));
 387         bits[3] = '0'+(!!(val&16));
 388         bits[2] = '0'+(!!(val&32));
 389         bits[1] = '0'+(!!(val&64));
 390         bits[0] = '0'+(!!(val&128));
 391         printk(KERN_DEBUG
 392             "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
 393             hc->id, reg, regname, val, bits, function, line);
 394         return val;
 395 }
 396 static u_short
 397 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 398 {
 399         char regname[256] = "";
 400         u_short val = HFC_inw_nodebug(hc, reg);
 401         int i;
 402
 403         i = 0;
 404         while (hfc_register_names[i++].name)
 405                 ;
 406         while (hfc_register_names[++i].name) {
 407                 if (hfc_register_names[i].reg == reg)
 408                         strcat(regname, hfc_register_names[i].name);
 409         }
 410         if (regname[0] == '\0')
 411                 strcpy(regname, "register");
 412
 413         printk(KERN_DEBUG
 414             "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
 415             hc->id, reg, regname, val, function, line);
 416         return val;
 417 }
 418 static void
 419 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
 420 {
 421         printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
 422             hc->id, function, line);
 423         HFC_wait_nodebug(hc);
 424 }
 425 #endif
 426
 427 /* write fifo data (REGIO) */
 428 static void
 429 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 430 {
 431         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 432         while (len>>2) {
 433                 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
 434                 data += 4;
 435                 len -= 4;
 436         }
 437         while (len>>1) {
 438                 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
 439                 data += 2;
 440                 len -= 2;
 441         }
 442         while (len) {
 443                 outb(*data, hc->pci_iobase);
 444                 data++;
 445                 len--;
 446         }
 447 }
 448 /* write fifo data (PCIMEM) */
 449 static void
 450 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 451 {
 452         while (len>>2) {
 453                 writel(cpu_to_le32(*(u32 *)data),
 454                         hc->pci_membase + A_FIFO_DATA0);
 455                 data += 4;
 456                 len -= 4;
 457         }
 458         while (len>>1) {
 459                 writew(cpu_to_le16(*(u16 *)data),
 460                         hc->pci_membase + A_FIFO_DATA0);
 461                 data += 2;
 462                 len -= 2;
 463         }
 464         while (len) {
 465                 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
 466                 data++;
 467                 len--;
 468         }
 469 }
 470 /* read fifo data (REGIO) */
 471 static void
 472 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 473 {
 474         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 475         while (len>>2) {
 476                 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
 477                 data += 4;
 478                 len -= 4;
 479         }
 480         while (len>>1) {
 481                 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
 482                 data += 2;
 483                 len -= 2;
 484         }
 485         while (len) {
 486                 *data = inb(hc->pci_iobase);
 487                 data++;
 488                 len--;
 489         }
 490 }
 491
 492 /* read fifo data (PCIMEM) */
 493 static void
 494 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 495 {
 496         while (len>>2) {
 497                 *(u32 *)data =
 498                         le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
 499                 data += 4;
 500                 len -= 4;
 501         }
 502         while (len>>1) {
 503                 *(u16 *)data =
 504                         le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
 505                 data += 2;
 506                 len -= 2;
 507         }
 508         while (len) {
 509                 *data = readb(hc->pci_membase + A_FIFO_DATA0);
 510                 data++;
 511                 len--;
 512         }
 513 }
 514
 515
 516 static void
 517 enable_hwirq(struct hfc_multi *hc)
 518 {
 519         hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
 520         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 521 }
 522
 523 static void
 524 disable_hwirq(struct hfc_multi *hc)
 525 {
 526         hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
 527         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 528 }
 529
 530 #define NUM_EC 2
 531 #define MAX_TDM_CHAN 32
 532
 533
 534 inline void
 535 enablepcibridge(struct hfc_multi *c)
 536 {
 537         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
 538 }
 539
 540 inline void
 541 disablepcibridge(struct hfc_multi *c)
 542 {
 543         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
 544 }
 545
 546 inline unsigned char
 547 readpcibridge(struct hfc_multi *hc, unsigned char address)
 548 {
 549         unsigned short cipv;
 550         unsigned char data;
 551
 552         if (!hc->pci_iobase)
 553                 return 0;
 554
 555         /* slow down a PCI read access by 1 PCI clock cycle */
 556         HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
 557
 558         if (address == 0)
 559                 cipv = 0x4000;
 560         else
 561                 cipv = 0x5800;
 562
 563         /* select local bridge port address by writing to CIP port */
 564         /* data = HFC_inb(c, cipv); * was _io before */
 565         outw(cipv, hc->pci_iobase + 4);
 566         data = inb(hc->pci_iobase);
 567
 568         /* restore R_CTRL for normal PCI read cycle speed */
 569         HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
 570
 571         return data;
 572 }
 573
 574 inline void
 575 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
 576 {
 577         unsigned short cipv;
 578         unsigned int datav;
 579
 580         if (!hc->pci_iobase)
 581                 return;
 582
 583         if (address == 0)
 584                 cipv = 0x4000;
 585         else
 586                 cipv = 0x5800;
 587
 588         /* select local bridge port address by writing to CIP port */
 589         outw(cipv, hc->pci_iobase + 4);
 590         /* define a 32 bit dword with 4 identical bytes for write sequence */
 591         datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
 592             ((__u32) data << 24);
 593
 594         /*
 595          * write this 32 bit dword to the bridge data port
 596          * this will initiate a write sequence of up to 4 writes to the same
 597          * address on the local bus interface the number of write accesses
 598          * is undefined but >=1 and depends on the next PCI transaction
 599          * during write sequence on the local bus
 600          */
 601         outl(datav, hc->pci_iobase);
 602 }
 603
 604 inline void
 605 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
 606 {
 607         /* Do data pin read low byte */
 608         HFC_outb(hc, R_GPIO_OUT1, reg);
 609 }
 610
 611 inline void
 612 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
 613 {
 614         cpld_set_reg(hc, reg);
 615
 616         enablepcibridge(hc);
 617         writepcibridge(hc, 1, val);
 618         disablepcibridge(hc);
 619
 620         return;
 621 }
 622
 623 inline unsigned char
 624 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
 625 {
 626         unsigned char bytein;
 627
 628         cpld_set_reg(hc, reg);
 629
 630         /* Do data pin read low byte */
 631         HFC_outb(hc, R_GPIO_OUT1, reg);
 632
 633         enablepcibridge(hc);
 634         bytein = readpcibridge(hc, 1);
 635         disablepcibridge(hc);
 636
 637         return bytein;
 638 }
 639
 640 inline void
 641 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
 642 {
 643         cpld_write_reg(hc, 0, 0xff & addr);
 644         cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
 645 }
 646
 647 inline unsigned short
 648 vpm_read_address(struct hfc_multi *c)
 649 {
 650         unsigned short addr;
 651         unsigned short highbit;
 652
 653         addr = cpld_read_reg(c, 0);
 654         highbit = cpld_read_reg(c, 1);
 655
 656         addr = addr | (highbit << 8);
 657
 658         return addr & 0x1ff;
 659 }
 660
 661 inline unsigned char
 662 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
 663 {
 664         unsigned char res;
 665
 666         vpm_write_address(c, addr);
 667
 668         if (!which)
 669                 cpld_set_reg(c, 2);
 670         else
 671                 cpld_set_reg(c, 3);
 672
 673         enablepcibridge(c);
 674         res = readpcibridge(c, 1);
 675         disablepcibridge(c);
 676
 677         cpld_set_reg(c, 0);
 678
 679         return res;
 680 }
 681
 682 inline void
 683 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
 684     unsigned char data)
 685 {
 686         vpm_write_address(c, addr);
 687
 688         enablepcibridge(c);
 689
 690         if (!which)
 691                 cpld_set_reg(c, 2);
 692         else
 693                 cpld_set_reg(c, 3);
 694
 695         writepcibridge(c, 1, data);
 696
 697         cpld_set_reg(c, 0);
 698
 699         disablepcibridge(c);
 700
 701         {
 702         unsigned char regin;
 703         regin = vpm_in(c, which, addr);
 704         if (regin != data)
 705                 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
 706                         "0x%x\n", data, addr, regin);
 707         }
 708
 709 }
 710
 711
 712 static void
 713 vpm_init(struct hfc_multi *wc)
 714 {
 715         unsigned char reg;
 716         unsigned int mask;
 717         unsigned int i, x, y;
 718         unsigned int ver;
 719
 720         for (x = 0; x < NUM_EC; x++) {
 721                 /* Setup GPIO's */
 722                 if (!x) {
 723                         ver = vpm_in(wc, x, 0x1a0);
 724                         printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
 725                 }
 726
 727                 for (y = 0; y < 4; y++) {
 728                         vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
 729                         vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
 730                         vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
 731                 }
 732
 733                 /* Setup TDM path - sets fsync and tdm_clk as inputs */
 734                 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
 735                 vpm_out(wc, x, 0x1a3, reg & ~2);
 736
 737                 /* Setup Echo length (256 taps) */
 738                 vpm_out(wc, x, 0x022, 1);
 739                 vpm_out(wc, x, 0x023, 0xff);
 740
 741                 /* Setup timeslots */
 742                 vpm_out(wc, x, 0x02f, 0x00);
 743                 mask = 0x02020202 << (x * 4);
 744
 745                 /* Setup the tdm channel masks for all chips */
 746                 for (i = 0; i < 4; i++)
 747                         vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
 748
 749                 /* Setup convergence rate */
 750                 printk(KERN_DEBUG "VPM: A-law mode\n");
 751                 reg = 0x00 | 0x10 | 0x01;
 752                 vpm_out(wc, x, 0x20, reg);
 753                 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
 754                 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
 755
 756                 vpm_out(wc, x, 0x24, 0x02);
 757                 reg = vpm_in(wc, x, 0x24);
 758                 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
 759
 760                 /* Initialize echo cans */
 761                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 762                         if (mask & (0x00000001 << i))
 763                                 vpm_out(wc, x, i, 0x00);
 764                 }
 765
 766                 /*
 767                  * ARM arch at least disallows a udelay of
 768                  * more than 2ms... it gives a fake "__bad_udelay"
 769                  * reference at link-time.
 770                  * long delays in kernel code are pretty sucky anyway
 771                  * for now work around it using 5 x 2ms instead of 1 x 10ms
 772                  */
 773
 774                 udelay(2000);
 775                 udelay(2000);
 776                 udelay(2000);
 777                 udelay(2000);
 778                 udelay(2000);
 779
 780                 /* Put in bypass mode */
 781                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 782                         if (mask & (0x00000001 << i))
 783                                 vpm_out(wc, x, i, 0x01);
 784                 }
 785
 786                 /* Enable bypass */
 787                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 788                         if (mask & (0x00000001 << i))
 789                                 vpm_out(wc, x, 0x78 + i, 0x01);
 790                 }
 791
 792         }
 793 }
 794
 795 #ifdef UNUSED
 796 static void
 797 vpm_check(struct hfc_multi *hctmp)
 798 {
 799         unsigned char gpi2;
 800
 801         gpi2 = HFC_inb(hctmp, R_GPI_IN2);
 802
 803         if ((gpi2 & 0x3) != 0x3)
 804                 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
 805 }
 806 #endif /* UNUSED */
 807
 808
 809 /*
 810  * Interface to enable/disable the HW Echocan
 811  *
 812  * these functions are called within a spin_lock_irqsave on
 813  * the channel instance lock, so we are not disturbed by irqs
 814  *
 815  * we can later easily change the interface to make  other
 816  * things configurable, for now we configure the taps
 817  *
 818  */
 819
 820 static void
 821 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
 822 {
 823         unsigned int timeslot;
 824         unsigned int unit;
 825         struct bchannel *bch = hc->chan[ch].bch;
 826 #ifdef TXADJ
 827         int txadj = -4;
 828         struct sk_buff *skb;
 829 #endif
 830         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 831                 return;
 832
 833         if (!bch)
 834                 return;
 835
 836 #ifdef TXADJ
 837         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 838                 sizeof(int), &txadj, GFP_ATOMIC);
 839         if (skb)
 840                 recv_Bchannel_skb(bch, skb);
 841 #endif
 842
 843         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 844         unit = ch % 4;
 845
 846         printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
 847             taps, timeslot);
 848
 849         vpm_out(hc, unit, timeslot, 0x7e);
 850 }
 851
 852 static void
 853 vpm_echocan_off(struct hfc_multi *hc, int ch)
 854 {
 855         unsigned int timeslot;
 856         unsigned int unit;
 857         struct bchannel *bch = hc->chan[ch].bch;
 858 #ifdef TXADJ
 859         int txadj = 0;
 860         struct sk_buff *skb;
 861 #endif
 862
 863         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 864                 return;
 865
 866         if (!bch)
 867                 return;
 868
 869 #ifdef TXADJ
 870         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 871                 sizeof(int), &txadj, GFP_ATOMIC);
 872         if (skb)
 873                 recv_Bchannel_skb(bch, skb);
 874 #endif
 875
 876         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 877         unit = ch % 4;
 878
 879         printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
 880             timeslot);
 881         /* FILLME */
 882         vpm_out(hc, unit, timeslot, 0x01);
 883 }
 884
 885
 886 /*
 887  * Speech Design resync feature
 888  * NOTE: This is called sometimes outside interrupt handler.
 889  * We must lock irqsave, so no other interrupt (other card) will occurr!
 890  * Also multiple interrupts may nest, so must lock each access (lists, card)!
 891  */
 892 static inline void
 893 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
 894 {
 895         struct hfc_multi *hc, *next, *pcmmaster = NULL;
 896         void __iomem *plx_acc_32;
 897         u_int pv;
 898         u_long flags;
 899
 900         spin_lock_irqsave(&HFClock, flags);
 901         spin_lock(&plx_lock); /* must be locked inside other locks */
 902
 903         if (debug & DEBUG_HFCMULTI_PLXSD)
 904                 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
 905                         __func__, syncmaster);
 906
 907         /* select new master */
 908         if (newmaster) {
 909                 if (debug & DEBUG_HFCMULTI_PLXSD)
 910                         printk(KERN_DEBUG "using provided controller\n");
 911         } else {
 912                 list_for_each_entry_safe(hc, next, &HFClist, list) {
 913                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 914                                 if (hc->syncronized) {
 915                                         newmaster = hc;
 916                                         break;
 917                                 }
 918                         }
 919                 }
 920         }
 921
 922         /* Disable sync of all cards */
 923         list_for_each_entry_safe(hc, next, &HFClist, list) {
 924                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 925                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 926                         pv = readl(plx_acc_32);
 927                         pv &= ~PLX_SYNC_O_EN;
 928                         writel(pv, plx_acc_32);
 929                         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
 930                                 pcmmaster = hc;
 931                                 if (hc->type == 1) {
 932                                         if (debug & DEBUG_HFCMULTI_PLXSD)
 933                                                 printk(KERN_DEBUG
 934                                                         "Schedule SYNC_I\n");
 935                                         hc->e1_resync |= 1; /* get SYNC_I */
 936                                 }
 937                         }
 938                 }
 939         }
 940
 941         if (newmaster) {
 942                 hc = newmaster;
 943                 if (debug & DEBUG_HFCMULTI_PLXSD)
 944                         printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
 945                                 "interface.\n", hc->id, hc);
 946                 /* Enable new sync master */
 947                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 948                 pv = readl(plx_acc_32);
 949                 pv |= PLX_SYNC_O_EN;
 950                 writel(pv, plx_acc_32);
 951                 /* switch to jatt PLL, if not disabled by RX_SYNC */
 952                 if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
 953                         if (debug & DEBUG_HFCMULTI_PLXSD)
 954                                 printk(KERN_DEBUG "Schedule jatt PLL\n");
 955                         hc->e1_resync |= 2; /* switch to jatt */
 956                 }
 957         } else {
 958                 if (pcmmaster) {
 959                         hc = pcmmaster;
 960                         if (debug & DEBUG_HFCMULTI_PLXSD)
 961                                 printk(KERN_DEBUG
 962                                         "id=%d (0x%p) = PCM master syncronized "
 963                                         "with QUARTZ\n", hc->id, hc);
 964                         if (hc->type == 1) {
 965                                 /* Use the crystal clock for the PCM
 966                                    master card */
 967                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 968                                         printk(KERN_DEBUG
 969                                             "Schedule QUARTZ for HFC-E1\n");
 970                                 hc->e1_resync |= 4; /* switch quartz */
 971                         } else {
 972                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 973                                         printk(KERN_DEBUG
 974                                             "QUARTZ is automatically "
 975                                             "enabled by HFC-%dS\n", hc->type);
 976                         }
 977                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 978                         pv = readl(plx_acc_32);
 979                         pv |= PLX_SYNC_O_EN;
 980                         writel(pv, plx_acc_32);
 981                 } else
 982                         if (!rm)
 983                                 printk(KERN_ERR "%s no pcm master, this MUST "
 984                                         "not happen!\n", __func__);
 985         }
 986         syncmaster = newmaster;
 987
 988         spin_unlock(&plx_lock);
 989         spin_unlock_irqrestore(&HFClock, flags);
 990 }
 991
 992 /* This must be called AND hc must be locked irqsave!!! */
 993 inline void
 994 plxsd_checksync(struct hfc_multi *hc, int rm)
 995 {
 996         if (hc->syncronized) {
 997                 if (syncmaster == NULL) {
 998                         if (debug & DEBUG_HFCMULTI_PLXSD)
 999                                 printk(KERN_WARNING "%s: GOT sync on card %d"
1000                                         " (id=%d)\n", __func__, hc->id + 1,
1001                                         hc->id);
1002                         hfcmulti_resync(hc, hc, rm);
1003                 }
1004         } else {
1005                 if (syncmaster == hc) {
1006                         if (debug & DEBUG_HFCMULTI_PLXSD)
1007                                 printk(KERN_WARNING "%s: LOST sync on card %d"
1008                                         " (id=%d)\n", __func__, hc->id + 1,
1009                                         hc->id);
1010                         hfcmulti_resync(hc, NULL, rm);
1011                 }
1012         }
1013 }
1014
1015
1016 /*
1017  * free hardware resources used by driver
1018  */
1019 static void
1020 release_io_hfcmulti(struct hfc_multi *hc)
1021 {
1022         void __iomem *plx_acc_32;
1023         u_int   pv;
1024         u_long  plx_flags;
1025
1026         if (debug & DEBUG_HFCMULTI_INIT)
1027                 printk(KERN_DEBUG "%s: entered\n", __func__);
1028
1029         /* soft reset also masks all interrupts */
1030         hc->hw.r_cirm |= V_SRES;
1031         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1032         udelay(1000);
1033         hc->hw.r_cirm &= ~V_SRES;
1034         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1035         udelay(1000); /* instead of 'wait' that may cause locking */
1036
1037         /* release Speech Design card, if PLX was initialized */
1038         if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1039                 if (debug & DEBUG_HFCMULTI_PLXSD)
1040                         printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1041                             __func__, hc->id + 1);
1042                 spin_lock_irqsave(&plx_lock, plx_flags);
1043                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1044                 writel(PLX_GPIOC_INIT, plx_acc_32);
1045                 pv = readl(plx_acc_32);
1046                 /* Termination off */
1047                 pv &= ~PLX_TERM_ON;
1048                 /* Disconnect the PCM */
1049                 pv |= PLX_SLAVE_EN_N;
1050                 pv &= ~PLX_MASTER_EN;
1051                 pv &= ~PLX_SYNC_O_EN;
1052                 /* Put the DSP in Reset */
1053                 pv &= ~PLX_DSP_RES_N;
1054                 writel(pv, plx_acc_32);
1055                 if (debug & DEBUG_HFCMULTI_INIT)
1056                         printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n",
1057                                 __func__, pv);
1058                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1059         }
1060
1061         /* disable memory mapped ports / io ports */
1062         test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1063         pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1064         if (hc->pci_membase)
1065                 iounmap(hc->pci_membase);
1066         if (hc->plx_membase)
1067                 iounmap(hc->plx_membase);
1068         if (hc->pci_iobase)
1069                 release_region(hc->pci_iobase, 8);
1070
1071         if (hc->pci_dev) {
1072                 pci_disable_device(hc->pci_dev);
1073                 pci_set_drvdata(hc->pci_dev, NULL);
1074         }
1075         if (debug & DEBUG_HFCMULTI_INIT)
1076                 printk(KERN_DEBUG "%s: done\n", __func__);
1077 }
1078
1079 /*
1080  * function called to reset the HFC chip. A complete software reset of chip
1081  * and fifos is done. All configuration of the chip is done.
1082  */
1083
1084 static int
1085 init_chip(struct hfc_multi *hc)
1086 {
1087         u_long                  flags, val, val2 = 0, rev;
1088         int                     i, err = 0;
1089         u_char                  r_conf_en, rval;
1090         void __iomem            *plx_acc_32;
1091         u_int                   pv;
1092         u_long                  plx_flags, hfc_flags;
1093         int                     plx_count;
1094         struct hfc_multi        *pos, *next, *plx_last_hc;
1095
1096         spin_lock_irqsave(&hc->lock, flags);
1097         /* reset all registers */
1098         memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1099
1100         /* revision check */
1101         if (debug & DEBUG_HFCMULTI_INIT)
1102                 printk(KERN_DEBUG "%s: entered\n", __func__);
1103         val = HFC_inb(hc, R_CHIP_ID)>>4;
1104         if (val != 0x8 && val != 0xc && val != 0xe) {
1105                 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1106                 err = -EIO;
1107                 goto out;
1108         }
1109         rev = HFC_inb(hc, R_CHIP_RV);
1110         printk(KERN_INFO
1111             "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1112             val, rev, (rev == 0) ? " (old FIFO handling)" : "");
1113         if (rev == 0) {
1114                 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1115                 printk(KERN_WARNING
1116                     "HFC_multi: NOTE: Your chip is revision 0, "
1117                     "ask Cologne Chip for update. Newer chips "
1118                     "have a better FIFO handling. Old chips "
1119                     "still work but may have slightly lower "
1120                     "HDLC transmit performance.\n");
1121         }
1122         if (rev > 1) {
1123                 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1124                     "consider chip revision = %ld. The chip / "
1125                     "bridge may not work.\n", rev);
1126         }
1127
1128         /* set s-ram size */
1129         hc->Flen = 0x10;
1130         hc->Zmin = 0x80;
1131         hc->Zlen = 384;
1132         hc->DTMFbase = 0x1000;
1133         if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1134                 if (debug & DEBUG_HFCMULTI_INIT)
1135                         printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1136                             __func__);
1137                 hc->hw.r_ctrl |= V_EXT_RAM;
1138                 hc->hw.r_ram_sz = 1;
1139                 hc->Flen = 0x20;
1140                 hc->Zmin = 0xc0;
1141                 hc->Zlen = 1856;
1142                 hc->DTMFbase = 0x2000;
1143         }
1144         if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1145                 if (debug & DEBUG_HFCMULTI_INIT)
1146                         printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1147                             __func__);
1148                 hc->hw.r_ctrl |= V_EXT_RAM;
1149                 hc->hw.r_ram_sz = 2;
1150                 hc->Flen = 0x20;
1151                 hc->Zmin = 0xc0;
1152                 hc->Zlen = 8000;
1153                 hc->DTMFbase = 0x2000;
1154         }
1155         hc->max_trans = poll << 1;
1156         if (hc->max_trans > hc->Zlen)
1157                 hc->max_trans = hc->Zlen;
1158
1159         /* Speech Design PLX bridge */
1160         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1161                 if (debug & DEBUG_HFCMULTI_PLXSD)
1162                         printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1163                             __func__, hc->id + 1);
1164                 spin_lock_irqsave(&plx_lock, plx_flags);
1165                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1166                 writel(PLX_GPIOC_INIT, plx_acc_32);
1167                 pv = readl(plx_acc_32);
1168                 /* The first and the last cards are terminating the PCM bus */
1169                 pv |= PLX_TERM_ON; /* hc is currently the last */
1170                 /* Disconnect the PCM */
1171                 pv |= PLX_SLAVE_EN_N;
1172                 pv &= ~PLX_MASTER_EN;
1173                 pv &= ~PLX_SYNC_O_EN;
1174                 /* Put the DSP in Reset */
1175                 pv &= ~PLX_DSP_RES_N;
1176                 writel(pv, plx_acc_32);
1177                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1178                 if (debug & DEBUG_HFCMULTI_INIT)
1179                         printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n",
1180                                 __func__, pv);
1181                 /*
1182                  * If we are the 3rd PLXSD card or higher, we must turn
1183                  * termination of last PLXSD card off.
1184                  */
1185                 spin_lock_irqsave(&HFClock, hfc_flags);
1186                 plx_count = 0;
1187                 plx_last_hc = NULL;
1188                 list_for_each_entry_safe(pos, next, &HFClist, list) {
1189                         if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1190                                 plx_count++;
1191                                 if (pos != hc)
1192                                         plx_last_hc = pos;
1193                         }
1194                 }
1195                 if (plx_count >= 3) {
1196                         if (debug & DEBUG_HFCMULTI_PLXSD)
1197                                 printk(KERN_DEBUG "%s: card %d is between, so "
1198                                         "we disable termination\n",
1199                                     __func__, plx_last_hc->id + 1);
1200                         spin_lock_irqsave(&plx_lock, plx_flags);
1201                         plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1202                         pv = readl(plx_acc_32);
1203                         pv &= ~PLX_TERM_ON;
1204                         writel(pv, plx_acc_32);
1205                         spin_unlock_irqrestore(&plx_lock, plx_flags);
1206                         if (debug & DEBUG_HFCMULTI_INIT)
1207                             printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n",
1208                                         __func__, pv);
1209                 }
1210                 spin_unlock_irqrestore(&HFClock, hfc_flags);
1211                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1212         }
1213
1214         /* we only want the real Z2 read-pointer for revision > 0 */
1215         if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1216                 hc->hw.r_ram_sz |= V_FZ_MD;
1217
1218         /* select pcm mode */
1219         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1220                 if (debug & DEBUG_HFCMULTI_INIT)
1221                         printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1222                             __func__);
1223         } else
1224         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1225                 if (debug & DEBUG_HFCMULTI_INIT)
1226                         printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1227                             __func__);
1228                 hc->hw.r_pcm_md0 |= V_PCM_MD;
1229         } else {
1230                 if (debug & DEBUG_HFCMULTI_INIT)
1231                         printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1232                             __func__);
1233         }
1234
1235         /* soft reset */
1236         HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1237         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1238         HFC_outb(hc, R_FIFO_MD, 0);
1239         hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
1240         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1241         udelay(100);
1242         hc->hw.r_cirm = 0;
1243         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1244         udelay(100);
1245         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1246
1247         /* Speech Design PLX bridge pcm and sync mode */
1248         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1249                 spin_lock_irqsave(&plx_lock, plx_flags);
1250                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1251                 pv = readl(plx_acc_32);
1252                 /* Connect PCM */
1253                 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1254                         pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1255                         pv |= PLX_SYNC_O_EN;
1256                         if (debug & DEBUG_HFCMULTI_INIT)
1257                                 printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n",
1258                                         __func__, pv);
1259                 } else {
1260                         pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1261                         pv &= ~PLX_SYNC_O_EN;
1262                         if (debug & DEBUG_HFCMULTI_INIT)
1263                                 printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n",
1264                                         __func__, pv);
1265                 }
1266                 writel(pv, plx_acc_32);
1267                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1268         }
1269
1270         /* PCM setup */
1271         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1272         if (hc->slots == 32)
1273                 HFC_outb(hc, R_PCM_MD1, 0x00);
1274         if (hc->slots == 64)
1275                 HFC_outb(hc, R_PCM_MD1, 0x10);
1276         if (hc->slots == 128)
1277                 HFC_outb(hc, R_PCM_MD1, 0x20);
1278         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1279         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1280                 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1281         else
1282                 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1283         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1284         for (i = 0; i < 256; i++) {
1285                 HFC_outb_nodebug(hc, R_SLOT, i);
1286                 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1287                 HFC_outb_nodebug(hc, A_CONF, 0);
1288                 hc->slot_owner[i] = -1;
1289         }
1290
1291         /* set clock speed */
1292         if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1293                 if (debug & DEBUG_HFCMULTI_INIT)
1294                         printk(KERN_DEBUG
1295                             "%s: setting double clock\n", __func__);
1296                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1297         }
1298
1299         /* B410P GPIO */
1300         if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1301                 printk(KERN_NOTICE "Setting GPIOs\n");
1302                 HFC_outb(hc, R_GPIO_SEL, 0x30);
1303                 HFC_outb(hc, R_GPIO_EN1, 0x3);
1304                 udelay(1000);
1305                 printk(KERN_NOTICE "calling vpm_init\n");
1306                 vpm_init(hc);
1307         }
1308
1309         /* check if R_F0_CNT counts (8 kHz frame count) */
1310         val = HFC_inb(hc, R_F0_CNTL);
1311         val += HFC_inb(hc, R_F0_CNTH) << 8;
1312         if (debug & DEBUG_HFCMULTI_INIT)
1313                 printk(KERN_DEBUG
1314                     "HFC_multi F0_CNT %ld after reset\n", val);
1315         spin_unlock_irqrestore(&hc->lock, flags);
1316         set_current_state(TASK_UNINTERRUPTIBLE);
1317         schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1318         spin_lock_irqsave(&hc->lock, flags);
1319         val2 = HFC_inb(hc, R_F0_CNTL);
1320         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1321         if (debug & DEBUG_HFCMULTI_INIT)
1322                 printk(KERN_DEBUG
1323                         "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1324                     val2);
1325         if (val2 >= val+8) { /* 1 ms */
1326                 /* it counts, so we keep the pcm mode */
1327                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1328                         printk(KERN_INFO "controller is PCM bus MASTER\n");
1329                 else
1330                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1331                         printk(KERN_INFO "controller is PCM bus SLAVE\n");
1332                 else {
1333                         test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1334                         printk(KERN_INFO "controller is PCM bus SLAVE "
1335                                 "(auto detected)\n");
1336                 }
1337         } else {
1338                 /* does not count */
1339                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1340 controller_fail:
1341                         printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1342                             "pulse. Seems that controller fails.\n");
1343                         err = -EIO;
1344                         goto out;
1345                 }
1346                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1347                         printk(KERN_INFO "controller is PCM bus SLAVE "
1348                                 "(ignoring missing PCM clock)\n");
1349                 } else {
1350                         /* only one pcm master */
1351                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1352                                 && plxsd_master) {
1353                                 printk(KERN_ERR "HFC_multi ERROR, no clock "
1354                                     "on another Speech Design card found. "
1355                                     "Please be sure to connect PCM cable.\n");
1356                                 err = -EIO;
1357                                 goto out;
1358                         }
1359                         /* retry with master clock */
1360                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1361                                 spin_lock_irqsave(&plx_lock, plx_flags);
1362                                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1363                                 pv = readl(plx_acc_32);
1364                                 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1365                                 pv |= PLX_SYNC_O_EN;
1366                                 writel(pv, plx_acc_32);
1367                                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1368                                 if (debug & DEBUG_HFCMULTI_INIT)
1369                                     printk(KERN_WARNING "%s: master: PLX_GPIO"
1370                                         "=%x\n", __func__, pv);
1371                         }
1372                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1373                         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1374                         spin_unlock_irqrestore(&hc->lock, flags);
1375                         set_current_state(TASK_UNINTERRUPTIBLE);
1376                         schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1377                         spin_lock_irqsave(&hc->lock, flags);
1378                         val2 = HFC_inb(hc, R_F0_CNTL);
1379                         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1380                         if (debug & DEBUG_HFCMULTI_INIT)
1381                                 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1382                                         "10 ms (2nd try)\n", val2);
1383                         if (val2 >= val+8) { /* 1 ms */
1384                                 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1385                                         &hc->chip);
1386                                 printk(KERN_INFO "controller is PCM bus MASTER "
1387                                         "(auto detected)\n");
1388                         } else
1389                                 goto controller_fail;
1390                 }
1391         }
1392
1393         /* Release the DSP Reset */
1394         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1395                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1396                         plxsd_master = 1;
1397                 spin_lock_irqsave(&plx_lock, plx_flags);
1398                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1399                 pv = readl(plx_acc_32);
1400                 pv |=  PLX_DSP_RES_N;
1401                 writel(pv, plx_acc_32);
1402                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1403                 if (debug & DEBUG_HFCMULTI_INIT)
1404                         printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n",
1405                                 __func__, pv);
1406         }
1407
1408         /* pcm id */
1409         if (hc->pcm)
1410                 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1411                         hc->pcm);
1412         else {
1413                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1414                  || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1415                         PCM_cnt++; /* SD has proprietary bridging */
1416                 }
1417                 hc->pcm = PCM_cnt;
1418                 printk(KERN_INFO "controller has PCM BUS ID %d "
1419                         "(auto selected)\n", hc->pcm);
1420         }
1421
1422         /* set up timer */
1423         HFC_outb(hc, R_TI_WD, poll_timer);
1424         hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1425
1426         /* set E1 state machine IRQ */
1427         if (hc->type == 1)
1428                 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1429
1430         /* set DTMF detection */
1431         if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1432                 if (debug & DEBUG_HFCMULTI_INIT)
1433                         printk(KERN_DEBUG "%s: enabling DTMF detection "
1434                             "for all B-channel\n", __func__);
1435                 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1436                 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1437                         hc->hw.r_dtmf |= V_ULAW_SEL;
1438                 HFC_outb(hc, R_DTMF_N, 102 - 1);
1439                 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1440         }
1441
1442         /* conference engine */
1443         if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1444                 r_conf_en = V_CONF_EN | V_ULAW;
1445         else
1446                 r_conf_en = V_CONF_EN;
1447         HFC_outb(hc, R_CONF_EN, r_conf_en);
1448
1449         /* setting leds */
1450         switch (hc->leds) {
1451         case 1: /* HFC-E1 OEM */
1452                 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1453                         HFC_outb(hc, R_GPIO_SEL, 0x32);
1454                 else
1455                         HFC_outb(hc, R_GPIO_SEL, 0x30);
1456
1457                 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1458                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1459
1460                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1461                 break;
1462
1463         case 2: /* HFC-4S OEM */
1464         case 3:
1465                 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1466                 HFC_outb(hc, R_GPIO_EN1, 0xff);
1467                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1468                 break;
1469         }
1470
1471         /* set master clock */
1472         if (hc->masterclk >= 0) {
1473                 if (debug & DEBUG_HFCMULTI_INIT)
1474                         printk(KERN_DEBUG "%s: setting ST master clock "
1475                             "to port %d (0..%d)\n",
1476                             __func__, hc->masterclk, hc->ports-1);
1477                 hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
1478                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1479         }
1480
1481         /* setting misc irq */
1482         HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1483         if (debug & DEBUG_HFCMULTI_INIT)
1484                 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1485                     hc->hw.r_irqmsk_misc);
1486
1487         /* RAM access test */
1488         HFC_outb(hc, R_RAM_ADDR0, 0);
1489         HFC_outb(hc, R_RAM_ADDR1, 0);
1490         HFC_outb(hc, R_RAM_ADDR2, 0);
1491         for (i = 0; i < 256; i++) {
1492                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1493                 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1494         }
1495         for (i = 0; i < 256; i++) {
1496                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1497                 HFC_inb_nodebug(hc, R_RAM_DATA);
1498                 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1499                 if (rval != ((i * 3) & 0xff)) {
1500                         printk(KERN_DEBUG
1501                             "addr:%x val:%x should:%x\n", i, rval,
1502                             (i * 3) & 0xff);
1503                         err++;
1504                 }
1505         }
1506         if (err) {
1507                 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1508                 err = -EIO;
1509                 goto out;
1510         }
1511
1512         if (debug & DEBUG_HFCMULTI_INIT)
1513                 printk(KERN_DEBUG "%s: done\n", __func__);
1514 out:
1515         spin_unlock_irqrestore(&hc->lock, flags);
1516         return err;
1517 }
1518
1519
1520 /*
1521  * control the watchdog
1522  */
1523 static void
1524 hfcmulti_watchdog(struct hfc_multi *hc)
1525 {
1526         hc->wdcount++;
1527
1528         if (hc->wdcount > 10) {
1529                 hc->wdcount = 0;
1530                 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1531                     V_GPIO_OUT3 : V_GPIO_OUT2;
1532
1533         /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1534                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1535                 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1536         }
1537 }
1538
1539
1540
1541 /*
1542  * output leds
1543  */
1544 static void
1545 hfcmulti_leds(struct hfc_multi *hc)
1546 {
1547         unsigned long lled;
1548         unsigned long leddw;
1549         int i, state, active, leds;
1550         struct dchannel *dch;
1551         int led[4];
1552
1553         hc->ledcount += poll;
1554         if (hc->ledcount > 4096) {
1555                 hc->ledcount -= 4096;
1556                 hc->ledstate = 0xAFFEAFFE;
1557         }
1558
1559         switch (hc->leds) {
1560         case 1: /* HFC-E1 OEM */
1561                 /* 2 red blinking: NT mode deactivate
1562                  * 2 red steady:   TE mode deactivate
1563                  * left green:     L1 active
1564                  * left red:       frame sync, but no L1
1565                  * right green:    L2 active
1566                  */
1567                 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1568                         if (hc->chan[hc->dslot].dch->dev.D.protocol
1569                                 != ISDN_P_NT_E1) {
1570                                 led[0] = 1;
1571                                 led[1] = 1;
1572                         } else if (hc->ledcount>>11) {
1573                                 led[0] = 1;
1574                                 led[1] = 1;
1575                         } else {
1576                                 led[0] = 0;
1577                                 led[1] = 0;
1578                         }
1579                         led[2] = 0;
1580                         led[3] = 0;
1581                 } else { /* with frame sync */
1582                         /* TODO make it work */
1583                         led[0] = 0;
1584                         led[1] = 0;
1585                         led[2] = 0;
1586                         led[3] = 1;
1587                 }
1588                 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1589                         /* leds are inverted */
1590                 if (leds != (int)hc->ledstate) {
1591                         HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1592                         hc->ledstate = leds;
1593                 }
1594                 break;
1595
1596         case 2: /* HFC-4S OEM */
1597                 /* red blinking = PH_DEACTIVATE NT Mode
1598                  * red steady   = PH_DEACTIVATE TE Mode
1599                  * green steady = PH_ACTIVATE
1600                  */
1601                 for (i = 0; i < 4; i++) {
1602                         state = 0;
1603                         active = -1;
1604                         dch = hc->chan[(i << 2) | 2].dch;
1605                         if (dch) {
1606                                 state = dch->state;
1607                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1608                                         active = 3;
1609                                 else
1610                                         active = 7;
1611                         }
1612                         if (state) {
1613                                 if (state == active) {
1614                                         led[i] = 1; /* led green */
1615                                 } else
1616                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1617                                                 /* TE mode: led red */
1618                                                 led[i] = 2;
1619                                         else
1620                                                 if (hc->ledcount>>11)
1621                                                         /* led red */
1622                                                         led[i] = 2;
1623                                                 else
1624                                                         /* led off */
1625                                                         led[i] = 0;
1626                         } else
1627                                 led[i] = 0; /* led off */
1628                 }
1629                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1630                         leds = 0;
1631                         for (i = 0; i < 4; i++) {
1632                                 if (led[i] == 1) {
1633                                         /*green*/
1634                                         leds |= (0x2 << (i * 2));
1635                                 } else if (led[i] == 2) {
1636                                         /*red*/
1637                                         leds |= (0x1 << (i * 2));
1638                                 }
1639                         }
1640                         if (leds != (int)hc->ledstate) {
1641                                 vpm_out(hc, 0, 0x1a8 + 3, leds);
1642                                 hc->ledstate = leds;
1643                         }
1644                 } else {
1645                         leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1646                             ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1647                             ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1648                             ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1649                         if (leds != (int)hc->ledstate) {
1650                                 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1651                                 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1652                                 hc->ledstate = leds;
1653                         }
1654                 }
1655                 break;
1656
1657         case 3: /* HFC 1S/2S Beronet */
1658                 /* red blinking = PH_DEACTIVATE NT Mode
1659                  * red steady   = PH_DEACTIVATE TE Mode
1660                  * green steady = PH_ACTIVATE
1661                  */
1662                 for (i = 0; i < 2; i++) {
1663                         state = 0;
1664                         active = -1;
1665                         dch = hc->chan[(i << 2) | 2].dch;
1666                         if (dch) {
1667                                 state = dch->state;
1668                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1669                                         active = 3;
1670                                 else
1671                                         active = 7;
1672                         }
1673                         if (state) {
1674                                 if (state == active) {
1675                                         led[i] = 1; /* led green */
1676                                 } else
1677                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1678                                                 /* TE mode: led red */
1679                                                 led[i] = 2;
1680                                         else
1681                                                 if (hc->ledcount >> 11)
1682                                                         /* led red */
1683                                                         led[i] = 2;
1684                                                 else
1685                                                         /* led off */
1686                                                         led[i] = 0;
1687                         } else
1688                                 led[i] = 0; /* led off */
1689                 }
1690
1691
1692                 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1693                         | ((led[1]&1)<<3);
1694                 if (leds != (int)hc->ledstate) {
1695                         HFC_outb_nodebug(hc, R_GPIO_EN1,
1696                             ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1697                         HFC_outb_nodebug(hc, R_GPIO_OUT1,
1698                             ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1699                         hc->ledstate = leds;
1700                 }
1701                 break;
1702         case 8: /* HFC 8S+ Beronet */
1703                 lled = 0;
1704
1705                 for (i = 0; i < 8; i++) {
1706                         state = 0;
1707                         active = -1;
1708                         dch = hc->chan[(i << 2) | 2].dch;
1709                         if (dch) {
1710                                 state = dch->state;
1711                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1712                                         active = 3;
1713                                 else
1714                                         active = 7;
1715                         }
1716                         if (state) {
1717                                 if (state == active) {
1718                                         lled |= 0 << i;
1719                                 } else
1720                                         if (hc->ledcount >> 11)
1721                                                 lled |= 0 << i;
1722                                         else
1723                                                 lled |= 1 << i;
1724                         } else
1725                                 lled |= 1 << i;
1726                 }
1727                 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1728                 if (leddw != hc->ledstate) {
1729                         /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1730                         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1731                         /* was _io before */
1732                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1733                         outw(0x4000, hc->pci_iobase + 4);
1734                         outl(leddw, hc->pci_iobase);
1735                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1736                         hc->ledstate = leddw;
1737                 }
1738                 break;
1739         }
1740 }
1741 /*
1742  * read dtmf coefficients
1743  */
1744
1745 static void
1746 hfcmulti_dtmf(struct hfc_multi *hc)
1747 {
1748         s32             *coeff;
1749         u_int           mantissa;
1750         int             co, ch;
1751         struct bchannel *bch = NULL;
1752         u8              exponent;
1753         int             dtmf = 0;
1754         int             addr;
1755         u16             w_float;
1756         struct sk_buff  *skb;
1757         struct mISDNhead *hh;
1758
1759         if (debug & DEBUG_HFCMULTI_DTMF)
1760                 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1761         for (ch = 0; ch <= 31; ch++) {
1762                 /* only process enabled B-channels */
1763                 bch = hc->chan[ch].bch;
1764                 if (!bch)
1765                         continue;
1766                 if (!hc->created[hc->chan[ch].port])
1767                         continue;
1768                 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1769                         continue;
1770                 if (debug & DEBUG_HFCMULTI_DTMF)
1771                         printk(KERN_DEBUG "%s: dtmf channel %d:",
1772                                 __func__, ch);
1773                 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1774                 dtmf = 1;
1775                 for (co = 0; co < 8; co++) {
1776                         /* read W(n-1) coefficient */
1777                         addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1778                         HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1779                         HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1780                         HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1781                                 | V_ADDR_INC);
1782                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1783                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1784                         if (debug & DEBUG_HFCMULTI_DTMF)
1785                                 printk(" %04x", w_float);
1786
1787                         /* decode float (see chip doc) */
1788                         mantissa = w_float & 0x0fff;
1789                         if (w_float & 0x8000)
1790                                 mantissa |= 0xfffff000;
1791                         exponent = (w_float>>12) & 0x7;
1792                         if (exponent) {
1793                                 mantissa ^= 0x1000;
1794                                 mantissa <<= (exponent-1);
1795                         }
1796
1797                         /* store coefficient */
1798                         coeff[co<<1] = mantissa;
1799
1800                         /* read W(n) coefficient */
1801                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1802                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1803                         if (debug & DEBUG_HFCMULTI_DTMF)
1804                                 printk(" %04x", w_float);
1805
1806                         /* decode float (see chip doc) */
1807                         mantissa = w_float & 0x0fff;
1808                         if (w_float & 0x8000)
1809                                 mantissa |= 0xfffff000;
1810                         exponent = (w_float>>12) & 0x7;
1811                         if (exponent) {
1812                                 mantissa ^= 0x1000;
1813                                 mantissa <<= (exponent-1);
1814                         }
1815
1816                         /* store coefficient */
1817                         coeff[(co<<1)|1] = mantissa;
1818                 }
1819                 if (debug & DEBUG_HFCMULTI_DTMF)
1820                         printk("%s: DTMF ready %08x %08x %08x %08x "
1821                             "%08x %08x %08x %08x\n", __func__,
1822                             coeff[0], coeff[1], coeff[2], coeff[3],
1823                             coeff[4], coeff[5], coeff[6], coeff[7]);
1824                 hc->chan[ch].coeff_count++;
1825                 if (hc->chan[ch].coeff_count == 8) {
1826                         hc->chan[ch].coeff_count = 0;
1827                         skb = mI_alloc_skb(512, GFP_ATOMIC);
1828                         if (!skb) {
1829                                 printk(KERN_WARNING "%s: No memory for skb\n",
1830                                     __func__);
1831                                 continue;
1832                         }
1833                         hh = mISDN_HEAD_P(skb);
1834                         hh->prim = PH_CONTROL_IND;
1835                         hh->id = DTMF_HFC_COEF;
1836                         memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1837                         recv_Bchannel_skb(bch, skb);
1838                 }
1839         }
1840
1841         /* restart DTMF processing */
1842         hc->dtmf = dtmf;
1843         if (dtmf)
1844                 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1845 }
1846
1847
1848 /*
1849  * fill fifo as much as possible
1850  */
1851
1852 static void
1853 hfcmulti_tx(struct hfc_multi *hc, int ch)
1854 {
1855         int i, ii, temp, len = 0;
1856         int Zspace, z1, z2; /* must be int for calculation */
1857         int Fspace, f1, f2;
1858         u_char *d;
1859         int *txpending, slot_tx;
1860         struct  bchannel *bch;
1861         struct  dchannel *dch;
1862         struct  sk_buff **sp = NULL;
1863         int *idxp;
1864
1865         bch = hc->chan[ch].bch;
1866         dch = hc->chan[ch].dch;
1867         if ((!dch) && (!bch))
1868                 return;
1869
1870         txpending = &hc->chan[ch].txpending;
1871         slot_tx = hc->chan[ch].slot_tx;
1872         if (dch) {
1873                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1874                         return;
1875                 sp = &dch->tx_skb;
1876                 idxp = &dch->tx_idx;
1877         } else {
1878                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1879                         return;
1880                 sp = &bch->tx_skb;
1881                 idxp = &bch->tx_idx;
1882         }
1883         if (*sp)
1884                 len = (*sp)->len;
1885
1886         if ((!len) && *txpending != 1)
1887                 return; /* no data */
1888
1889         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1890             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1891             (hc->chan[ch].slot_rx < 0) &&
1892             (hc->chan[ch].slot_tx < 0))
1893                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1894         else
1895                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1896         HFC_wait_nodebug(hc);
1897
1898         if (*txpending == 2) {
1899                 /* reset fifo */
1900                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1901                 HFC_wait_nodebug(hc);
1902                 HFC_outb(hc, A_SUBCH_CFG, 0);
1903                 *txpending = 1;
1904         }
1905 next_frame:
1906         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1907                 f1 = HFC_inb_nodebug(hc, A_F1);
1908                 f2 = HFC_inb_nodebug(hc, A_F2);
1909                 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1910                         if (debug & DEBUG_HFCMULTI_FIFO)
1911                                 printk(KERN_DEBUG
1912                                     "%s(card %d): reread f2 because %d!=%d\n",
1913                                     __func__, hc->id + 1, temp, f2);
1914                         f2 = temp; /* repeat until F2 is equal */
1915                 }
1916                 Fspace = f2 - f1 - 1;
1917                 if (Fspace < 0)
1918                         Fspace += hc->Flen;
1919                 /*
1920                  * Old FIFO handling doesn't give us the current Z2 read
1921                  * pointer, so we cannot send the next frame before the fifo
1922                  * is empty. It makes no difference except for a slightly
1923                  * lower performance.
1924                  */
1925                 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1926                         if (f1 != f2)
1927                                 Fspace = 0;
1928                         else
1929                                 Fspace = 1;
1930                 }
1931                 /* one frame only for ST D-channels, to allow resending */
1932                 if (hc->type != 1 && dch) {
1933                         if (f1 != f2)
1934                                 Fspace = 0;
1935                 }
1936                 /* F-counter full condition */
1937                 if (Fspace == 0)
1938                         return;
1939         }
1940         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1941         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1942         while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1943                 if (debug & DEBUG_HFCMULTI_FIFO)
1944                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
1945                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1946                 z2 = temp; /* repeat unti Z2 is equal */
1947         }
1948         Zspace = z2 - z1;
1949         if (Zspace <= 0)
1950                 Zspace += hc->Zlen;
1951         Zspace -= 4; /* keep not too full, so pointers will not overrun */
1952         /* fill transparent data only to maxinum transparent load (minus 4) */
1953         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
1954                 Zspace = Zspace - hc->Zlen + hc->max_trans;
1955         if (Zspace <= 0) /* no space of 4 bytes */
1956                 return;
1957
1958         /* if no data */
1959         if (!len) {
1960                 if (z1 == z2) { /* empty */
1961                         /* if done with FIFO audio data during PCM connection */
1962                         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
1963                             *txpending && slot_tx >= 0) {
1964                                 if (debug & DEBUG_HFCMULTI_MODE)
1965                                         printk(KERN_DEBUG
1966                                             "%s: reconnecting PCM due to no "
1967                                             "more FIFO data: channel %d "
1968                                             "slot_tx %d\n",
1969                                             __func__, ch, slot_tx);
1970                                 /* connect slot */
1971                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1972                                     V_HDLC_TRP | V_IFF);
1973                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1974                                 HFC_wait_nodebug(hc);
1975                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1976                                     V_HDLC_TRP | V_IFF);
1977                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
1978                                 HFC_wait_nodebug(hc);
1979                         }
1980                         *txpending = 0;
1981                 }
1982                 return; /* no data */
1983         }
1984
1985         /* "fill fifo if empty" feature */
1986         if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
1987                 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
1988                 if (debug & DEBUG_HFCMULTI_FILL)
1989                         printk(KERN_DEBUG "%s: buffer empty, so we have "
1990                                 "underrun\n", __func__);
1991                 /* fill buffer, to prevent future underrun */
1992                 hc->write_fifo(hc, hc->silence_data, poll >> 1);
1993                 Zspace -= (poll >> 1);
1994         }
1995
1996         /* if audio data and connected slot */
1997         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
1998                 && slot_tx >= 0) {
1999                 if (debug & DEBUG_HFCMULTI_MODE)
2000                         printk(KERN_DEBUG "%s: disconnecting PCM due to "
2001                             "FIFO data: channel %d slot_tx %d\n",
2002                             __func__, ch, slot_tx);
2003                 /* disconnect slot */
2004                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2005                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2006                 HFC_wait_nodebug(hc);
2007                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2008                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2009                 HFC_wait_nodebug(hc);
2010         }
2011         *txpending = 1;
2012
2013         /* show activity */
2014         hc->activity[hc->chan[ch].port] = 1;
2015
2016         /* fill fifo to what we have left */
2017         ii = len;
2018         if (dch || test_bit(FLG_HDLC, &bch->Flags))
2019                 temp = 1;
2020         else
2021                 temp = 0;
2022         i = *idxp;
2023         d = (*sp)->data + i;
2024         if (ii - i > Zspace)
2025                 ii = Zspace + i;
2026         if (debug & DEBUG_HFCMULTI_FIFO)
2027                 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2028                     "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2029                         __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2030                         temp ? "HDLC":"TRANS");
2031
2032         /* Have to prep the audio data */
2033         hc->write_fifo(hc, d, ii - i);
2034         *idxp = ii;
2035
2036         /* if not all data has been written */
2037         if (ii != len) {
2038                 /* NOTE: fifo is started by the calling function */
2039                 return;
2040         }
2041
2042         /* if all data has been written, terminate frame */
2043         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2044                 /* increment f-counter */
2045                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2046                 HFC_wait_nodebug(hc);
2047         }
2048
2049         /* send confirm, since get_net_bframe will not do it with trans */
2050         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2051                 confirm_Bsend(bch);
2052
2053         /* check for next frame */
2054         dev_kfree_skb(*sp);
2055         if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2056                 len = (*sp)->len;
2057                 goto next_frame;
2058         }
2059         if (dch && get_next_dframe(dch)) {
2060                 len = (*sp)->len;
2061                 goto next_frame;
2062         }
2063
2064         /*
2065          * now we have no more data, so in case of transparent,
2066          * we set the last byte in fifo to 'silence' in case we will get
2067          * no more data at all. this prevents sending an undefined value.
2068          */
2069         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2070                 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2071 }
2072
2073
2074 /* NOTE: only called if E1 card is in active state */
2075 static void
2076 hfcmulti_rx(struct hfc_multi *hc, int ch)
2077 {
2078         int temp;
2079         int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2080         int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2081         int again = 0;
2082         struct  bchannel *bch;
2083         struct  dchannel *dch;
2084         struct sk_buff  *skb, **sp = NULL;
2085         int     maxlen;
2086
2087         bch = hc->chan[ch].bch;
2088         dch = hc->chan[ch].dch;
2089         if ((!dch) && (!bch))
2090                 return;
2091         if (dch) {
2092                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2093                         return;
2094                 sp = &dch->rx_skb;
2095                 maxlen = dch->maxlen;
2096         } else {
2097                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2098                         return;
2099                 sp = &bch->rx_skb;
2100                 maxlen = bch->maxlen;
2101         }
2102 next_frame:
2103         /* on first AND before getting next valid frame, R_FIFO must be written
2104            to. */
2105         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2106             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2107             (hc->chan[ch].slot_rx < 0) &&
2108             (hc->chan[ch].slot_tx < 0))
2109                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2110         else
2111                 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2112         HFC_wait_nodebug(hc);
2113
2114         /* ignore if rx is off BUT change fifo (above) to start pending TX */
2115         if (hc->chan[ch].rx_off)
2116                 return;
2117
2118         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2119                 f1 = HFC_inb_nodebug(hc, A_F1);
2120                 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2121                         if (debug & DEBUG_HFCMULTI_FIFO)
2122                                 printk(KERN_DEBUG
2123                                     "%s(card %d): reread f1 because %d!=%d\n",
2124                                     __func__, hc->id + 1, temp, f1);
2125                         f1 = temp; /* repeat until F1 is equal */
2126                 }
2127                 f2 = HFC_inb_nodebug(hc, A_F2);
2128         }
2129         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2130         while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2131                 if (debug & DEBUG_HFCMULTI_FIFO)
2132                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2133                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2134                 z1 = temp; /* repeat until Z1 is equal */
2135         }
2136         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2137         Zsize = z1 - z2;
2138         if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2139                 /* complete hdlc frame */
2140                 Zsize++;
2141         if (Zsize < 0)
2142                 Zsize += hc->Zlen;
2143         /* if buffer is empty */
2144         if (Zsize <= 0)
2145                 return;
2146
2147         if (*sp == NULL) {
2148                 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2149                 if (*sp == NULL) {
2150                         printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2151                             __func__);
2152                         return;
2153                 }
2154         }
2155         /* show activity */
2156         hc->activity[hc->chan[ch].port] = 1;
2157
2158         /* empty fifo with what we have */
2159         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2160                 if (debug & DEBUG_HFCMULTI_FIFO)
2161                         printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2162                             "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2163                             "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2164                             Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2165                             f1, f2, Zsize + (*sp)->len, again);
2166                 /* HDLC */
2167                 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2168                         if (debug & DEBUG_HFCMULTI_FIFO)
2169                                 printk(KERN_DEBUG
2170                                     "%s(card %d): hdlc-frame too large.\n",
2171                                     __func__, hc->id + 1);
2172                         skb_trim(*sp, 0);
2173                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2174                         HFC_wait_nodebug(hc);
2175                         return;
2176                 }
2177
2178                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2179
2180                 if (f1 != f2) {
2181                         /* increment Z2,F2-counter */
2182                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2183                         HFC_wait_nodebug(hc);
2184                         /* check size */
2185                         if ((*sp)->len < 4) {
2186                                 if (debug & DEBUG_HFCMULTI_FIFO)
2187                                         printk(KERN_DEBUG
2188                                             "%s(card %d): Frame below minimum "
2189                                             "size\n", __func__, hc->id + 1);
2190                                 skb_trim(*sp, 0);
2191                                 goto next_frame;
2192                         }
2193                         /* there is at least one complete frame, check crc */
2194                         if ((*sp)->data[(*sp)->len - 1]) {
2195                                 if (debug & DEBUG_HFCMULTI_CRC)
2196                                         printk(KERN_DEBUG
2197                                             "%s: CRC-error\n", __func__);
2198                                 skb_trim(*sp, 0);
2199                                 goto next_frame;
2200                         }
2201                         skb_trim(*sp, (*sp)->len - 3);
2202                         if ((*sp)->len < MISDN_COPY_SIZE) {
2203                                 skb = *sp;
2204                                 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2205                                 if (*sp) {
2206                                         memcpy(skb_put(*sp, skb->len),
2207                                             skb->data, skb->len);
2208                                         skb_trim(skb, 0);
2209                                 } else {
2210                                         printk(KERN_DEBUG "%s: No mem\n",
2211                                             __func__);
2212                                         *sp = skb;
2213                                         skb = NULL;
2214                                 }
2215                         } else {
2216                                 skb = NULL;
2217                         }
2218                         if (debug & DEBUG_HFCMULTI_FIFO) {
2219                                 printk(KERN_DEBUG "%s(card %d):",
2220                                         __func__, hc->id + 1);
2221                                 temp = 0;
2222                                 while (temp < (*sp)->len)
2223                                         printk(" %02x", (*sp)->data[temp++]);
2224                                 printk("\n");
2225                         }
2226                         if (dch)
2227                                 recv_Dchannel(dch);
2228                         else
2229                                 recv_Bchannel(bch);
2230                         *sp = skb;
2231                         again++;
2232                         goto next_frame;
2233                 }
2234                 /* there is an incomplete frame */
2235         } else {
2236                 /* transparent */
2237                 if (Zsize > skb_tailroom(*sp))
2238                         Zsize = skb_tailroom(*sp);
2239                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2240                 if (((*sp)->len) < MISDN_COPY_SIZE) {
2241                         skb = *sp;
2242                         *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2243                         if (*sp) {
2244                                 memcpy(skb_put(*sp, skb->len),
2245                                     skb->data, skb->len);
2246                                 skb_trim(skb, 0);
2247                         } else {
2248                                 printk(KERN_DEBUG "%s: No mem\n", __func__);
2249                                 *sp = skb;
2250                                 skb = NULL;
2251                         }
2252                 } else {
2253                         skb = NULL;
2254                 }
2255                 if (debug & DEBUG_HFCMULTI_FIFO)
2256                         printk(KERN_DEBUG
2257                             "%s(card %d): fifo(%d) reading %d bytes "
2258                             "(z1=%04x, z2=%04x) TRANS\n",
2259                                 __func__, hc->id + 1, ch, Zsize, z1, z2);
2260                 /* only bch is transparent */
2261                 recv_Bchannel(bch);
2262                 *sp = skb;
2263         }
2264 }
2265
2266
2267 /*
2268  * Interrupt handler
2269  */
2270 static void
2271 signal_state_up(struct dchannel *dch, int info, char *msg)
2272 {
2273         struct sk_buff  *skb;
2274         int             id, data = info;
2275
2276         if (debug & DEBUG_HFCMULTI_STATE)
2277                 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2278
2279         id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2280
2281         skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2282                 GFP_ATOMIC);
2283         if (!skb)
2284                 return;
2285         recv_Dchannel_skb(dch, skb);
2286 }
2287
2288 static inline void
2289 handle_timer_irq(struct hfc_multi *hc)
2290 {
2291         int             ch, temp;
2292         struct dchannel *dch;
2293         u_long          flags;
2294
2295         /* process queued resync jobs */
2296         if (hc->e1_resync) {
2297                 /* lock, so e1_resync gets not changed */
2298                 spin_lock_irqsave(&HFClock, flags);
2299                 if (hc->e1_resync & 1) {
2300                         if (debug & DEBUG_HFCMULTI_PLXSD)
2301                                 printk(KERN_DEBUG "Enable SYNC_I\n");
2302                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2303                         /* disable JATT, if RX_SYNC is set */
2304                         if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2305                                 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2306                 }
2307                 if (hc->e1_resync & 2) {
2308                         if (debug & DEBUG_HFCMULTI_PLXSD)
2309                                 printk(KERN_DEBUG "Enable jatt PLL\n");
2310                         HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2311                 }
2312                 if (hc->e1_resync & 4) {
2313                         if (debug & DEBUG_HFCMULTI_PLXSD)
2314                                 printk(KERN_DEBUG
2315                                     "Enable QUARTZ for HFC-E1\n");
2316                         /* set jatt to quartz */
2317                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2318                                 | V_JATT_OFF);
2319                         /* switch to JATT, in case it is not already */
2320                         HFC_outb(hc, R_SYNC_OUT, 0);
2321                 }
2322                 hc->e1_resync = 0;
2323                 spin_unlock_irqrestore(&HFClock, flags);
2324         }
2325
2326         if (hc->type != 1 || hc->e1_state == 1)
2327                 for (ch = 0; ch <= 31; ch++) {
2328                         if (hc->created[hc->chan[ch].port]) {
2329                                 hfcmulti_tx(hc, ch);
2330                                 /* fifo is started when switching to rx-fifo */
2331                                 hfcmulti_rx(hc, ch);
2332                                 if (hc->chan[ch].dch &&
2333                                     hc->chan[ch].nt_timer > -1) {
2334                                         dch = hc->chan[ch].dch;
2335                                         if (!(--hc->chan[ch].nt_timer)) {
2336                                                 schedule_event(dch,
2337                                                     FLG_PHCHANGE);
2338                                                 if (debug &
2339                                                     DEBUG_HFCMULTI_STATE)
2340                                                         printk(KERN_DEBUG
2341                                                             "%s: nt_timer at "
2342                                                             "state %x\n",
2343                                                             __func__,
2344                                                             dch->state);
2345                                         }
2346                                 }
2347                         }
2348                 }
2349         if (hc->type == 1 && hc->created[0]) {
2350                 dch = hc->chan[hc->dslot].dch;
2351                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2352                         /* LOS */
2353                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2354                         if (!temp && hc->chan[hc->dslot].los)
2355                                 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2356                                     "LOS detected");
2357                         if (temp && !hc->chan[hc->dslot].los)
2358                                 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2359                                     "LOS gone");
2360                         hc->chan[hc->dslot].los = temp;
2361                 }
2362                 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2363                         /* AIS */
2364                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2365                         if (!temp && hc->chan[hc->dslot].ais)
2366                                 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2367                                     "AIS detected");
2368                         if (temp && !hc->chan[hc->dslot].ais)
2369                                 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2370                                     "AIS gone");
2371                         hc->chan[hc->dslot].ais = temp;
2372                 }
2373                 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2374                         /* SLIP */
2375                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2376                         if (!temp && hc->chan[hc->dslot].slip_rx)
2377                                 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2378                                     " bit SLIP detected RX");
2379                         hc->chan[hc->dslot].slip_rx = temp;
2380                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2381                         if (!temp && hc->chan[hc->dslot].slip_tx)
2382                                 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2383                                     " bit SLIP detected TX");
2384                         hc->chan[hc->dslot].slip_tx = temp;
2385                 }
2386                 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2387                         /* RDI */
2388                         temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2389                         if (!temp && hc->chan[hc->dslot].rdi)
2390                                 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2391                                     "RDI detected");
2392                         if (temp && !hc->chan[hc->dslot].rdi)
2393                                 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2394                                     "RDI gone");
2395                         hc->chan[hc->dslot].rdi = temp;
2396                 }
2397                 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2398                 switch (hc->chan[hc->dslot].sync) {
2399                 case 0:
2400                         if ((temp & 0x60) == 0x60) {
2401                                 if (debug & DEBUG_HFCMULTI_SYNC)
2402                                         printk(KERN_DEBUG
2403                                             "%s: (id=%d) E1 now "
2404                                             "in clock sync\n",
2405                                             __func__, hc->id);
2406                                 HFC_outb(hc, R_RX_OFF,
2407                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2408                                 HFC_outb(hc, R_TX_OFF,
2409                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2410                                 hc->chan[hc->dslot].sync = 1;
2411                                 goto check_framesync;
2412                         }
2413                         break;
2414                 case 1:
2415                         if ((temp & 0x60) != 0x60) {
2416                                 if (debug & DEBUG_HFCMULTI_SYNC)
2417                                         printk(KERN_DEBUG
2418                                             "%s: (id=%d) E1 "
2419                                             "lost clock sync\n",
2420                                             __func__, hc->id);
2421                                 hc->chan[hc->dslot].sync = 0;
2422                                 break;
2423                         }
2424 check_framesync:
2425                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2426                         if (temp == 0x27) {
2427                                 if (debug & DEBUG_HFCMULTI_SYNC)
2428                                         printk(KERN_DEBUG
2429                                             "%s: (id=%d) E1 "
2430                                             "now in frame sync\n",
2431                                             __func__, hc->id);
2432                                 hc->chan[hc->dslot].sync = 2;
2433                         }
2434                         break;
2435                 case 2:
2436                         if ((temp & 0x60) != 0x60) {
2437                                 if (debug & DEBUG_HFCMULTI_SYNC)
2438                                         printk(KERN_DEBUG
2439                                             "%s: (id=%d) E1 lost "
2440                                             "clock & frame sync\n",
2441                                             __func__, hc->id);
2442                                 hc->chan[hc->dslot].sync = 0;
2443                                 break;
2444                         }
2445                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2446                         if (temp != 0x27) {
2447                                 if (debug & DEBUG_HFCMULTI_SYNC)
2448                                         printk(KERN_DEBUG
2449                                             "%s: (id=%d) E1 "
2450                                             "lost frame sync\n",
2451                                             __func__, hc->id);
2452                                 hc->chan[hc->dslot].sync = 1;
2453                         }
2454                         break;
2455                 }
2456         }
2457
2458         if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2459                 hfcmulti_watchdog(hc);
2460
2461         if (hc->leds)
2462                 hfcmulti_leds(hc);
2463 }
2464
2465 static void
2466 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2467 {
2468         struct dchannel *dch;
2469         int             ch;
2470         int             active;
2471         u_char          st_status, temp;
2472
2473         /* state machine */
2474         for (ch = 0; ch <= 31; ch++) {
2475                 if (hc->chan[ch].dch) {
2476                         dch = hc->chan[ch].dch;
2477                         if (r_irq_statech & 1) {
2478                                 HFC_outb_nodebug(hc, R_ST_SEL,
2479                                         hc->chan[ch].port);
2480                                 /* undocumented: delay after R_ST_SEL */
2481                                 udelay(1);
2482                                 /* undocumented: status changes during read */
2483                                 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2484                                 while (st_status != (temp =
2485                                         HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2486                                         if (debug & DEBUG_HFCMULTI_STATE)
2487                                                 printk(KERN_DEBUG "%s: reread "
2488                                                     "STATE because %d!=%d\n",
2489                                                     __func__, temp,
2490                                                     st_status);
2491                                         st_status = temp; /* repeat */
2492                                 }
2493
2494                                 /* Speech Design TE-sync indication */
2495                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2496                                         dch->dev.D.protocol == ISDN_P_TE_S0) {
2497                                         if (st_status & V_FR_SYNC_ST)
2498                                                 hc->syncronized |=
2499                                                     (1 << hc->chan[ch].port);
2500                                         else
2501                                                 hc->syncronized &=
2502                                                    ~(1 << hc->chan[ch].port);
2503                                 }
2504                                 dch->state = st_status & 0x0f;
2505                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2506                                         active = 3;
2507                                 else
2508                                         active = 7;
2509                                 if (dch->state == active) {
2510                                         HFC_outb_nodebug(hc, R_FIFO,
2511                                                 (ch << 1) | 1);
2512                                         HFC_wait_nodebug(hc);
2513                                         HFC_outb_nodebug(hc,
2514                                                 R_INC_RES_FIFO, V_RES_F);
2515                                         HFC_wait_nodebug(hc);
2516                                         dch->tx_idx = 0;
2517                                 }
2518                                 schedule_event(dch, FLG_PHCHANGE);
2519                                 if (debug & DEBUG_HFCMULTI_STATE)
2520                                         printk(KERN_DEBUG
2521                                             "%s: S/T newstate %x port %d\n",
2522                                             __func__, dch->state,
2523                                             hc->chan[ch].port);
2524                         }
2525                         r_irq_statech >>= 1;
2526                 }
2527         }
2528         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2529                 plxsd_checksync(hc, 0);
2530 }
2531
2532 static void
2533 fifo_irq(struct hfc_multi *hc, int block)
2534 {
2535         int     ch, j;
2536         struct dchannel *dch;
2537         struct bchannel *bch;
2538         u_char r_irq_fifo_bl;
2539
2540         r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2541         j = 0;
2542         while (j < 8) {
2543                 ch = (block << 2) + (j >> 1);
2544                 dch = hc->chan[ch].dch;
2545                 bch = hc->chan[ch].bch;
2546                 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2547                         j += 2;
2548                         continue;
2549                 }
2550                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2551                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2552                         hfcmulti_tx(hc, ch);
2553                         /* start fifo */
2554                         HFC_outb_nodebug(hc, R_FIFO, 0);
2555                         HFC_wait_nodebug(hc);
2556                 }
2557                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2558                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2559                         hfcmulti_tx(hc, ch);
2560                         /* start fifo */
2561                         HFC_outb_nodebug(hc, R_FIFO, 0);
2562                         HFC_wait_nodebug(hc);
2563                 }
2564                 j++;
2565                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2566                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2567                         hfcmulti_rx(hc, ch);
2568                 }
2569                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2570                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2571                         hfcmulti_rx(hc, ch);
2572                 }
2573                 j++;
2574         }
2575 }
2576
2577 #ifdef IRQ_DEBUG
2578 int irqsem;
2579 #endif
2580 static irqreturn_t
2581 hfcmulti_interrupt(int intno, void *dev_id)
2582 {
2583 #ifdef IRQCOUNT_DEBUG
2584         static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2585             iq5 = 0, iq6 = 0, iqcnt = 0;
2586 #endif
2587         struct hfc_multi        *hc = dev_id;
2588         struct dchannel         *dch;
2589         u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
2590         int                     i;
2591         void __iomem            *plx_acc;
2592         u_short                 wval;
2593         u_char                  e1_syncsta, temp;
2594         u_long                  flags;
2595
2596         if (!hc) {
2597                 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2598                 return IRQ_NONE;
2599         }
2600
2601         spin_lock(&hc->lock);
2602
2603 #ifdef IRQ_DEBUG
2604         if (irqsem)
2605                 printk(KERN_ERR "irq for card %d during irq from "
2606                 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2607         irqsem = hc->id + 1;
2608 #endif
2609
2610         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2611                 spin_lock_irqsave(&plx_lock, flags);
2612                 plx_acc = hc->plx_membase + PLX_INTCSR;
2613                 wval = readw(plx_acc);
2614                 spin_unlock_irqrestore(&plx_lock, flags);
2615                 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2616                         goto irq_notforus;
2617         }
2618
2619         status = HFC_inb_nodebug(hc, R_STATUS);
2620         r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2621 #ifdef IRQCOUNT_DEBUG
2622         if (r_irq_statech)
2623                 iq1++;
2624         if (status & V_DTMF_STA)
2625                 iq2++;
2626         if (status & V_LOST_STA)
2627                 iq3++;
2628         if (status & V_EXT_IRQSTA)
2629                 iq4++;
2630         if (status & V_MISC_IRQSTA)
2631                 iq5++;
2632         if (status & V_FR_IRQSTA)
2633                 iq6++;
2634         if (iqcnt++ > 5000) {
2635                 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2636                     iq1, iq2, iq3, iq4, iq5, iq6);
2637                 iqcnt = 0;
2638         }
2639 #endif
2640
2641         if (!r_irq_statech &&
2642             !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2643             V_MISC_IRQSTA | V_FR_IRQSTA))) {
2644                 /* irq is not for us */
2645                 goto irq_notforus;
2646         }
2647         hc->irqcnt++;
2648         if (r_irq_statech) {
2649                 if (hc->type != 1)
2650                         ph_state_irq(hc, r_irq_statech);
2651         }
2652         if (status & V_EXT_IRQSTA)
2653                 ; /* external IRQ */
2654         if (status & V_LOST_STA) {
2655                 /* LOST IRQ */
2656                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2657         }
2658         if (status & V_MISC_IRQSTA) {
2659                 /* misc IRQ */
2660                 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2661                 if (r_irq_misc & V_STA_IRQ) {
2662                         if (hc->type == 1) {
2663                                 /* state machine */
2664                                 dch = hc->chan[hc->dslot].dch;
2665                                 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2666                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2667                                  && hc->e1_getclock) {
2668                                         if (e1_syncsta & V_FR_SYNC_E1)
2669                                                 hc->syncronized = 1;
2670                                         else
2671                                                 hc->syncronized = 0;
2672                                 }
2673                                 /* undocumented: status changes during read */
2674                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2675                                 while (dch->state != (temp =
2676                                         HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2677                                         if (debug & DEBUG_HFCMULTI_STATE)
2678                                                 printk(KERN_DEBUG "%s: reread "
2679                                                     "STATE because %d!=%d\n",
2680                                                     __func__, temp,
2681                                                     dch->state);
2682                                         dch->state = temp; /* repeat */
2683                                 }
2684                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2685                                         & 0x7;
2686                                 schedule_event(dch, FLG_PHCHANGE);
2687                                 if (debug & DEBUG_HFCMULTI_STATE)
2688                                         printk(KERN_DEBUG
2689                                             "%s: E1 (id=%d) newstate %x\n",
2690                                             __func__, hc->id, dch->state);
2691                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2692                                         plxsd_checksync(hc, 0);
2693                         }
2694                 }
2695                 if (r_irq_misc & V_TI_IRQ) {
2696                         if (hc->iclock_on)
2697                                 mISDN_clock_update(hc->iclock, poll, NULL);
2698                         handle_timer_irq(hc);
2699                 }
2700
2701                 if (r_irq_misc & V_DTMF_IRQ) {
2702                         hfcmulti_dtmf(hc);
2703                 }
2704                 if (r_irq_misc & V_IRQ_PROC) {
2705                         static int irq_proc_cnt;
2706                         if (!irq_proc_cnt++)
2707                                 printk(KERN_WARNING "%s: got V_IRQ_PROC -"
2708                                     " this should not happen\n", __func__);
2709                 }
2710
2711         }
2712         if (status & V_FR_IRQSTA) {
2713                 /* FIFO IRQ */
2714                 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2715                 for (i = 0; i < 8; i++) {
2716                         if (r_irq_oview & (1 << i))
2717                                 fifo_irq(hc, i);
2718                 }
2719         }
2720
2721 #ifdef IRQ_DEBUG
2722         irqsem = 0;
2723 #endif
2724         spin_unlock(&hc->lock);
2725         return IRQ_HANDLED;
2726
2727 irq_notforus:
2728 #ifdef IRQ_DEBUG
2729         irqsem = 0;
2730 #endif
2731         spin_unlock(&hc->lock);
2732         return IRQ_NONE;
2733 }
2734
2735
2736 /*
2737  * timer callback for D-chan busy resolution. Currently no function
2738  */
2739
2740 static void
2741 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2742 {
2743 }
2744
2745
2746 /*
2747  * activate/deactivate hardware for selected channels and mode
2748  *
2749  * configure B-channel with the given protocol
2750  * ch eqals to the HFC-channel (0-31)
2751  * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2752  * for S/T, 1-31 for E1)
2753  * the hdlc interrupts will be set/unset
2754  */
2755 static int
2756 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2757     int bank_tx, int slot_rx, int bank_rx)
2758 {
2759         int flow_tx = 0, flow_rx = 0, routing = 0;
2760         int oslot_tx, oslot_rx;
2761         int conf;
2762
2763         if (ch < 0 || ch > 31)
2764                 return EINVAL;
2765         oslot_tx = hc->chan[ch].slot_tx;
2766         oslot_rx = hc->chan[ch].slot_rx;
2767         conf = hc->chan[ch].conf;
2768
2769         if (debug & DEBUG_HFCMULTI_MODE)
2770                 printk(KERN_DEBUG
2771                     "%s: card %d channel %d protocol %x slot old=%d new=%d "
2772                     "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2773                     __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2774                     bank_tx, oslot_rx, slot_rx, bank_rx);
2775
2776         if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2777                 /* remove from slot */
2778                 if (debug & DEBUG_HFCMULTI_MODE)
2779                         printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2780                             __func__, oslot_tx);
2781                 if (hc->slot_owner[oslot_tx<<1] == ch) {
2782                         HFC_outb(hc, R_SLOT, oslot_tx << 1);
2783                         HFC_outb(hc, A_SL_CFG, 0);
2784                         HFC_outb(hc, A_CONF, 0);
2785                         hc->slot_owner[oslot_tx<<1] = -1;
2786                 } else {
2787                         if (debug & DEBUG_HFCMULTI_MODE)
2788                                 printk(KERN_DEBUG
2789                                     "%s: we are not owner of this tx slot "
2790                                     "anymore, channel %d is.\n",
2791                                     __func__, hc->slot_owner[oslot_tx<<1]);
2792                 }
2793         }
2794
2795         if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2796                 /* remove from slot */
2797                 if (debug & DEBUG_HFCMULTI_MODE)
2798                         printk(KERN_DEBUG
2799                             "%s: remove from slot %d (RX)\n",
2800                             __func__, oslot_rx);
2801                 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2802                         HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2803                         HFC_outb(hc, A_SL_CFG, 0);
2804                         hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2805                 } else {
2806                         if (debug & DEBUG_HFCMULTI_MODE)
2807                                 printk(KERN_DEBUG
2808                                     "%s: we are not owner of this rx slot "
2809                                     "anymore, channel %d is.\n",
2810                                     __func__,
2811                                     hc->slot_owner[(oslot_rx << 1) | 1]);
2812                 }
2813         }
2814
2815         if (slot_tx < 0) {
2816                 flow_tx = 0x80; /* FIFO->ST */
2817                 /* disable pcm slot */
2818                 hc->chan[ch].slot_tx = -1;
2819                 hc->chan[ch].bank_tx = 0;
2820         } else {
2821                 /* set pcm slot */
2822                 if (hc->chan[ch].txpending)
2823                         flow_tx = 0x80; /* FIFO->ST */
2824                 else
2825                         flow_tx = 0xc0; /* PCM->ST */
2826                 /* put on slot */
2827                 routing = bank_tx ? 0xc0 : 0x80;
2828                 if (conf >= 0 || bank_tx > 1)
2829                         routing = 0x40; /* loop */
2830                 if (debug & DEBUG_HFCMULTI_MODE)
2831                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2832                             " %d flow %02x routing %02x conf %d (TX)\n",
2833                             __func__, ch, slot_tx, bank_tx,
2834                             flow_tx, routing, conf);
2835                 HFC_outb(hc, R_SLOT, slot_tx << 1);
2836                 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2837                 HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
2838                 hc->slot_owner[slot_tx << 1] = ch;
2839                 hc->chan[ch].slot_tx = slot_tx;
2840                 hc->chan[ch].bank_tx = bank_tx;
2841         }
2842         if (slot_rx < 0) {
2843                 /* disable pcm slot */
2844                 flow_rx = 0x80; /* ST->FIFO */
2845                 hc->chan[ch].slot_rx = -1;
2846                 hc->chan[ch].bank_rx = 0;
2847         } else {
2848                 /* set pcm slot */
2849                 if (hc->chan[ch].txpending)
2850                         flow_rx = 0x80; /* ST->FIFO */
2851                 else
2852                         flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2853                 /* put on slot */
2854                 routing = bank_rx?0x80:0xc0; /* reversed */
2855                 if (conf >= 0 || bank_rx > 1)
2856                         routing = 0x40; /* loop */
2857                 if (debug & DEBUG_HFCMULTI_MODE)
2858                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2859                             " %d flow %02x routing %02x conf %d (RX)\n",
2860                             __func__, ch, slot_rx, bank_rx,
2861                             flow_rx, routing, conf);
2862                 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2863                 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2864                 hc->slot_owner[(slot_rx<<1)|1] = ch;
2865                 hc->chan[ch].slot_rx = slot_rx;
2866                 hc->chan[ch].bank_rx = bank_rx;
2867         }
2868
2869         switch (protocol) {
2870         case (ISDN_P_NONE):
2871                 /* disable TX fifo */
2872                 HFC_outb(hc, R_FIFO, ch << 1);
2873                 HFC_wait(hc);
2874                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2875                 HFC_outb(hc, A_SUBCH_CFG, 0);
2876                 HFC_outb(hc, A_IRQ_MSK, 0);
2877                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2878                 HFC_wait(hc);
2879                 /* disable RX fifo */
2880                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2881                 HFC_wait(hc);
2882                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2883                 HFC_outb(hc, A_SUBCH_CFG, 0);
2884                 HFC_outb(hc, A_IRQ_MSK, 0);
2885                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2886                 HFC_wait(hc);
2887                 if (hc->chan[ch].bch && hc->type != 1) {
2888                         hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2889                             ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
2890                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2891                         /* undocumented: delay after R_ST_SEL */
2892                         udelay(1);
2893                         HFC_outb(hc, A_ST_CTRL0,
2894                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2895                 }
2896                 if (hc->chan[ch].bch) {
2897                         test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2898                         test_and_clear_bit(FLG_TRANSPARENT,
2899                             &hc->chan[ch].bch->Flags);
2900                 }
2901                 break;
2902         case (ISDN_P_B_RAW): /* B-channel */
2903
2904                 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2905                     (hc->chan[ch].slot_rx < 0) &&
2906                     (hc->chan[ch].slot_tx < 0)) {
2907
2908                         printk(KERN_DEBUG
2909                             "Setting B-channel %d to echo cancelable "
2910                             "state on PCM slot %d\n", ch,
2911                             ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2912                         printk(KERN_DEBUG
2913                             "Enabling pass through for channel\n");
2914                         vpm_out(hc, ch, ((ch / 4) * 8) +
2915                             ((ch % 4) * 4) + 1, 0x01);
2916                         /* rx path */
2917                         /* S/T -> PCM */
2918                         HFC_outb(hc, R_FIFO, (ch << 1));
2919                         HFC_wait(hc);
2920                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2921                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2922                             ((ch % 4) * 4) + 1) << 1);
2923                         HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2924
2925                         /* PCM -> FIFO */
2926                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2927                         HFC_wait(hc);
2928                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2929                         HFC_outb(hc, A_SUBCH_CFG, 0);
2930                         HFC_outb(hc, A_IRQ_MSK, 0);
2931                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2932                         HFC_wait(hc);
2933                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2934                             ((ch % 4) * 4) + 1) << 1) | 1);
2935                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
2936
2937                         /* tx path */
2938                         /* PCM -> S/T */
2939                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2940                         HFC_wait(hc);
2941                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2942                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2943                             ((ch % 4) * 4)) << 1) | 1);
2944                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
2945
2946                         /* FIFO -> PCM */
2947                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
2948                         HFC_wait(hc);
2949                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2950                         HFC_outb(hc, A_SUBCH_CFG, 0);
2951                         HFC_outb(hc, A_IRQ_MSK, 0);
2952                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2953                         HFC_wait(hc);
2954                         /* tx silence */
2955                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2956                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2957                             ((ch % 4) * 4)) << 1);
2958                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
2959                 } else {
2960                         /* enable TX fifo */
2961                         HFC_outb(hc, R_FIFO, ch << 1);
2962                         HFC_wait(hc);
2963                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
2964                             V_HDLC_TRP | V_IFF);
2965                         HFC_outb(hc, A_SUBCH_CFG, 0);
2966                         HFC_outb(hc, A_IRQ_MSK, 0);
2967                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2968                         HFC_wait(hc);
2969                         /* tx silence */
2970                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2971                         /* enable RX fifo */
2972                         HFC_outb(hc, R_FIFO, (ch<<1)|1);
2973                         HFC_wait(hc);
2974                         HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
2975                         HFC_outb(hc, A_SUBCH_CFG, 0);
2976                         HFC_outb(hc, A_IRQ_MSK, 0);
2977                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2978                         HFC_wait(hc);
2979                 }
2980                 if (hc->type != 1) {
2981                         hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
2982                             ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
2983                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2984                         /* undocumented: delay after R_ST_SEL */
2985                         udelay(1);
2986                         HFC_outb(hc, A_ST_CTRL0,
2987                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2988                 }
2989                 if (hc->chan[ch].bch)
2990                         test_and_set_bit(FLG_TRANSPARENT,
2991                             &hc->chan[ch].bch->Flags);
2992                 break;
2993         case (ISDN_P_B_HDLC): /* B-channel */
2994         case (ISDN_P_TE_S0): /* D-channel */
2995         case (ISDN_P_NT_S0):
2996         case (ISDN_P_TE_E1):
2997         case (ISDN_P_NT_E1):
2998                 /* enable TX fifo */
2999                 HFC_outb(hc, R_FIFO, ch<<1);
3000                 HFC_wait(hc);
3001                 if (hc->type == 1 || hc->chan[ch].bch) {
3002                         /* E1 or B-channel */
3003                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3004                         HFC_outb(hc, A_SUBCH_CFG, 0);
3005                 } else {
3006                         /* D-Channel without HDLC fill flags */
3007                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3008                         HFC_outb(hc, A_SUBCH_CFG, 2);
3009                 }
3010                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3011                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3012                 HFC_wait(hc);
3013                 /* enable RX fifo */
3014                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3015                 HFC_wait(hc);
3016                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3017                 if (hc->type == 1 || hc->chan[ch].bch)
3018                         HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3019                 else
3020                         HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3021                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3022                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3023                 HFC_wait(hc);
3024                 if (hc->chan[ch].bch) {
3025                         test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3026                         if (hc->type != 1) {
3027                                 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3028                                   ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3029                                 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3030                                 /* undocumented: delay after R_ST_SEL */
3031                                 udelay(1);
3032                                 HFC_outb(hc, A_ST_CTRL0,
3033                                   hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3034                         }
3035                 }
3036                 break;
3037         default:
3038                 printk(KERN_DEBUG "%s: protocol not known %x\n",
3039                     __func__, protocol);
3040                 hc->chan[ch].protocol = ISDN_P_NONE;
3041                 return -ENOPROTOOPT;
3042         }
3043         hc->chan[ch].protocol = protocol;
3044         return 0;
3045 }
3046
3047
3048 /*
3049  * connect/disconnect PCM
3050  */
3051
3052 static void
3053 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3054     int slot_rx, int bank_rx)
3055 {
3056         if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3057                 /* disable PCM */
3058                 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3059                 return;
3060         }
3061
3062         /* enable pcm */
3063         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3064                 slot_rx, bank_rx);
3065 }
3066
3067 /*
3068  * set/disable conference
3069  */
3070
3071 static void
3072 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3073 {
3074         if (num >= 0 && num <= 7)
3075                 hc->chan[ch].conf = num;
3076         else
3077                 hc->chan[ch].conf = -1;
3078         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3079             hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3080             hc->chan[ch].bank_rx);
3081 }
3082
3083
3084 /*
3085  * set/disable sample loop
3086  */
3087
3088 /* NOTE: this function is experimental and therefore disabled */
3089
3090 /*
3091  * Layer 1 callback function
3092  */
3093 static int
3094 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3095 {
3096         struct hfc_multi        *hc = dch->hw;
3097         u_long  flags;
3098
3099         switch (cmd) {
3100         case INFO3_P8:
3101         case INFO3_P10:
3102                 break;
3103         case HW_RESET_REQ:
3104                 /* start activation */
3105                 spin_lock_irqsave(&hc->lock, flags);
3106                 if (hc->type == 1) {
3107                         if (debug & DEBUG_HFCMULTI_MSG)
3108                                 printk(KERN_DEBUG
3109                                     "%s: HW_RESET_REQ no BRI\n",
3110                                     __func__);
3111                 } else {
3112                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3113                         /* undocumented: delay after R_ST_SEL */
3114                         udelay(1);
3115                         HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3116                         udelay(6); /* wait at least 5,21us */
3117                         HFC_outb(hc, A_ST_WR_STATE, 3);
3118                         HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3119                                 /* activate */
3120                 }
3121                 spin_unlock_irqrestore(&hc->lock, flags);
3122                 l1_event(dch->l1, HW_POWERUP_IND);
3123                 break;
3124         case HW_DEACT_REQ:
3125                 /* start deactivation */
3126                 spin_lock_irqsave(&hc->lock, flags);
3127                 if (hc->type == 1) {
3128                         if (debug & DEBUG_HFCMULTI_MSG)
3129                                 printk(KERN_DEBUG
3130                                     "%s: HW_DEACT_REQ no BRI\n",
3131                                     __func__);
3132                 } else {
3133                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3134                         /* undocumented: delay after R_ST_SEL */
3135                         udelay(1);
3136                         HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3137                                 /* deactivate */
3138                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3139                                 hc->syncronized &=
3140                                    ~(1 << hc->chan[dch->slot].port);
3141                                 plxsd_checksync(hc, 0);
3142                         }
3143                 }
3144                 skb_queue_purge(&dch->squeue);
3145                 if (dch->tx_skb) {
3146                         dev_kfree_skb(dch->tx_skb);
3147                         dch->tx_skb = NULL;
3148                 }
3149                 dch->tx_idx = 0;
3150                 if (dch->rx_skb) {
3151                         dev_kfree_skb(dch->rx_skb);
3152                         dch->rx_skb = NULL;
3153                 }
3154                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3155                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3156                         del_timer(&dch->timer);
3157                 spin_unlock_irqrestore(&hc->lock, flags);
3158                 break;
3159         case HW_POWERUP_REQ:
3160                 spin_lock_irqsave(&hc->lock, flags);
3161                 if (hc->type == 1) {
3162                         if (debug & DEBUG_HFCMULTI_MSG)
3163                                 printk(KERN_DEBUG
3164                                     "%s: HW_POWERUP_REQ no BRI\n",
3165                                     __func__);
3166                 } else {
3167                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3168                         /* undocumented: delay after R_ST_SEL */
3169                         udelay(1);
3170                         HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3171                         udelay(6); /* wait at least 5,21us */
3172                         HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3173                 }
3174                 spin_unlock_irqrestore(&hc->lock, flags);
3175                 break;
3176         case PH_ACTIVATE_IND:
3177                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3178                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3179                         GFP_ATOMIC);
3180                 break;
3181         case PH_DEACTIVATE_IND:
3182                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3183                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3184                         GFP_ATOMIC);
3185                 break;
3186         default:
3187                 if (dch->debug & DEBUG_HW)
3188                         printk(KERN_DEBUG "%s: unknown command %x\n",
3189                             __func__, cmd);
3190                 return -1;
3191         }
3192         return 0;
3193 }
3194
3195 /*
3196  * Layer2 -> Layer 1 Transfer
3197  */
3198
3199 static int
3200 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3201 {
3202         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
3203         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
3204         struct hfc_multi        *hc = dch->hw;
3205         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3206         int                     ret = -EINVAL;
3207         unsigned int            id;
3208         u_long                  flags;
3209
3210         switch (hh->prim) {
3211         case PH_DATA_REQ:
3212                 if (skb->len < 1)
3213                         break;
3214                 spin_lock_irqsave(&hc->lock, flags);
3215                 ret = dchannel_senddata(dch, skb);
3216                 if (ret > 0) { /* direct TX */
3217                         id = hh->id; /* skb can be freed */
3218                         hfcmulti_tx(hc, dch->slot);
3219                         ret = 0;
3220                         /* start fifo */
3221                         HFC_outb(hc, R_FIFO, 0);
3222                         HFC_wait(hc);
3223                         spin_unlock_irqrestore(&hc->lock, flags);
3224                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3225                 } else
3226                         spin_unlock_irqrestore(&hc->lock, flags);
3227                 return ret;
3228         case PH_ACTIVATE_REQ:
3229                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3230                         spin_lock_irqsave(&hc->lock, flags);
3231                         ret = 0;
3232                         if (debug & DEBUG_HFCMULTI_MSG)
3233                                 printk(KERN_DEBUG
3234                                     "%s: PH_ACTIVATE port %d (0..%d)\n",
3235                                     __func__, hc->chan[dch->slot].port,
3236                                     hc->ports-1);
3237                         /* start activation */
3238                         if (hc->type == 1) {
3239                                 ph_state_change(dch);
3240                                 if (debug & DEBUG_HFCMULTI_STATE)
3241                                         printk(KERN_DEBUG
3242                                             "%s: E1 report state %x \n",
3243                                             __func__, dch->state);
3244                         } else {
3245                                 HFC_outb(hc, R_ST_SEL,
3246                                     hc->chan[dch->slot].port);
3247                                 /* undocumented: delay after R_ST_SEL */
3248                                 udelay(1);
3249                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3250                                     /* G1 */
3251                                 udelay(6); /* wait at least 5,21us */
3252                                 HFC_outb(hc, A_ST_WR_STATE, 1);
3253                                 HFC_outb(hc, A_ST_WR_STATE, 1 |
3254                                     (V_ST_ACT*3)); /* activate */
3255                                 dch->state = 1;
3256                         }
3257                         spin_unlock_irqrestore(&hc->lock, flags);
3258                 } else
3259                         ret = l1_event(dch->l1, hh->prim);
3260                 break;
3261         case PH_DEACTIVATE_REQ:
3262                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3263                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3264                         spin_lock_irqsave(&hc->lock, flags);
3265                         if (debug & DEBUG_HFCMULTI_MSG)
3266                                 printk(KERN_DEBUG
3267                                     "%s: PH_DEACTIVATE port %d (0..%d)\n",
3268                                     __func__, hc->chan[dch->slot].port,
3269                                     hc->ports-1);
3270                         /* start deactivation */
3271                         if (hc->type == 1) {
3272                                 if (debug & DEBUG_HFCMULTI_MSG)
3273                                         printk(KERN_DEBUG
3274                                             "%s: PH_DEACTIVATE no BRI\n",
3275                                             __func__);
3276                         } else {
3277                                 HFC_outb(hc, R_ST_SEL,
3278                                     hc->chan[dch->slot].port);
3279                                 /* undocumented: delay after R_ST_SEL */
3280                                 udelay(1);
3281                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3282                                     /* deactivate */
3283                                 dch->state = 1;
3284                         }
3285                         skb_queue_purge(&dch->squeue);
3286                         if (dch->tx_skb) {
3287                                 dev_kfree_skb(dch->tx_skb);
3288                                 dch->tx_skb = NULL;
3289                         }
3290                         dch->tx_idx = 0;
3291                         if (dch->rx_skb) {
3292                                 dev_kfree_skb(dch->rx_skb);
3293                                 dch->rx_skb = NULL;
3294                         }
3295                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3296                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3297                                 del_timer(&dch->timer);
3298 #ifdef FIXME
3299                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3300                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3301 #endif
3302                         ret = 0;
3303                         spin_unlock_irqrestore(&hc->lock, flags);
3304                 } else
3305                         ret = l1_event(dch->l1, hh->prim);
3306                 break;
3307         }
3308         if (!ret)
3309                 dev_kfree_skb(skb);
3310         return ret;
3311 }
3312
3313 static void
3314 deactivate_bchannel(struct bchannel *bch)
3315 {
3316         struct hfc_multi        *hc = bch->hw;
3317         u_long                  flags;
3318
3319         spin_lock_irqsave(&hc->lock, flags);
3320         if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
3321                 dev_kfree_skb(bch->next_skb);
3322                 bch->next_skb = NULL;
3323         }
3324         if (bch->tx_skb) {
3325                 dev_kfree_skb(bch->tx_skb);
3326                 bch->tx_skb = NULL;
3327         }
3328         bch->tx_idx = 0;
3329         if (bch->rx_skb) {
3330                 dev_kfree_skb(bch->rx_skb);
3331                 bch->rx_skb = NULL;
3332         }
3333         hc->chan[bch->slot].coeff_count = 0;
3334         test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
3335         test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
3336         hc->chan[bch->slot].rx_off = 0;
3337         hc->chan[bch->slot].conf = -1;
3338         mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3339         spin_unlock_irqrestore(&hc->lock, flags);
3340 }
3341
3342 static int
3343 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3344 {
3345         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3346         struct hfc_multi        *hc = bch->hw;
3347         int                     ret = -EINVAL;
3348         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3349         unsigned int            id;
3350         u_long                  flags;
3351
3352         switch (hh->prim) {
3353         case PH_DATA_REQ:
3354                 if (!skb->len)
3355                         break;
3356                 spin_lock_irqsave(&hc->lock, flags);
3357                 ret = bchannel_senddata(bch, skb);
3358                 if (ret > 0) { /* direct TX */
3359                         id = hh->id; /* skb can be freed */
3360                         hfcmulti_tx(hc, bch->slot);
3361                         ret = 0;
3362                         /* start fifo */
3363                         HFC_outb_nodebug(hc, R_FIFO, 0);
3364                         HFC_wait_nodebug(hc);
3365                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3366                                 spin_unlock_irqrestore(&hc->lock, flags);
3367                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3368                         } else
3369                                 spin_unlock_irqrestore(&hc->lock, flags);
3370                 } else
3371                         spin_unlock_irqrestore(&hc->lock, flags);
3372                 return ret;
3373         case PH_ACTIVATE_REQ:
3374                 if (debug & DEBUG_HFCMULTI_MSG)
3375                         printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3376                                 __func__, bch->slot);
3377                 spin_lock_irqsave(&hc->lock, flags);
3378                 /* activate B-channel if not already activated */
3379                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3380                         hc->chan[bch->slot].txpending = 0;
3381                         ret = mode_hfcmulti(hc, bch->slot,
3382                                 ch->protocol,
3383                                 hc->chan[bch->slot].slot_tx,
3384                                 hc->chan[bch->slot].bank_tx,
3385                                 hc->chan[bch->slot].slot_rx,
3386                                 hc->chan[bch->slot].bank_rx);
3387                         if (!ret) {
3388                                 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3389                                         && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3390                                         /* start decoder */
3391                                         hc->dtmf = 1;
3392                                         if (debug & DEBUG_HFCMULTI_DTMF)
3393                                                 printk(KERN_DEBUG
3394                                                     "%s: start dtmf decoder\n",
3395                                                         __func__);
3396                                         HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3397                                             V_RST_DTMF);
3398                                 }
3399                         }
3400                 } else
3401                         ret = 0;
3402                 spin_unlock_irqrestore(&hc->lock, flags);
3403                 if (!ret)
3404                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3405                                 GFP_KERNEL);
3406                 break;
3407         case PH_CONTROL_REQ:
3408                 spin_lock_irqsave(&hc->lock, flags);
3409                 switch (hh->id) {
3410                 case HFC_SPL_LOOP_ON: /* set sample loop */
3411                         if (debug & DEBUG_HFCMULTI_MSG)
3412                         printk(KERN_DEBUG
3413                             "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3414                             __func__, skb->len);
3415                         ret = 0;
3416                         break;
3417                 case HFC_SPL_LOOP_OFF: /* set silence */
3418                         if (debug & DEBUG_HFCMULTI_MSG)
3419                                 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3420                                     __func__);
3421                         ret = 0;
3422                         break;
3423                 default:
3424                         printk(KERN_ERR
3425                              "%s: unknown PH_CONTROL_REQ info %x\n",
3426                              __func__, hh->id);
3427                         ret = -EINVAL;
3428                 }
3429                 spin_unlock_irqrestore(&hc->lock, flags);
3430                 break;
3431         case PH_DEACTIVATE_REQ:
3432                 deactivate_bchannel(bch); /* locked there */
3433                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3434                         GFP_KERNEL);
3435                 ret = 0;
3436                 break;
3437         }
3438         if (!ret)
3439                 dev_kfree_skb(skb);
3440         return ret;
3441 }
3442
3443 /*
3444  * bchannel control function
3445  */
3446 static int
3447 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3448 {
3449         int                     ret = 0;
3450         struct dsp_features     *features =
3451                 (struct dsp_features *)(*((u_long *)&cq->p1));
3452         struct hfc_multi        *hc = bch->hw;
3453         int                     slot_tx;
3454         int                     bank_tx;
3455         int                     slot_rx;
3456         int                     bank_rx;
3457         int                     num;
3458
3459         switch (cq->op) {
3460         case MISDN_CTRL_GETOP:
3461                 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3462                         | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY;
3463                 break;
3464         case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3465                 hc->chan[bch->slot].rx_off = !!cq->p1;
3466                 if (!hc->chan[bch->slot].rx_off) {
3467                         /* reset fifo on rx on */
3468                         HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3469                         HFC_wait_nodebug(hc);
3470                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3471                         HFC_wait_nodebug(hc);
3472                 }
3473                 if (debug & DEBUG_HFCMULTI_MSG)
3474                         printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3475                             __func__, bch->nr, hc->chan[bch->slot].rx_off);
3476                 break;
3477         case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
3478                 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
3479                 if (debug & DEBUG_HFCMULTI_MSG)
3480                         printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
3481                                 "off=%d)\n", __func__, bch->nr, !!cq->p1);
3482                 break;
3483         case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3484                 if (debug & DEBUG_HFCMULTI_MSG)
3485                         printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3486                             __func__);
3487                 /* create confirm */
3488                 features->hfc_id = hc->id;
3489                 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3490                         features->hfc_dtmf = 1;
3491                 features->hfc_loops = 0;
3492                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3493                         features->hfc_echocanhw = 1;
3494                 } else {
3495                         features->pcm_id = hc->pcm;
3496                         features->pcm_slots = hc->slots;
3497                         features->pcm_banks = 2;
3498                 }
3499                 break;
3500         case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3501                 slot_tx = cq->p1 & 0xff;
3502                 bank_tx = cq->p1 >> 8;
3503                 slot_rx = cq->p2 & 0xff;
3504                 bank_rx = cq->p2 >> 8;
3505                 if (debug & DEBUG_HFCMULTI_MSG)
3506                         printk(KERN_DEBUG
3507                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3508                             "slot %d bank %d (RX)\n",
3509                             __func__, slot_tx, bank_tx,
3510                             slot_rx, bank_rx);
3511                 if (slot_tx < hc->slots && bank_tx <= 2 &&
3512                     slot_rx < hc->slots && bank_rx <= 2)
3513                         hfcmulti_pcm(hc, bch->slot,
3514                             slot_tx, bank_tx, slot_rx, bank_rx);
3515                 else {
3516                         printk(KERN_WARNING
3517                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3518                             "slot %d bank %d (RX) out of range\n",
3519                             __func__, slot_tx, bank_tx,
3520                             slot_rx, bank_rx);
3521                         ret = -EINVAL;
3522                 }
3523                 break;
3524         case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3525                 if (debug & DEBUG_HFCMULTI_MSG)
3526                         printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3527                             __func__);
3528                 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3529                 break;
3530         case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3531                 num = cq->p1 & 0xff;
3532                 if (debug & DEBUG_HFCMULTI_MSG)
3533                         printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3534                             __func__, num);
3535                 if (num <= 7)
3536                         hfcmulti_conf(hc, bch->slot, num);
3537                 else {
3538                         printk(KERN_WARNING
3539                             "%s: HW_CONF_JOIN conf %d out of range\n",
3540                             __func__, num);
3541                         ret = -EINVAL;
3542                 }
3543                 break;
3544         case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3545                 if (debug & DEBUG_HFCMULTI_MSG)
3546                         printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3547                 hfcmulti_conf(hc, bch->slot, -1);
3548                 break;
3549         case MISDN_CTRL_HFC_ECHOCAN_ON:
3550                 if (debug & DEBUG_HFCMULTI_MSG)
3551                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3552                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3553                         vpm_echocan_on(hc, bch->slot, cq->p1);
3554                 else
3555                         ret = -EINVAL;
3556                 break;
3557
3558         case MISDN_CTRL_HFC_ECHOCAN_OFF:
3559                 if (debug & DEBUG_HFCMULTI_MSG)
3560                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3561                                 __func__);
3562                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3563                         vpm_echocan_off(hc, bch->slot);
3564                 else
3565                         ret = -EINVAL;
3566                 break;
3567         default:
3568                 printk(KERN_WARNING "%s: unknown Op %x\n",
3569                     __func__, cq->op);
3570                 ret = -EINVAL;
3571                 break;
3572         }
3573         return ret;
3574 }
3575
3576 static int
3577 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3578 {
3579         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3580         struct hfc_multi        *hc = bch->hw;
3581         int                     err = -EINVAL;
3582         u_long  flags;
3583
3584         if (bch->debug & DEBUG_HW)
3585                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3586                     __func__, cmd, arg);
3587         switch (cmd) {
3588         case CLOSE_CHANNEL:
3589                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3590                 if (test_bit(FLG_ACTIVE, &bch->Flags))
3591                         deactivate_bchannel(bch); /* locked there */
3592                 ch->protocol = ISDN_P_NONE;
3593                 ch->peer = NULL;
3594                 module_put(THIS_MODULE);
3595                 err = 0;
3596                 break;
3597         case CONTROL_CHANNEL:
3598                 spin_lock_irqsave(&hc->lock, flags);
3599                 err = channel_bctrl(bch, arg);
3600                 spin_unlock_irqrestore(&hc->lock, flags);
3601                 break;
3602         default:
3603                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3604                         __func__, cmd);
3605         }
3606         return err;
3607 }
3608
3609 /*
3610  * handle D-channel events
3611  *
3612  * handle state change event
3613  */
3614 static void
3615 ph_state_change(struct dchannel *dch)
3616 {
3617         struct hfc_multi *hc = dch->hw;
3618         int ch, i;
3619
3620         if (!dch) {
3621                 printk(KERN_WARNING "%s: ERROR given dch is NULL\n",
3622                     __func__);
3623                 return;
3624         }
3625         ch = dch->slot;
3626
3627         if (hc->type == 1) {
3628                 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3629                         if (debug & DEBUG_HFCMULTI_STATE)
3630                                 printk(KERN_DEBUG
3631                                     "%s: E1 TE (id=%d) newstate %x\n",
3632                                     __func__, hc->id, dch->state);
3633                 } else {
3634                         if (debug & DEBUG_HFCMULTI_STATE)
3635                                 printk(KERN_DEBUG
3636                                     "%s: E1 NT (id=%d) newstate %x\n",
3637                                     __func__, hc->id, dch->state);
3638                 }
3639                 switch (dch->state) {
3640                 case (1):
3641                         if (hc->e1_state != 1) {
3642                             for (i = 1; i <= 31; i++) {
3643                                 /* reset fifos on e1 activation */
3644                                 HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1);
3645                                 HFC_wait_nodebug(hc);
3646                                 HFC_outb_nodebug(hc,
3647                                         R_INC_RES_FIFO, V_RES_F);
3648                                 HFC_wait_nodebug(hc);
3649                             }
3650                         }
3651                         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3652                         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3653                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3654                         break;
3655
3656                 default:
3657                         if (hc->e1_state != 1)
3658                                 return;
3659                         test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3660                         _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3661                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3662                 }
3663                 hc->e1_state = dch->state;
3664         } else {
3665                 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3666                         if (debug & DEBUG_HFCMULTI_STATE)
3667                                 printk(KERN_DEBUG
3668                                     "%s: S/T TE newstate %x\n",
3669                                     __func__, dch->state);
3670                         switch (dch->state) {
3671                         case (0):
3672                                 l1_event(dch->l1, HW_RESET_IND);
3673                                 break;
3674                         case (3):
3675                                 l1_event(dch->l1, HW_DEACT_IND);
3676                                 break;
3677                         case (5):
3678                         case (8):
3679                                 l1_event(dch->l1, ANYSIGNAL);
3680                                 break;
3681                         case (6):
3682                                 l1_event(dch->l1, INFO2);
3683                                 break;
3684                         case (7):
3685                                 l1_event(dch->l1, INFO4_P8);
3686                                 break;
3687                         }
3688                 } else {
3689                         if (debug & DEBUG_HFCMULTI_STATE)
3690                                 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3691                                     __func__, dch->state);
3692                         switch (dch->state) {
3693                         case (2):
3694                                 if (hc->chan[ch].nt_timer == 0) {
3695                                         hc->chan[ch].nt_timer = -1;
3696                                         HFC_outb(hc, R_ST_SEL,
3697                                             hc->chan[ch].port);
3698                                         /* undocumented: delay after R_ST_SEL */
3699                                         udelay(1);
3700                                         HFC_outb(hc, A_ST_WR_STATE, 4 |
3701                                             V_ST_LD_STA); /* G4 */
3702                                         udelay(6); /* wait at least 5,21us */
3703                                         HFC_outb(hc, A_ST_WR_STATE, 4);
3704                                         dch->state = 4;
3705                                 } else {
3706                                         /* one extra count for the next event */
3707                                         hc->chan[ch].nt_timer =
3708                                             nt_t1_count[poll_timer] + 1;
3709                                         HFC_outb(hc, R_ST_SEL,
3710                                             hc->chan[ch].port);
3711                                         /* undocumented: delay after R_ST_SEL */
3712                                         udelay(1);
3713                                         /* allow G2 -> G3 transition */
3714                                         HFC_outb(hc, A_ST_WR_STATE, 2 |
3715                                             V_SET_G2_G3);
3716                                 }
3717                                 break;
3718                         case (1):
3719                                 hc->chan[ch].nt_timer = -1;
3720                                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3721                                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3722                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3723                                 break;
3724                         case (4):
3725                                 hc->chan[ch].nt_timer = -1;
3726                                 break;
3727                         case (3):
3728                                 hc->chan[ch].nt_timer = -1;
3729                                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3730                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3731                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3732                                 break;
3733                         }
3734                 }
3735         }
3736 }
3737
3738 /*
3739  * called for card mode init message
3740  */
3741
3742 static void
3743 hfcmulti_initmode(struct dchannel *dch)
3744 {
3745         struct hfc_multi *hc = dch->hw;
3746         u_char          a_st_wr_state, r_e1_wr_sta;
3747         int             i, pt;
3748
3749         if (debug & DEBUG_HFCMULTI_INIT)
3750                 printk(KERN_DEBUG "%s: entered\n", __func__);
3751
3752         if (hc->type == 1) {
3753                 hc->chan[hc->dslot].slot_tx = -1;
3754                 hc->chan[hc->dslot].slot_rx = -1;
3755                 hc->chan[hc->dslot].conf = -1;
3756                 if (hc->dslot) {
3757                         mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3758                                 -1, 0, -1, 0);
3759                         dch->timer.function = (void *) hfcmulti_dbusy_timer;
3760                         dch->timer.data = (long) dch;
3761                         init_timer(&dch->timer);
3762                 }
3763                 for (i = 1; i <= 31; i++) {
3764                         if (i == hc->dslot)
3765                                 continue;
3766                         hc->chan[i].slot_tx = -1;
3767                         hc->chan[i].slot_rx = -1;
3768                         hc->chan[i].conf = -1;
3769                         mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3770                 }
3771                 /* E1 */
3772                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3773                         HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3774                         HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3775                 }
3776                 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3777                         HFC_outb(hc, R_RX0, 0);
3778                         hc->hw.r_tx0 = 0 | V_OUT_EN;
3779                 } else {
3780                         HFC_outb(hc, R_RX0, 1);
3781                         hc->hw.r_tx0 = 1 | V_OUT_EN;
3782                 }
3783                 hc->hw.r_tx1 = V_ATX | V_NTRI;
3784                 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3785                 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3786                 HFC_outb(hc, R_TX_FR0, 0x00);
3787                 HFC_outb(hc, R_TX_FR1, 0xf8);
3788
3789                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3790                         HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3791
3792                 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3793
3794                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3795                         HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3796
3797                 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3798                         if (debug & DEBUG_HFCMULTI_INIT)
3799                                 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3800                                     __func__);
3801                         r_e1_wr_sta = 0; /* G0 */
3802                         hc->e1_getclock = 0;
3803                 } else {
3804                         if (debug & DEBUG_HFCMULTI_INIT)
3805                                 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3806                                     __func__);
3807                         r_e1_wr_sta = 0; /* F0 */
3808                         hc->e1_getclock = 1;
3809                 }
3810                 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3811                         HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3812                 else
3813                         HFC_outb(hc, R_SYNC_OUT, 0);
3814                 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3815                         hc->e1_getclock = 1;
3816                 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3817                         hc->e1_getclock = 0;
3818                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3819                         /* SLAVE (clock master) */
3820                         if (debug & DEBUG_HFCMULTI_INIT)
3821                                 printk(KERN_DEBUG
3822                                     "%s: E1 port is clock master "
3823                                     "(clock from PCM)\n", __func__);
3824                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3825                 } else {
3826                         if (hc->e1_getclock) {
3827                                 /* MASTER (clock slave) */
3828                                 if (debug & DEBUG_HFCMULTI_INIT)
3829                                         printk(KERN_DEBUG
3830                                             "%s: E1 port is clock slave "
3831                                             "(clock to PCM)\n", __func__);
3832                                 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3833                         } else {
3834                                 /* MASTER (clock master) */
3835                                 if (debug & DEBUG_HFCMULTI_INIT)
3836                                         printk(KERN_DEBUG "%s: E1 port is "
3837                                             "clock master "
3838                                             "(clock from QUARTZ)\n",
3839                                             __func__);
3840                                 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3841                                     V_PCM_SYNC | V_JATT_OFF);
3842                                 HFC_outb(hc, R_SYNC_OUT, 0);
3843                         }
3844                 }
3845                 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3846                 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3847                 HFC_outb(hc, R_PWM0, 0x50);
3848                 HFC_outb(hc, R_PWM1, 0xff);
3849                 /* state machine setup */
3850                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3851                 udelay(6); /* wait at least 5,21us */
3852                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3853                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3854                         hc->syncronized = 0;
3855                         plxsd_checksync(hc, 0);
3856                 }
3857         } else {
3858                 i = dch->slot;
3859                 hc->chan[i].slot_tx = -1;
3860                 hc->chan[i].slot_rx = -1;
3861                 hc->chan[i].conf = -1;
3862                 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3863                 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3864                 dch->timer.data = (long) dch;
3865                 init_timer(&dch->timer);
3866                 hc->chan[i - 2].slot_tx = -1;
3867                 hc->chan[i - 2].slot_rx = -1;
3868                 hc->chan[i - 2].conf = -1;
3869                 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3870                 hc->chan[i - 1].slot_tx = -1;
3871                 hc->chan[i - 1].slot_rx = -1;
3872                 hc->chan[i - 1].conf = -1;
3873                 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3874                 /* ST */
3875                 pt = hc->chan[i].port;
3876                 /* select interface */
3877                 HFC_outb(hc, R_ST_SEL, pt);
3878                 /* undocumented: delay after R_ST_SEL */
3879                 udelay(1);
3880                 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3881                         if (debug & DEBUG_HFCMULTI_INIT)
3882                                 printk(KERN_DEBUG
3883                                     "%s: ST port %d is NT-mode\n",
3884                                     __func__, pt);
3885                         /* clock delay */
3886                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3887                         a_st_wr_state = 1; /* G1 */
3888                         hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3889                 } else {
3890                         if (debug & DEBUG_HFCMULTI_INIT)
3891                                 printk(KERN_DEBUG
3892                                     "%s: ST port %d is TE-mode\n",
3893                                     __func__, pt);
3894                         /* clock delay */
3895                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3896                         a_st_wr_state = 2; /* F2 */
3897                         hc->hw.a_st_ctrl0[pt] = 0;
3898                 }
3899                 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3900                         hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3901                 /* line setup */
3902                 HFC_outb(hc, A_ST_CTRL0,  hc->hw.a_st_ctrl0[pt]);
3903                 /* disable E-channel */
3904                 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3905                     test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3906                         HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3907                 else
3908                         HFC_outb(hc, A_ST_CTRL1, 0);
3909                 /* enable B-channel receive */
3910                 HFC_outb(hc, A_ST_CTRL2,  V_B1_RX_EN | V_B2_RX_EN);
3911                 /* state machine setup */
3912                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3913                 udelay(6); /* wait at least 5,21us */
3914                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
3915                 hc->hw.r_sci_msk |= 1 << pt;
3916                 /* state machine interrupts */
3917                 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
3918                 /* unset sync on port */
3919                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3920                         hc->syncronized &=
3921                            ~(1 << hc->chan[dch->slot].port);
3922                         plxsd_checksync(hc, 0);
3923                 }
3924         }
3925         if (debug & DEBUG_HFCMULTI_INIT)
3926                 printk("%s: done\n", __func__);
3927 }
3928
3929
3930 static int
3931 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
3932     struct channel_req *rq)
3933 {
3934         int     err = 0;
3935         u_long  flags;
3936
3937         if (debug & DEBUG_HW_OPEN)
3938                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
3939                     dch->dev.id, __builtin_return_address(0));
3940         if (rq->protocol == ISDN_P_NONE)
3941                 return -EINVAL;
3942         if ((dch->dev.D.protocol != ISDN_P_NONE) &&
3943             (dch->dev.D.protocol != rq->protocol)) {
3944             if (debug & DEBUG_HFCMULTI_MODE)
3945                 printk(KERN_WARNING "%s: change protocol %x to %x\n",
3946                     __func__, dch->dev.D.protocol, rq->protocol);
3947         }
3948         if ((dch->dev.D.protocol == ISDN_P_TE_S0)
3949          && (rq->protocol != ISDN_P_TE_S0))
3950                 l1_event(dch->l1, CLOSE_CHANNEL);
3951         if (dch->dev.D.protocol != rq->protocol) {
3952                 if (rq->protocol == ISDN_P_TE_S0) {
3953                         err = create_l1(dch, hfcm_l1callback);
3954                         if (err)
3955                                 return err;
3956                 }
3957                 dch->dev.D.protocol = rq->protocol;
3958                 spin_lock_irqsave(&hc->lock, flags);
3959                 hfcmulti_initmode(dch);
3960                 spin_unlock_irqrestore(&hc->lock, flags);
3961         }
3962
3963         if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
3964             ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
3965             ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
3966             ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
3967                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
3968                     0, NULL, GFP_KERNEL);
3969         }
3970         rq->ch = &dch->dev.D;
3971         if (!try_module_get(THIS_MODULE))
3972                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3973         return 0;
3974 }
3975
3976 static int
3977 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
3978     struct channel_req *rq)
3979 {
3980         struct bchannel *bch;
3981         int             ch;
3982
3983         if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
3984                 return -EINVAL;
3985         if (rq->protocol == ISDN_P_NONE)
3986                 return -EINVAL;
3987         if (hc->type == 1)
3988                 ch = rq->adr.channel;
3989         else
3990                 ch = (rq->adr.channel - 1) + (dch->slot - 2);
3991         bch = hc->chan[ch].bch;
3992         if (!bch) {
3993                 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
3994                     __func__, ch);
3995                 return -EINVAL;
3996         }
3997         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
3998                 return -EBUSY; /* b-channel can be only open once */
3999         test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
4000         bch->ch.protocol = rq->protocol;
4001         hc->chan[ch].rx_off = 0;
4002         rq->ch = &bch->ch;
4003         if (!try_module_get(THIS_MODULE))
4004                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4005         return 0;
4006 }
4007
4008 /*
4009  * device control function
4010  */
4011 static int
4012 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4013 {
4014         int     ret = 0;
4015
4016         switch (cq->op) {
4017         case MISDN_CTRL_GETOP:
4018                 cq->op = 0;
4019                 break;
4020         default:
4021                 printk(KERN_WARNING "%s: unknown Op %x\n",
4022                     __func__, cq->op);
4023                 ret = -EINVAL;
4024                 break;
4025         }
4026         return ret;
4027 }
4028
4029 static int
4030 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4031 {
4032         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
4033         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
4034         struct hfc_multi        *hc = dch->hw;
4035         struct channel_req      *rq;
4036         int                     err = 0;
4037         u_long                  flags;
4038
4039         if (dch->debug & DEBUG_HW)
4040                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4041                     __func__, cmd, arg);
4042         switch (cmd) {
4043         case OPEN_CHANNEL:
4044                 rq = arg;
4045                 switch (rq->protocol) {
4046                 case ISDN_P_TE_S0:
4047                 case ISDN_P_NT_S0:
4048                         if (hc->type == 1) {
4049                                 err = -EINVAL;
4050                                 break;
4051                         }
4052                         err = open_dchannel(hc, dch, rq); /* locked there */
4053                         break;
4054                 case ISDN_P_TE_E1:
4055                 case ISDN_P_NT_E1:
4056                         if (hc->type != 1) {
4057                                 err = -EINVAL;
4058                                 break;
4059                         }
4060                         err = open_dchannel(hc, dch, rq); /* locked there */
4061                         break;
4062                 default:
4063                         spin_lock_irqsave(&hc->lock, flags);
4064                         err = open_bchannel(hc, dch, rq);
4065                         spin_unlock_irqrestore(&hc->lock, flags);
4066                 }
4067                 break;
4068         case CLOSE_CHANNEL:
4069                 if (debug & DEBUG_HW_OPEN)
4070                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4071                             __func__, dch->dev.id,
4072                             __builtin_return_address(0));
4073                 module_put(THIS_MODULE);
4074                 break;
4075         case CONTROL_CHANNEL:
4076                 spin_lock_irqsave(&hc->lock, flags);
4077                 err = channel_dctrl(dch, arg);
4078                 spin_unlock_irqrestore(&hc->lock, flags);
4079                 break;
4080         default:
4081                 if (dch->debug & DEBUG_HW)
4082                         printk(KERN_DEBUG "%s: unknown command %x\n",
4083                             __func__, cmd);
4084                 err = -EINVAL;
4085         }
4086         return err;
4087 }
4088
4089 static int
4090 clockctl(void *priv, int enable)
4091 {
4092         struct hfc_multi *hc = priv;
4093
4094         hc->iclock_on = enable;
4095         return 0;
4096 }
4097
4098 /*
4099  * initialize the card
4100  */
4101
4102 /*
4103  * start timer irq, wait some time and check if we have interrupts.
4104  * if not, reset chip and try again.
4105  */
4106 static int
4107 init_card(struct hfc_multi *hc)
4108 {
4109         int     err = -EIO;
4110         u_long  flags;
4111         void    __iomem *plx_acc;
4112         u_long  plx_flags;
4113
4114         if (debug & DEBUG_HFCMULTI_INIT)
4115                 printk(KERN_DEBUG "%s: entered\n", __func__);
4116
4117         spin_lock_irqsave(&hc->lock, flags);
4118         /* set interrupts but leave global interrupt disabled */
4119         hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4120         disable_hwirq(hc);
4121         spin_unlock_irqrestore(&hc->lock, flags);
4122
4123         if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
4124             "HFC-multi", hc)) {
4125                 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4126                     hc->pci_dev->irq);
4127                 return -EIO;
4128         }
4129         hc->irq = hc->pci_dev->irq;
4130
4131         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4132                 spin_lock_irqsave(&plx_lock, plx_flags);
4133                 plx_acc = hc->plx_membase + PLX_INTCSR;
4134                 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4135                         plx_acc); /* enable PCI & LINT1 irq */
4136                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4137         }
4138
4139         if (debug & DEBUG_HFCMULTI_INIT)
4140                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4141                     __func__, hc->irq, hc->irqcnt);
4142         err = init_chip(hc);
4143         if (err)
4144                 goto error;
4145         /*
4146          * Finally enable IRQ output
4147          * this is only allowed, if an IRQ routine is allready
4148          * established for this HFC, so don't do that earlier
4149          */
4150         spin_lock_irqsave(&hc->lock, flags);
4151         enable_hwirq(hc);
4152         spin_unlock_irqrestore(&hc->lock, flags);
4153         /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4154         set_current_state(TASK_UNINTERRUPTIBLE);
4155         schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4156         /* turn IRQ off until chip is completely initialized */
4157         spin_lock_irqsave(&hc->lock, flags);
4158         disable_hwirq(hc);
4159         spin_unlock_irqrestore(&hc->lock, flags);
4160         if (debug & DEBUG_HFCMULTI_INIT)
4161                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4162                     __func__, hc->irq, hc->irqcnt);
4163         if (hc->irqcnt) {
4164                 if (debug & DEBUG_HFCMULTI_INIT)
4165                         printk(KERN_DEBUG "%s: done\n", __func__);
4166
4167                 return 0;
4168         }
4169         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4170                 printk(KERN_INFO "ignoring missing interrupts\n");
4171                 return 0;
4172         }
4173
4174         printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4175                 hc->irq);
4176
4177         err = -EIO;
4178
4179 error:
4180         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4181                 spin_lock_irqsave(&plx_lock, plx_flags);
4182                 plx_acc = hc->plx_membase + PLX_INTCSR;
4183                 writew(0x00, plx_acc); /*disable IRQs*/
4184                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4185         }
4186
4187         if (debug & DEBUG_HFCMULTI_INIT)
4188                 printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq);
4189         if (hc->irq) {
4190                 free_irq(hc->irq, hc);
4191                 hc->irq = 0;
4192         }
4193
4194         if (debug & DEBUG_HFCMULTI_INIT)
4195                 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4196         return err;
4197 }
4198
4199 /*
4200  * find pci device and set it up
4201  */
4202
4203 static int
4204 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4205                 const struct pci_device_id *ent)
4206 {
4207         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4208
4209         printk(KERN_INFO
4210             "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4211             m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4212
4213         hc->pci_dev = pdev;
4214         if (m->clock2)
4215                 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4216
4217         if (ent->device == 0xB410) {
4218                 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4219                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4220                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4221                 hc->slots = 32;
4222         }
4223
4224         if (hc->pci_dev->irq <= 0) {
4225                 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4226                 return -EIO;
4227         }
4228         if (pci_enable_device(hc->pci_dev)) {
4229                 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4230                 return -EIO;
4231         }
4232         hc->leds = m->leds;
4233         hc->ledstate = 0xAFFEAFFE;
4234         hc->opticalsupport = m->opticalsupport;
4235
4236         /* set memory access methods */
4237         if (m->io_mode) /* use mode from card config */
4238                 hc->io_mode = m->io_mode;
4239         switch (hc->io_mode) {
4240         case HFC_IO_MODE_PLXSD:
4241                 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4242                 hc->slots = 128; /* required */
4243                 /* fall through */
4244         case HFC_IO_MODE_PCIMEM:
4245                 hc->HFC_outb = HFC_outb_pcimem;
4246                 hc->HFC_inb = HFC_inb_pcimem;
4247                 hc->HFC_inw = HFC_inw_pcimem;
4248                 hc->HFC_wait = HFC_wait_pcimem;
4249                 hc->read_fifo = read_fifo_pcimem;
4250                 hc->write_fifo = write_fifo_pcimem;
4251                 break;
4252         case HFC_IO_MODE_REGIO:
4253                 hc->HFC_outb = HFC_outb_regio;
4254                 hc->HFC_inb = HFC_inb_regio;
4255                 hc->HFC_inw = HFC_inw_regio;
4256                 hc->HFC_wait = HFC_wait_regio;
4257                 hc->read_fifo = read_fifo_regio;
4258                 hc->write_fifo = write_fifo_regio;
4259                 break;
4260         default:
4261                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4262                 pci_disable_device(hc->pci_dev);
4263                 return -EIO;
4264         }
4265         hc->HFC_outb_nodebug = hc->HFC_outb;
4266         hc->HFC_inb_nodebug = hc->HFC_inb;
4267         hc->HFC_inw_nodebug = hc->HFC_inw;
4268         hc->HFC_wait_nodebug = hc->HFC_wait;
4269 #ifdef HFC_REGISTER_DEBUG
4270         hc->HFC_outb = HFC_outb_debug;
4271         hc->HFC_inb = HFC_inb_debug;
4272         hc->HFC_inw = HFC_inw_debug;
4273         hc->HFC_wait = HFC_wait_debug;
4274 #endif
4275         hc->pci_iobase = 0;
4276         hc->pci_membase = NULL;
4277         hc->plx_membase = NULL;
4278
4279         switch (hc->io_mode) {
4280         case HFC_IO_MODE_PLXSD:
4281                 hc->plx_origmembase =  hc->pci_dev->resource[0].start;
4282                 /* MEMBASE 1 is PLX PCI Bridge */
4283
4284                 if (!hc->plx_origmembase) {
4285                         printk(KERN_WARNING
4286                           "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4287                         pci_disable_device(hc->pci_dev);
4288                         return -EIO;
4289                 }
4290
4291                 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4292                 if (!hc->plx_membase) {
4293                         printk(KERN_WARNING
4294                             "HFC-multi: failed to remap plx address space. "
4295                             "(internal error)\n");
4296                         pci_disable_device(hc->pci_dev);
4297                         return -EIO;
4298                 }
4299                 printk(KERN_INFO
4300                     "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4301                     (u_long)hc->plx_membase, hc->plx_origmembase);
4302
4303                 hc->pci_origmembase =  hc->pci_dev->resource[2].start;
4304                     /* MEMBASE 1 is PLX PCI Bridge */
4305                 if (!hc->pci_origmembase) {
4306                         printk(KERN_WARNING
4307                             "HFC-multi: No IO-Memory for PCI card found\n");
4308                         pci_disable_device(hc->pci_dev);
4309                         return -EIO;
4310                 }
4311
4312                 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4313                 if (!hc->pci_membase) {
4314                         printk(KERN_WARNING "HFC-multi: failed to remap io "
4315                             "address space. (internal error)\n");
4316                         pci_disable_device(hc->pci_dev);
4317                         return -EIO;
4318                 }
4319
4320                 printk(KERN_INFO
4321                     "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4322                     "leds-type %d\n",
4323                     hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4324                     hc->pci_dev->irq, HZ, hc->leds);
4325                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4326                 break;
4327         case HFC_IO_MODE_PCIMEM:
4328                 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4329                 if (!hc->pci_origmembase) {
4330                         printk(KERN_WARNING
4331                             "HFC-multi: No IO-Memory for PCI card found\n");
4332                         pci_disable_device(hc->pci_dev);
4333                         return -EIO;
4334                 }
4335
4336                 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4337                 if (!hc->pci_membase) {
4338                         printk(KERN_WARNING
4339                             "HFC-multi: failed to remap io address space. "
4340                             "(internal error)\n");
4341                         pci_disable_device(hc->pci_dev);
4342                         return -EIO;
4343                 }
4344                 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
4345                     "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4346                     hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4347                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4348                 break;
4349         case HFC_IO_MODE_REGIO:
4350                 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4351                 if (!hc->pci_iobase) {
4352                         printk(KERN_WARNING
4353                                 "HFC-multi: No IO for PCI card found\n");
4354                         pci_disable_device(hc->pci_dev);
4355                         return -EIO;
4356                 }
4357
4358                 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4359                         printk(KERN_WARNING "HFC-multi: failed to request "
4360                             "address space at 0x%08lx (internal error)\n",
4361                             hc->pci_iobase);
4362                         pci_disable_device(hc->pci_dev);
4363                         return -EIO;
4364                 }
4365
4366                 printk(KERN_INFO
4367                     "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4368                     m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4369                     hc->pci_dev->irq, HZ, hc->leds);
4370                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4371                 break;
4372         default:
4373                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4374                 pci_disable_device(hc->pci_dev);
4375                 return -EIO;
4376         }
4377
4378         pci_set_drvdata(hc->pci_dev, hc);
4379
4380         /* At this point the needed PCI config is done */
4381         /* fifos are still not enabled */
4382         return 0;
4383 }
4384
4385
4386 /*
4387  * remove port
4388  */
4389
4390 static void
4391 release_port(struct hfc_multi *hc, struct dchannel *dch)
4392 {
4393         int     pt, ci, i = 0;
4394         u_long  flags;
4395         struct bchannel *pb;
4396
4397         ci = dch->slot;
4398         pt = hc->chan[ci].port;
4399
4400         if (debug & DEBUG_HFCMULTI_INIT)
4401                 printk(KERN_DEBUG "%s: entered for port %d\n",
4402                         __func__, pt + 1);
4403
4404         if (pt >= hc->ports) {
4405                 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4406                      __func__, pt + 1);
4407                 return;
4408         }
4409
4410         if (debug & DEBUG_HFCMULTI_INIT)
4411                 printk(KERN_DEBUG "%s: releasing port=%d\n",
4412                     __func__, pt + 1);
4413
4414         if (dch->dev.D.protocol == ISDN_P_TE_S0)
4415                 l1_event(dch->l1, CLOSE_CHANNEL);
4416
4417         hc->chan[ci].dch = NULL;
4418
4419         if (hc->created[pt]) {
4420                 hc->created[pt] = 0;
4421                 mISDN_unregister_device(&dch->dev);
4422         }
4423
4424         spin_lock_irqsave(&hc->lock, flags);
4425
4426         if (dch->timer.function) {
4427                 del_timer(&dch->timer);
4428                 dch->timer.function = NULL;
4429         }
4430
4431         if (hc->type == 1) { /* E1 */
4432                 /* remove sync */
4433                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4434                         hc->syncronized = 0;
4435                         plxsd_checksync(hc, 1);
4436                 }
4437                 /* free channels */
4438                 for (i = 0; i <= 31; i++) {
4439                         if (hc->chan[i].bch) {
4440                                 if (debug & DEBUG_HFCMULTI_INIT)
4441                                         printk(KERN_DEBUG
4442                                             "%s: free port %d channel %d\n",
4443                                             __func__, hc->chan[i].port+1, i);
4444                                 pb = hc->chan[i].bch;
4445                                 hc->chan[i].bch = NULL;
4446                                 spin_unlock_irqrestore(&hc->lock, flags);
4447                                 mISDN_freebchannel(pb);
4448                                 kfree(pb);
4449                                 kfree(hc->chan[i].coeff);
4450                                 spin_lock_irqsave(&hc->lock, flags);
4451                         }
4452                 }
4453         } else {
4454                 /* remove sync */
4455                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4456                         hc->syncronized &=
4457                            ~(1 << hc->chan[ci].port);
4458                         plxsd_checksync(hc, 1);
4459                 }
4460                 /* free channels */
4461                 if (hc->chan[ci - 2].bch) {
4462                         if (debug & DEBUG_HFCMULTI_INIT)
4463                                 printk(KERN_DEBUG
4464                                     "%s: free port %d channel %d\n",
4465                                     __func__, hc->chan[ci - 2].port+1,
4466                                     ci - 2);
4467                         pb = hc->chan[ci - 2].bch;
4468                         hc->chan[ci - 2].bch = NULL;
4469                         spin_unlock_irqrestore(&hc->lock, flags);
4470                         mISDN_freebchannel(pb);
4471                         kfree(pb);
4472                         kfree(hc->chan[ci - 2].coeff);
4473                         spin_lock_irqsave(&hc->lock, flags);
4474                 }
4475                 if (hc->chan[ci - 1].bch) {
4476                         if (debug & DEBUG_HFCMULTI_INIT)
4477                                 printk(KERN_DEBUG
4478                                     "%s: free port %d channel %d\n",
4479                                     __func__, hc->chan[ci - 1].port+1,
4480                                     ci - 1);
4481                         pb = hc->chan[ci - 1].bch;
4482                         hc->chan[ci - 1].bch = NULL;
4483                         spin_unlock_irqrestore(&hc->lock, flags);
4484                         mISDN_freebchannel(pb);
4485                         kfree(pb);
4486                         kfree(hc->chan[ci - 1].coeff);
4487                         spin_lock_irqsave(&hc->lock, flags);
4488                 }
4489         }
4490
4491         spin_unlock_irqrestore(&hc->lock, flags);
4492
4493         if (debug & DEBUG_HFCMULTI_INIT)
4494                 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4495         mISDN_freedchannel(dch);
4496         kfree(dch);
4497
4498         if (debug & DEBUG_HFCMULTI_INIT)
4499                 printk(KERN_DEBUG "%s: done!\n", __func__);
4500 }
4501
4502 static void
4503 release_card(struct hfc_multi *hc)
4504 {
4505         u_long  flags;
4506         int     ch;
4507
4508         if (debug & DEBUG_HFCMULTI_INIT)
4509                 printk(KERN_WARNING "%s: release card (%d) entered\n",
4510                     __func__, hc->id);
4511
4512         /* unregister clock source */
4513         if (hc->iclock)
4514                 mISDN_unregister_clock(hc->iclock);
4515
4516         /* disable irq */
4517         spin_lock_irqsave(&hc->lock, flags);
4518         disable_hwirq(hc);
4519         spin_unlock_irqrestore(&hc->lock, flags);
4520         udelay(1000);
4521
4522         /* dimm leds */
4523         if (hc->leds)
4524                 hfcmulti_leds(hc);
4525
4526         /* disable D-channels & B-channels */
4527         if (debug & DEBUG_HFCMULTI_INIT)
4528                 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4529                     __func__);
4530         for (ch = 0; ch <= 31; ch++) {
4531                 if (hc->chan[ch].dch)
4532                         release_port(hc, hc->chan[ch].dch);
4533         }
4534
4535         /* release hardware & irq */
4536         if (hc->irq) {
4537                 if (debug & DEBUG_HFCMULTI_INIT)
4538                         printk(KERN_WARNING "%s: free irq %d\n",
4539                             __func__, hc->irq);
4540                 free_irq(hc->irq, hc);
4541                 hc->irq = 0;
4542
4543         }
4544         release_io_hfcmulti(hc);
4545
4546         if (debug & DEBUG_HFCMULTI_INIT)
4547                 printk(KERN_WARNING "%s: remove instance from list\n",
4548                      __func__);
4549         list_del(&hc->list);
4550
4551         if (debug & DEBUG_HFCMULTI_INIT)
4552                 printk(KERN_WARNING "%s: delete instance\n", __func__);
4553         if (hc == syncmaster)
4554                 syncmaster = NULL;
4555         kfree(hc);
4556         if (debug & DEBUG_HFCMULTI_INIT)
4557                 printk(KERN_WARNING "%s: card successfully removed\n",
4558                     __func__);
4559 }
4560
4561 static int
4562 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4563 {
4564         struct dchannel *dch;
4565         struct bchannel *bch;
4566         int             ch, ret = 0;
4567         char            name[MISDN_MAX_IDLEN];
4568
4569         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4570         if (!dch)
4571                 return -ENOMEM;
4572         dch->debug = debug;
4573         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4574         dch->hw = hc;
4575         dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4576         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4577             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4578         dch->dev.D.send = handle_dmsg;
4579         dch->dev.D.ctrl = hfcm_dctrl;
4580         dch->dev.nrbchan = (hc->dslot)?30:31;
4581         dch->slot = hc->dslot;
4582         hc->chan[hc->dslot].dch = dch;
4583         hc->chan[hc->dslot].port = 0;
4584         hc->chan[hc->dslot].nt_timer = -1;
4585         for (ch = 1; ch <= 31; ch++) {
4586                 if (ch == hc->dslot) /* skip dchannel */
4587                         continue;
4588                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4589                 if (!bch) {
4590                         printk(KERN_ERR "%s: no memory for bchannel\n",
4591                             __func__);
4592                         ret = -ENOMEM;
4593                         goto free_chan;
4594                 }
4595                 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4596                 if (!hc->chan[ch].coeff) {
4597                         printk(KERN_ERR "%s: no memory for coeffs\n",
4598                             __func__);
4599                         ret = -ENOMEM;
4600                         goto free_chan;
4601                 }
4602                 bch->nr = ch;
4603                 bch->slot = ch;
4604                 bch->debug = debug;
4605                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4606                 bch->hw = hc;
4607                 bch->ch.send = handle_bmsg;
4608                 bch->ch.ctrl = hfcm_bctrl;
4609                 bch->ch.nr = ch;
4610                 list_add(&bch->ch.list, &dch->dev.bchannels);
4611                 hc->chan[ch].bch = bch;
4612                 hc->chan[ch].port = 0;
4613                 set_channelmap(bch->nr, dch->dev.channelmap);
4614         }
4615         /* set optical line type */
4616         if (port[Port_cnt] & 0x001) {
4617                 if (!m->opticalsupport)  {
4618                         printk(KERN_INFO
4619                             "This board has no optical "
4620                             "support\n");
4621                 } else {
4622                         if (debug & DEBUG_HFCMULTI_INIT)
4623                                 printk(KERN_DEBUG
4624                                     "%s: PORT set optical "
4625                                     "interfacs: card(%d) "
4626                                     "port(%d)\n",
4627                                     __func__,
4628                                     HFC_cnt + 1, 1);
4629                         test_and_set_bit(HFC_CFG_OPTICAL,
4630                             &hc->chan[hc->dslot].cfg);
4631                 }
4632         }
4633         /* set LOS report */
4634         if (port[Port_cnt] & 0x004) {
4635                 if (debug & DEBUG_HFCMULTI_INIT)
4636                         printk(KERN_DEBUG "%s: PORT set "
4637                             "LOS report: card(%d) port(%d)\n",
4638                             __func__, HFC_cnt + 1, 1);
4639                 test_and_set_bit(HFC_CFG_REPORT_LOS,
4640                     &hc->chan[hc->dslot].cfg);
4641         }
4642         /* set AIS report */
4643         if (port[Port_cnt] & 0x008) {
4644                 if (debug & DEBUG_HFCMULTI_INIT)
4645                         printk(KERN_DEBUG "%s: PORT set "
4646                             "AIS report: card(%d) port(%d)\n",
4647                             __func__, HFC_cnt + 1, 1);
4648                 test_and_set_bit(HFC_CFG_REPORT_AIS,
4649                     &hc->chan[hc->dslot].cfg);
4650         }
4651         /* set SLIP report */
4652         if (port[Port_cnt] & 0x010) {
4653                 if (debug & DEBUG_HFCMULTI_INIT)
4654                         printk(KERN_DEBUG
4655                             "%s: PORT set SLIP report: "
4656                             "card(%d) port(%d)\n",
4657                             __func__, HFC_cnt + 1, 1);
4658                 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4659                     &hc->chan[hc->dslot].cfg);
4660         }
4661         /* set RDI report */
4662         if (port[Port_cnt] & 0x020) {
4663                 if (debug & DEBUG_HFCMULTI_INIT)
4664                         printk(KERN_DEBUG
4665                             "%s: PORT set RDI report: "
4666                             "card(%d) port(%d)\n",
4667                             __func__, HFC_cnt + 1, 1);
4668                 test_and_set_bit(HFC_CFG_REPORT_RDI,
4669                     &hc->chan[hc->dslot].cfg);
4670         }
4671         /* set CRC-4 Mode */
4672         if (!(port[Port_cnt] & 0x100)) {
4673                 if (debug & DEBUG_HFCMULTI_INIT)
4674                         printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4675                                 " card(%d) port(%d)\n",
4676                                 __func__, HFC_cnt + 1, 1);
4677                 test_and_set_bit(HFC_CFG_CRC4,
4678                     &hc->chan[hc->dslot].cfg);
4679         } else {
4680                 if (debug & DEBUG_HFCMULTI_INIT)
4681                         printk(KERN_DEBUG "%s: PORT turn off CRC4"
4682                                 " report: card(%d) port(%d)\n",
4683                                 __func__, HFC_cnt + 1, 1);
4684         }
4685         /* set forced clock */
4686         if (port[Port_cnt] & 0x0200) {
4687                 if (debug & DEBUG_HFCMULTI_INIT)
4688                         printk(KERN_DEBUG "%s: PORT force getting clock from "
4689                                 "E1: card(%d) port(%d)\n",
4690                                 __func__, HFC_cnt + 1, 1);
4691                 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4692         } else
4693         if (port[Port_cnt] & 0x0400) {
4694                 if (debug & DEBUG_HFCMULTI_INIT)
4695                         printk(KERN_DEBUG "%s: PORT force putting clock to "
4696                                 "E1: card(%d) port(%d)\n",
4697                                 __func__, HFC_cnt + 1, 1);
4698                 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4699         }
4700         /* set JATT PLL */
4701         if (port[Port_cnt] & 0x0800) {
4702                 if (debug & DEBUG_HFCMULTI_INIT)
4703                         printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4704                                 "E1: card(%d) port(%d)\n",
4705                                 __func__, HFC_cnt + 1, 1);
4706                 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4707         }
4708         /* set elastic jitter buffer */
4709         if (port[Port_cnt] & 0x3000) {
4710                 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4711                 if (debug & DEBUG_HFCMULTI_INIT)
4712                         printk(KERN_DEBUG
4713                             "%s: PORT set elastic "
4714                             "buffer to %d: card(%d) port(%d)\n",
4715                             __func__, hc->chan[hc->dslot].jitter,
4716                             HFC_cnt + 1, 1);
4717         } else
4718                 hc->chan[hc->dslot].jitter = 2; /* default */
4719         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4720         ret = mISDN_register_device(&dch->dev, name);
4721         if (ret)
4722                 goto free_chan;
4723         hc->created[0] = 1;
4724         return ret;
4725 free_chan:
4726         release_port(hc, dch);
4727         return ret;
4728 }
4729
4730 static int
4731 init_multi_port(struct hfc_multi *hc, int pt)
4732 {
4733         struct dchannel *dch;
4734         struct bchannel *bch;
4735         int             ch, i, ret = 0;
4736         char            name[MISDN_MAX_IDLEN];
4737
4738         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4739         if (!dch)
4740                 return -ENOMEM;
4741         dch->debug = debug;
4742         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4743         dch->hw = hc;
4744         dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4745         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4746             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4747         dch->dev.D.send = handle_dmsg;
4748         dch->dev.D.ctrl = hfcm_dctrl;
4749         dch->dev.nrbchan = 2;
4750         i = pt << 2;
4751         dch->slot = i + 2;
4752         hc->chan[i + 2].dch = dch;
4753         hc->chan[i + 2].port = pt;
4754         hc->chan[i + 2].nt_timer = -1;
4755         for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4756                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4757                 if (!bch) {
4758                         printk(KERN_ERR "%s: no memory for bchannel\n",
4759                             __func__);
4760                         ret = -ENOMEM;
4761                         goto free_chan;
4762                 }
4763                 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4764                 if (!hc->chan[i + ch].coeff) {
4765                         printk(KERN_ERR "%s: no memory for coeffs\n",
4766                             __func__);
4767                         ret = -ENOMEM;
4768                         goto free_chan;
4769                 }
4770                 bch->nr = ch + 1;
4771                 bch->slot = i + ch;
4772                 bch->debug = debug;
4773                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4774                 bch->hw = hc;
4775                 bch->ch.send = handle_bmsg;
4776                 bch->ch.ctrl = hfcm_bctrl;
4777                 bch->ch.nr = ch + 1;
4778                 list_add(&bch->ch.list, &dch->dev.bchannels);
4779                 hc->chan[i + ch].bch = bch;
4780                 hc->chan[i + ch].port = pt;
4781                 set_channelmap(bch->nr, dch->dev.channelmap);
4782         }
4783         /* set master clock */
4784         if (port[Port_cnt] & 0x001) {
4785                 if (debug & DEBUG_HFCMULTI_INIT)
4786                         printk(KERN_DEBUG
4787                             "%s: PROTOCOL set master clock: "
4788                             "card(%d) port(%d)\n",
4789                             __func__, HFC_cnt + 1, pt + 1);
4790                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4791                         printk(KERN_ERR "Error: Master clock "
4792                             "for port(%d) of card(%d) is only"
4793                             " possible with TE-mode\n",
4794                             pt + 1, HFC_cnt + 1);
4795                         ret = -EINVAL;
4796                         goto free_chan;
4797                 }
4798                 if (hc->masterclk >= 0) {
4799                         printk(KERN_ERR "Error: Master clock "
4800                             "for port(%d) of card(%d) already "
4801                             "defined for port(%d)\n",
4802                             pt + 1, HFC_cnt + 1, hc->masterclk+1);
4803                         ret = -EINVAL;
4804                         goto free_chan;
4805                 }
4806                 hc->masterclk = pt;
4807         }
4808         /* set transmitter line to non capacitive */
4809         if (port[Port_cnt] & 0x002) {
4810                 if (debug & DEBUG_HFCMULTI_INIT)
4811                         printk(KERN_DEBUG
4812                             "%s: PROTOCOL set non capacitive "
4813                             "transmitter: card(%d) port(%d)\n",
4814                             __func__, HFC_cnt + 1, pt + 1);
4815                 test_and_set_bit(HFC_CFG_NONCAP_TX,
4816                     &hc->chan[i + 2].cfg);
4817         }
4818         /* disable E-channel */
4819         if (port[Port_cnt] & 0x004) {
4820         if (debug & DEBUG_HFCMULTI_INIT)
4821                         printk(KERN_DEBUG
4822                             "%s: PROTOCOL disable E-channel: "
4823                             "card(%d) port(%d)\n",
4824                             __func__, HFC_cnt + 1, pt + 1);
4825                 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4826                     &hc->chan[i + 2].cfg);
4827         }
4828         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d/%d",
4829                 hc->type, HFC_cnt + 1, pt + 1);
4830         ret = mISDN_register_device(&dch->dev, name);
4831         if (ret)
4832                 goto free_chan;
4833         hc->created[pt] = 1;
4834         return ret;
4835 free_chan:
4836         release_port(hc, dch);
4837         return ret;
4838 }
4839
4840 static int
4841 hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
4842 {
4843         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4844         int             ret_err = 0;
4845         int             pt;
4846         struct hfc_multi        *hc;
4847         u_long          flags;
4848         u_char          dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4849         int             i;
4850
4851         if (HFC_cnt >= MAX_CARDS) {
4852                 printk(KERN_ERR "too many cards (max=%d).\n",
4853                         MAX_CARDS);
4854                 return -EINVAL;
4855         }
4856         if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4857                 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4858                     "type[%d] %d was supplied as module parameter\n",
4859                     m->vendor_name, m->card_name, m->type, HFC_cnt,
4860                     type[HFC_cnt] & 0xff);
4861                 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4862                         "first, to see cards and their types.");
4863                 return -EINVAL;
4864         }
4865         if (debug & DEBUG_HFCMULTI_INIT)
4866                 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4867                     __func__, m->vendor_name, m->card_name, m->type,
4868                     type[HFC_cnt]);
4869
4870         /* allocate card+fifo structure */
4871         hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4872         if (!hc) {
4873                 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4874                 return -ENOMEM;
4875         }
4876         spin_lock_init(&hc->lock);
4877         hc->mtyp = m;
4878         hc->type =  m->type;
4879         hc->ports = m->ports;
4880         hc->id = HFC_cnt;
4881         hc->pcm = pcm[HFC_cnt];
4882         hc->io_mode = iomode[HFC_cnt];
4883         if (dslot[HFC_cnt] < 0 && hc->type == 1) {
4884                 hc->dslot = 0;
4885                 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
4886                         "31 B-channels\n");
4887         } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32 && hc->type == 1) {
4888                 hc->dslot = dslot[HFC_cnt];
4889                 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
4890                         "time slot %d\n", dslot[HFC_cnt]);
4891         } else
4892                 hc->dslot = 16;
4893
4894         /* set chip specific features */
4895         hc->masterclk = -1;
4896         if (type[HFC_cnt] & 0x100) {
4897                 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
4898                 hc->silence = 0xff; /* ulaw silence */
4899         } else
4900                 hc->silence = 0x2a; /* alaw silence */
4901         if ((poll >> 1) > sizeof(hc->silence_data)) {
4902                 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
4903                         "please fix\n");
4904                 return -EINVAL;
4905         }
4906         for (i = 0; i < (poll >> 1); i++)
4907                 hc->silence_data[i] = hc->silence;
4908
4909         if (!(type[HFC_cnt] & 0x200))
4910                 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4911
4912         if (type[HFC_cnt] & 0x800)
4913                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4914         if (type[HFC_cnt] & 0x1000) {
4915                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4916                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4917         }
4918         if (type[HFC_cnt] & 0x4000)
4919                 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
4920         if (type[HFC_cnt] & 0x8000)
4921                 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
4922         hc->slots = 32;
4923         if (type[HFC_cnt] & 0x10000)
4924                 hc->slots = 64;
4925         if (type[HFC_cnt] & 0x20000)
4926                 hc->slots = 128;
4927         if (type[HFC_cnt] & 0x80000) {
4928                 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
4929                 hc->wdcount = 0;
4930                 hc->wdbyte = V_GPIO_OUT2;
4931                 printk(KERN_NOTICE "Watchdog enabled\n");
4932         }
4933
4934         /* setup pci, hc->slots may change due to PLXSD */
4935         ret_err = setup_pci(hc, pdev, ent);
4936         if (ret_err) {
4937                 if (hc == syncmaster)
4938                         syncmaster = NULL;
4939                 kfree(hc);
4940                 return ret_err;
4941         }
4942
4943         /* crate channels */
4944         for (pt = 0; pt < hc->ports; pt++) {
4945                 if (Port_cnt >= MAX_PORTS) {
4946                         printk(KERN_ERR "too many ports (max=%d).\n",
4947                                 MAX_PORTS);
4948                         ret_err = -EINVAL;
4949                         goto free_card;
4950                 }
4951                 if (hc->type == 1)
4952                         ret_err = init_e1_port(hc, m);
4953                 else
4954                         ret_err = init_multi_port(hc, pt);
4955                 if (debug & DEBUG_HFCMULTI_INIT)
4956                         printk(KERN_DEBUG
4957                             "%s: Registering D-channel, card(%d) port(%d)"
4958                             "result %d\n",
4959                             __func__, HFC_cnt + 1, pt, ret_err);
4960
4961                 if (ret_err) {
4962                         while (pt) { /* release already registered ports */
4963                                 pt--;
4964                                 release_port(hc, hc->chan[(pt << 2) + 2].dch);
4965                         }
4966                         goto free_card;
4967                 }
4968                 Port_cnt++;
4969         }
4970
4971         /* disp switches */
4972         switch (m->dip_type) {
4973         case DIP_4S:
4974                 /*
4975                  * Get DIP setting for beroNet 1S/2S/4S cards
4976                  * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
4977                  * GPI 19/23 (R_GPI_IN2))
4978                  */
4979                 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
4980                         ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
4981                         (~HFC_inb(hc, R_GPI_IN2) & 0x08);
4982
4983                 /* Port mode (TE/NT) jumpers */
4984                 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4)  & 0xf);
4985
4986                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
4987                         pmj = ~pmj & 0xf;
4988
4989                 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
4990                         m->vendor_name, m->card_name, dips, pmj);
4991                 break;
4992         case DIP_8S:
4993                 /*
4994                  * Get DIP Setting for beroNet 8S0+ cards
4995                  * Enable PCI auxbridge function
4996                  */
4997                 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
4998                 /* prepare access to auxport */
4999                 outw(0x4000, hc->pci_iobase + 4);
5000                 /*
5001                  * some dummy reads are required to
5002                  * read valid DIP switch data
5003                  */
5004                 dips = inb(hc->pci_iobase);
5005                 dips = inb(hc->pci_iobase);
5006                 dips = inb(hc->pci_iobase);
5007                 dips = ~inb(hc->pci_iobase) & 0x3F;
5008                 outw(0x0, hc->pci_iobase + 4);
5009                 /* disable PCI auxbridge function */
5010                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5011                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5012                     m->vendor_name, m->card_name, dips);
5013                 break;
5014         case DIP_E1:
5015                 /*
5016                  * get DIP Setting for beroNet E1 cards
5017                  * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5018                  */
5019                 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
5020                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5021                     m->vendor_name, m->card_name, dips);
5022                 break;
5023         }
5024
5025         /* add to list */
5026         spin_lock_irqsave(&HFClock, flags);
5027         list_add_tail(&hc->list, &HFClist);
5028         spin_unlock_irqrestore(&HFClock, flags);
5029
5030         /* use as clock source */
5031         if (clock == HFC_cnt + 1)
5032                 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5033
5034         /* initialize hardware */
5035         ret_err = init_card(hc);
5036         if (ret_err) {
5037                 printk(KERN_ERR "init card returns %d\n", ret_err);
5038                 release_card(hc);
5039                 return ret_err;
5040         }
5041
5042         /* start IRQ and return */
5043         spin_lock_irqsave(&hc->lock, flags);
5044         enable_hwirq(hc);
5045         spin_unlock_irqrestore(&hc->lock, flags);
5046         return 0;
5047
5048 free_card:
5049         release_io_hfcmulti(hc);
5050         if (hc == syncmaster)
5051                 syncmaster = NULL;
5052         kfree(hc);
5053         return ret_err;
5054 }
5055
5056 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5057 {
5058         struct hfc_multi        *card = pci_get_drvdata(pdev);
5059         u_long                  flags;
5060
5061         if (debug)
5062                 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5063                     "device:%x subvendor:%x subdevice:%x\n",
5064                     pdev->vendor, pdev->device,
5065                     pdev->subsystem_vendor, pdev->subsystem_device);
5066
5067         if (card) {
5068                 spin_lock_irqsave(&HFClock, flags);
5069                 release_card(card);
5070                 spin_unlock_irqrestore(&HFClock, flags);
5071         }  else {
5072                 if (debug)
5073                         printk(KERN_WARNING "%s: drvdata allready removed\n",
5074                             __func__);
5075         }
5076 }
5077
5078 #define VENDOR_CCD      "Cologne Chip AG"
5079 #define VENDOR_BN       "beroNet GmbH"
5080 #define VENDOR_DIG      "Digium Inc."
5081 #define VENDOR_JH       "Junghanns.NET GmbH"
5082 #define VENDOR_PRIM     "PrimuX"
5083
5084 static const struct hm_map hfcm_map[] = {
5085 /*0*/   {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
5086 /*1*/   {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0},
5087 /*2*/   {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
5088 /*3*/   {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
5089 /*4*/   {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
5090 /*5*/   {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
5091 /*6*/   {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0},
5092 /*7*/   {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
5093 /*8*/   {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
5094 /*9*/   {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
5095 /*10*/  {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
5096 /*11*/  {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
5097
5098 /*12*/  {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
5099 /*13*/  {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5100                 HFC_IO_MODE_REGIO},
5101 /*14*/  {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
5102 /*15*/  {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
5103
5104 /*16*/  {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
5105 /*17*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5106 /*18*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5107
5108 /*19*/  {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
5109 /*20*/  {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
5110 /*21*/  {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5111 /*22*/  {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5112
5113 /*23*/  {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
5114 /*24*/  {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
5115 /*25*/  {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
5116
5117 /*26*/  {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5118                 HFC_IO_MODE_PLXSD},
5119 /*27*/  {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5120                 HFC_IO_MODE_PLXSD},
5121 /*28*/  {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
5122 /*29*/  {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
5123 /*30*/  {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
5124 };
5125
5126 #undef H
5127 #define H(x)    ((unsigned long)&hfcm_map[x])
5128 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5129
5130         /* Cards with HFC-4S Chip */
5131         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5132                 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5133         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5134                 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5135         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5136                 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5137         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5138                 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5139         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5140                 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5141         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5142                 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5143         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5144                 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5145         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5146                 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5147         { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5148                 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5149         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5150                 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5151         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5152                 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5153         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5154                 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5155         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5156                 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5157         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5158                 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5159
5160         /* Cards with HFC-8S Chip */
5161         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5162         PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5163         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5164         PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5165         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5166         PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5167         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5168         PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5169         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5170                 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST  */
5171         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5172                 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST  */
5173         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5174                 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5175         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5176                 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5177
5178
5179         /* Cards with HFC-E1 Chip */
5180         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5181                 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5182         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5183                 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5184         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5185                 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5186         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5187                 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5188
5189         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5190                 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5191         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5192                 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5193         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5194                 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5195
5196         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5197                 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5198         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5199                 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5200         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5201                 0, 0, 0},
5202         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5203                 0, 0, 0},
5204         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5205                 0, 0, 0},
5206         {0, }
5207 };
5208 #undef H
5209
5210 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5211
5212 static int
5213 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5214 {
5215         struct hm_map   *m = (struct hm_map *)ent->driver_data;
5216         int             ret;
5217
5218         if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5219             ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5220             ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5221             ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5222                 printk(KERN_ERR
5223                     "Unknown HFC multiport controller (vendor:%x device:%x "
5224                     "subvendor:%x subdevice:%x)\n", ent->vendor, ent->device,
5225                     ent->subvendor, ent->subdevice);
5226                 printk(KERN_ERR
5227                     "Please contact the driver maintainer for support.\n");
5228                 return -ENODEV;
5229         }
5230         ret = hfcmulti_init(pdev, ent);
5231         if (ret)
5232                 return ret;
5233         HFC_cnt++;
5234         printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5235         return 0;
5236 }
5237
5238 static struct pci_driver hfcmultipci_driver = {
5239         .name           = "hfc_multi",
5240         .probe          = hfcmulti_probe,
5241         .remove         = __devexit_p(hfc_remove_pci),
5242         .id_table       = hfmultipci_ids,
5243 };
5244
5245 static void __exit
5246 HFCmulti_cleanup(void)
5247 {
5248         struct hfc_multi *card, *next;
5249
5250         /* get rid of all devices of this driver */
5251         list_for_each_entry_safe(card, next, &HFClist, list)
5252                 release_card(card);
5253         pci_unregister_driver(&hfcmultipci_driver);
5254 }
5255
5256 static int __init
5257 HFCmulti_init(void)
5258 {
5259         int err;
5260
5261         printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5262
5263 #ifdef IRQ_DEBUG
5264         printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5265 #endif
5266
5267         spin_lock_init(&HFClock);
5268         spin_lock_init(&plx_lock);
5269
5270         if (debug & DEBUG_HFCMULTI_INIT)
5271                 printk(KERN_DEBUG "%s: init entered\n", __func__);
5272
5273         switch (poll) {
5274         case 0:
5275                 poll_timer = 6;
5276                 poll = 128;
5277                 break;
5278         case 8:
5279                 poll_timer = 2;
5280                 break;
5281         case 16:
5282                 poll_timer = 3;
5283                 break;
5284         case 32:
5285                 poll_timer = 4;
5286                 break;
5287         case 64:
5288                 poll_timer = 5;
5289                 break;
5290         case 128:
5291                 poll_timer = 6;
5292                 break;
5293         case 256:
5294                 poll_timer = 7;
5295                 break;
5296         default:
5297                 printk(KERN_ERR
5298                     "%s: Wrong poll value (%d).\n", __func__, poll);
5299                 err = -EINVAL;
5300                 return err;
5301
5302         }
5303
5304         if (!clock)
5305                 clock = 1;
5306
5307         err = pci_register_driver(&hfcmultipci_driver);
5308         if (err < 0) {
5309                 printk(KERN_ERR "error registering pci driver: %x\n", err);
5310                 return err;
5311         }
5312         return 0;
5313 }
5314
5315
5316 module_init(HFCmulti_init);
5317 module_exit(HFCmulti_cleanup);