SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/isdn/hardware/mISDN/hfcmulti.c

   1 /*
   2  * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
   3  *
   4  * Author       Andreas Eversberg (jolly@eversberg.eu)
   5  * ported to mqueue mechanism:
   6  *              Peter Sprenger (sprengermoving-bytes.de)
   7  *
   8  * inspired by existing hfc-pci driver:
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil (kkeil@suse.de)
  11  * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2, or (at your option)
  16  * any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  * Thanks to Cologne Chip AG for this great controller!
  29  */
  30
  31 /*
  32  * module parameters:
  33  * type:
  34  *      By default (0), the card is automatically detected.
  35  *      Or use the following combinations:
  36  *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
  37  * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
  38  * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
  39  *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
  40  *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
  41  *      Bit 10    = spare
  42  *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
  43  * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
  44  *      Bit 13    = spare
  45  *      Bit 14    = 0x04000 = Use external ram (128K)
  46  *      Bit 15    = 0x08000 = Use external ram (512K)
  47  *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
  48  * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
  49  *      Bit 18    = spare
  50  *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
  51  * (all other bits are reserved and shall be 0)
  52  *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
  53  *               bus (PCM master)
  54  *
  55  * port: (optional or required for all ports on all installed cards)
  56  *      HFC-4S/HFC-8S only bits:
  57  *      Bit 0     = 0x001 = Use master clock for this S/T interface
  58  *                          (ony once per chip).
  59  *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
  60  *                          Don't use this unless you know what you are doing!
  61  *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
  62  *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
  63  *               received from port 1
  64  *
  65  *      HFC-E1 only bits:
  66  *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
  67  *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
  68  *      Bit 2     = 0x0004 = Report LOS
  69  *      Bit 3     = 0x0008 = Report AIS
  70  *      Bit 4     = 0x0010 = Report SLIP
  71  *      Bit 5     = 0x0020 = Report RDI
  72  *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
  73  *                           mode instead.
  74  *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
  75  * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
  76  *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
  77  *                           (E1 only)
  78  *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
  79  *                           for default.
  80  * (all other bits are reserved and shall be 0)
  81  *
  82  * debug:
  83  *      NOTE: only one debug value must be given for all cards
  84  *      enable debugging (see hfc_multi.h for debug options)
  85  *
  86  * poll:
  87  *      NOTE: only one poll value must be given for all cards
  88  *      Give the number of samples for each fifo process.
  89  *      By default 128 is used. Decrease to reduce delay, increase to
  90  *      reduce cpu load. If unsure, don't mess with it!
  91  *      Valid is 8, 16, 32, 64, 128, 256.
  92  *
  93  * pcm:
  94  *      NOTE: only one pcm value must be given for every card.
  95  *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
  96  *      By default (0), the PCM bus id is 100 for the card that is PCM master.
  97  *      If multiple cards are PCM master (because they are not interconnected),
  98  *      each card with PCM master will have increasing PCM id.
  99  *      All PCM busses with the same ID are expected to be connected and have
 100  *      common time slots slots.
 101  *      Only one chip of the PCM bus must be master, the others slave.
 102  *      -1 means no support of PCM bus not even.
 103  *      Omit this value, if all cards are interconnected or none is connected.
 104  *      If unsure, don't give this parameter.
 105  *
 106  * dslot:
 107  *      NOTE: only one poll value must be given for every card.
 108  *      Also this value must be given for non-E1 cards. If omitted, the E1
 109  *      card has D-channel on time slot 16, which is default.
 110  *      If 1..15 or 17..31, an alternate time slot is used for D-channel.
 111  *      In this case, the application must be able to handle this.
 112  *      If -1 is given, the D-channel is disabled and all 31 slots can be used
 113  *      for B-channel. (only for specific applications)
 114  *      If you don't know how to use it, you don't need it!
 115  *
 116  * iomode:
 117  *      NOTE: only one mode value must be given for every card.
 118  *      -> See hfc_multi.h for HFC_IO_MODE_* values
 119  *      By default, the IO mode is pci memory IO (MEMIO).
 120  *      Some cards requre specific IO mode, so it cannot be changed.
 121  *      It may be usefull to set IO mode to register io (REGIO) to solve
 122  *      PCI bridge problems.
 123  *      If unsure, don't give this parameter.
 124  *
 125  * clockdelay_nt:
 126  *      NOTE: only one clockdelay_nt value must be given once for all cards.
 127  *      Give the value of the clock control register (A_ST_CLK_DLY)
 128  *      of the S/T interfaces in NT mode.
 129  *      This register is needed for the TBR3 certification, so don't change it.
 130  *
 131  * clockdelay_te:
 132  *      NOTE: only one clockdelay_te value must be given once
 133  *      Give the value of the clock control register (A_ST_CLK_DLY)
 134  *      of the S/T interfaces in TE mode.
 135  *      This register is needed for the TBR3 certification, so don't change it.
 136  */
 137
 138 /*
 139  * debug register access (never use this, it will flood your system log)
 140  * #define HFC_REGISTER_DEBUG
 141  */
 142
 143 static const char *hfcmulti_revision = "2.02";
 144
 145 #include <linux/module.h>
 146 #include <linux/pci.h>
 147 #include <linux/delay.h>
 148 #include <linux/mISDNhw.h>
 149 #include <linux/mISDNdsp.h>
 150
 151 /*
 152 #define IRQCOUNT_DEBUG
 153 #define IRQ_DEBUG
 154 */
 155
 156 #include "hfc_multi.h"
 157 #ifdef ECHOPREP
 158 #include "gaintab.h"
 159 #endif
 160
 161 #define MAX_CARDS       8
 162 #define MAX_PORTS       (8 * MAX_CARDS)
 163
 164 static LIST_HEAD(HFClist);
 165 static spinlock_t HFClock; /* global hfc list lock */
 166
 167 static void ph_state_change(struct dchannel *);
 168 static void (*hfc_interrupt)(void);
 169 static void (*register_interrupt)(void);
 170 static int (*unregister_interrupt)(void);
 171 static int interrupt_registered;
 172
 173 static struct hfc_multi *syncmaster;
 174 static int plxsd_master; /* if we have a master card (yet) */
 175 static spinlock_t plx_lock; /* may not acquire other lock inside */
 176
 177 #define TYP_E1          1
 178 #define TYP_4S          4
 179 #define TYP_8S          8
 180
 181 static int poll_timer = 6;      /* default = 128 samples = 16ms */
 182 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
 183 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
 184 #define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
 185 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
 186                                    (0x60 MUST be included!) */
 187 static u_char silence = 0xff;   /* silence by LAW */
 188
 189 #define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
 190 #define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
 191 #define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */
 192
 193 /*
 194  * module stuff
 195  */
 196
 197 static uint     type[MAX_CARDS];
 198 static uint     pcm[MAX_CARDS];
 199 static uint     dslot[MAX_CARDS];
 200 static uint     iomode[MAX_CARDS];
 201 static uint     port[MAX_PORTS];
 202 static uint     debug;
 203 static uint     poll;
 204 static uint     timer;
 205 static uint     clockdelay_te = CLKDEL_TE;
 206 static uint     clockdelay_nt = CLKDEL_NT;
 207
 208 static int      HFC_cnt, Port_cnt, PCM_cnt = 99;
 209
 210 MODULE_AUTHOR("Andreas Eversberg");
 211 MODULE_LICENSE("GPL");
 212 module_param(debug, uint, S_IRUGO | S_IWUSR);
 213 module_param(poll, uint, S_IRUGO | S_IWUSR);
 214 module_param(timer, uint, S_IRUGO | S_IWUSR);
 215 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
 216 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
 217 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
 218 module_param_array(pcm, uint, NULL, S_IRUGO | S_IWUSR);
 219 module_param_array(dslot, uint, NULL, S_IRUGO | S_IWUSR);
 220 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
 221 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
 222
 223 #ifdef HFC_REGISTER_DEBUG
 224 #define HFC_outb(hc, reg, val) \
 225         (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
 226 #define HFC_outb_nodebug(hc, reg, val) \
 227         (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
 228 #define HFC_inb(hc, reg) \
 229         (hc->HFC_inb(hc, reg, __func__, __LINE__))
 230 #define HFC_inb_nodebug(hc, reg) \
 231         (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
 232 #define HFC_inw(hc, reg) \
 233         (hc->HFC_inw(hc, reg, __func__, __LINE__))
 234 #define HFC_inw_nodebug(hc, reg) \
 235         (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
 236 #define HFC_wait(hc) \
 237         (hc->HFC_wait(hc, __func__, __LINE__))
 238 #define HFC_wait_nodebug(hc) \
 239         (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
 240 #else
 241 #define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
 242 #define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
 243 #define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
 244 #define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
 245 #define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
 246 #define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
 247 #define HFC_wait(hc)                    (hc->HFC_wait(hc))
 248 #define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
 249 #endif
 250
 251 /* HFC_IO_MODE_PCIMEM */
 252 static void
 253 #ifdef HFC_REGISTER_DEBUG
 254 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
 255                 const char *function, int line)
 256 #else
 257 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
 258 #endif
 259 {
 260         writeb(val, (hc->pci_membase)+reg);
 261 }
 262 static u_char
 263 #ifdef HFC_REGISTER_DEBUG
 264 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 265 #else
 266 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
 267 #endif
 268 {
 269         return readb((hc->pci_membase)+reg);
 270 }
 271 static u_short
 272 #ifdef HFC_REGISTER_DEBUG
 273 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 274 #else
 275 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
 276 #endif
 277 {
 278         return readw((hc->pci_membase)+reg);
 279 }
 280 static void
 281 #ifdef HFC_REGISTER_DEBUG
 282 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
 283 #else
 284 HFC_wait_pcimem(struct hfc_multi *hc)
 285 #endif
 286 {
 287         while (readb((hc->pci_membase)+R_STATUS) & V_BUSY);
 288 }
 289
 290 /* HFC_IO_MODE_REGIO */
 291 static void
 292 #ifdef HFC_REGISTER_DEBUG
 293 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
 294         const char *function, int line)
 295 #else
 296 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
 297 #endif
 298 {
 299         outb(reg, (hc->pci_iobase)+4);
 300         outb(val, hc->pci_iobase);
 301 }
 302 static u_char
 303 #ifdef HFC_REGISTER_DEBUG
 304 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 305 #else
 306 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
 307 #endif
 308 {
 309         outb(reg, (hc->pci_iobase)+4);
 310         return inb(hc->pci_iobase);
 311 }
 312 static u_short
 313 #ifdef HFC_REGISTER_DEBUG
 314 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 315 #else
 316 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
 317 #endif
 318 {
 319         outb(reg, (hc->pci_iobase)+4);
 320         return inw(hc->pci_iobase);
 321 }
 322 static void
 323 #ifdef HFC_REGISTER_DEBUG
 324 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
 325 #else
 326 HFC_wait_regio(struct hfc_multi *hc)
 327 #endif
 328 {
 329         outb(R_STATUS, (hc->pci_iobase)+4);
 330         while (inb(hc->pci_iobase) & V_BUSY);
 331 }
 332
 333 #ifdef HFC_REGISTER_DEBUG
 334 static void
 335 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
 336                 const char *function, int line)
 337 {
 338         char regname[256] = "", bits[9] = "xxxxxxxx";
 339         int i;
 340
 341         i = -1;
 342         while (hfc_register_names[++i].name) {
 343                 if (hfc_register_names[i].reg == reg)
 344                         strcat(regname, hfc_register_names[i].name);
 345         }
 346         if (regname[0] == '\0')
 347                 strcpy(regname, "register");
 348
 349         bits[7] = '0'+(!!(val&1));
 350         bits[6] = '0'+(!!(val&2));
 351         bits[5] = '0'+(!!(val&4));
 352         bits[4] = '0'+(!!(val&8));
 353         bits[3] = '0'+(!!(val&16));
 354         bits[2] = '0'+(!!(val&32));
 355         bits[1] = '0'+(!!(val&64));
 356         bits[0] = '0'+(!!(val&128));
 357         printk(KERN_DEBUG
 358             "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
 359             hc->id, reg, regname, val, bits, function, line);
 360         HFC_outb_nodebug(hc, reg, val);
 361 }
 362 static u_char
 363 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 364 {
 365         char regname[256] = "", bits[9] = "xxxxxxxx";
 366         u_char val = HFC_inb_nodebug(hc, reg);
 367         int i;
 368
 369         i = 0;
 370         while (hfc_register_names[i++].name)
 371                 ;
 372         while (hfc_register_names[++i].name) {
 373                 if (hfc_register_names[i].reg == reg)
 374                         strcat(regname, hfc_register_names[i].name);
 375         }
 376         if (regname[0] == '\0')
 377                 strcpy(regname, "register");
 378
 379         bits[7] = '0'+(!!(val&1));
 380         bits[6] = '0'+(!!(val&2));
 381         bits[5] = '0'+(!!(val&4));
 382         bits[4] = '0'+(!!(val&8));
 383         bits[3] = '0'+(!!(val&16));
 384         bits[2] = '0'+(!!(val&32));
 385         bits[1] = '0'+(!!(val&64));
 386         bits[0] = '0'+(!!(val&128));
 387         printk(KERN_DEBUG
 388             "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
 389             hc->id, reg, regname, val, bits, function, line);
 390         return val;
 391 }
 392 static u_short
 393 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 394 {
 395         char regname[256] = "";
 396         u_short val = HFC_inw_nodebug(hc, reg);
 397         int i;
 398
 399         i = 0;
 400         while (hfc_register_names[i++].name)
 401                 ;
 402         while (hfc_register_names[++i].name) {
 403                 if (hfc_register_names[i].reg == reg)
 404                         strcat(regname, hfc_register_names[i].name);
 405         }
 406         if (regname[0] == '\0')
 407                 strcpy(regname, "register");
 408
 409         printk(KERN_DEBUG
 410             "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
 411             hc->id, reg, regname, val, function, line);
 412         return val;
 413 }
 414 static void
 415 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
 416 {
 417         printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
 418             hc->id, function, line);
 419         HFC_wait_nodebug(hc);
 420 }
 421 #endif
 422
 423 /* write fifo data (REGIO) */
 424 static void
 425 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 426 {
 427         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 428         while (len>>2) {
 429                 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
 430                 data += 4;
 431                 len -= 4;
 432         }
 433         while (len>>1) {
 434                 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
 435                 data += 2;
 436                 len -= 2;
 437         }
 438         while (len) {
 439                 outb(*data, hc->pci_iobase);
 440                 data++;
 441                 len--;
 442         }
 443 }
 444 /* write fifo data (PCIMEM) */
 445 static void
 446 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 447 {
 448         while (len>>2) {
 449                 writel(cpu_to_le32(*(u32 *)data),
 450                         hc->pci_membase + A_FIFO_DATA0);
 451                 data += 4;
 452                 len -= 4;
 453         }
 454         while (len>>1) {
 455                 writew(cpu_to_le16(*(u16 *)data),
 456                         hc->pci_membase + A_FIFO_DATA0);
 457                 data += 2;
 458                 len -= 2;
 459         }
 460         while (len) {
 461                 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
 462                 data++;
 463                 len--;
 464         }
 465 }
 466 /* read fifo data (REGIO) */
 467 static void
 468 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 469 {
 470         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 471         while (len>>2) {
 472                 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
 473                 data += 4;
 474                 len -= 4;
 475         }
 476         while (len>>1) {
 477                 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
 478                 data += 2;
 479                 len -= 2;
 480         }
 481         while (len) {
 482                 *data = inb(hc->pci_iobase);
 483                 data++;
 484                 len--;
 485         }
 486 }
 487
 488 /* read fifo data (PCIMEM) */
 489 static void
 490 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 491 {
 492         while (len>>2) {
 493                 *(u32 *)data =
 494                         le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
 495                 data += 4;
 496                 len -= 4;
 497         }
 498         while (len>>1) {
 499                 *(u16 *)data =
 500                         le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
 501                 data += 2;
 502                 len -= 2;
 503         }
 504         while (len) {
 505                 *data = readb(hc->pci_membase + A_FIFO_DATA0);
 506                 data++;
 507                 len--;
 508         }
 509 }
 510
 511
 512 static void
 513 enable_hwirq(struct hfc_multi *hc)
 514 {
 515         hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
 516         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 517 }
 518
 519 static void
 520 disable_hwirq(struct hfc_multi *hc)
 521 {
 522         hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
 523         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 524 }
 525
 526 #define NUM_EC 2
 527 #define MAX_TDM_CHAN 32
 528
 529
 530 inline void
 531 enablepcibridge(struct hfc_multi *c)
 532 {
 533         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
 534 }
 535
 536 inline void
 537 disablepcibridge(struct hfc_multi *c)
 538 {
 539         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
 540 }
 541
 542 inline unsigned char
 543 readpcibridge(struct hfc_multi *hc, unsigned char address)
 544 {
 545         unsigned short cipv;
 546         unsigned char data;
 547
 548         if (!hc->pci_iobase)
 549                 return 0;
 550
 551         /* slow down a PCI read access by 1 PCI clock cycle */
 552         HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
 553
 554         if (address == 0)
 555                 cipv = 0x4000;
 556         else
 557                 cipv = 0x5800;
 558
 559         /* select local bridge port address by writing to CIP port */
 560         /* data = HFC_inb(c, cipv); * was _io before */
 561         outw(cipv, hc->pci_iobase + 4);
 562         data = inb(hc->pci_iobase);
 563
 564         /* restore R_CTRL for normal PCI read cycle speed */
 565         HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
 566
 567         return data;
 568 }
 569
 570 inline void
 571 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
 572 {
 573         unsigned short cipv;
 574         unsigned int datav;
 575
 576         if (!hc->pci_iobase)
 577                 return;
 578
 579         if (address == 0)
 580                 cipv = 0x4000;
 581         else
 582                 cipv = 0x5800;
 583
 584         /* select local bridge port address by writing to CIP port */
 585         outw(cipv, hc->pci_iobase + 4);
 586         /* define a 32 bit dword with 4 identical bytes for write sequence */
 587         datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
 588             ((__u32) data << 24);
 589
 590         /*
 591          * write this 32 bit dword to the bridge data port
 592          * this will initiate a write sequence of up to 4 writes to the same
 593          * address on the local bus interface the number of write accesses
 594          * is undefined but >=1 and depends on the next PCI transaction
 595          * during write sequence on the local bus
 596          */
 597         outl(datav, hc->pci_iobase);
 598 }
 599
 600 inline void
 601 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
 602 {
 603         /* Do data pin read low byte */
 604         HFC_outb(hc, R_GPIO_OUT1, reg);
 605 }
 606
 607 inline void
 608 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
 609 {
 610         cpld_set_reg(hc, reg);
 611
 612         enablepcibridge(hc);
 613         writepcibridge(hc, 1, val);
 614         disablepcibridge(hc);
 615
 616         return;
 617 }
 618
 619 inline unsigned char
 620 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
 621 {
 622         unsigned char bytein;
 623
 624         cpld_set_reg(hc, reg);
 625
 626         /* Do data pin read low byte */
 627         HFC_outb(hc, R_GPIO_OUT1, reg);
 628
 629         enablepcibridge(hc);
 630         bytein = readpcibridge(hc, 1);
 631         disablepcibridge(hc);
 632
 633         return bytein;
 634 }
 635
 636 inline void
 637 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
 638 {
 639         cpld_write_reg(hc, 0, 0xff & addr);
 640         cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
 641 }
 642
 643 inline unsigned short
 644 vpm_read_address(struct hfc_multi *c)
 645 {
 646         unsigned short addr;
 647         unsigned short highbit;
 648
 649         addr = cpld_read_reg(c, 0);
 650         highbit = cpld_read_reg(c, 1);
 651
 652         addr = addr | (highbit << 8);
 653
 654         return addr & 0x1ff;
 655 }
 656
 657 inline unsigned char
 658 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
 659 {
 660         unsigned char res;
 661
 662         vpm_write_address(c, addr);
 663
 664         if (!which)
 665                 cpld_set_reg(c, 2);
 666         else
 667                 cpld_set_reg(c, 3);
 668
 669         enablepcibridge(c);
 670         res = readpcibridge(c, 1);
 671         disablepcibridge(c);
 672
 673         cpld_set_reg(c, 0);
 674
 675         return res;
 676 }
 677
 678 inline void
 679 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
 680     unsigned char data)
 681 {
 682         vpm_write_address(c, addr);
 683
 684         enablepcibridge(c);
 685
 686         if (!which)
 687                 cpld_set_reg(c, 2);
 688         else
 689                 cpld_set_reg(c, 3);
 690
 691         writepcibridge(c, 1, data);
 692
 693         cpld_set_reg(c, 0);
 694
 695         disablepcibridge(c);
 696
 697         {
 698         unsigned char regin;
 699         regin = vpm_in(c, which, addr);
 700         if (regin != data)
 701                 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
 702                         "0x%x\n", data, addr, regin);
 703         }
 704
 705 }
 706
 707
 708 static void
 709 vpm_init(struct hfc_multi *wc)
 710 {
 711         unsigned char reg;
 712         unsigned int mask;
 713         unsigned int i, x, y;
 714         unsigned int ver;
 715
 716         for (x = 0; x < NUM_EC; x++) {
 717                 /* Setup GPIO's */
 718                 if (!x) {
 719                         ver = vpm_in(wc, x, 0x1a0);
 720                         printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
 721                 }
 722
 723                 for (y = 0; y < 4; y++) {
 724                         vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
 725                         vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
 726                         vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
 727                 }
 728
 729                 /* Setup TDM path - sets fsync and tdm_clk as inputs */
 730                 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
 731                 vpm_out(wc, x, 0x1a3, reg & ~2);
 732
 733                 /* Setup Echo length (256 taps) */
 734                 vpm_out(wc, x, 0x022, 1);
 735                 vpm_out(wc, x, 0x023, 0xff);
 736
 737                 /* Setup timeslots */
 738                 vpm_out(wc, x, 0x02f, 0x00);
 739                 mask = 0x02020202 << (x * 4);
 740
 741                 /* Setup the tdm channel masks for all chips */
 742                 for (i = 0; i < 4; i++)
 743                         vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
 744
 745                 /* Setup convergence rate */
 746                 printk(KERN_DEBUG "VPM: A-law mode\n");
 747                 reg = 0x00 | 0x10 | 0x01;
 748                 vpm_out(wc, x, 0x20, reg);
 749                 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
 750                 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
 751
 752                 vpm_out(wc, x, 0x24, 0x02);
 753                 reg = vpm_in(wc, x, 0x24);
 754                 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
 755
 756                 /* Initialize echo cans */
 757                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 758                         if (mask & (0x00000001 << i))
 759                                 vpm_out(wc, x, i, 0x00);
 760                 }
 761
 762                 /*
 763                  * ARM arch at least disallows a udelay of
 764                  * more than 2ms... it gives a fake "__bad_udelay"
 765                  * reference at link-time.
 766                  * long delays in kernel code are pretty sucky anyway
 767                  * for now work around it using 5 x 2ms instead of 1 x 10ms
 768                  */
 769
 770                 udelay(2000);
 771                 udelay(2000);
 772                 udelay(2000);
 773                 udelay(2000);
 774                 udelay(2000);
 775
 776                 /* Put in bypass mode */
 777                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 778                         if (mask & (0x00000001 << i))
 779                                 vpm_out(wc, x, i, 0x01);
 780                 }
 781
 782                 /* Enable bypass */
 783                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 784                         if (mask & (0x00000001 << i))
 785                                 vpm_out(wc, x, 0x78 + i, 0x01);
 786                 }
 787
 788         }
 789 }
 790
 791 #ifdef UNUSED
 792 static void
 793 vpm_check(struct hfc_multi *hctmp)
 794 {
 795         unsigned char gpi2;
 796
 797         gpi2 = HFC_inb(hctmp, R_GPI_IN2);
 798
 799         if ((gpi2 & 0x3) != 0x3)
 800                 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
 801 }
 802 #endif /* UNUSED */
 803
 804
 805 /*
 806  * Interface to enable/disable the HW Echocan
 807  *
 808  * these functions are called within a spin_lock_irqsave on
 809  * the channel instance lock, so we are not disturbed by irqs
 810  *
 811  * we can later easily change the interface to make  other
 812  * things configurable, for now we configure the taps
 813  *
 814  */
 815
 816 static void
 817 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
 818 {
 819         unsigned int timeslot;
 820         unsigned int unit;
 821         struct bchannel *bch = hc->chan[ch].bch;
 822 #ifdef TXADJ
 823         int txadj = -4;
 824         struct sk_buff *skb;
 825 #endif
 826         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 827                 return;
 828
 829         if (!bch)
 830                 return;
 831
 832 #ifdef TXADJ
 833         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 834                 sizeof(int), &txadj, GFP_ATOMIC);
 835         if (skb)
 836                 recv_Bchannel_skb(bch, skb);
 837 #endif
 838
 839         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 840         unit = ch % 4;
 841
 842         printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
 843             taps, timeslot);
 844
 845         vpm_out(hc, unit, timeslot, 0x7e);
 846 }
 847
 848 static void
 849 vpm_echocan_off(struct hfc_multi *hc, int ch)
 850 {
 851         unsigned int timeslot;
 852         unsigned int unit;
 853         struct bchannel *bch = hc->chan[ch].bch;
 854 #ifdef TXADJ
 855         int txadj = 0;
 856         struct sk_buff *skb;
 857 #endif
 858
 859         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 860                 return;
 861
 862         if (!bch)
 863                 return;
 864
 865 #ifdef TXADJ
 866         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 867                 sizeof(int), &txadj, GFP_ATOMIC);
 868         if (skb)
 869                 recv_Bchannel_skb(bch, skb);
 870 #endif
 871
 872         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 873         unit = ch % 4;
 874
 875         printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
 876             timeslot);
 877         /* FILLME */
 878         vpm_out(hc, unit, timeslot, 0x01);
 879 }
 880
 881
 882 /*
 883  * Speech Design resync feature
 884  * NOTE: This is called sometimes outside interrupt handler.
 885  * We must lock irqsave, so no other interrupt (other card) will occurr!
 886  * Also multiple interrupts may nest, so must lock each access (lists, card)!
 887  */
 888 static inline void
 889 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
 890 {
 891         struct hfc_multi *hc, *next, *pcmmaster = NULL;
 892         u_int *plx_acc_32, pv;
 893         u_long flags;
 894
 895         spin_lock_irqsave(&HFClock, flags);
 896         spin_lock(&plx_lock); /* must be locked inside other locks */
 897
 898         if (debug & DEBUG_HFCMULTI_PLXSD)
 899                 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
 900                         __func__, syncmaster);
 901
 902         /* select new master */
 903         if (newmaster) {
 904                 if (debug & DEBUG_HFCMULTI_PLXSD)
 905                         printk(KERN_DEBUG "using provided controller\n");
 906         } else {
 907                 list_for_each_entry_safe(hc, next, &HFClist, list) {
 908                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 909                                 if (hc->syncronized) {
 910                                         newmaster = hc;
 911                                         break;
 912                                 }
 913                         }
 914                 }
 915         }
 916
 917         /* Disable sync of all cards */
 918         list_for_each_entry_safe(hc, next, &HFClist, list) {
 919                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 920                         plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
 921                         pv = readl(plx_acc_32);
 922                         pv &= ~PLX_SYNC_O_EN;
 923                         writel(pv, plx_acc_32);
 924                         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
 925                                 pcmmaster = hc;
 926                                 if (hc->type == 1) {
 927                                         if (debug & DEBUG_HFCMULTI_PLXSD)
 928                                                 printk(KERN_DEBUG
 929                                                         "Schedule SYNC_I\n");
 930                                         hc->e1_resync |= 1; /* get SYNC_I */
 931                                 }
 932                         }
 933                 }
 934         }
 935
 936         if (newmaster) {
 937                 hc = newmaster;
 938                 if (debug & DEBUG_HFCMULTI_PLXSD)
 939                         printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
 940                                 "interface.\n", hc->id, hc);
 941                 /* Enable new sync master */
 942                 plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
 943                 pv = readl(plx_acc_32);
 944                 pv |= PLX_SYNC_O_EN;
 945                 writel(pv, plx_acc_32);
 946                 /* switch to jatt PLL, if not disabled by RX_SYNC */
 947                 if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
 948                         if (debug & DEBUG_HFCMULTI_PLXSD)
 949                                 printk(KERN_DEBUG "Schedule jatt PLL\n");
 950                         hc->e1_resync |= 2; /* switch to jatt */
 951                 }
 952         } else {
 953                 if (pcmmaster) {
 954                         hc = pcmmaster;
 955                         if (debug & DEBUG_HFCMULTI_PLXSD)
 956                                 printk(KERN_DEBUG
 957                                         "id=%d (0x%p) = PCM master syncronized "
 958                                         "with QUARTZ\n", hc->id, hc);
 959                         if (hc->type == 1) {
 960                                 /* Use the crystal clock for the PCM
 961                                    master card */
 962                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 963                                         printk(KERN_DEBUG
 964                                             "Schedule QUARTZ for HFC-E1\n");
 965                                 hc->e1_resync |= 4; /* switch quartz */
 966                         } else {
 967                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 968                                         printk(KERN_DEBUG
 969                                             "QUARTZ is automatically "
 970                                             "enabled by HFC-%dS\n", hc->type);
 971                         }
 972                         plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
 973                         pv = readl(plx_acc_32);
 974                         pv |= PLX_SYNC_O_EN;
 975                         writel(pv, plx_acc_32);
 976                 } else
 977                         if (!rm)
 978                                 printk(KERN_ERR "%s no pcm master, this MUST "
 979                                         "not happen!\n", __func__);
 980         }
 981         syncmaster = newmaster;
 982
 983         spin_unlock(&plx_lock);
 984         spin_unlock_irqrestore(&HFClock, flags);
 985 }
 986
 987 /* This must be called AND hc must be locked irqsave!!! */
 988 inline void
 989 plxsd_checksync(struct hfc_multi *hc, int rm)
 990 {
 991         if (hc->syncronized) {
 992                 if (syncmaster == NULL) {
 993                         if (debug & DEBUG_HFCMULTI_PLXSD)
 994                                 printk(KERN_WARNING "%s: GOT sync on card %d"
 995                                         " (id=%d)\n", __func__, hc->id + 1,
 996                                         hc->id);
 997                         hfcmulti_resync(hc, hc, rm);
 998                 }
 999         } else {
1000                 if (syncmaster == hc) {
1001                         if (debug & DEBUG_HFCMULTI_PLXSD)
1002                                 printk(KERN_WARNING "%s: LOST sync on card %d"
1003                                         " (id=%d)\n", __func__, hc->id + 1,
1004                                         hc->id);
1005                         hfcmulti_resync(hc, NULL, rm);
1006                 }
1007         }
1008 }
1009
1010
1011 /*
1012  * free hardware resources used by driver
1013  */
1014 static void
1015 release_io_hfcmulti(struct hfc_multi *hc)
1016 {
1017         u_int   *plx_acc_32, pv;
1018         u_long  plx_flags;
1019
1020         if (debug & DEBUG_HFCMULTI_INIT)
1021                 printk(KERN_DEBUG "%s: entered\n", __func__);
1022
1023         /* soft reset also masks all interrupts */
1024         hc->hw.r_cirm |= V_SRES;
1025         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1026         udelay(1000);
1027         hc->hw.r_cirm &= ~V_SRES;
1028         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1029         udelay(1000); /* instead of 'wait' that may cause locking */
1030
1031         /* release Speech Design card, if PLX was initialized */
1032         if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1033                 if (debug & DEBUG_HFCMULTI_PLXSD)
1034                         printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1035                             __func__, hc->id + 1);
1036                 spin_lock_irqsave(&plx_lock, plx_flags);
1037                 plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
1038                 writel(PLX_GPIOC_INIT, plx_acc_32);
1039                 pv = readl(plx_acc_32);
1040                 /* Termination off */
1041                 pv &= ~PLX_TERM_ON;
1042                 /* Disconnect the PCM */
1043                 pv |= PLX_SLAVE_EN_N;
1044                 pv &= ~PLX_MASTER_EN;
1045                 pv &= ~PLX_SYNC_O_EN;
1046                 /* Put the DSP in Reset */
1047                 pv &= ~PLX_DSP_RES_N;
1048                 writel(pv, plx_acc_32);
1049                 if (debug & DEBUG_HFCMULTI_INIT)
1050                         printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n",
1051                                 __func__, pv);
1052                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1053         }
1054
1055         /* disable memory mapped ports / io ports */
1056         test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1057         pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1058         if (hc->pci_membase)
1059                 iounmap((void *)hc->pci_membase);
1060         if (hc->plx_membase)
1061                 iounmap((void *)hc->plx_membase);
1062         if (hc->pci_iobase)
1063                 release_region(hc->pci_iobase, 8);
1064
1065         if (hc->pci_dev) {
1066                 pci_disable_device(hc->pci_dev);
1067                 pci_set_drvdata(hc->pci_dev, NULL);
1068         }
1069         if (debug & DEBUG_HFCMULTI_INIT)
1070                 printk(KERN_DEBUG "%s: done\n", __func__);
1071 }
1072
1073 /*
1074  * function called to reset the HFC chip. A complete software reset of chip
1075  * and fifos is done. All configuration of the chip is done.
1076  */
1077
1078 static int
1079 init_chip(struct hfc_multi *hc)
1080 {
1081         u_long                  flags, val, val2 = 0, rev;
1082         int                     i, err = 0;
1083         u_char                  r_conf_en, rval;
1084         u_int                   *plx_acc_32, pv;
1085         u_long                  plx_flags, hfc_flags;
1086         int                     plx_count;
1087         struct hfc_multi        *pos, *next, *plx_last_hc;
1088
1089         spin_lock_irqsave(&hc->lock, flags);
1090         /* reset all registers */
1091         memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1092
1093         /* revision check */
1094         if (debug & DEBUG_HFCMULTI_INIT)
1095                 printk(KERN_DEBUG "%s: entered\n", __func__);
1096         val = HFC_inb(hc, R_CHIP_ID)>>4;
1097         if (val != 0x8 && val != 0xc && val != 0xe) {
1098                 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1099                 err = -EIO;
1100                 goto out;
1101         }
1102         rev = HFC_inb(hc, R_CHIP_RV);
1103         printk(KERN_INFO
1104             "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1105             val, rev, (rev == 0) ? " (old FIFO handling)" : "");
1106         if (rev == 0) {
1107                 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1108                 printk(KERN_WARNING
1109                     "HFC_multi: NOTE: Your chip is revision 0, "
1110                     "ask Cologne Chip for update. Newer chips "
1111                     "have a better FIFO handling. Old chips "
1112                     "still work but may have slightly lower "
1113                     "HDLC transmit performance.\n");
1114         }
1115         if (rev > 1) {
1116                 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1117                     "consider chip revision = %ld. The chip / "
1118                     "bridge may not work.\n", rev);
1119         }
1120
1121         /* set s-ram size */
1122         hc->Flen = 0x10;
1123         hc->Zmin = 0x80;
1124         hc->Zlen = 384;
1125         hc->DTMFbase = 0x1000;
1126         if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1127                 if (debug & DEBUG_HFCMULTI_INIT)
1128                         printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1129                             __func__);
1130                 hc->hw.r_ctrl |= V_EXT_RAM;
1131                 hc->hw.r_ram_sz = 1;
1132                 hc->Flen = 0x20;
1133                 hc->Zmin = 0xc0;
1134                 hc->Zlen = 1856;
1135                 hc->DTMFbase = 0x2000;
1136         }
1137         if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1138                 if (debug & DEBUG_HFCMULTI_INIT)
1139                         printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1140                             __func__);
1141                 hc->hw.r_ctrl |= V_EXT_RAM;
1142                 hc->hw.r_ram_sz = 2;
1143                 hc->Flen = 0x20;
1144                 hc->Zmin = 0xc0;
1145                 hc->Zlen = 8000;
1146                 hc->DTMFbase = 0x2000;
1147         }
1148         hc->max_trans = poll << 1;
1149         if (hc->max_trans > hc->Zlen)
1150                 hc->max_trans = hc->Zlen;
1151
1152         /* Speech Design PLX bridge */
1153         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1154                 if (debug & DEBUG_HFCMULTI_PLXSD)
1155                         printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1156                             __func__, hc->id + 1);
1157                 spin_lock_irqsave(&plx_lock, plx_flags);
1158                 plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
1159                 writel(PLX_GPIOC_INIT, plx_acc_32);
1160                 pv = readl(plx_acc_32);
1161                 /* The first and the last cards are terminating the PCM bus */
1162                 pv |= PLX_TERM_ON; /* hc is currently the last */
1163                 /* Disconnect the PCM */
1164                 pv |= PLX_SLAVE_EN_N;
1165                 pv &= ~PLX_MASTER_EN;
1166                 pv &= ~PLX_SYNC_O_EN;
1167                 /* Put the DSP in Reset */
1168                 pv &= ~PLX_DSP_RES_N;
1169                 writel(pv, plx_acc_32);
1170                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1171                 if (debug & DEBUG_HFCMULTI_INIT)
1172                         printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n",
1173                                 __func__, pv);
1174                 /*
1175                  * If we are the 3rd PLXSD card or higher, we must turn
1176                  * termination of last PLXSD card off.
1177                  */
1178                 spin_lock_irqsave(&HFClock, hfc_flags);
1179                 plx_count = 0;
1180                 plx_last_hc = NULL;
1181                 list_for_each_entry_safe(pos, next, &HFClist, list) {
1182                         if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1183                                 plx_count++;
1184                                 if (pos != hc)
1185                                         plx_last_hc = pos;
1186                         }
1187                 }
1188                 if (plx_count >= 3) {
1189                         if (debug & DEBUG_HFCMULTI_PLXSD)
1190                                 printk(KERN_DEBUG "%s: card %d is between, so "
1191                                         "we disable termination\n",
1192                                     __func__, plx_last_hc->id + 1);
1193                         spin_lock_irqsave(&plx_lock, plx_flags);
1194                         plx_acc_32 = (u_int *)(plx_last_hc->plx_membase
1195                                         + PLX_GPIOC);
1196                         pv = readl(plx_acc_32);
1197                         pv &= ~PLX_TERM_ON;
1198                         writel(pv, plx_acc_32);
1199                         spin_unlock_irqrestore(&plx_lock, plx_flags);
1200                         if (debug & DEBUG_HFCMULTI_INIT)
1201                             printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n",
1202                                         __func__, pv);
1203                 }
1204                 spin_unlock_irqrestore(&HFClock, hfc_flags);
1205                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1206         }
1207
1208         /* we only want the real Z2 read-pointer for revision > 0 */
1209         if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1210                 hc->hw.r_ram_sz |= V_FZ_MD;
1211
1212         /* select pcm mode */
1213         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1214                 if (debug & DEBUG_HFCMULTI_INIT)
1215                         printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1216                             __func__);
1217         } else
1218         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1219                 if (debug & DEBUG_HFCMULTI_INIT)
1220                         printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1221                             __func__);
1222                 hc->hw.r_pcm_md0 |= V_PCM_MD;
1223         } else {
1224                 if (debug & DEBUG_HFCMULTI_INIT)
1225                         printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1226                             __func__);
1227         }
1228
1229         /* soft reset */
1230         HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1231         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1232         HFC_outb(hc, R_FIFO_MD, 0);
1233         hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
1234         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1235         udelay(100);
1236         hc->hw.r_cirm = 0;
1237         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1238         udelay(100);
1239         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1240
1241         /* Speech Design PLX bridge pcm and sync mode */
1242         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1243                 spin_lock_irqsave(&plx_lock, plx_flags);
1244                 plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
1245                 pv = readl(plx_acc_32);
1246                 /* Connect PCM */
1247                 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1248                         pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1249                         pv |= PLX_SYNC_O_EN;
1250                         if (debug & DEBUG_HFCMULTI_INIT)
1251                                 printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n",
1252                                         __func__, pv);
1253                 } else {
1254                         pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1255                         pv &= ~PLX_SYNC_O_EN;
1256                         if (debug & DEBUG_HFCMULTI_INIT)
1257                                 printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n",
1258                                         __func__, pv);
1259                 }
1260                 writel(pv, plx_acc_32);
1261                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1262         }
1263
1264         /* PCM setup */
1265         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1266         if (hc->slots == 32)
1267                 HFC_outb(hc, R_PCM_MD1, 0x00);
1268         if (hc->slots == 64)
1269                 HFC_outb(hc, R_PCM_MD1, 0x10);
1270         if (hc->slots == 128)
1271                 HFC_outb(hc, R_PCM_MD1, 0x20);
1272         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1273         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1274                 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1275         else
1276                 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1277         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1278         for (i = 0; i < 256; i++) {
1279                 HFC_outb_nodebug(hc, R_SLOT, i);
1280                 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1281                 HFC_outb_nodebug(hc, A_CONF, 0);
1282                 hc->slot_owner[i] = -1;
1283         }
1284
1285         /* set clock speed */
1286         if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1287                 if (debug & DEBUG_HFCMULTI_INIT)
1288                         printk(KERN_DEBUG
1289                             "%s: setting double clock\n", __func__);
1290                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1291         }
1292
1293         /* B410P GPIO */
1294         if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1295                 printk(KERN_NOTICE "Setting GPIOs\n");
1296                 HFC_outb(hc, R_GPIO_SEL, 0x30);
1297                 HFC_outb(hc, R_GPIO_EN1, 0x3);
1298                 udelay(1000);
1299                 printk(KERN_NOTICE "calling vpm_init\n");
1300                 vpm_init(hc);
1301         }
1302
1303         /* check if R_F0_CNT counts (8 kHz frame count) */
1304         val = HFC_inb(hc, R_F0_CNTL);
1305         val += HFC_inb(hc, R_F0_CNTH) << 8;
1306         if (debug & DEBUG_HFCMULTI_INIT)
1307                 printk(KERN_DEBUG
1308                     "HFC_multi F0_CNT %ld after reset\n", val);
1309         spin_unlock_irqrestore(&hc->lock, flags);
1310         set_current_state(TASK_UNINTERRUPTIBLE);
1311         schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1312         spin_lock_irqsave(&hc->lock, flags);
1313         val2 = HFC_inb(hc, R_F0_CNTL);
1314         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1315         if (debug & DEBUG_HFCMULTI_INIT)
1316                 printk(KERN_DEBUG
1317                         "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1318                     val2);
1319         if (val2 >= val+8) { /* 1 ms */
1320                 /* it counts, so we keep the pcm mode */
1321                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1322                         printk(KERN_INFO "controller is PCM bus MASTER\n");
1323                 else
1324                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1325                         printk(KERN_INFO "controller is PCM bus SLAVE\n");
1326                 else {
1327                         test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1328                         printk(KERN_INFO "controller is PCM bus SLAVE "
1329                                 "(auto detected)\n");
1330                 }
1331         } else {
1332                 /* does not count */
1333                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1334 controller_fail:
1335                         printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1336                             "pulse. Seems that controller fails.\n");
1337                         err = -EIO;
1338                         goto out;
1339                 }
1340                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1341                         printk(KERN_INFO "controller is PCM bus SLAVE "
1342                                 "(ignoring missing PCM clock)\n");
1343                 } else {
1344                         /* only one pcm master */
1345                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1346                                 && plxsd_master) {
1347                                 printk(KERN_ERR "HFC_multi ERROR, no clock "
1348                                     "on another Speech Design card found. "
1349                                     "Please be sure to connect PCM cable.\n");
1350                                 err = -EIO;
1351                                 goto out;
1352                         }
1353                         /* retry with master clock */
1354                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1355                                 spin_lock_irqsave(&plx_lock, plx_flags);
1356                                 plx_acc_32 = (u_int *)(hc->plx_membase +
1357                                         PLX_GPIOC);
1358                                 pv = readl(plx_acc_32);
1359                                 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1360                                 pv |= PLX_SYNC_O_EN;
1361                                 writel(pv, plx_acc_32);
1362                                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1363                                 if (debug & DEBUG_HFCMULTI_INIT)
1364                                     printk(KERN_WARNING "%s: master: PLX_GPIO"
1365                                         "=%x\n", __func__, pv);
1366                         }
1367                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1368                         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1369                         spin_unlock_irqrestore(&hc->lock, flags);
1370                         set_current_state(TASK_UNINTERRUPTIBLE);
1371                         schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1372                         spin_lock_irqsave(&hc->lock, flags);
1373                         val2 = HFC_inb(hc, R_F0_CNTL);
1374                         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1375                         if (debug & DEBUG_HFCMULTI_INIT)
1376                                 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1377                                         "10 ms (2nd try)\n", val2);
1378                         if (val2 >= val+8) { /* 1 ms */
1379                                 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1380                                         &hc->chip);
1381                                 printk(KERN_INFO "controller is PCM bus MASTER "
1382                                         "(auto detected)\n");
1383                         } else
1384                                 goto controller_fail;
1385                 }
1386         }
1387
1388         /* Release the DSP Reset */
1389         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1390                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1391                         plxsd_master = 1;
1392                 spin_lock_irqsave(&plx_lock, plx_flags);
1393                 plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
1394                 pv = readl(plx_acc_32);
1395                 pv |=  PLX_DSP_RES_N;
1396                 writel(pv, plx_acc_32);
1397                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1398                 if (debug & DEBUG_HFCMULTI_INIT)
1399                         printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n",
1400                                 __func__, pv);
1401         }
1402
1403         /* pcm id */
1404         if (hc->pcm)
1405                 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1406                         hc->pcm);
1407         else {
1408                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1409                  || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1410                         PCM_cnt++; /* SD has proprietary bridging */
1411                 }
1412                 hc->pcm = PCM_cnt;
1413                 printk(KERN_INFO "controller has PCM BUS ID %d "
1414                         "(auto selected)\n", hc->pcm);
1415         }
1416
1417         /* set up timer */
1418         HFC_outb(hc, R_TI_WD, poll_timer);
1419         hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1420
1421         /*
1422          * set up 125us interrupt, only if function pointer is available
1423          * and module parameter timer is set
1424          */
1425         if (timer && hfc_interrupt && register_interrupt) {
1426                 /* only one chip should use this interrupt */
1427                 timer = 0;
1428                 interrupt_registered = 1;
1429                 hc->hw.r_irqmsk_misc |= V_PROC_IRQMSK;
1430                 /* deactivate other interrupts in ztdummy */
1431                 register_interrupt();
1432         }
1433
1434         /* set E1 state machine IRQ */
1435         if (hc->type == 1)
1436                 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1437
1438         /* set DTMF detection */
1439         if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1440                 if (debug & DEBUG_HFCMULTI_INIT)
1441                         printk(KERN_DEBUG "%s: enabling DTMF detection "
1442                             "for all B-channel\n", __func__);
1443                 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1444                 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1445                         hc->hw.r_dtmf |= V_ULAW_SEL;
1446                 HFC_outb(hc, R_DTMF_N, 102 - 1);
1447                 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1448         }
1449
1450         /* conference engine */
1451         if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1452                 r_conf_en = V_CONF_EN | V_ULAW;
1453         else
1454                 r_conf_en = V_CONF_EN;
1455         HFC_outb(hc, R_CONF_EN, r_conf_en);
1456
1457         /* setting leds */
1458         switch (hc->leds) {
1459         case 1: /* HFC-E1 OEM */
1460                 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1461                         HFC_outb(hc, R_GPIO_SEL, 0x32);
1462                 else
1463                         HFC_outb(hc, R_GPIO_SEL, 0x30);
1464
1465                 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1466                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1467
1468                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1469                 break;
1470
1471         case 2: /* HFC-4S OEM */
1472         case 3:
1473                 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1474                 HFC_outb(hc, R_GPIO_EN1, 0xff);
1475                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1476                 break;
1477         }
1478
1479         /* set master clock */
1480         if (hc->masterclk >= 0) {
1481                 if (debug & DEBUG_HFCMULTI_INIT)
1482                         printk(KERN_DEBUG "%s: setting ST master clock "
1483                             "to port %d (0..%d)\n",
1484                             __func__, hc->masterclk, hc->ports-1);
1485                 hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
1486                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1487         }
1488
1489         /* setting misc irq */
1490         HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1491         if (debug & DEBUG_HFCMULTI_INIT)
1492                 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1493                     hc->hw.r_irqmsk_misc);
1494
1495         /* RAM access test */
1496         HFC_outb(hc, R_RAM_ADDR0, 0);
1497         HFC_outb(hc, R_RAM_ADDR1, 0);
1498         HFC_outb(hc, R_RAM_ADDR2, 0);
1499         for (i = 0; i < 256; i++) {
1500                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1501                 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1502         }
1503         for (i = 0; i < 256; i++) {
1504                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1505                 HFC_inb_nodebug(hc, R_RAM_DATA);
1506                 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1507                 if (rval != ((i * 3) & 0xff)) {
1508                         printk(KERN_DEBUG
1509                             "addr:%x val:%x should:%x\n", i, rval,
1510                             (i * 3) & 0xff);
1511                         err++;
1512                 }
1513         }
1514         if (err) {
1515                 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1516                 err = -EIO;
1517                 goto out;
1518         }
1519
1520         if (debug & DEBUG_HFCMULTI_INIT)
1521                 printk(KERN_DEBUG "%s: done\n", __func__);
1522 out:
1523         spin_unlock_irqrestore(&hc->lock, flags);
1524         return err;
1525 }
1526
1527
1528 /*
1529  * control the watchdog
1530  */
1531 static void
1532 hfcmulti_watchdog(struct hfc_multi *hc)
1533 {
1534         hc->wdcount++;
1535
1536         if (hc->wdcount > 10) {
1537                 hc->wdcount = 0;
1538                 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1539                     V_GPIO_OUT3 : V_GPIO_OUT2;
1540
1541         /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1542                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1543                 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1544         }
1545 }
1546
1547
1548
1549 /*
1550  * output leds
1551  */
1552 static void
1553 hfcmulti_leds(struct hfc_multi *hc)
1554 {
1555         unsigned long lled;
1556         unsigned long leddw;
1557         int i, state, active, leds;
1558         struct dchannel *dch;
1559         int led[4];
1560
1561         hc->ledcount += poll;
1562         if (hc->ledcount > 4096) {
1563                 hc->ledcount -= 4096;
1564                 hc->ledstate = 0xAFFEAFFE;
1565         }
1566
1567         switch (hc->leds) {
1568         case 1: /* HFC-E1 OEM */
1569                 /* 2 red blinking: NT mode deactivate
1570                  * 2 red steady:   TE mode deactivate
1571                  * left green:     L1 active
1572                  * left red:       frame sync, but no L1
1573                  * right green:    L2 active
1574                  */
1575                 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1576                         if (hc->chan[hc->dslot].dch->dev.D.protocol
1577                                 != ISDN_P_NT_E1) {
1578                                 led[0] = 1;
1579                                 led[1] = 1;
1580                         } else if (hc->ledcount>>11) {
1581                                 led[0] = 1;
1582                                 led[1] = 1;
1583                         } else {
1584                                 led[0] = 0;
1585                                 led[1] = 0;
1586                         }
1587                         led[2] = 0;
1588                         led[3] = 0;
1589                 } else { /* with frame sync */
1590                         /* TODO make it work */
1591                         led[0] = 0;
1592                         led[1] = 0;
1593                         led[2] = 0;
1594                         led[3] = 1;
1595                 }
1596                 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1597                         /* leds are inverted */
1598                 if (leds != (int)hc->ledstate) {
1599                         HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1600                         hc->ledstate = leds;
1601                 }
1602                 break;
1603
1604         case 2: /* HFC-4S OEM */
1605                 /* red blinking = PH_DEACTIVATE NT Mode
1606                  * red steady   = PH_DEACTIVATE TE Mode
1607                  * green steady = PH_ACTIVATE
1608                  */
1609                 for (i = 0; i < 4; i++) {
1610                         state = 0;
1611                         active = -1;
1612                         dch = hc->chan[(i << 2) | 2].dch;
1613                         if (dch) {
1614                                 state = dch->state;
1615                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1616                                         active = 3;
1617                                 else
1618                                         active = 7;
1619                         }
1620                         if (state) {
1621                                 if (state == active) {
1622                                         led[i] = 1; /* led green */
1623                                 } else
1624                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1625                                                 /* TE mode: led red */
1626                                                 led[i] = 2;
1627                                         else
1628                                                 if (hc->ledcount>>11)
1629                                                         /* led red */
1630                                                         led[i] = 2;
1631                                                 else
1632                                                         /* led off */
1633                                                         led[i] = 0;
1634                         } else
1635                                 led[i] = 0; /* led off */
1636                 }
1637                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1638                         leds = 0;
1639                         for (i = 0; i < 4; i++) {
1640                                 if (led[i] == 1) {
1641                                         /*green*/
1642                                         leds |= (0x2 << (i * 2));
1643                                 } else if (led[i] == 2) {
1644                                         /*red*/
1645                                         leds |= (0x1 << (i * 2));
1646                                 }
1647                         }
1648                         if (leds != (int)hc->ledstate) {
1649                                 vpm_out(hc, 0, 0x1a8 + 3, leds);
1650                                 hc->ledstate = leds;
1651                         }
1652                 } else {
1653                         leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1654                             ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1655                             ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1656                             ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1657                         if (leds != (int)hc->ledstate) {
1658                                 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1659                                 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1660                                 hc->ledstate = leds;
1661                         }
1662                 }
1663                 break;
1664
1665         case 3: /* HFC 1S/2S Beronet */
1666                 /* red blinking = PH_DEACTIVATE NT Mode
1667                  * red steady   = PH_DEACTIVATE TE Mode
1668                  * green steady = PH_ACTIVATE
1669                  */
1670                 for (i = 0; i < 2; i++) {
1671                         state = 0;
1672                         active = -1;
1673                         dch = hc->chan[(i << 2) | 2].dch;
1674                         if (dch) {
1675                                 state = dch->state;
1676                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1677                                         active = 3;
1678                                 else
1679                                         active = 7;
1680                         }
1681                         if (state) {
1682                                 if (state == active) {
1683                                         led[i] = 1; /* led green */
1684                                 } else
1685                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1686                                                 /* TE mode: led red */
1687                                                 led[i] = 2;
1688                                         else
1689                                                 if (hc->ledcount >> 11)
1690                                                         /* led red */
1691                                                         led[i] = 2;
1692                                                 else
1693                                                         /* led off */
1694                                                         led[i] = 0;
1695                         } else
1696                                 led[i] = 0; /* led off */
1697                 }
1698
1699
1700                 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1701                         | ((led[1]&1)<<3);
1702                 if (leds != (int)hc->ledstate) {
1703                         HFC_outb_nodebug(hc, R_GPIO_EN1,
1704                             ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1705                         HFC_outb_nodebug(hc, R_GPIO_OUT1,
1706                             ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1707                         hc->ledstate = leds;
1708                 }
1709                 break;
1710         case 8: /* HFC 8S+ Beronet */
1711                 lled = 0;
1712
1713                 for (i = 0; i < 8; i++) {
1714                         state = 0;
1715                         active = -1;
1716                         dch = hc->chan[(i << 2) | 2].dch;
1717                         if (dch) {
1718                                 state = dch->state;
1719                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1720                                         active = 3;
1721                                 else
1722                                         active = 7;
1723                         }
1724                         if (state) {
1725                                 if (state == active) {
1726                                         lled |= 0 << i;
1727                                 } else
1728                                         if (hc->ledcount >> 11)
1729                                                 lled |= 0 << i;
1730                                         else
1731                                                 lled |= 1 << i;
1732                         } else
1733                                 lled |= 1 << i;
1734                 }
1735                 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1736                 if (leddw != hc->ledstate) {
1737                         /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1738                         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1739                         /* was _io before */
1740                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1741                         outw(0x4000, hc->pci_iobase + 4);
1742                         outl(leddw, hc->pci_iobase);
1743                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1744                         hc->ledstate = leddw;
1745                 }
1746                 break;
1747         }
1748 }
1749 /*
1750  * read dtmf coefficients
1751  */
1752
1753 static void
1754 hfcmulti_dtmf(struct hfc_multi *hc)
1755 {
1756         s32             *coeff;
1757         u_int           mantissa;
1758         int             co, ch;
1759         struct bchannel *bch = NULL;
1760         u8              exponent;
1761         int             dtmf = 0;
1762         int             addr;
1763         u16             w_float;
1764         struct sk_buff  *skb;
1765         struct mISDNhead *hh;
1766
1767         if (debug & DEBUG_HFCMULTI_DTMF)
1768                 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1769         for (ch = 0; ch <= 31; ch++) {
1770                 /* only process enabled B-channels */
1771                 bch = hc->chan[ch].bch;
1772                 if (!bch)
1773                         continue;
1774                 if (!hc->created[hc->chan[ch].port])
1775                         continue;
1776                 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1777                         continue;
1778                 if (debug & DEBUG_HFCMULTI_DTMF)
1779                         printk(KERN_DEBUG "%s: dtmf channel %d:",
1780                                 __func__, ch);
1781                 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1782                 dtmf = 1;
1783                 for (co = 0; co < 8; co++) {
1784                         /* read W(n-1) coefficient */
1785                         addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1786                         HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1787                         HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1788                         HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1789                                 | V_ADDR_INC);
1790                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1791                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1792                         if (debug & DEBUG_HFCMULTI_DTMF)
1793                                 printk(" %04x", w_float);
1794
1795                         /* decode float (see chip doc) */
1796                         mantissa = w_float & 0x0fff;
1797                         if (w_float & 0x8000)
1798                                 mantissa |= 0xfffff000;
1799                         exponent = (w_float>>12) & 0x7;
1800                         if (exponent) {
1801                                 mantissa ^= 0x1000;
1802                                 mantissa <<= (exponent-1);
1803                         }
1804
1805                         /* store coefficient */
1806                         coeff[co<<1] = mantissa;
1807
1808                         /* read W(n) coefficient */
1809                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1810                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1811                         if (debug & DEBUG_HFCMULTI_DTMF)
1812                                 printk(" %04x", w_float);
1813
1814                         /* decode float (see chip doc) */
1815                         mantissa = w_float & 0x0fff;
1816                         if (w_float & 0x8000)
1817                                 mantissa |= 0xfffff000;
1818                         exponent = (w_float>>12) & 0x7;
1819                         if (exponent) {
1820                                 mantissa ^= 0x1000;
1821                                 mantissa <<= (exponent-1);
1822                         }
1823
1824                         /* store coefficient */
1825                         coeff[(co<<1)|1] = mantissa;
1826                 }
1827                 if (debug & DEBUG_HFCMULTI_DTMF)
1828                         printk("%s: DTMF ready %08x %08x %08x %08x "
1829                             "%08x %08x %08x %08x\n", __func__,
1830                             coeff[0], coeff[1], coeff[2], coeff[3],
1831                             coeff[4], coeff[5], coeff[6], coeff[7]);
1832                 hc->chan[ch].coeff_count++;
1833                 if (hc->chan[ch].coeff_count == 8) {
1834                         hc->chan[ch].coeff_count = 0;
1835                         skb = mI_alloc_skb(512, GFP_ATOMIC);
1836                         if (!skb) {
1837                                 printk(KERN_WARNING "%s: No memory for skb\n",
1838                                     __func__);
1839                                 continue;
1840                         }
1841                         hh = mISDN_HEAD_P(skb);
1842                         hh->prim = PH_CONTROL_IND;
1843                         hh->id = DTMF_HFC_COEF;
1844                         memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1845                         recv_Bchannel_skb(bch, skb);
1846                 }
1847         }
1848
1849         /* restart DTMF processing */
1850         hc->dtmf = dtmf;
1851         if (dtmf)
1852                 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1853 }
1854
1855
1856 /*
1857  * fill fifo as much as possible
1858  */
1859
1860 static void
1861 hfcmulti_tx(struct hfc_multi *hc, int ch)
1862 {
1863         int i, ii, temp, len = 0;
1864         int Zspace, z1, z2; /* must be int for calculation */
1865         int Fspace, f1, f2;
1866         u_char *d;
1867         int *txpending, slot_tx;
1868         struct  bchannel *bch;
1869         struct  dchannel *dch;
1870         struct  sk_buff **sp = NULL;
1871         int *idxp;
1872
1873         bch = hc->chan[ch].bch;
1874         dch = hc->chan[ch].dch;
1875         if ((!dch) && (!bch))
1876                 return;
1877
1878         txpending = &hc->chan[ch].txpending;
1879         slot_tx = hc->chan[ch].slot_tx;
1880         if (dch) {
1881                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1882                         return;
1883                 sp = &dch->tx_skb;
1884                 idxp = &dch->tx_idx;
1885         } else {
1886                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1887                         return;
1888                 sp = &bch->tx_skb;
1889                 idxp = &bch->tx_idx;
1890         }
1891         if (*sp)
1892                 len = (*sp)->len;
1893
1894         if ((!len) && *txpending != 1)
1895                 return; /* no data */
1896
1897         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1898             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1899             (hc->chan[ch].slot_rx < 0) &&
1900             (hc->chan[ch].slot_tx < 0))
1901                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1902         else
1903                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1904         HFC_wait_nodebug(hc);
1905
1906         if (*txpending == 2) {
1907                 /* reset fifo */
1908                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1909                 HFC_wait_nodebug(hc);
1910                 HFC_outb(hc, A_SUBCH_CFG, 0);
1911                 *txpending = 1;
1912         }
1913 next_frame:
1914         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1915                 f1 = HFC_inb_nodebug(hc, A_F1);
1916                 f2 = HFC_inb_nodebug(hc, A_F2);
1917                 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1918                         if (debug & DEBUG_HFCMULTI_FIFO)
1919                                 printk(KERN_DEBUG
1920                                     "%s(card %d): reread f2 because %d!=%d\n",
1921                                     __func__, hc->id + 1, temp, f2);
1922                         f2 = temp; /* repeat until F2 is equal */
1923                 }
1924                 Fspace = f2 - f1 - 1;
1925                 if (Fspace < 0)
1926                         Fspace += hc->Flen;
1927                 /*
1928                  * Old FIFO handling doesn't give us the current Z2 read
1929                  * pointer, so we cannot send the next frame before the fifo
1930                  * is empty. It makes no difference except for a slightly
1931                  * lower performance.
1932                  */
1933                 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1934                         if (f1 != f2)
1935                                 Fspace = 0;
1936                         else
1937                                 Fspace = 1;
1938                 }
1939                 /* one frame only for ST D-channels, to allow resending */
1940                 if (hc->type != 1 && dch) {
1941                         if (f1 != f2)
1942                                 Fspace = 0;
1943                 }
1944                 /* F-counter full condition */
1945                 if (Fspace == 0)
1946                         return;
1947         }
1948         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1949         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1950         while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1951                 if (debug & DEBUG_HFCMULTI_FIFO)
1952                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
1953                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1954                 z2 = temp; /* repeat unti Z2 is equal */
1955         }
1956         Zspace = z2 - z1;
1957         if (Zspace <= 0)
1958                 Zspace += hc->Zlen;
1959         Zspace -= 4; /* keep not too full, so pointers will not overrun */
1960         /* fill transparent data only to maxinum transparent load (minus 4) */
1961         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
1962                 Zspace = Zspace - hc->Zlen + hc->max_trans;
1963         if (Zspace <= 0) /* no space of 4 bytes */
1964                 return;
1965
1966         /* if no data */
1967         if (!len) {
1968                 if (z1 == z2) { /* empty */
1969                         /* if done with FIFO audio data during PCM connection */
1970                         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
1971                             *txpending && slot_tx >= 0) {
1972                                 if (debug & DEBUG_HFCMULTI_MODE)
1973                                         printk(KERN_DEBUG
1974                                             "%s: reconnecting PCM due to no "
1975                                             "more FIFO data: channel %d "
1976                                             "slot_tx %d\n",
1977                                             __func__, ch, slot_tx);
1978                                 /* connect slot */
1979                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1980                                     V_HDLC_TRP | V_IFF);
1981                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1982                                 HFC_wait_nodebug(hc);
1983                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1984                                     V_HDLC_TRP | V_IFF);
1985                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
1986                                 HFC_wait_nodebug(hc);
1987                         }
1988                         *txpending = 0;
1989                 }
1990                 return; /* no data */
1991         }
1992
1993         /* if audio data and connected slot */
1994         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
1995                 && slot_tx >= 0) {
1996                 if (debug & DEBUG_HFCMULTI_MODE)
1997                         printk(KERN_DEBUG "%s: disconnecting PCM due to "
1998                             "FIFO data: channel %d slot_tx %d\n",
1999                             __func__, ch, slot_tx);
2000                 /* disconnect slot */
2001                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2002                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2003                 HFC_wait_nodebug(hc);
2004                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2005                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2006                 HFC_wait_nodebug(hc);
2007         }
2008         *txpending = 1;
2009
2010         /* show activity */
2011         hc->activity[hc->chan[ch].port] = 1;
2012
2013         /* fill fifo to what we have left */
2014         ii = len;
2015         if (dch || test_bit(FLG_HDLC, &bch->Flags))
2016                 temp = 1;
2017         else
2018                 temp = 0;
2019         i = *idxp;
2020         d = (*sp)->data + i;
2021         if (ii - i > Zspace)
2022                 ii = Zspace + i;
2023         if (debug & DEBUG_HFCMULTI_FIFO)
2024                 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2025                     "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2026                         __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2027                         temp ? "HDLC":"TRANS");
2028
2029
2030         /* Have to prep the audio data */
2031         hc->write_fifo(hc, d, ii - i);
2032         *idxp = ii;
2033
2034         /* if not all data has been written */
2035         if (ii != len) {
2036                 /* NOTE: fifo is started by the calling function */
2037                 return;
2038         }
2039
2040         /* if all data has been written, terminate frame */
2041         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2042                 /* increment f-counter */
2043                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2044                 HFC_wait_nodebug(hc);
2045         }
2046
2047         /* send confirm, since get_net_bframe will not do it with trans */
2048         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2049                 confirm_Bsend(bch);
2050
2051         /* check for next frame */
2052         dev_kfree_skb(*sp);
2053         if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2054                 len = (*sp)->len;
2055                 goto next_frame;
2056         }
2057         if (dch && get_next_dframe(dch)) {
2058                 len = (*sp)->len;
2059                 goto next_frame;
2060         }
2061
2062         /*
2063          * now we have no more data, so in case of transparent,
2064          * we set the last byte in fifo to 'silence' in case we will get
2065          * no more data at all. this prevents sending an undefined value.
2066          */
2067         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2068                 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2069 }
2070
2071
2072 /* NOTE: only called if E1 card is in active state */
2073 static void
2074 hfcmulti_rx(struct hfc_multi *hc, int ch)
2075 {
2076         int temp;
2077         int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2078         int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2079         int again = 0;
2080         struct  bchannel *bch;
2081         struct  dchannel *dch;
2082         struct sk_buff  *skb, **sp = NULL;
2083         int     maxlen;
2084
2085         bch = hc->chan[ch].bch;
2086         dch = hc->chan[ch].dch;
2087         if ((!dch) && (!bch))
2088                 return;
2089         if (dch) {
2090                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2091                         return;
2092                 sp = &dch->rx_skb;
2093                 maxlen = dch->maxlen;
2094         } else {
2095                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2096                         return;
2097                 sp = &bch->rx_skb;
2098                 maxlen = bch->maxlen;
2099         }
2100 next_frame:
2101         /* on first AND before getting next valid frame, R_FIFO must be written
2102            to. */
2103         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2104             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2105             (hc->chan[ch].slot_rx < 0) &&
2106             (hc->chan[ch].slot_tx < 0))
2107                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2108         else
2109                 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2110         HFC_wait_nodebug(hc);
2111
2112         /* ignore if rx is off BUT change fifo (above) to start pending TX */
2113         if (hc->chan[ch].rx_off)
2114                 return;
2115
2116         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2117                 f1 = HFC_inb_nodebug(hc, A_F1);
2118                 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2119                         if (debug & DEBUG_HFCMULTI_FIFO)
2120                                 printk(KERN_DEBUG
2121                                     "%s(card %d): reread f1 because %d!=%d\n",
2122                                     __func__, hc->id + 1, temp, f1);
2123                         f1 = temp; /* repeat until F1 is equal */
2124                 }
2125                 f2 = HFC_inb_nodebug(hc, A_F2);
2126         }
2127         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2128         while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2129                 if (debug & DEBUG_HFCMULTI_FIFO)
2130                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2131                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2132                 z1 = temp; /* repeat until Z1 is equal */
2133         }
2134         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2135         Zsize = z1 - z2;
2136         if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2137                 /* complete hdlc frame */
2138                 Zsize++;
2139         if (Zsize < 0)
2140                 Zsize += hc->Zlen;
2141         /* if buffer is empty */
2142         if (Zsize <= 0)
2143                 return;
2144
2145         if (*sp == NULL) {
2146                 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2147                 if (*sp == NULL) {
2148                         printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2149                             __func__);
2150                         return;
2151                 }
2152         }
2153         /* show activity */
2154         hc->activity[hc->chan[ch].port] = 1;
2155
2156         /* empty fifo with what we have */
2157         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2158                 if (debug & DEBUG_HFCMULTI_FIFO)
2159                         printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2160                             "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2161                             "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2162                             Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2163                             f1, f2, Zsize + (*sp)->len, again);
2164                 /* HDLC */
2165                 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2166                         if (debug & DEBUG_HFCMULTI_FIFO)
2167                                 printk(KERN_DEBUG
2168                                     "%s(card %d): hdlc-frame too large.\n",
2169                                     __func__, hc->id + 1);
2170                         skb_trim(*sp, 0);
2171                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2172                         HFC_wait_nodebug(hc);
2173                         return;
2174                 }
2175
2176                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2177
2178                 if (f1 != f2) {
2179                         /* increment Z2,F2-counter */
2180                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2181                         HFC_wait_nodebug(hc);
2182                         /* check size */
2183                         if ((*sp)->len < 4) {
2184                                 if (debug & DEBUG_HFCMULTI_FIFO)
2185                                         printk(KERN_DEBUG
2186                                             "%s(card %d): Frame below minimum "
2187                                             "size\n", __func__, hc->id + 1);
2188                                 skb_trim(*sp, 0);
2189                                 goto next_frame;
2190                         }
2191                         /* there is at least one complete frame, check crc */
2192                         if ((*sp)->data[(*sp)->len - 1]) {
2193                                 if (debug & DEBUG_HFCMULTI_CRC)
2194                                         printk(KERN_DEBUG
2195                                             "%s: CRC-error\n", __func__);
2196                                 skb_trim(*sp, 0);
2197                                 goto next_frame;
2198                         }
2199                         skb_trim(*sp, (*sp)->len - 3);
2200                         if ((*sp)->len < MISDN_COPY_SIZE) {
2201                                 skb = *sp;
2202                                 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2203                                 if (*sp) {
2204                                         memcpy(skb_put(*sp, skb->len),
2205                                             skb->data, skb->len);
2206                                         skb_trim(skb, 0);
2207                                 } else {
2208                                         printk(KERN_DEBUG "%s: No mem\n",
2209                                             __func__);
2210                                         *sp = skb;
2211                                         skb = NULL;
2212                                 }
2213                         } else {
2214                                 skb = NULL;
2215                         }
2216                         if (debug & DEBUG_HFCMULTI_FIFO) {
2217                                 printk(KERN_DEBUG "%s(card %d):",
2218                                         __func__, hc->id + 1);
2219                                 temp = 0;
2220                                 while (temp < (*sp)->len)
2221                                         printk(" %02x", (*sp)->data[temp++]);
2222                                 printk("\n");
2223                         }
2224                         if (dch)
2225                                 recv_Dchannel(dch);
2226                         else
2227                                 recv_Bchannel(bch);
2228                         *sp = skb;
2229                         again++;
2230                         goto next_frame;
2231                 }
2232                 /* there is an incomplete frame */
2233         } else {
2234                 /* transparent */
2235                 if (Zsize > skb_tailroom(*sp))
2236                         Zsize = skb_tailroom(*sp);
2237                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2238                 if (((*sp)->len) < MISDN_COPY_SIZE) {
2239                         skb = *sp;
2240                         *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2241                         if (*sp) {
2242                                 memcpy(skb_put(*sp, skb->len),
2243                                     skb->data, skb->len);
2244                                 skb_trim(skb, 0);
2245                         } else {
2246                                 printk(KERN_DEBUG "%s: No mem\n", __func__);
2247                                 *sp = skb;
2248                                 skb = NULL;
2249                         }
2250                 } else {
2251                         skb = NULL;
2252                 }
2253                 if (debug & DEBUG_HFCMULTI_FIFO)
2254                         printk(KERN_DEBUG
2255                             "%s(card %d): fifo(%d) reading %d bytes "
2256                             "(z1=%04x, z2=%04x) TRANS\n",
2257                                 __func__, hc->id + 1, ch, Zsize, z1, z2);
2258                 /* only bch is transparent */
2259                 recv_Bchannel(bch);
2260                 *sp = skb;
2261         }
2262 }
2263
2264
2265 /*
2266  * Interrupt handler
2267  */
2268 static void
2269 signal_state_up(struct dchannel *dch, int info, char *msg)
2270 {
2271         struct sk_buff  *skb;
2272         int             id, data = info;
2273
2274         if (debug & DEBUG_HFCMULTI_STATE)
2275                 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2276
2277         id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2278
2279         skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2280                 GFP_ATOMIC);
2281         if (!skb)
2282                 return;
2283         recv_Dchannel_skb(dch, skb);
2284 }
2285
2286 static inline void
2287 handle_timer_irq(struct hfc_multi *hc)
2288 {
2289         int             ch, temp;
2290         struct dchannel *dch;
2291         u_long          flags;
2292
2293         /* process queued resync jobs */
2294         if (hc->e1_resync) {
2295                 /* lock, so e1_resync gets not changed */
2296                 spin_lock_irqsave(&HFClock, flags);
2297                 if (hc->e1_resync & 1) {
2298                         if (debug & DEBUG_HFCMULTI_PLXSD)
2299                                 printk(KERN_DEBUG "Enable SYNC_I\n");
2300                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2301                         /* disable JATT, if RX_SYNC is set */
2302                         if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2303                                 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2304                 }
2305                 if (hc->e1_resync & 2) {
2306                         if (debug & DEBUG_HFCMULTI_PLXSD)
2307                                 printk(KERN_DEBUG "Enable jatt PLL\n");
2308                         HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2309                 }
2310                 if (hc->e1_resync & 4) {
2311                         if (debug & DEBUG_HFCMULTI_PLXSD)
2312                                 printk(KERN_DEBUG
2313                                     "Enable QUARTZ for HFC-E1\n");
2314                         /* set jatt to quartz */
2315                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2316                                 | V_JATT_OFF);
2317                         /* switch to JATT, in case it is not already */
2318                         HFC_outb(hc, R_SYNC_OUT, 0);
2319                 }
2320                 hc->e1_resync = 0;
2321                 spin_unlock_irqrestore(&HFClock, flags);
2322         }
2323
2324         if (hc->type != 1 || hc->e1_state == 1)
2325                 for (ch = 0; ch <= 31; ch++) {
2326                         if (hc->created[hc->chan[ch].port]) {
2327                                 hfcmulti_tx(hc, ch);
2328                                 /* fifo is started when switching to rx-fifo */
2329                                 hfcmulti_rx(hc, ch);
2330                                 if (hc->chan[ch].dch &&
2331                                     hc->chan[ch].nt_timer > -1) {
2332                                         dch = hc->chan[ch].dch;
2333                                         if (!(--hc->chan[ch].nt_timer)) {
2334                                                 schedule_event(dch,
2335                                                     FLG_PHCHANGE);
2336                                                 if (debug &
2337                                                     DEBUG_HFCMULTI_STATE)
2338                                                         printk(KERN_DEBUG
2339                                                             "%s: nt_timer at "
2340                                                             "state %x\n",
2341                                                             __func__,
2342                                                             dch->state);
2343                                         }
2344                                 }
2345                         }
2346                 }
2347         if (hc->type == 1 && hc->created[0]) {
2348                 dch = hc->chan[hc->dslot].dch;
2349                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2350                         /* LOS */
2351                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2352                         if (!temp && hc->chan[hc->dslot].los)
2353                                 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2354                                     "LOS detected");
2355                         if (temp && !hc->chan[hc->dslot].los)
2356                                 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2357                                     "LOS gone");
2358                         hc->chan[hc->dslot].los = temp;
2359                 }
2360                 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2361                         /* AIS */
2362                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2363                         if (!temp && hc->chan[hc->dslot].ais)
2364                                 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2365                                     "AIS detected");
2366                         if (temp && !hc->chan[hc->dslot].ais)
2367                                 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2368                                     "AIS gone");
2369                         hc->chan[hc->dslot].ais = temp;
2370                 }
2371                 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2372                         /* SLIP */
2373                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2374                         if (!temp && hc->chan[hc->dslot].slip_rx)
2375                                 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2376                                     " bit SLIP detected RX");
2377                         hc->chan[hc->dslot].slip_rx = temp;
2378                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2379                         if (!temp && hc->chan[hc->dslot].slip_tx)
2380                                 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2381                                     " bit SLIP detected TX");
2382                         hc->chan[hc->dslot].slip_tx = temp;
2383                 }
2384                 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2385                         /* RDI */
2386                         temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2387                         if (!temp && hc->chan[hc->dslot].rdi)
2388                                 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2389                                     "RDI detected");
2390                         if (temp && !hc->chan[hc->dslot].rdi)
2391                                 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2392                                     "RDI gone");
2393                         hc->chan[hc->dslot].rdi = temp;
2394                 }
2395                 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2396                 switch (hc->chan[hc->dslot].sync) {
2397                 case 0:
2398                         if ((temp & 0x60) == 0x60) {
2399                                 if (debug & DEBUG_HFCMULTI_SYNC)
2400                                         printk(KERN_DEBUG
2401                                             "%s: (id=%d) E1 now "
2402                                             "in clock sync\n",
2403                                             __func__, hc->id);
2404                                 HFC_outb(hc, R_RX_OFF,
2405                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2406                                 HFC_outb(hc, R_TX_OFF,
2407                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2408                                 hc->chan[hc->dslot].sync = 1;
2409                                 goto check_framesync;
2410                         }
2411                         break;
2412                 case 1:
2413                         if ((temp & 0x60) != 0x60) {
2414                                 if (debug & DEBUG_HFCMULTI_SYNC)
2415                                         printk(KERN_DEBUG
2416                                             "%s: (id=%d) E1 "
2417                                             "lost clock sync\n",
2418                                             __func__, hc->id);
2419                                 hc->chan[hc->dslot].sync = 0;
2420                                 break;
2421                         }
2422 check_framesync:
2423                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2424                         if (temp == 0x27) {
2425                                 if (debug & DEBUG_HFCMULTI_SYNC)
2426                                         printk(KERN_DEBUG
2427                                             "%s: (id=%d) E1 "
2428                                             "now in frame sync\n",
2429                                             __func__, hc->id);
2430                                 hc->chan[hc->dslot].sync = 2;
2431                         }
2432                         break;
2433                 case 2:
2434                         if ((temp & 0x60) != 0x60) {
2435                                 if (debug & DEBUG_HFCMULTI_SYNC)
2436                                         printk(KERN_DEBUG
2437                                             "%s: (id=%d) E1 lost "
2438                                             "clock & frame sync\n",
2439                                             __func__, hc->id);
2440                                 hc->chan[hc->dslot].sync = 0;
2441                                 break;
2442                         }
2443                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2444                         if (temp != 0x27) {
2445                                 if (debug & DEBUG_HFCMULTI_SYNC)
2446                                         printk(KERN_DEBUG
2447                                             "%s: (id=%d) E1 "
2448                                             "lost frame sync\n",
2449                                             __func__, hc->id);
2450                                 hc->chan[hc->dslot].sync = 1;
2451                         }
2452                         break;
2453                 }
2454         }
2455
2456         if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2457                 hfcmulti_watchdog(hc);
2458
2459         if (hc->leds)
2460                 hfcmulti_leds(hc);
2461 }
2462
2463 static void
2464 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2465 {
2466         struct dchannel *dch;
2467         int             ch;
2468         int             active;
2469         u_char          st_status, temp;
2470
2471         /* state machine */
2472         for (ch = 0; ch <= 31; ch++) {
2473                 if (hc->chan[ch].dch) {
2474                         dch = hc->chan[ch].dch;
2475                         if (r_irq_statech & 1) {
2476                                 HFC_outb_nodebug(hc, R_ST_SEL,
2477                                         hc->chan[ch].port);
2478                                 /* undocumented: delay after R_ST_SEL */
2479                                 udelay(1);
2480                                 /* undocumented: status changes during read */
2481                                 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2482                                 while (st_status != (temp =
2483                                         HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2484                                         if (debug & DEBUG_HFCMULTI_STATE)
2485                                                 printk(KERN_DEBUG "%s: reread "
2486                                                     "STATE because %d!=%d\n",
2487                                                     __func__, temp,
2488                                                     st_status);
2489                                         st_status = temp; /* repeat */
2490                                 }
2491
2492                                 /* Speech Design TE-sync indication */
2493                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2494                                         dch->dev.D.protocol == ISDN_P_TE_S0) {
2495                                         if (st_status & V_FR_SYNC_ST)
2496                                                 hc->syncronized |=
2497                                                     (1 << hc->chan[ch].port);
2498                                         else
2499                                                 hc->syncronized &=
2500                                                    ~(1 << hc->chan[ch].port);
2501                                 }
2502                                 dch->state = st_status & 0x0f;
2503                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2504                                         active = 3;
2505                                 else
2506                                         active = 7;
2507                                 if (dch->state == active) {
2508                                         HFC_outb_nodebug(hc, R_FIFO,
2509                                                 (ch << 1) | 1);
2510                                         HFC_wait_nodebug(hc);
2511                                         HFC_outb_nodebug(hc,
2512                                                 R_INC_RES_FIFO, V_RES_F);
2513                                         HFC_wait_nodebug(hc);
2514                                         dch->tx_idx = 0;
2515                                 }
2516                                 schedule_event(dch, FLG_PHCHANGE);
2517                                 if (debug & DEBUG_HFCMULTI_STATE)
2518                                         printk(KERN_DEBUG
2519                                             "%s: S/T newstate %x port %d\n",
2520                                             __func__, dch->state,
2521                                             hc->chan[ch].port);
2522                         }
2523                         r_irq_statech >>= 1;
2524                 }
2525         }
2526         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2527                 plxsd_checksync(hc, 0);
2528 }
2529
2530 static void
2531 fifo_irq(struct hfc_multi *hc, int block)
2532 {
2533         int     ch, j;
2534         struct dchannel *dch;
2535         struct bchannel *bch;
2536         u_char r_irq_fifo_bl;
2537
2538         r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2539         j = 0;
2540         while (j < 8) {
2541                 ch = (block << 2) + (j >> 1);
2542                 dch = hc->chan[ch].dch;
2543                 bch = hc->chan[ch].bch;
2544                 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2545                         j += 2;
2546                         continue;
2547                 }
2548                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2549                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2550                         hfcmulti_tx(hc, ch);
2551                         /* start fifo */
2552                         HFC_outb_nodebug(hc, R_FIFO, 0);
2553                         HFC_wait_nodebug(hc);
2554                 }
2555                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2556                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2557                         hfcmulti_tx(hc, ch);
2558                         /* start fifo */
2559                         HFC_outb_nodebug(hc, R_FIFO, 0);
2560                         HFC_wait_nodebug(hc);
2561                 }
2562                 j++;
2563                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2564                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2565                         hfcmulti_rx(hc, ch);
2566                 }
2567                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2568                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2569                         hfcmulti_rx(hc, ch);
2570                 }
2571                 j++;
2572         }
2573 }
2574
2575 #ifdef IRQ_DEBUG
2576 int irqsem;
2577 #endif
2578 static irqreturn_t
2579 hfcmulti_interrupt(int intno, void *dev_id)
2580 {
2581 #ifdef IRQCOUNT_DEBUG
2582         static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2583             iq5 = 0, iq6 = 0, iqcnt = 0;
2584 #endif
2585         static int              count;
2586         struct hfc_multi        *hc = dev_id;
2587         struct dchannel         *dch;
2588         u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
2589         int                     i;
2590         u_short                 *plx_acc, wval;
2591         u_char                  e1_syncsta, temp;
2592         u_long                  flags;
2593
2594         if (!hc) {
2595                 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2596                 return IRQ_NONE;
2597         }
2598
2599         spin_lock(&hc->lock);
2600
2601 #ifdef IRQ_DEBUG
2602         if (irqsem)
2603                 printk(KERN_ERR "irq for card %d during irq from "
2604                 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2605         irqsem = hc->id + 1;
2606 #endif
2607
2608         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2609                 spin_lock_irqsave(&plx_lock, flags);
2610                 plx_acc = (u_short *)(hc->plx_membase + PLX_INTCSR);
2611                 wval = readw(plx_acc);
2612                 spin_unlock_irqrestore(&plx_lock, flags);
2613                 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2614                         goto irq_notforus;
2615         }
2616
2617         status = HFC_inb_nodebug(hc, R_STATUS);
2618         r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2619 #ifdef IRQCOUNT_DEBUG
2620         if (r_irq_statech)
2621                 iq1++;
2622         if (status & V_DTMF_STA)
2623                 iq2++;
2624         if (status & V_LOST_STA)
2625                 iq3++;
2626         if (status & V_EXT_IRQSTA)
2627                 iq4++;
2628         if (status & V_MISC_IRQSTA)
2629                 iq5++;
2630         if (status & V_FR_IRQSTA)
2631                 iq6++;
2632         if (iqcnt++ > 5000) {
2633                 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2634                     iq1, iq2, iq3, iq4, iq5, iq6);
2635                 iqcnt = 0;
2636         }
2637 #endif
2638         if (!r_irq_statech &&
2639             !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2640             V_MISC_IRQSTA | V_FR_IRQSTA))) {
2641                 /* irq is not for us */
2642                 goto irq_notforus;
2643         }
2644         hc->irqcnt++;
2645         if (r_irq_statech) {
2646                 if (hc->type != 1)
2647                         ph_state_irq(hc, r_irq_statech);
2648         }
2649         if (status & V_EXT_IRQSTA)
2650                 ; /* external IRQ */
2651         if (status & V_LOST_STA) {
2652                 /* LOST IRQ */
2653                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2654         }
2655         if (status & V_MISC_IRQSTA) {
2656                 /* misc IRQ */
2657                 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2658                 if (r_irq_misc & V_STA_IRQ) {
2659                         if (hc->type == 1) {
2660                                 /* state machine */
2661                                 dch = hc->chan[hc->dslot].dch;
2662                                 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2663                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2664                                  && hc->e1_getclock) {
2665                                         if (e1_syncsta & V_FR_SYNC_E1)
2666                                                 hc->syncronized = 1;
2667                                         else
2668                                                 hc->syncronized = 0;
2669                                 }
2670                                 /* undocumented: status changes during read */
2671                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2672                                 while (dch->state != (temp =
2673                                         HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2674                                         if (debug & DEBUG_HFCMULTI_STATE)
2675                                                 printk(KERN_DEBUG "%s: reread "
2676                                                     "STATE because %d!=%d\n",
2677                                                     __func__, temp,
2678                                                     dch->state);
2679                                         dch->state = temp; /* repeat */
2680                                 }
2681                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2682                                         & 0x7;
2683                                 schedule_event(dch, FLG_PHCHANGE);
2684                                 if (debug & DEBUG_HFCMULTI_STATE)
2685                                         printk(KERN_DEBUG
2686                                             "%s: E1 (id=%d) newstate %x\n",
2687                                             __func__, hc->id, dch->state);
2688                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2689                                         plxsd_checksync(hc, 0);
2690                         }
2691                 }
2692                 if (r_irq_misc & V_TI_IRQ)
2693                         handle_timer_irq(hc);
2694
2695                 if (r_irq_misc & V_DTMF_IRQ) {
2696                         /* -> DTMF IRQ */
2697                         hfcmulti_dtmf(hc);
2698                 }
2699                 /* TODO: REPLACE !!!! 125 us Interrupts are not acceptable  */
2700                 if (r_irq_misc & V_IRQ_PROC) {
2701                         /* IRQ every 125us */
2702                         count++;
2703                         /* generate 1kHz signal */
2704                         if (count == 8) {
2705                                 if (hfc_interrupt)
2706                                         hfc_interrupt();
2707                                 count = 0;
2708                         }
2709                 }
2710
2711         }
2712         if (status & V_FR_IRQSTA) {
2713                 /* FIFO IRQ */
2714                 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2715                 for (i = 0; i < 8; i++) {
2716                         if (r_irq_oview & (1 << i))
2717                                 fifo_irq(hc, i);
2718                 }
2719         }
2720
2721 #ifdef IRQ_DEBUG
2722         irqsem = 0;
2723 #endif
2724         spin_unlock(&hc->lock);
2725         return IRQ_HANDLED;
2726
2727 irq_notforus:
2728 #ifdef IRQ_DEBUG
2729         irqsem = 0;
2730 #endif
2731         spin_unlock(&hc->lock);
2732         return IRQ_NONE;
2733 }
2734
2735
2736 /*
2737  * timer callback for D-chan busy resolution. Currently no function
2738  */
2739
2740 static void
2741 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2742 {
2743 }
2744
2745
2746 /*
2747  * activate/deactivate hardware for selected channels and mode
2748  *
2749  * configure B-channel with the given protocol
2750  * ch eqals to the HFC-channel (0-31)
2751  * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2752  * for S/T, 1-31 for E1)
2753  * the hdlc interrupts will be set/unset
2754  */
2755 static int
2756 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2757     int bank_tx, int slot_rx, int bank_rx)
2758 {
2759         int flow_tx = 0, flow_rx = 0, routing = 0;
2760         int oslot_tx, oslot_rx;
2761         int conf;
2762
2763         if (ch < 0 || ch > 31)
2764                 return EINVAL;
2765         oslot_tx = hc->chan[ch].slot_tx;
2766         oslot_rx = hc->chan[ch].slot_rx;
2767         conf = hc->chan[ch].conf;
2768
2769         if (debug & DEBUG_HFCMULTI_MODE)
2770                 printk(KERN_DEBUG
2771                     "%s: card %d channel %d protocol %x slot old=%d new=%d "
2772                     "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2773                     __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2774                     bank_tx, oslot_rx, slot_rx, bank_rx);
2775
2776         if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2777                 /* remove from slot */
2778                 if (debug & DEBUG_HFCMULTI_MODE)
2779                         printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2780                             __func__, oslot_tx);
2781                 if (hc->slot_owner[oslot_tx<<1] == ch) {
2782                         HFC_outb(hc, R_SLOT, oslot_tx << 1);
2783                         HFC_outb(hc, A_SL_CFG, 0);
2784                         HFC_outb(hc, A_CONF, 0);
2785                         hc->slot_owner[oslot_tx<<1] = -1;
2786                 } else {
2787                         if (debug & DEBUG_HFCMULTI_MODE)
2788                                 printk(KERN_DEBUG
2789                                     "%s: we are not owner of this tx slot "
2790                                     "anymore, channel %d is.\n",
2791                                     __func__, hc->slot_owner[oslot_tx<<1]);
2792                 }
2793         }
2794
2795         if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2796                 /* remove from slot */
2797                 if (debug & DEBUG_HFCMULTI_MODE)
2798                         printk(KERN_DEBUG
2799                             "%s: remove from slot %d (RX)\n",
2800                             __func__, oslot_rx);
2801                 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2802                         HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2803                         HFC_outb(hc, A_SL_CFG, 0);
2804                         hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2805                 } else {
2806                         if (debug & DEBUG_HFCMULTI_MODE)
2807                                 printk(KERN_DEBUG
2808                                     "%s: we are not owner of this rx slot "
2809                                     "anymore, channel %d is.\n",
2810                                     __func__,
2811                                     hc->slot_owner[(oslot_rx << 1) | 1]);
2812                 }
2813         }
2814
2815         if (slot_tx < 0) {
2816                 flow_tx = 0x80; /* FIFO->ST */
2817                 /* disable pcm slot */
2818                 hc->chan[ch].slot_tx = -1;
2819                 hc->chan[ch].bank_tx = 0;
2820         } else {
2821                 /* set pcm slot */
2822                 if (hc->chan[ch].txpending)
2823                         flow_tx = 0x80; /* FIFO->ST */
2824                 else
2825                         flow_tx = 0xc0; /* PCM->ST */
2826                 /* put on slot */
2827                 routing = bank_tx ? 0xc0 : 0x80;
2828                 if (conf >= 0 || bank_tx > 1)
2829                         routing = 0x40; /* loop */
2830                 if (debug & DEBUG_HFCMULTI_MODE)
2831                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2832                             " %d flow %02x routing %02x conf %d (TX)\n",
2833                             __func__, ch, slot_tx, bank_tx,
2834                             flow_tx, routing, conf);
2835                 HFC_outb(hc, R_SLOT, slot_tx << 1);
2836                 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2837                 HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
2838                 hc->slot_owner[slot_tx << 1] = ch;
2839                 hc->chan[ch].slot_tx = slot_tx;
2840                 hc->chan[ch].bank_tx = bank_tx;
2841         }
2842         if (slot_rx < 0) {
2843                 /* disable pcm slot */
2844                 flow_rx = 0x80; /* ST->FIFO */
2845                 hc->chan[ch].slot_rx = -1;
2846                 hc->chan[ch].bank_rx = 0;
2847         } else {
2848                 /* set pcm slot */
2849                 if (hc->chan[ch].txpending)
2850                         flow_rx = 0x80; /* ST->FIFO */
2851                 else
2852                         flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2853                 /* put on slot */
2854                 routing = bank_rx?0x80:0xc0; /* reversed */
2855                 if (conf >= 0 || bank_rx > 1)
2856                         routing = 0x40; /* loop */
2857                 if (debug & DEBUG_HFCMULTI_MODE)
2858                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2859                             " %d flow %02x routing %02x conf %d (RX)\n",
2860                             __func__, ch, slot_rx, bank_rx,
2861                             flow_rx, routing, conf);
2862                 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2863                 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2864                 hc->slot_owner[(slot_rx<<1)|1] = ch;
2865                 hc->chan[ch].slot_rx = slot_rx;
2866                 hc->chan[ch].bank_rx = bank_rx;
2867         }
2868
2869         switch (protocol) {
2870         case (ISDN_P_NONE):
2871                 /* disable TX fifo */
2872                 HFC_outb(hc, R_FIFO, ch << 1);
2873                 HFC_wait(hc);
2874                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2875                 HFC_outb(hc, A_SUBCH_CFG, 0);
2876                 HFC_outb(hc, A_IRQ_MSK, 0);
2877                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2878                 HFC_wait(hc);
2879                 /* disable RX fifo */
2880                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2881                 HFC_wait(hc);
2882                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2883                 HFC_outb(hc, A_SUBCH_CFG, 0);
2884                 HFC_outb(hc, A_IRQ_MSK, 0);
2885                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2886                 HFC_wait(hc);
2887                 if (hc->chan[ch].bch && hc->type != 1) {
2888                         hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2889                             ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
2890                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2891                         /* undocumented: delay after R_ST_SEL */
2892                         udelay(1);
2893                         HFC_outb(hc, A_ST_CTRL0,
2894                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2895                 }
2896                 if (hc->chan[ch].bch) {
2897                         test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2898                         test_and_clear_bit(FLG_TRANSPARENT,
2899                             &hc->chan[ch].bch->Flags);
2900                 }
2901                 break;
2902         case (ISDN_P_B_RAW): /* B-channel */
2903
2904                 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2905                     (hc->chan[ch].slot_rx < 0) &&
2906                     (hc->chan[ch].slot_tx < 0)) {
2907
2908                         printk(KERN_DEBUG
2909                             "Setting B-channel %d to echo cancelable "
2910                             "state on PCM slot %d\n", ch,
2911                             ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2912                         printk(KERN_DEBUG
2913                             "Enabling pass through for channel\n");
2914                         vpm_out(hc, ch, ((ch / 4) * 8) +
2915                             ((ch % 4) * 4) + 1, 0x01);
2916                         /* rx path */
2917                         /* S/T -> PCM */
2918                         HFC_outb(hc, R_FIFO, (ch << 1));
2919                         HFC_wait(hc);
2920                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2921                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2922                             ((ch % 4) * 4) + 1) << 1);
2923                         HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2924
2925                         /* PCM -> FIFO */
2926                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2927                         HFC_wait(hc);
2928                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2929                         HFC_outb(hc, A_SUBCH_CFG, 0);
2930                         HFC_outb(hc, A_IRQ_MSK, 0);
2931                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2932                         HFC_wait(hc);
2933                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2934                             ((ch % 4) * 4) + 1) << 1) | 1);
2935                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
2936
2937                         /* tx path */
2938                         /* PCM -> S/T */
2939                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2940                         HFC_wait(hc);
2941                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2942                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2943                             ((ch % 4) * 4)) << 1) | 1);
2944                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
2945
2946                         /* FIFO -> PCM */
2947                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
2948                         HFC_wait(hc);
2949                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2950                         HFC_outb(hc, A_SUBCH_CFG, 0);
2951                         HFC_outb(hc, A_IRQ_MSK, 0);
2952                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2953                         HFC_wait(hc);
2954                         /* tx silence */
2955                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2956                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2957                             ((ch % 4) * 4)) << 1);
2958                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
2959                 } else {
2960                         /* enable TX fifo */
2961                         HFC_outb(hc, R_FIFO, ch << 1);
2962                         HFC_wait(hc);
2963                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
2964                             V_HDLC_TRP | V_IFF);
2965                         HFC_outb(hc, A_SUBCH_CFG, 0);
2966                         HFC_outb(hc, A_IRQ_MSK, 0);
2967                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2968                         HFC_wait(hc);
2969                         /* tx silence */
2970                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2971                         /* enable RX fifo */
2972                         HFC_outb(hc, R_FIFO, (ch<<1)|1);
2973                         HFC_wait(hc);
2974                         HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
2975                         HFC_outb(hc, A_SUBCH_CFG, 0);
2976                         HFC_outb(hc, A_IRQ_MSK, 0);
2977                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2978                         HFC_wait(hc);
2979                 }
2980                 if (hc->type != 1) {
2981                         hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
2982                             ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
2983                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2984                         /* undocumented: delay after R_ST_SEL */
2985                         udelay(1);
2986                         HFC_outb(hc, A_ST_CTRL0,
2987                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2988                 }
2989                 if (hc->chan[ch].bch)
2990                         test_and_set_bit(FLG_TRANSPARENT,
2991                             &hc->chan[ch].bch->Flags);
2992                 break;
2993         case (ISDN_P_B_HDLC): /* B-channel */
2994         case (ISDN_P_TE_S0): /* D-channel */
2995         case (ISDN_P_NT_S0):
2996         case (ISDN_P_TE_E1):
2997         case (ISDN_P_NT_E1):
2998                 /* enable TX fifo */
2999                 HFC_outb(hc, R_FIFO, ch<<1);
3000                 HFC_wait(hc);
3001                 if (hc->type == 1 || hc->chan[ch].bch) {
3002                         /* E1 or B-channel */
3003                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3004                         HFC_outb(hc, A_SUBCH_CFG, 0);
3005                 } else {
3006                         /* D-Channel without HDLC fill flags */
3007                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3008                         HFC_outb(hc, A_SUBCH_CFG, 2);
3009                 }
3010                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3011                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3012                 HFC_wait(hc);
3013                 /* enable RX fifo */
3014                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3015                 HFC_wait(hc);
3016                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3017                 if (hc->type == 1 || hc->chan[ch].bch)
3018                         HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3019                 else
3020                         HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3021                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3022                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3023                 HFC_wait(hc);
3024                 if (hc->chan[ch].bch) {
3025                         test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3026                         if (hc->type != 1) {
3027                                 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3028                                   ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3029                                 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3030                                 /* undocumented: delay after R_ST_SEL */
3031                                 udelay(1);
3032                                 HFC_outb(hc, A_ST_CTRL0,
3033                                   hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3034                         }
3035                 }
3036                 break;
3037         default:
3038                 printk(KERN_DEBUG "%s: protocol not known %x\n",
3039                     __func__, protocol);
3040                 hc->chan[ch].protocol = ISDN_P_NONE;
3041                 return -ENOPROTOOPT;
3042         }
3043         hc->chan[ch].protocol = protocol;
3044         return 0;
3045 }
3046
3047
3048 /*
3049  * connect/disconnect PCM
3050  */
3051
3052 static void
3053 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3054     int slot_rx, int bank_rx)
3055 {
3056         if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3057                 /* disable PCM */
3058                 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3059                 return;
3060         }
3061
3062         /* enable pcm */
3063         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3064                 slot_rx, bank_rx);
3065 }
3066
3067 /*
3068  * set/disable conference
3069  */
3070
3071 static void
3072 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3073 {
3074         if (num >= 0 && num <= 7)
3075                 hc->chan[ch].conf = num;
3076         else
3077                 hc->chan[ch].conf = -1;
3078         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3079             hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3080             hc->chan[ch].bank_rx);
3081 }
3082
3083
3084 /*
3085  * set/disable sample loop
3086  */
3087
3088 /* NOTE: this function is experimental and therefore disabled */
3089
3090 /*
3091  * Layer 1 callback function
3092  */
3093 static int
3094 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3095 {
3096         struct hfc_multi        *hc = dch->hw;
3097         u_long  flags;
3098
3099         switch (cmd) {
3100         case INFO3_P8:
3101         case INFO3_P10:
3102                 break;
3103         case HW_RESET_REQ:
3104                 /* start activation */
3105                 spin_lock_irqsave(&hc->lock, flags);
3106                 if (hc->type == 1) {
3107                         if (debug & DEBUG_HFCMULTI_MSG)
3108                                 printk(KERN_DEBUG
3109                                     "%s: HW_RESET_REQ no BRI\n",
3110                                     __func__);
3111                 } else {
3112                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3113                         /* undocumented: delay after R_ST_SEL */
3114                         udelay(1);
3115                         HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3116                         udelay(6); /* wait at least 5,21us */
3117                         HFC_outb(hc, A_ST_WR_STATE, 3);
3118                         HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3119                                 /* activate */
3120                 }
3121                 spin_unlock_irqrestore(&hc->lock, flags);
3122                 l1_event(dch->l1, HW_POWERUP_IND);
3123                 break;
3124         case HW_DEACT_REQ:
3125                 /* start deactivation */
3126                 spin_lock_irqsave(&hc->lock, flags);
3127                 if (hc->type == 1) {
3128                         if (debug & DEBUG_HFCMULTI_MSG)
3129                                 printk(KERN_DEBUG
3130                                     "%s: HW_DEACT_REQ no BRI\n",
3131                                     __func__);
3132                 } else {
3133                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3134                         /* undocumented: delay after R_ST_SEL */
3135                         udelay(1);
3136                         HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3137                                 /* deactivate */
3138                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3139                                 hc->syncronized &=
3140                                    ~(1 << hc->chan[dch->slot].port);
3141                                 plxsd_checksync(hc, 0);
3142                         }
3143                 }
3144                 skb_queue_purge(&dch->squeue);
3145                 if (dch->tx_skb) {
3146                         dev_kfree_skb(dch->tx_skb);
3147                         dch->tx_skb = NULL;
3148                 }
3149                 dch->tx_idx = 0;
3150                 if (dch->rx_skb) {
3151                         dev_kfree_skb(dch->rx_skb);
3152                         dch->rx_skb = NULL;
3153                 }
3154                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3155                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3156                         del_timer(&dch->timer);
3157                 spin_unlock_irqrestore(&hc->lock, flags);
3158                 break;
3159         case HW_POWERUP_REQ:
3160                 spin_lock_irqsave(&hc->lock, flags);
3161                 if (hc->type == 1) {
3162                         if (debug & DEBUG_HFCMULTI_MSG)
3163                                 printk(KERN_DEBUG
3164                                     "%s: HW_POWERUP_REQ no BRI\n",
3165                                     __func__);
3166                 } else {
3167                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3168                         /* undocumented: delay after R_ST_SEL */
3169                         udelay(1);
3170                         HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3171                         udelay(6); /* wait at least 5,21us */
3172                         HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3173                 }
3174                 spin_unlock_irqrestore(&hc->lock, flags);
3175                 break;
3176         case PH_ACTIVATE_IND:
3177                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3178                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3179                         GFP_ATOMIC);
3180                 break;
3181         case PH_DEACTIVATE_IND:
3182                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3183                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3184                         GFP_ATOMIC);
3185                 break;
3186         default:
3187                 if (dch->debug & DEBUG_HW)
3188                         printk(KERN_DEBUG "%s: unknown command %x\n",
3189                             __func__, cmd);
3190                 return -1;
3191         }
3192         return 0;
3193 }
3194
3195 /*
3196  * Layer2 -> Layer 1 Transfer
3197  */
3198
3199 static int
3200 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3201 {
3202         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
3203         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
3204         struct hfc_multi        *hc = dch->hw;
3205         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3206         int                     ret = -EINVAL;
3207         unsigned int            id;
3208         u_long                  flags;
3209
3210         switch (hh->prim) {
3211         case PH_DATA_REQ:
3212                 if (skb->len < 1)
3213                         break;
3214                 spin_lock_irqsave(&hc->lock, flags);
3215                 ret = dchannel_senddata(dch, skb);
3216                 if (ret > 0) { /* direct TX */
3217                         id = hh->id; /* skb can be freed */
3218                         hfcmulti_tx(hc, dch->slot);
3219                         ret = 0;
3220                         /* start fifo */
3221                         HFC_outb(hc, R_FIFO, 0);
3222                         HFC_wait(hc);
3223                         spin_unlock_irqrestore(&hc->lock, flags);
3224                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3225                 } else
3226                         spin_unlock_irqrestore(&hc->lock, flags);
3227                 return ret;
3228         case PH_ACTIVATE_REQ:
3229                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3230                         spin_lock_irqsave(&hc->lock, flags);
3231                         ret = 0;
3232                         if (debug & DEBUG_HFCMULTI_MSG)
3233                                 printk(KERN_DEBUG
3234                                     "%s: PH_ACTIVATE port %d (0..%d)\n",
3235                                     __func__, hc->chan[dch->slot].port,
3236                                     hc->ports-1);
3237                         /* start activation */
3238                         if (hc->type == 1) {
3239                                 ph_state_change(dch);
3240                                 if (debug & DEBUG_HFCMULTI_STATE)
3241                                         printk(KERN_DEBUG
3242                                             "%s: E1 report state %x \n",
3243                                             __func__, dch->state);
3244                         } else {
3245                                 HFC_outb(hc, R_ST_SEL,
3246                                     hc->chan[dch->slot].port);
3247                                 /* undocumented: delay after R_ST_SEL */
3248                                 udelay(1);
3249                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3250                                     /* G1 */
3251                                 udelay(6); /* wait at least 5,21us */
3252                                 HFC_outb(hc, A_ST_WR_STATE, 1);
3253                                 HFC_outb(hc, A_ST_WR_STATE, 1 |
3254                                     (V_ST_ACT*3)); /* activate */
3255                                 dch->state = 1;
3256                         }
3257                         spin_unlock_irqrestore(&hc->lock, flags);
3258                 } else
3259                         ret = l1_event(dch->l1, hh->prim);
3260                 break;
3261         case PH_DEACTIVATE_REQ:
3262                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3263                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3264                         spin_lock_irqsave(&hc->lock, flags);
3265                         if (debug & DEBUG_HFCMULTI_MSG)
3266                                 printk(KERN_DEBUG
3267                                     "%s: PH_DEACTIVATE port %d (0..%d)\n",
3268                                     __func__, hc->chan[dch->slot].port,
3269                                     hc->ports-1);
3270                         /* start deactivation */
3271                         if (hc->type == 1) {
3272                                 if (debug & DEBUG_HFCMULTI_MSG)
3273                                         printk(KERN_DEBUG
3274                                             "%s: PH_DEACTIVATE no BRI\n",
3275                                             __func__);
3276                         } else {
3277                                 HFC_outb(hc, R_ST_SEL,
3278                                     hc->chan[dch->slot].port);
3279                                 /* undocumented: delay after R_ST_SEL */
3280                                 udelay(1);
3281                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3282                                     /* deactivate */
3283                                 dch->state = 1;
3284                         }
3285                         skb_queue_purge(&dch->squeue);
3286                         if (dch->tx_skb) {
3287                                 dev_kfree_skb(dch->tx_skb);
3288                                 dch->tx_skb = NULL;
3289                         }
3290                         dch->tx_idx = 0;
3291                         if (dch->rx_skb) {
3292                                 dev_kfree_skb(dch->rx_skb);
3293                                 dch->rx_skb = NULL;
3294                         }
3295                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3296                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3297                                 del_timer(&dch->timer);
3298 #ifdef FIXME
3299                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3300                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3301 #endif
3302                         ret = 0;
3303                         spin_unlock_irqrestore(&hc->lock, flags);
3304                 } else
3305                         ret = l1_event(dch->l1, hh->prim);
3306                 break;
3307         }
3308         if (!ret)
3309                 dev_kfree_skb(skb);
3310         return ret;
3311 }
3312
3313 static void
3314 deactivate_bchannel(struct bchannel *bch)
3315 {
3316         struct hfc_multi        *hc = bch->hw;
3317         u_long                  flags;
3318
3319         spin_lock_irqsave(&hc->lock, flags);
3320         if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
3321                 dev_kfree_skb(bch->next_skb);
3322                 bch->next_skb = NULL;
3323         }
3324         if (bch->tx_skb) {
3325                 dev_kfree_skb(bch->tx_skb);
3326                 bch->tx_skb = NULL;
3327         }
3328         bch->tx_idx = 0;
3329         if (bch->rx_skb) {
3330                 dev_kfree_skb(bch->rx_skb);
3331                 bch->rx_skb = NULL;
3332         }
3333         hc->chan[bch->slot].coeff_count = 0;
3334         test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
3335         test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
3336         hc->chan[bch->slot].rx_off = 0;
3337         hc->chan[bch->slot].conf = -1;
3338         mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3339         spin_unlock_irqrestore(&hc->lock, flags);
3340 }
3341
3342 static int
3343 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3344 {
3345         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3346         struct hfc_multi        *hc = bch->hw;
3347         int                     ret = -EINVAL;
3348         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3349         unsigned int            id;
3350         u_long                  flags;
3351
3352         switch (hh->prim) {
3353         case PH_DATA_REQ:
3354                 if (!skb->len)
3355                         break;
3356                 spin_lock_irqsave(&hc->lock, flags);
3357                 ret = bchannel_senddata(bch, skb);
3358                 if (ret > 0) { /* direct TX */
3359                         id = hh->id; /* skb can be freed */
3360                         hfcmulti_tx(hc, bch->slot);
3361                         ret = 0;
3362                         /* start fifo */
3363                         HFC_outb_nodebug(hc, R_FIFO, 0);
3364                         HFC_wait_nodebug(hc);
3365                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3366                                 spin_unlock_irqrestore(&hc->lock, flags);
3367                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3368                         } else
3369                                 spin_unlock_irqrestore(&hc->lock, flags);
3370                 } else
3371                         spin_unlock_irqrestore(&hc->lock, flags);
3372                 return ret;
3373         case PH_ACTIVATE_REQ:
3374                 if (debug & DEBUG_HFCMULTI_MSG)
3375                         printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3376                                 __func__, bch->slot);
3377                 spin_lock_irqsave(&hc->lock, flags);
3378                 /* activate B-channel if not already activated */
3379                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3380                         hc->chan[bch->slot].txpending = 0;
3381                         ret = mode_hfcmulti(hc, bch->slot,
3382                                 ch->protocol,
3383                                 hc->chan[bch->slot].slot_tx,
3384                                 hc->chan[bch->slot].bank_tx,
3385                                 hc->chan[bch->slot].slot_rx,
3386                                 hc->chan[bch->slot].bank_rx);
3387                         if (!ret) {
3388                                 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3389                                         && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3390                                         /* start decoder */
3391                                         hc->dtmf = 1;
3392                                         if (debug & DEBUG_HFCMULTI_DTMF)
3393                                                 printk(KERN_DEBUG
3394                                                     "%s: start dtmf decoder\n",
3395                                                         __func__);
3396                                         HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3397                                             V_RST_DTMF);
3398                                 }
3399                         }
3400                 } else
3401                         ret = 0;
3402                 spin_unlock_irqrestore(&hc->lock, flags);
3403                 if (!ret)
3404                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3405                                 GFP_KERNEL);
3406                 break;
3407         case PH_CONTROL_REQ:
3408                 spin_lock_irqsave(&hc->lock, flags);
3409                 switch (hh->id) {
3410                 case HFC_SPL_LOOP_ON: /* set sample loop */
3411                         if (debug & DEBUG_HFCMULTI_MSG)
3412                         printk(KERN_DEBUG
3413                             "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3414                             __func__, skb->len);
3415                         ret = 0;
3416                         break;
3417                 case HFC_SPL_LOOP_OFF: /* set silence */
3418                         if (debug & DEBUG_HFCMULTI_MSG)
3419                                 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3420                                     __func__);
3421                         ret = 0;
3422                         break;
3423                 default:
3424                         printk(KERN_ERR
3425                              "%s: unknown PH_CONTROL_REQ info %x\n",
3426                              __func__, hh->id);
3427                         ret = -EINVAL;
3428                 }
3429                 spin_unlock_irqrestore(&hc->lock, flags);
3430                 break;
3431         case PH_DEACTIVATE_REQ:
3432                 deactivate_bchannel(bch); /* locked there */
3433                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3434                         GFP_KERNEL);
3435                 ret = 0;
3436                 break;
3437         }
3438         if (!ret)
3439                 dev_kfree_skb(skb);
3440         return ret;
3441 }
3442
3443 /*
3444  * bchannel control function
3445  */
3446 static int
3447 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3448 {
3449         int                     ret = 0;
3450         struct dsp_features     *features =
3451                 (struct dsp_features *)(*((u_long *)&cq->p1));
3452         struct hfc_multi        *hc = bch->hw;
3453         int                     slot_tx;
3454         int                     bank_tx;
3455         int                     slot_rx;
3456         int                     bank_rx;
3457         int                     num;
3458
3459         switch (cq->op) {
3460         case MISDN_CTRL_GETOP:
3461                 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3462                         | MISDN_CTRL_RX_OFF;
3463                 break;
3464         case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3465                 hc->chan[bch->slot].rx_off = !!cq->p1;
3466                 if (!hc->chan[bch->slot].rx_off) {
3467                         /* reset fifo on rx on */
3468                         HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3469                         HFC_wait_nodebug(hc);
3470                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3471                         HFC_wait_nodebug(hc);
3472                 }
3473                 if (debug & DEBUG_HFCMULTI_MSG)
3474                         printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3475                             __func__, bch->nr, hc->chan[bch->slot].rx_off);
3476                 break;
3477         case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3478                 if (debug & DEBUG_HFCMULTI_MSG)
3479                         printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3480                             __func__);
3481                 /* create confirm */
3482                 features->hfc_id = hc->id;
3483                 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3484                         features->hfc_dtmf = 1;
3485                 features->hfc_loops = 0;
3486                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3487                         features->hfc_echocanhw = 1;
3488                 } else {
3489                         features->pcm_id = hc->pcm;
3490                         features->pcm_slots = hc->slots;
3491                         features->pcm_banks = 2;
3492                 }
3493                 break;
3494         case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3495                 slot_tx = cq->p1 & 0xff;
3496                 bank_tx = cq->p1 >> 8;
3497                 slot_rx = cq->p2 & 0xff;
3498                 bank_rx = cq->p2 >> 8;
3499                 if (debug & DEBUG_HFCMULTI_MSG)
3500                         printk(KERN_DEBUG
3501                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3502                             "slot %d bank %d (RX)\n",
3503                             __func__, slot_tx, bank_tx,
3504                             slot_rx, bank_rx);
3505                 if (slot_tx < hc->slots && bank_tx <= 2 &&
3506                     slot_rx < hc->slots && bank_rx <= 2)
3507                         hfcmulti_pcm(hc, bch->slot,
3508                             slot_tx, bank_tx, slot_rx, bank_rx);
3509                 else {
3510                         printk(KERN_WARNING
3511                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3512                             "slot %d bank %d (RX) out of range\n",
3513                             __func__, slot_tx, bank_tx,
3514                             slot_rx, bank_rx);
3515                         ret = -EINVAL;
3516                 }
3517                 break;
3518         case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3519                 if (debug & DEBUG_HFCMULTI_MSG)
3520                         printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3521                             __func__);
3522                 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3523                 break;
3524         case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3525                 num = cq->p1 & 0xff;
3526                 if (debug & DEBUG_HFCMULTI_MSG)
3527                         printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3528                             __func__, num);
3529                 if (num <= 7)
3530                         hfcmulti_conf(hc, bch->slot, num);
3531                 else {
3532                         printk(KERN_WARNING
3533                             "%s: HW_CONF_JOIN conf %d out of range\n",
3534                             __func__, num);
3535                         ret = -EINVAL;
3536                 }
3537                 break;
3538         case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3539                 if (debug & DEBUG_HFCMULTI_MSG)
3540                         printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3541                 hfcmulti_conf(hc, bch->slot, -1);
3542                 break;
3543         case MISDN_CTRL_HFC_ECHOCAN_ON:
3544                 if (debug & DEBUG_HFCMULTI_MSG)
3545                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3546                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3547                         vpm_echocan_on(hc, bch->slot, cq->p1);
3548                 else
3549                         ret = -EINVAL;
3550                 break;
3551
3552         case MISDN_CTRL_HFC_ECHOCAN_OFF:
3553                 if (debug & DEBUG_HFCMULTI_MSG)
3554                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3555                                 __func__);
3556                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3557                         vpm_echocan_off(hc, bch->slot);
3558                 else
3559                         ret = -EINVAL;
3560                 break;
3561         default:
3562                 printk(KERN_WARNING "%s: unknown Op %x\n",
3563                     __func__, cq->op);
3564                 ret = -EINVAL;
3565                 break;
3566         }
3567         return ret;
3568 }
3569
3570 static int
3571 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3572 {
3573         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3574         struct hfc_multi        *hc = bch->hw;
3575         int                     err = -EINVAL;
3576         u_long  flags;
3577
3578         if (bch->debug & DEBUG_HW)
3579                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3580                     __func__, cmd, arg);
3581         switch (cmd) {
3582         case CLOSE_CHANNEL:
3583                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3584                 if (test_bit(FLG_ACTIVE, &bch->Flags))
3585                         deactivate_bchannel(bch); /* locked there */
3586                 ch->protocol = ISDN_P_NONE;
3587                 ch->peer = NULL;
3588                 module_put(THIS_MODULE);
3589                 err = 0;
3590                 break;
3591         case CONTROL_CHANNEL:
3592                 spin_lock_irqsave(&hc->lock, flags);
3593                 err = channel_bctrl(bch, arg);
3594                 spin_unlock_irqrestore(&hc->lock, flags);
3595                 break;
3596         default:
3597                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3598                         __func__, cmd);
3599         }
3600         return err;
3601 }
3602
3603 /*
3604  * handle D-channel events
3605  *
3606  * handle state change event
3607  */
3608 static void
3609 ph_state_change(struct dchannel *dch)
3610 {
3611         struct hfc_multi *hc = dch->hw;
3612         int ch, i;
3613
3614         if (!dch) {
3615                 printk(KERN_WARNING "%s: ERROR given dch is NULL\n",
3616                     __func__);
3617                 return;
3618         }
3619         ch = dch->slot;
3620
3621         if (hc->type == 1) {
3622                 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3623                         if (debug & DEBUG_HFCMULTI_STATE)
3624                                 printk(KERN_DEBUG
3625                                     "%s: E1 TE (id=%d) newstate %x\n",
3626                                     __func__, hc->id, dch->state);
3627                 } else {
3628                         if (debug & DEBUG_HFCMULTI_STATE)
3629                                 printk(KERN_DEBUG
3630                                     "%s: E1 NT (id=%d) newstate %x\n",
3631                                     __func__, hc->id, dch->state);
3632                 }
3633                 switch (dch->state) {
3634                 case (1):
3635                         if (hc->e1_state != 1) {
3636                             for (i = 1; i <= 31; i++) {
3637                                 /* reset fifos on e1 activation */
3638                                 HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1);
3639                                 HFC_wait_nodebug(hc);
3640                                 HFC_outb_nodebug(hc,
3641                                         R_INC_RES_FIFO, V_RES_F);
3642                                 HFC_wait_nodebug(hc);
3643                             }
3644                         }
3645                         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3646                         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3647                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3648                         break;
3649
3650                 default:
3651                         if (hc->e1_state != 1)
3652                                 return;
3653                         test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3654                         _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3655                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3656                 }
3657                 hc->e1_state = dch->state;
3658         } else {
3659                 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3660                         if (debug & DEBUG_HFCMULTI_STATE)
3661                                 printk(KERN_DEBUG
3662                                     "%s: S/T TE newstate %x\n",
3663                                     __func__, dch->state);
3664                         switch (dch->state) {
3665                         case (0):
3666                                 l1_event(dch->l1, HW_RESET_IND);
3667                                 break;
3668                         case (3):
3669                                 l1_event(dch->l1, HW_DEACT_IND);
3670                                 break;
3671                         case (5):
3672                         case (8):
3673                                 l1_event(dch->l1, ANYSIGNAL);
3674                                 break;
3675                         case (6):
3676                                 l1_event(dch->l1, INFO2);
3677                                 break;
3678                         case (7):
3679                                 l1_event(dch->l1, INFO4_P8);
3680                                 break;
3681                         }
3682                 } else {
3683                         if (debug & DEBUG_HFCMULTI_STATE)
3684                                 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3685                                     __func__, dch->state);
3686                         switch (dch->state) {
3687                         case (2):
3688                                 if (hc->chan[ch].nt_timer == 0) {
3689                                         hc->chan[ch].nt_timer = -1;
3690                                         HFC_outb(hc, R_ST_SEL,
3691                                             hc->chan[ch].port);
3692                                         /* undocumented: delay after R_ST_SEL */
3693                                         udelay(1);
3694                                         HFC_outb(hc, A_ST_WR_STATE, 4 |
3695                                             V_ST_LD_STA); /* G4 */
3696                                         udelay(6); /* wait at least 5,21us */
3697                                         HFC_outb(hc, A_ST_WR_STATE, 4);
3698                                         dch->state = 4;
3699                                 } else {
3700                                         /* one extra count for the next event */
3701                                         hc->chan[ch].nt_timer =
3702                                             nt_t1_count[poll_timer] + 1;
3703                                         HFC_outb(hc, R_ST_SEL,
3704                                             hc->chan[ch].port);
3705                                         /* undocumented: delay after R_ST_SEL */
3706                                         udelay(1);
3707                                         /* allow G2 -> G3 transition */
3708                                         HFC_outb(hc, A_ST_WR_STATE, 2 |
3709                                             V_SET_G2_G3);
3710                                 }
3711                                 break;
3712                         case (1):
3713                                 hc->chan[ch].nt_timer = -1;
3714                                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3715                                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3716                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3717                                 break;
3718                         case (4):
3719                                 hc->chan[ch].nt_timer = -1;
3720                                 break;
3721                         case (3):
3722                                 hc->chan[ch].nt_timer = -1;
3723                                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3724                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3725                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3726                                 break;
3727                         }
3728                 }
3729         }
3730 }
3731
3732 /*
3733  * called for card mode init message
3734  */
3735
3736 static void
3737 hfcmulti_initmode(struct dchannel *dch)
3738 {
3739         struct hfc_multi *hc = dch->hw;
3740         u_char          a_st_wr_state, r_e1_wr_sta;
3741         int             i, pt;
3742
3743         if (debug & DEBUG_HFCMULTI_INIT)
3744                 printk(KERN_DEBUG "%s: entered\n", __func__);
3745
3746         if (hc->type == 1) {
3747                 hc->chan[hc->dslot].slot_tx = -1;
3748                 hc->chan[hc->dslot].slot_rx = -1;
3749                 hc->chan[hc->dslot].conf = -1;
3750                 if (hc->dslot) {
3751                         mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3752                                 -1, 0, -1, 0);
3753                         dch->timer.function = (void *) hfcmulti_dbusy_timer;
3754                         dch->timer.data = (long) dch;
3755                         init_timer(&dch->timer);
3756                 }
3757                 for (i = 1; i <= 31; i++) {
3758                         if (i == hc->dslot)
3759                                 continue;
3760                         hc->chan[i].slot_tx = -1;
3761                         hc->chan[i].slot_rx = -1;
3762                         hc->chan[i].conf = -1;
3763                         mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3764                 }
3765                 /* E1 */
3766                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3767                         HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3768                         HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3769                 }
3770                 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3771                         HFC_outb(hc, R_RX0, 0);
3772                         hc->hw.r_tx0 = 0 | V_OUT_EN;
3773                 } else {
3774                         HFC_outb(hc, R_RX0, 1);
3775                         hc->hw.r_tx0 = 1 | V_OUT_EN;
3776                 }
3777                 hc->hw.r_tx1 = V_ATX | V_NTRI;
3778                 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3779                 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3780                 HFC_outb(hc, R_TX_FR0, 0x00);
3781                 HFC_outb(hc, R_TX_FR1, 0xf8);
3782
3783                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3784                         HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3785
3786                 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3787
3788                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3789                         HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3790
3791                 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3792                         if (debug & DEBUG_HFCMULTI_INIT)
3793                                 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3794                                     __func__);
3795                         r_e1_wr_sta = 0; /* G0 */
3796                         hc->e1_getclock = 0;
3797                 } else {
3798                         if (debug & DEBUG_HFCMULTI_INIT)
3799                                 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3800                                     __func__);
3801                         r_e1_wr_sta = 0; /* F0 */
3802                         hc->e1_getclock = 1;
3803                 }
3804                 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3805                         HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3806                 else
3807                         HFC_outb(hc, R_SYNC_OUT, 0);
3808                 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3809                         hc->e1_getclock = 1;
3810                 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3811                         hc->e1_getclock = 0;
3812                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3813                         /* SLAVE (clock master) */
3814                         if (debug & DEBUG_HFCMULTI_INIT)
3815                                 printk(KERN_DEBUG
3816                                     "%s: E1 port is clock master "
3817                                     "(clock from PCM)\n", __func__);
3818                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3819                 } else {
3820                         if (hc->e1_getclock) {
3821                                 /* MASTER (clock slave) */
3822                                 if (debug & DEBUG_HFCMULTI_INIT)
3823                                         printk(KERN_DEBUG
3824                                             "%s: E1 port is clock slave "
3825                                             "(clock to PCM)\n", __func__);
3826                                 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3827                         } else {
3828                                 /* MASTER (clock master) */
3829                                 if (debug & DEBUG_HFCMULTI_INIT)
3830                                         printk(KERN_DEBUG "%s: E1 port is "
3831                                             "clock master "
3832                                             "(clock from QUARTZ)\n",
3833                                             __func__);
3834                                 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3835                                     V_PCM_SYNC | V_JATT_OFF);
3836                                 HFC_outb(hc, R_SYNC_OUT, 0);
3837                         }
3838                 }
3839                 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3840                 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3841                 HFC_outb(hc, R_PWM0, 0x50);
3842                 HFC_outb(hc, R_PWM1, 0xff);
3843                 /* state machine setup */
3844                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3845                 udelay(6); /* wait at least 5,21us */
3846                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3847                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3848                         hc->syncronized = 0;
3849                         plxsd_checksync(hc, 0);
3850                 }
3851         } else {
3852                 i = dch->slot;
3853                 hc->chan[i].slot_tx = -1;
3854                 hc->chan[i].slot_rx = -1;
3855                 hc->chan[i].conf = -1;
3856                 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3857                 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3858                 dch->timer.data = (long) dch;
3859                 init_timer(&dch->timer);
3860                 hc->chan[i - 2].slot_tx = -1;
3861                 hc->chan[i - 2].slot_rx = -1;
3862                 hc->chan[i - 2].conf = -1;
3863                 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3864                 hc->chan[i - 1].slot_tx = -1;
3865                 hc->chan[i - 1].slot_rx = -1;
3866                 hc->chan[i - 1].conf = -1;
3867                 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3868                 /* ST */
3869                 pt = hc->chan[i].port;
3870                 /* select interface */
3871                 HFC_outb(hc, R_ST_SEL, pt);
3872                 /* undocumented: delay after R_ST_SEL */
3873                 udelay(1);
3874                 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3875                         if (debug & DEBUG_HFCMULTI_INIT)
3876                                 printk(KERN_DEBUG
3877                                     "%s: ST port %d is NT-mode\n",
3878                                     __func__, pt);
3879                         /* clock delay */
3880                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3881                         a_st_wr_state = 1; /* G1 */
3882                         hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3883                 } else {
3884                         if (debug & DEBUG_HFCMULTI_INIT)
3885                                 printk(KERN_DEBUG
3886                                     "%s: ST port %d is TE-mode\n",
3887                                     __func__, pt);
3888                         /* clock delay */
3889                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3890                         a_st_wr_state = 2; /* F2 */
3891                         hc->hw.a_st_ctrl0[pt] = 0;
3892                 }
3893                 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3894                         hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3895                 /* line setup */
3896                 HFC_outb(hc, A_ST_CTRL0,  hc->hw.a_st_ctrl0[pt]);
3897                 /* disable E-channel */
3898                 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3899                     test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3900                         HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3901                 else
3902                         HFC_outb(hc, A_ST_CTRL1, 0);
3903                 /* enable B-channel receive */
3904                 HFC_outb(hc, A_ST_CTRL2,  V_B1_RX_EN | V_B2_RX_EN);
3905                 /* state machine setup */
3906                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3907                 udelay(6); /* wait at least 5,21us */
3908                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
3909                 hc->hw.r_sci_msk |= 1 << pt;
3910                 /* state machine interrupts */
3911                 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
3912                 /* unset sync on port */
3913                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3914                         hc->syncronized &=
3915                            ~(1 << hc->chan[dch->slot].port);
3916                         plxsd_checksync(hc, 0);
3917                 }
3918         }
3919         if (debug & DEBUG_HFCMULTI_INIT)
3920                 printk("%s: done\n", __func__);
3921 }
3922
3923
3924 static int
3925 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
3926     struct channel_req *rq)
3927 {
3928         int     err = 0;
3929         u_long  flags;
3930
3931         if (debug & DEBUG_HW_OPEN)
3932                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
3933                     dch->dev.id, __builtin_return_address(0));
3934         if (rq->protocol == ISDN_P_NONE)
3935                 return -EINVAL;
3936         if ((dch->dev.D.protocol != ISDN_P_NONE) &&
3937             (dch->dev.D.protocol != rq->protocol)) {
3938             if (debug & DEBUG_HFCMULTI_MODE)
3939                 printk(KERN_WARNING "%s: change protocol %x to %x\n",
3940                     __func__, dch->dev.D.protocol, rq->protocol);
3941         }
3942         if ((dch->dev.D.protocol == ISDN_P_TE_S0)
3943          && (rq->protocol != ISDN_P_TE_S0))
3944                 l1_event(dch->l1, CLOSE_CHANNEL);
3945         if (dch->dev.D.protocol != rq->protocol) {
3946                 if (rq->protocol == ISDN_P_TE_S0) {
3947                         err = create_l1(dch, hfcm_l1callback);
3948                         if (err)
3949                                 return err;
3950                 }
3951                 dch->dev.D.protocol = rq->protocol;
3952                 spin_lock_irqsave(&hc->lock, flags);
3953                 hfcmulti_initmode(dch);
3954                 spin_unlock_irqrestore(&hc->lock, flags);
3955         }
3956
3957         if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
3958             ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
3959             ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
3960             ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
3961                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
3962                     0, NULL, GFP_KERNEL);
3963         }
3964         rq->ch = &dch->dev.D;
3965         if (!try_module_get(THIS_MODULE))
3966                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3967         return 0;
3968 }
3969
3970 static int
3971 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
3972     struct channel_req *rq)
3973 {
3974         struct bchannel *bch;
3975         int             ch;
3976
3977         if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
3978                 return -EINVAL;
3979         if (rq->protocol == ISDN_P_NONE)
3980                 return -EINVAL;
3981         if (hc->type == 1)
3982                 ch = rq->adr.channel;
3983         else
3984                 ch = (rq->adr.channel - 1) + (dch->slot - 2);
3985         bch = hc->chan[ch].bch;
3986         if (!bch) {
3987                 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
3988                     __func__, ch);
3989                 return -EINVAL;
3990         }
3991         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
3992                 return -EBUSY; /* b-channel can be only open once */
3993         bch->ch.protocol = rq->protocol;
3994         hc->chan[ch].rx_off = 0;
3995         rq->ch = &bch->ch;
3996         if (!try_module_get(THIS_MODULE))
3997                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3998         return 0;
3999 }
4000
4001 /*
4002  * device control function
4003  */
4004 static int
4005 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4006 {
4007         int     ret = 0;
4008
4009         switch (cq->op) {
4010         case MISDN_CTRL_GETOP:
4011                 cq->op = 0;
4012                 break;
4013         default:
4014                 printk(KERN_WARNING "%s: unknown Op %x\n",
4015                     __func__, cq->op);
4016                 ret = -EINVAL;
4017                 break;
4018         }
4019         return ret;
4020 }
4021
4022 static int
4023 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4024 {
4025         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
4026         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
4027         struct hfc_multi        *hc = dch->hw;
4028         struct channel_req      *rq;
4029         int                     err = 0;
4030         u_long                  flags;
4031
4032         if (dch->debug & DEBUG_HW)
4033                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4034                     __func__, cmd, arg);
4035         switch (cmd) {
4036         case OPEN_CHANNEL:
4037                 rq = arg;
4038                 switch (rq->protocol) {
4039                 case ISDN_P_TE_S0:
4040                 case ISDN_P_NT_S0:
4041                         if (hc->type == 1) {
4042                                 err = -EINVAL;
4043                                 break;
4044                         }
4045                         err = open_dchannel(hc, dch, rq); /* locked there */
4046                         break;
4047                 case ISDN_P_TE_E1:
4048                 case ISDN_P_NT_E1:
4049                         if (hc->type != 1) {
4050                                 err = -EINVAL;
4051                                 break;
4052                         }
4053                         err = open_dchannel(hc, dch, rq); /* locked there */
4054                         break;
4055                 default:
4056                         spin_lock_irqsave(&hc->lock, flags);
4057                         err = open_bchannel(hc, dch, rq);
4058                         spin_unlock_irqrestore(&hc->lock, flags);
4059                 }
4060                 break;
4061         case CLOSE_CHANNEL:
4062                 if (debug & DEBUG_HW_OPEN)
4063                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4064                             __func__, dch->dev.id,
4065                             __builtin_return_address(0));
4066                 module_put(THIS_MODULE);
4067                 break;
4068         case CONTROL_CHANNEL:
4069                 spin_lock_irqsave(&hc->lock, flags);
4070                 err = channel_dctrl(dch, arg);
4071                 spin_unlock_irqrestore(&hc->lock, flags);
4072                 break;
4073         default:
4074                 if (dch->debug & DEBUG_HW)
4075                         printk(KERN_DEBUG "%s: unknown command %x\n",
4076                             __func__, cmd);
4077                 err = -EINVAL;
4078         }
4079         return err;
4080 }
4081
4082 /*
4083  * initialize the card
4084  */
4085
4086 /*
4087  * start timer irq, wait some time and check if we have interrupts.
4088  * if not, reset chip and try again.
4089  */
4090 static int
4091 init_card(struct hfc_multi *hc)
4092 {
4093         int     err = -EIO;
4094         u_long  flags;
4095         u_short *plx_acc;
4096         u_long  plx_flags;
4097
4098         if (debug & DEBUG_HFCMULTI_INIT)
4099                 printk(KERN_DEBUG "%s: entered\n", __func__);
4100
4101         spin_lock_irqsave(&hc->lock, flags);
4102         /* set interrupts but leave global interrupt disabled */
4103         hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4104         disable_hwirq(hc);
4105         spin_unlock_irqrestore(&hc->lock, flags);
4106
4107         if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
4108             "HFC-multi", hc)) {
4109                 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4110                     hc->pci_dev->irq);
4111                 return -EIO;
4112         }
4113         hc->irq = hc->pci_dev->irq;
4114
4115         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4116                 spin_lock_irqsave(&plx_lock, plx_flags);
4117                 plx_acc = (u_short *)(hc->plx_membase+PLX_INTCSR);
4118                 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4119                         plx_acc); /* enable PCI & LINT1 irq */
4120                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4121         }
4122
4123         if (debug & DEBUG_HFCMULTI_INIT)
4124                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4125                     __func__, hc->irq, hc->irqcnt);
4126         err = init_chip(hc);
4127         if (err)
4128                 goto error;
4129         /*
4130          * Finally enable IRQ output
4131          * this is only allowed, if an IRQ routine is allready
4132          * established for this HFC, so don't do that earlier
4133          */
4134         spin_lock_irqsave(&hc->lock, flags);
4135         enable_hwirq(hc);
4136         spin_unlock_irqrestore(&hc->lock, flags);
4137         /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4138         set_current_state(TASK_UNINTERRUPTIBLE);
4139         schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4140         /* turn IRQ off until chip is completely initialized */
4141         spin_lock_irqsave(&hc->lock, flags);
4142         disable_hwirq(hc);
4143         spin_unlock_irqrestore(&hc->lock, flags);
4144         if (debug & DEBUG_HFCMULTI_INIT)
4145                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4146                     __func__, hc->irq, hc->irqcnt);
4147         if (hc->irqcnt) {
4148                 if (debug & DEBUG_HFCMULTI_INIT)
4149                         printk(KERN_DEBUG "%s: done\n", __func__);
4150
4151                 return 0;
4152         }
4153         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4154                 printk(KERN_INFO "ignoring missing interrupts\n");
4155                 return 0;
4156         }
4157
4158         printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4159                 hc->irq);
4160
4161         err = -EIO;
4162
4163 error:
4164         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4165                 spin_lock_irqsave(&plx_lock, plx_flags);
4166                 plx_acc = (u_short *)(hc->plx_membase+PLX_INTCSR);
4167                 writew(0x00, plx_acc); /*disable IRQs*/
4168                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4169         }
4170
4171         if (debug & DEBUG_HFCMULTI_INIT)
4172                 printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq);
4173         if (hc->irq) {
4174                 free_irq(hc->irq, hc);
4175                 hc->irq = 0;
4176         }
4177
4178         if (debug & DEBUG_HFCMULTI_INIT)
4179                 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4180         return err;
4181 }
4182
4183 /*
4184  * find pci device and set it up
4185  */
4186
4187 static int
4188 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4189                 const struct pci_device_id *ent)
4190 {
4191         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4192
4193         printk(KERN_INFO
4194             "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4195             m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4196
4197         hc->pci_dev = pdev;
4198         if (m->clock2)
4199                 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4200
4201         if (ent->device == 0xB410) {
4202                 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4203                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4204                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4205                 hc->slots = 32;
4206         }
4207
4208         if (hc->pci_dev->irq <= 0) {
4209                 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4210                 return -EIO;
4211         }
4212         if (pci_enable_device(hc->pci_dev)) {
4213                 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4214                 return -EIO;
4215         }
4216         hc->leds = m->leds;
4217         hc->ledstate = 0xAFFEAFFE;
4218         hc->opticalsupport = m->opticalsupport;
4219
4220         /* set memory access methods */
4221         if (m->io_mode) /* use mode from card config */
4222                 hc->io_mode = m->io_mode;
4223         switch (hc->io_mode) {
4224         case HFC_IO_MODE_PLXSD:
4225                 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4226                 hc->slots = 128; /* required */
4227                 /* fall through */
4228         case HFC_IO_MODE_PCIMEM:
4229                 hc->HFC_outb = HFC_outb_pcimem;
4230                 hc->HFC_inb = HFC_inb_pcimem;
4231                 hc->HFC_inw = HFC_inw_pcimem;
4232                 hc->HFC_wait = HFC_wait_pcimem;
4233                 hc->read_fifo = read_fifo_pcimem;
4234                 hc->write_fifo = write_fifo_pcimem;
4235                 break;
4236         case HFC_IO_MODE_REGIO:
4237                 hc->HFC_outb = HFC_outb_regio;
4238                 hc->HFC_inb = HFC_inb_regio;
4239                 hc->HFC_inw = HFC_inw_regio;
4240                 hc->HFC_wait = HFC_wait_regio;
4241                 hc->read_fifo = read_fifo_regio;
4242                 hc->write_fifo = write_fifo_regio;
4243                 break;
4244         default:
4245                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4246                 pci_disable_device(hc->pci_dev);
4247                 return -EIO;
4248         }
4249         hc->HFC_outb_nodebug = hc->HFC_outb;
4250         hc->HFC_inb_nodebug = hc->HFC_inb;
4251         hc->HFC_inw_nodebug = hc->HFC_inw;
4252         hc->HFC_wait_nodebug = hc->HFC_wait;
4253 #ifdef HFC_REGISTER_DEBUG
4254         hc->HFC_outb = HFC_outb_debug;
4255         hc->HFC_inb = HFC_inb_debug;
4256         hc->HFC_inw = HFC_inw_debug;
4257         hc->HFC_wait = HFC_wait_debug;
4258 #endif
4259         hc->pci_iobase = 0;
4260         hc->pci_membase = NULL;
4261         hc->plx_membase = NULL;
4262
4263         switch (hc->io_mode) {
4264         case HFC_IO_MODE_PLXSD:
4265                 hc->plx_origmembase =  hc->pci_dev->resource[0].start;
4266                 /* MEMBASE 1 is PLX PCI Bridge */
4267
4268                 if (!hc->plx_origmembase) {
4269                         printk(KERN_WARNING
4270                           "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4271                         pci_disable_device(hc->pci_dev);
4272                         return -EIO;
4273                 }
4274
4275                 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4276                 if (!hc->plx_membase) {
4277                         printk(KERN_WARNING
4278                             "HFC-multi: failed to remap plx address space. "
4279                             "(internal error)\n");
4280                         pci_disable_device(hc->pci_dev);
4281                         return -EIO;
4282                 }
4283                 printk(KERN_INFO
4284                     "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4285                     (u_long)hc->plx_membase, hc->plx_origmembase);
4286
4287                 hc->pci_origmembase =  hc->pci_dev->resource[2].start;
4288                     /* MEMBASE 1 is PLX PCI Bridge */
4289                 if (!hc->pci_origmembase) {
4290                         printk(KERN_WARNING
4291                             "HFC-multi: No IO-Memory for PCI card found\n");
4292                         pci_disable_device(hc->pci_dev);
4293                         return -EIO;
4294                 }
4295
4296                 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4297                 if (!hc->pci_membase) {
4298                         printk(KERN_WARNING "HFC-multi: failed to remap io "
4299                             "address space. (internal error)\n");
4300                         pci_disable_device(hc->pci_dev);
4301                         return -EIO;
4302                 }
4303
4304                 printk(KERN_INFO
4305                     "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4306                     "leds-type %d\n",
4307                     hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4308                     hc->pci_dev->irq, HZ, hc->leds);
4309                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4310                 break;
4311         case HFC_IO_MODE_PCIMEM:
4312                 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4313                 if (!hc->pci_origmembase) {
4314                         printk(KERN_WARNING
4315                             "HFC-multi: No IO-Memory for PCI card found\n");
4316                         pci_disable_device(hc->pci_dev);
4317                         return -EIO;
4318                 }
4319
4320                 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4321                 if (!hc->pci_membase) {
4322                         printk(KERN_WARNING
4323                             "HFC-multi: failed to remap io address space. "
4324                             "(internal error)\n");
4325                         pci_disable_device(hc->pci_dev);
4326                         return -EIO;
4327                 }
4328                 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
4329                     "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4330                     hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4331                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4332                 break;
4333         case HFC_IO_MODE_REGIO:
4334                 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4335                 if (!hc->pci_iobase) {
4336                         printk(KERN_WARNING
4337                                 "HFC-multi: No IO for PCI card found\n");
4338                         pci_disable_device(hc->pci_dev);
4339                         return -EIO;
4340                 }
4341
4342                 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4343                         printk(KERN_WARNING "HFC-multi: failed to request "
4344                             "address space at 0x%08lx (internal error)\n",
4345                             hc->pci_iobase);
4346                         pci_disable_device(hc->pci_dev);
4347                         return -EIO;
4348                 }
4349
4350                 printk(KERN_INFO
4351                     "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4352                     m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4353                     hc->pci_dev->irq, HZ, hc->leds);
4354                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4355                 break;
4356         default:
4357                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4358                 pci_disable_device(hc->pci_dev);
4359                 return -EIO;
4360         }
4361
4362         pci_set_drvdata(hc->pci_dev, hc);
4363
4364         /* At this point the needed PCI config is done */
4365         /* fifos are still not enabled */
4366         return 0;
4367 }
4368
4369
4370 /*
4371  * remove port
4372  */
4373
4374 static void
4375 release_port(struct hfc_multi *hc, struct dchannel *dch)
4376 {
4377         int     pt, ci, i = 0;
4378         u_long  flags;
4379         struct bchannel *pb;
4380
4381         ci = dch->slot;
4382         pt = hc->chan[ci].port;
4383
4384         if (debug & DEBUG_HFCMULTI_INIT)
4385                 printk(KERN_DEBUG "%s: entered for port %d\n",
4386                         __func__, pt + 1);
4387
4388         if (pt >= hc->ports) {
4389                 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4390                      __func__, pt + 1);
4391                 return;
4392         }
4393
4394         if (debug & DEBUG_HFCMULTI_INIT)
4395                 printk(KERN_DEBUG "%s: releasing port=%d\n",
4396                     __func__, pt + 1);
4397
4398         if (dch->dev.D.protocol == ISDN_P_TE_S0)
4399                 l1_event(dch->l1, CLOSE_CHANNEL);
4400
4401         hc->chan[ci].dch = NULL;
4402
4403         if (hc->created[pt]) {
4404                 hc->created[pt] = 0;
4405                 mISDN_unregister_device(&dch->dev);
4406         }
4407
4408         spin_lock_irqsave(&hc->lock, flags);
4409
4410         if (dch->timer.function) {
4411                 del_timer(&dch->timer);
4412                 dch->timer.function = NULL;
4413         }
4414
4415         if (hc->type == 1) { /* E1 */
4416                 /* remove sync */
4417                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4418                         hc->syncronized = 0;
4419                         plxsd_checksync(hc, 1);
4420                 }
4421                 /* free channels */
4422                 for (i = 0; i <= 31; i++) {
4423                         if (hc->chan[i].bch) {
4424                                 if (debug & DEBUG_HFCMULTI_INIT)
4425                                         printk(KERN_DEBUG
4426                                             "%s: free port %d channel %d\n",
4427                                             __func__, hc->chan[i].port+1, i);
4428                                 pb = hc->chan[i].bch;
4429                                 hc->chan[i].bch = NULL;
4430                                 spin_unlock_irqrestore(&hc->lock, flags);
4431                                 mISDN_freebchannel(pb);
4432                                 kfree(pb);
4433                                 kfree(hc->chan[i].coeff);
4434                                 spin_lock_irqsave(&hc->lock, flags);
4435                         }
4436                 }
4437         } else {
4438                 /* remove sync */
4439                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4440                         hc->syncronized &=
4441                            ~(1 << hc->chan[ci].port);
4442                         plxsd_checksync(hc, 1);
4443                 }
4444                 /* free channels */
4445                 if (hc->chan[ci - 2].bch) {
4446                         if (debug & DEBUG_HFCMULTI_INIT)
4447                                 printk(KERN_DEBUG
4448                                     "%s: free port %d channel %d\n",
4449                                     __func__, hc->chan[ci - 2].port+1,
4450                                     ci - 2);
4451                         pb = hc->chan[ci - 2].bch;
4452                         hc->chan[ci - 2].bch = NULL;
4453                         spin_unlock_irqrestore(&hc->lock, flags);
4454                         mISDN_freebchannel(pb);
4455                         kfree(pb);
4456                         kfree(hc->chan[ci - 2].coeff);
4457                         spin_lock_irqsave(&hc->lock, flags);
4458                 }
4459                 if (hc->chan[ci - 1].bch) {
4460                         if (debug & DEBUG_HFCMULTI_INIT)
4461                                 printk(KERN_DEBUG
4462                                     "%s: free port %d channel %d\n",
4463                                     __func__, hc->chan[ci - 1].port+1,
4464                                     ci - 1);
4465                         pb = hc->chan[ci - 1].bch;
4466                         hc->chan[ci - 1].bch = NULL;
4467                         spin_unlock_irqrestore(&hc->lock, flags);
4468                         mISDN_freebchannel(pb);
4469                         kfree(pb);
4470                         kfree(hc->chan[ci - 1].coeff);
4471                         spin_lock_irqsave(&hc->lock, flags);
4472                 }
4473         }
4474
4475         spin_unlock_irqrestore(&hc->lock, flags);
4476
4477         if (debug & DEBUG_HFCMULTI_INIT)
4478                 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4479         mISDN_freedchannel(dch);
4480         kfree(dch);
4481
4482         if (debug & DEBUG_HFCMULTI_INIT)
4483                 printk(KERN_DEBUG "%s: done!\n", __func__);
4484 }
4485
4486 static void
4487 release_card(struct hfc_multi *hc)
4488 {
4489         u_long  flags;
4490         int     ch;
4491
4492         if (debug & DEBUG_HFCMULTI_INIT)
4493                 printk(KERN_WARNING "%s: release card (%d) entered\n",
4494                     __func__, hc->id);
4495
4496         spin_lock_irqsave(&hc->lock, flags);
4497         disable_hwirq(hc);
4498         spin_unlock_irqrestore(&hc->lock, flags);
4499
4500         udelay(1000);
4501
4502         /* dimm leds */
4503         if (hc->leds)
4504                 hfcmulti_leds(hc);
4505
4506         /* disable D-channels & B-channels */
4507         if (debug & DEBUG_HFCMULTI_INIT)
4508                 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4509                     __func__);
4510         for (ch = 0; ch <= 31; ch++) {
4511                 if (hc->chan[ch].dch)
4512                         release_port(hc, hc->chan[ch].dch);
4513         }
4514
4515         /* release hardware & irq */
4516         if (hc->irq) {
4517                 if (debug & DEBUG_HFCMULTI_INIT)
4518                         printk(KERN_WARNING "%s: free irq %d\n",
4519                             __func__, hc->irq);
4520                 free_irq(hc->irq, hc);
4521                 hc->irq = 0;
4522
4523         }
4524         release_io_hfcmulti(hc);
4525
4526         if (debug & DEBUG_HFCMULTI_INIT)
4527                 printk(KERN_WARNING "%s: remove instance from list\n",
4528                      __func__);
4529         list_del(&hc->list);
4530
4531         if (debug & DEBUG_HFCMULTI_INIT)
4532                 printk(KERN_WARNING "%s: delete instance\n", __func__);
4533         if (hc == syncmaster)
4534                 syncmaster = NULL;
4535         kfree(hc);
4536         if (debug & DEBUG_HFCMULTI_INIT)
4537                 printk(KERN_WARNING "%s: card successfully removed\n",
4538                     __func__);
4539 }
4540
4541 static int
4542 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4543 {
4544         struct dchannel *dch;
4545         struct bchannel *bch;
4546         int             ch, ret = 0;
4547         char            name[MISDN_MAX_IDLEN];
4548
4549         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4550         if (!dch)
4551                 return -ENOMEM;
4552         dch->debug = debug;
4553         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4554         dch->hw = hc;
4555         dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4556         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4557             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4558         dch->dev.D.send = handle_dmsg;
4559         dch->dev.D.ctrl = hfcm_dctrl;
4560         dch->dev.nrbchan = (hc->dslot)?30:31;
4561         dch->slot = hc->dslot;
4562         hc->chan[hc->dslot].dch = dch;
4563         hc->chan[hc->dslot].port = 0;
4564         hc->chan[hc->dslot].nt_timer = -1;
4565         for (ch = 1; ch <= 31; ch++) {
4566                 if (ch == hc->dslot) /* skip dchannel */
4567                         continue;
4568                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4569                 if (!bch) {
4570                         printk(KERN_ERR "%s: no memory for bchannel\n",
4571                             __func__);
4572                         ret = -ENOMEM;
4573                         goto free_chan;
4574                 }
4575                 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4576                 if (!hc->chan[ch].coeff) {
4577                         printk(KERN_ERR "%s: no memory for coeffs\n",
4578                             __func__);
4579                         ret = -ENOMEM;
4580                         goto free_chan;
4581                 }
4582                 bch->nr = ch;
4583                 bch->slot = ch;
4584                 bch->debug = debug;
4585                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4586                 bch->hw = hc;
4587                 bch->ch.send = handle_bmsg;
4588                 bch->ch.ctrl = hfcm_bctrl;
4589                 bch->ch.nr = ch;
4590                 list_add(&bch->ch.list, &dch->dev.bchannels);
4591                 hc->chan[ch].bch = bch;
4592                 hc->chan[ch].port = 0;
4593                 set_channelmap(bch->nr, dch->dev.channelmap);
4594         }
4595         /* set optical line type */
4596         if (port[Port_cnt] & 0x001) {
4597                 if (!m->opticalsupport)  {
4598                         printk(KERN_INFO
4599                             "This board has no optical "
4600                             "support\n");
4601                 } else {
4602                         if (debug & DEBUG_HFCMULTI_INIT)
4603                                 printk(KERN_DEBUG
4604                                     "%s: PORT set optical "
4605                                     "interfacs: card(%d) "
4606                                     "port(%d)\n",
4607                                     __func__,
4608                                     HFC_cnt + 1, 1);
4609                         test_and_set_bit(HFC_CFG_OPTICAL,
4610                             &hc->chan[hc->dslot].cfg);
4611                 }
4612         }
4613         /* set LOS report */
4614         if (port[Port_cnt] & 0x004) {
4615                 if (debug & DEBUG_HFCMULTI_INIT)
4616                         printk(KERN_DEBUG "%s: PORT set "
4617                             "LOS report: card(%d) port(%d)\n",
4618                             __func__, HFC_cnt + 1, 1);
4619                 test_and_set_bit(HFC_CFG_REPORT_LOS,
4620                     &hc->chan[hc->dslot].cfg);
4621         }
4622         /* set AIS report */
4623         if (port[Port_cnt] & 0x008) {
4624                 if (debug & DEBUG_HFCMULTI_INIT)
4625                         printk(KERN_DEBUG "%s: PORT set "
4626                             "AIS report: card(%d) port(%d)\n",
4627                             __func__, HFC_cnt + 1, 1);
4628                 test_and_set_bit(HFC_CFG_REPORT_AIS,
4629                     &hc->chan[hc->dslot].cfg);
4630         }
4631         /* set SLIP report */
4632         if (port[Port_cnt] & 0x010) {
4633                 if (debug & DEBUG_HFCMULTI_INIT)
4634                         printk(KERN_DEBUG
4635                             "%s: PORT set SLIP report: "
4636                             "card(%d) port(%d)\n",
4637                             __func__, HFC_cnt + 1, 1);
4638                 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4639                     &hc->chan[hc->dslot].cfg);
4640         }
4641         /* set RDI report */
4642         if (port[Port_cnt] & 0x020) {
4643                 if (debug & DEBUG_HFCMULTI_INIT)
4644                         printk(KERN_DEBUG
4645                             "%s: PORT set RDI report: "
4646                             "card(%d) port(%d)\n",
4647                             __func__, HFC_cnt + 1, 1);
4648                 test_and_set_bit(HFC_CFG_REPORT_RDI,
4649                     &hc->chan[hc->dslot].cfg);
4650         }
4651         /* set CRC-4 Mode */
4652         if (!(port[Port_cnt] & 0x100)) {
4653                 if (debug & DEBUG_HFCMULTI_INIT)
4654                         printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4655                                 " card(%d) port(%d)\n",
4656                                 __func__, HFC_cnt + 1, 1);
4657                 test_and_set_bit(HFC_CFG_CRC4,
4658                     &hc->chan[hc->dslot].cfg);
4659         } else {
4660                 if (debug & DEBUG_HFCMULTI_INIT)
4661                         printk(KERN_DEBUG "%s: PORT turn off CRC4"
4662                                 " report: card(%d) port(%d)\n",
4663                                 __func__, HFC_cnt + 1, 1);
4664         }
4665         /* set forced clock */
4666         if (port[Port_cnt] & 0x0200) {
4667                 if (debug & DEBUG_HFCMULTI_INIT)
4668                         printk(KERN_DEBUG "%s: PORT force getting clock from "
4669                                 "E1: card(%d) port(%d)\n",
4670                                 __func__, HFC_cnt + 1, 1);
4671                 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4672         } else
4673         if (port[Port_cnt] & 0x0400) {
4674                 if (debug & DEBUG_HFCMULTI_INIT)
4675                         printk(KERN_DEBUG "%s: PORT force putting clock to "
4676                                 "E1: card(%d) port(%d)\n",
4677                                 __func__, HFC_cnt + 1, 1);
4678                 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4679         }
4680         /* set JATT PLL */
4681         if (port[Port_cnt] & 0x0800) {
4682                 if (debug & DEBUG_HFCMULTI_INIT)
4683                         printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4684                                 "E1: card(%d) port(%d)\n",
4685                                 __func__, HFC_cnt + 1, 1);
4686                 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4687         }
4688         /* set elastic jitter buffer */
4689         if (port[Port_cnt] & 0x3000) {
4690                 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4691                 if (debug & DEBUG_HFCMULTI_INIT)
4692                         printk(KERN_DEBUG
4693                             "%s: PORT set elastic "
4694                             "buffer to %d: card(%d) port(%d)\n",
4695                             __func__, hc->chan[hc->dslot].jitter,
4696                             HFC_cnt + 1, 1);
4697         } else
4698                 hc->chan[hc->dslot].jitter = 2; /* default */
4699         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4700         ret = mISDN_register_device(&dch->dev, name);
4701         if (ret)
4702                 goto free_chan;
4703         hc->created[0] = 1;
4704         return ret;
4705 free_chan:
4706         release_port(hc, dch);
4707         return ret;
4708 }
4709
4710 static int
4711 init_multi_port(struct hfc_multi *hc, int pt)
4712 {
4713         struct dchannel *dch;
4714         struct bchannel *bch;
4715         int             ch, i, ret = 0;
4716         char            name[MISDN_MAX_IDLEN];
4717
4718         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4719         if (!dch)
4720                 return -ENOMEM;
4721         dch->debug = debug;
4722         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4723         dch->hw = hc;
4724         dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4725         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4726             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4727         dch->dev.D.send = handle_dmsg;
4728         dch->dev.D.ctrl = hfcm_dctrl;
4729         dch->dev.nrbchan = 2;
4730         i = pt << 2;
4731         dch->slot = i + 2;
4732         hc->chan[i + 2].dch = dch;
4733         hc->chan[i + 2].port = pt;
4734         hc->chan[i + 2].nt_timer = -1;
4735         for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4736                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4737                 if (!bch) {
4738                         printk(KERN_ERR "%s: no memory for bchannel\n",
4739                             __func__);
4740                         ret = -ENOMEM;
4741                         goto free_chan;
4742                 }
4743                 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4744                 if (!hc->chan[i + ch].coeff) {
4745                         printk(KERN_ERR "%s: no memory for coeffs\n",
4746                             __func__);
4747                         ret = -ENOMEM;
4748                         goto free_chan;
4749                 }
4750                 bch->nr = ch + 1;
4751                 bch->slot = i + ch;
4752                 bch->debug = debug;
4753                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4754                 bch->hw = hc;
4755                 bch->ch.send = handle_bmsg;
4756                 bch->ch.ctrl = hfcm_bctrl;
4757                 bch->ch.nr = ch + 1;
4758                 list_add(&bch->ch.list, &dch->dev.bchannels);
4759                 hc->chan[i + ch].bch = bch;
4760                 hc->chan[i + ch].port = pt;
4761                 set_channelmap(bch->nr, dch->dev.channelmap);
4762         }
4763         /* set master clock */
4764         if (port[Port_cnt] & 0x001) {
4765                 if (debug & DEBUG_HFCMULTI_INIT)
4766                         printk(KERN_DEBUG
4767                             "%s: PROTOCOL set master clock: "
4768                             "card(%d) port(%d)\n",
4769                             __func__, HFC_cnt + 1, pt + 1);
4770                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4771                         printk(KERN_ERR "Error: Master clock "
4772                             "for port(%d) of card(%d) is only"
4773                             " possible with TE-mode\n",
4774                             pt + 1, HFC_cnt + 1);
4775                         ret = -EINVAL;
4776                         goto free_chan;
4777                 }
4778                 if (hc->masterclk >= 0) {
4779                         printk(KERN_ERR "Error: Master clock "
4780                             "for port(%d) of card(%d) already "
4781                             "defined for port(%d)\n",
4782                             pt + 1, HFC_cnt + 1, hc->masterclk+1);
4783                         ret = -EINVAL;
4784                         goto free_chan;
4785                 }
4786                 hc->masterclk = pt;
4787         }
4788         /* set transmitter line to non capacitive */
4789         if (port[Port_cnt] & 0x002) {
4790                 if (debug & DEBUG_HFCMULTI_INIT)
4791                         printk(KERN_DEBUG
4792                             "%s: PROTOCOL set non capacitive "
4793                             "transmitter: card(%d) port(%d)\n",
4794                             __func__, HFC_cnt + 1, pt + 1);
4795                 test_and_set_bit(HFC_CFG_NONCAP_TX,
4796                     &hc->chan[i + 2].cfg);
4797         }
4798         /* disable E-channel */
4799         if (port[Port_cnt] & 0x004) {
4800         if (debug & DEBUG_HFCMULTI_INIT)
4801                         printk(KERN_DEBUG
4802                             "%s: PROTOCOL disable E-channel: "
4803                             "card(%d) port(%d)\n",
4804                             __func__, HFC_cnt + 1, pt + 1);
4805                 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4806                     &hc->chan[i + 2].cfg);
4807         }
4808         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d/%d",
4809                 hc->type, HFC_cnt + 1, pt + 1);
4810         ret = mISDN_register_device(&dch->dev, name);
4811         if (ret)
4812                 goto free_chan;
4813         hc->created[pt] = 1;
4814         return ret;
4815 free_chan:
4816         release_port(hc, dch);
4817         return ret;
4818 }
4819
4820 static int
4821 hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
4822 {
4823         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4824         int             ret_err = 0;
4825         int             pt;
4826         struct hfc_multi        *hc;
4827         u_long          flags;
4828         u_char          dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4829
4830         if (HFC_cnt >= MAX_CARDS) {
4831                 printk(KERN_ERR "too many cards (max=%d).\n",
4832                         MAX_CARDS);
4833                 return -EINVAL;
4834         }
4835         if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4836                 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4837                     "type[%d] %d was supplied as module parameter\n",
4838                     m->vendor_name, m->card_name, m->type, HFC_cnt,
4839                     type[HFC_cnt] & 0xff);
4840                 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4841                         "first, to see cards and their types.");
4842                 return -EINVAL;
4843         }
4844         if (debug & DEBUG_HFCMULTI_INIT)
4845                 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4846                     __func__, m->vendor_name, m->card_name, m->type,
4847                     type[HFC_cnt]);
4848
4849         /* allocate card+fifo structure */
4850         hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4851         if (!hc) {
4852                 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4853                 return -ENOMEM;
4854         }
4855         spin_lock_init(&hc->lock);
4856         hc->mtyp = m;
4857         hc->type =  m->type;
4858         hc->ports = m->ports;
4859         hc->id = HFC_cnt;
4860         hc->pcm = pcm[HFC_cnt];
4861         hc->io_mode = iomode[HFC_cnt];
4862         if (dslot[HFC_cnt] < 0) {
4863                 hc->dslot = 0;
4864                 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
4865                         "31 B-channels\n");
4866         } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32) {
4867                 hc->dslot = dslot[HFC_cnt];
4868                 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
4869                         "time slot %d\n", dslot[HFC_cnt]);
4870         } else
4871                 hc->dslot = 16;
4872
4873         /* set chip specific features */
4874         hc->masterclk = -1;
4875         if (type[HFC_cnt] & 0x100) {
4876                 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
4877                 silence = 0xff; /* ulaw silence */
4878         } else
4879                 silence = 0x2a; /* alaw silence */
4880         if (!(type[HFC_cnt] & 0x200))
4881                 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4882
4883         if (type[HFC_cnt] & 0x800)
4884                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4885         if (type[HFC_cnt] & 0x1000) {
4886                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4887                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4888         }
4889         if (type[HFC_cnt] & 0x4000)
4890                 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
4891         if (type[HFC_cnt] & 0x8000)
4892                 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
4893         hc->slots = 32;
4894         if (type[HFC_cnt] & 0x10000)
4895                 hc->slots = 64;
4896         if (type[HFC_cnt] & 0x20000)
4897                 hc->slots = 128;
4898         if (type[HFC_cnt] & 0x80000) {
4899                 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
4900                 hc->wdcount = 0;
4901                 hc->wdbyte = V_GPIO_OUT2;
4902                 printk(KERN_NOTICE "Watchdog enabled\n");
4903         }
4904
4905         /* setup pci, hc->slots may change due to PLXSD */
4906         ret_err = setup_pci(hc, pdev, ent);
4907         if (ret_err) {
4908                 if (hc == syncmaster)
4909                         syncmaster = NULL;
4910                 kfree(hc);
4911                 return ret_err;
4912         }
4913
4914         /* crate channels */
4915         for (pt = 0; pt < hc->ports; pt++) {
4916                 if (Port_cnt >= MAX_PORTS) {
4917                         printk(KERN_ERR "too many ports (max=%d).\n",
4918                                 MAX_PORTS);
4919                         ret_err = -EINVAL;
4920                         goto free_card;
4921                 }
4922                 if (hc->type == 1)
4923                         ret_err = init_e1_port(hc, m);
4924                 else
4925                         ret_err = init_multi_port(hc, pt);
4926                 if (debug & DEBUG_HFCMULTI_INIT)
4927                         printk(KERN_DEBUG
4928                             "%s: Registering D-channel, card(%d) port(%d)"
4929                             "result %d\n",
4930                             __func__, HFC_cnt + 1, pt, ret_err);
4931
4932                 if (ret_err) {
4933                         while (pt) { /* release already registered ports */
4934                                 pt--;
4935                                 release_port(hc, hc->chan[(pt << 2) + 2].dch);
4936                         }
4937                         goto free_card;
4938                 }
4939                 Port_cnt++;
4940         }
4941
4942         /* disp switches */
4943         switch (m->dip_type) {
4944         case DIP_4S:
4945                 /*
4946                  * get DIP Setting for beroNet 1S/2S/4S cards
4947                  *  check if Port Jumper config matches
4948                  * module param 'protocol'
4949                  * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
4950                  * GPI 19/23 (R_GPI_IN2))
4951                  */
4952                 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
4953                         ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
4954                         (~HFC_inb(hc, R_GPI_IN2) & 0x08);
4955
4956                 /* Port mode (TE/NT) jumpers */
4957                 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4)  & 0xf);
4958
4959                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
4960                         pmj = ~pmj & 0xf;
4961
4962                 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
4963                         m->vendor_name, m->card_name, dips, pmj);
4964                 break;
4965         case DIP_8S:
4966                 /*
4967                  * get DIP Setting for beroNet 8S0+ cards
4968                  *
4969                  * enable PCI auxbridge function
4970                  */
4971                 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
4972                 /* prepare access to auxport */
4973                 outw(0x4000, hc->pci_iobase + 4);
4974                 /*
4975                  * some dummy reads are required to
4976                  * read valid DIP switch data
4977                  */
4978                 dips = inb(hc->pci_iobase);
4979                 dips = inb(hc->pci_iobase);
4980                 dips = inb(hc->pci_iobase);
4981                 dips = ~inb(hc->pci_iobase) & 0x3F;
4982                 outw(0x0, hc->pci_iobase + 4);
4983                 /* disable PCI auxbridge function */
4984                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
4985                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4986                     m->vendor_name, m->card_name, dips);
4987                 break;
4988         case DIP_E1:
4989                 /*
4990                  * get DIP Setting for beroNet E1 cards
4991                  * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
4992                  */
4993                 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
4994                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4995                     m->vendor_name, m->card_name, dips);
4996                 break;
4997         }
4998
4999         /* add to list */
5000         spin_lock_irqsave(&HFClock, flags);
5001         list_add_tail(&hc->list, &HFClist);
5002         spin_unlock_irqrestore(&HFClock, flags);
5003
5004         /* initialize hardware */
5005         ret_err = init_card(hc);
5006         if (ret_err) {
5007                 printk(KERN_ERR "init card returns %d\n", ret_err);
5008                 release_card(hc);
5009                 return ret_err;
5010         }
5011
5012         /* start IRQ and return */
5013         spin_lock_irqsave(&hc->lock, flags);
5014         enable_hwirq(hc);
5015         spin_unlock_irqrestore(&hc->lock, flags);
5016         return 0;
5017
5018 free_card:
5019         release_io_hfcmulti(hc);
5020         if (hc == syncmaster)
5021                 syncmaster = NULL;
5022         kfree(hc);
5023         return ret_err;
5024 }
5025
5026 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5027 {
5028         struct hfc_multi        *card = pci_get_drvdata(pdev);
5029         u_long                  flags;
5030
5031         if (debug)
5032                 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5033                     "device:%x subvendor:%x subdevice:%x\n",
5034                     pdev->vendor, pdev->device,
5035                     pdev->subsystem_vendor, pdev->subsystem_device);
5036
5037         if (card) {
5038                 spin_lock_irqsave(&HFClock, flags);
5039                 release_card(card);
5040                 spin_unlock_irqrestore(&HFClock, flags);
5041         }  else {
5042                 if (debug)
5043                         printk(KERN_WARNING "%s: drvdata allready removed\n",
5044                             __func__);
5045         }
5046 }
5047
5048 #define VENDOR_CCD      "Cologne Chip AG"
5049 #define VENDOR_BN       "beroNet GmbH"
5050 #define VENDOR_DIG      "Digium Inc."
5051 #define VENDOR_JH       "Junghanns.NET GmbH"
5052 #define VENDOR_PRIM     "PrimuX"
5053
5054 static const struct hm_map hfcm_map[] = {
5055 /*0*/   {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
5056 /*1*/   {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0},
5057 /*2*/   {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
5058 /*3*/   {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
5059 /*4*/   {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
5060 /*5*/   {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
5061 /*6*/   {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0},
5062 /*7*/   {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
5063 /*8*/   {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
5064 /*9*/   {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
5065 /*10*/  {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
5066 /*11*/  {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
5067
5068 /*12*/  {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
5069 /*13*/  {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5070                 HFC_IO_MODE_REGIO},
5071 /*14*/  {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
5072 /*15*/  {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
5073
5074 /*16*/  {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
5075 /*17*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5076 /*18*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5077
5078 /*19*/  {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
5079 /*20*/  {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
5080 /*21*/  {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5081 /*22*/  {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5082
5083 /*23*/  {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
5084 /*24*/  {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
5085 /*25*/  {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
5086
5087 /*26*/  {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5088                 HFC_IO_MODE_PLXSD},
5089 /*27*/  {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5090                 HFC_IO_MODE_PLXSD},
5091 /*28*/  {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
5092 /*29*/  {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
5093 /*30*/  {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
5094 };
5095
5096 #undef H
5097 #define H(x)    ((unsigned long)&hfcm_map[x])
5098 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5099
5100         /* Cards with HFC-4S Chip */
5101         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5102                 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5103         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5104                 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5105         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5106                 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5107         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5108                 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5109         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5110                 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5111         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5112                 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5113         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5114                 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5115         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5116                 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5117         { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5118                 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5119         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5120                 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5121         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5122                 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5123         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5124                 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5125         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5126                 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5127         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5128                 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5129
5130         /* Cards with HFC-8S Chip */
5131         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5132         PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5133         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5134         PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5135         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5136         PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5137         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5138         PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)},
5139             /* IOB8ST Recording */
5140         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5141                 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST  */
5142         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5143                 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST  */
5144         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5145                 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5146         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5147                 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5148
5149
5150         /* Cards with HFC-E1 Chip */
5151         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5152                 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5153         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5154                 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5155         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5156                 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5157         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5158                 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5159
5160         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5161                 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5162         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5163                 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5164         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5165                 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5166
5167         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5168                 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5169         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5170                 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5171         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5172                 0, 0, 0},
5173         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5174                 0, 0, 0},
5175         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5176                 0, 0, 0},
5177         {0, }
5178 };
5179 #undef H
5180
5181 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5182
5183 static int
5184 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5185 {
5186         struct hm_map   *m = (struct hm_map *)ent->driver_data;
5187         int             ret;
5188
5189         if (m == NULL) {
5190                 if (ent->vendor == PCI_VENDOR_ID_CCD)
5191                         if (ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5192                             ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5193                             ent->device == PCI_DEVICE_ID_CCD_HFCE1)
5194                                 printk(KERN_ERR
5195                                     "unknown HFC multiport controller "
5196                                     "(vendor:%x device:%x subvendor:%x "
5197                                     "subdevice:%x) Please contact the "
5198                                     "driver maintainer for support.\n",
5199                                     ent->vendor, ent->device,
5200                                     ent->subvendor, ent->subdevice);
5201                 return -ENODEV;
5202         }
5203         ret = hfcmulti_init(pdev, ent);
5204         if (ret)
5205                 return ret;
5206         HFC_cnt++;
5207         printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5208         return 0;
5209 }
5210
5211 static struct pci_driver hfcmultipci_driver = {
5212         .name           = "hfc_multi",
5213         .probe          = hfcmulti_probe,
5214         .remove         = __devexit_p(hfc_remove_pci),
5215         .id_table       = hfmultipci_ids,
5216 };
5217
5218 static void __exit
5219 HFCmulti_cleanup(void)
5220 {
5221         struct hfc_multi *card, *next;
5222
5223         /* unload interrupt function symbol */
5224         if (hfc_interrupt)
5225                 symbol_put(ztdummy_extern_interrupt);
5226         if (register_interrupt)
5227                 symbol_put(ztdummy_register_interrupt);
5228         if (unregister_interrupt) {
5229                 if (interrupt_registered) {
5230                         interrupt_registered = 0;
5231                         unregister_interrupt();
5232                 }
5233                 symbol_put(ztdummy_unregister_interrupt);
5234         }
5235
5236         list_for_each_entry_safe(card, next, &HFClist, list)
5237                 release_card(card);
5238         /* get rid of all devices of this driver */
5239         pci_unregister_driver(&hfcmultipci_driver);
5240 }
5241
5242 static int __init
5243 HFCmulti_init(void)
5244 {
5245         int err;
5246
5247 #ifdef IRQ_DEBUG
5248         printk(KERN_ERR "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5249 #endif
5250
5251         spin_lock_init(&HFClock);
5252         spin_lock_init(&plx_lock);
5253
5254         if (debug & DEBUG_HFCMULTI_INIT)
5255                 printk(KERN_DEBUG "%s: init entered\n", __func__);
5256
5257         hfc_interrupt = symbol_get(ztdummy_extern_interrupt);
5258         register_interrupt = symbol_get(ztdummy_register_interrupt);
5259         unregister_interrupt = symbol_get(ztdummy_unregister_interrupt);
5260         printk(KERN_INFO "mISDN: HFC-multi driver %s\n",
5261             hfcmulti_revision);
5262
5263         switch (poll) {
5264         case 0:
5265                 poll_timer = 6;
5266                 poll = 128;
5267                 break;
5268                 /*
5269                  * wenn dieses break nochmal verschwindet,
5270                  * gibt es heisse ohren :-)
5271                  * "without the break you will get hot ears ???"
5272                  */
5273         case 8:
5274                 poll_timer = 2;
5275                 break;
5276         case 16:
5277                 poll_timer = 3;
5278                 break;
5279         case 32:
5280                 poll_timer = 4;
5281                 break;
5282         case 64:
5283                 poll_timer = 5;
5284                 break;
5285         case 128:
5286                 poll_timer = 6;
5287                 break;
5288         case 256:
5289                 poll_timer = 7;
5290                 break;
5291         default:
5292                 printk(KERN_ERR
5293                     "%s: Wrong poll value (%d).\n", __func__, poll);
5294                 err = -EINVAL;
5295                 return err;
5296
5297         }
5298
5299         err = pci_register_driver(&hfcmultipci_driver);
5300         if (err < 0) {
5301                 printk(KERN_ERR "error registering pci driver: %x\n", err);
5302                 if (hfc_interrupt)
5303                         symbol_put(ztdummy_extern_interrupt);
5304                 if (register_interrupt)
5305                         symbol_put(ztdummy_register_interrupt);
5306                 if (unregister_interrupt) {
5307                         if (interrupt_registered) {
5308                                 interrupt_registered = 0;
5309                                 unregister_interrupt();
5310                         }
5311                         symbol_put(ztdummy_unregister_interrupt);
5312                 }
5313                 return err;
5314         }
5315         return 0;
5316 }
5317
5318
5319 module_init(HFCmulti_init);
5320 module_exit(HFCmulti_cleanup);