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   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  *
  33  * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $
  34  */
  35
  36 #include <linux/sched.h>
  37 #include <linux/pci.h>
  38 #include <linux/errno.h>
  39 #include <asm/io.h>
  40 #include <rdma/ib_mad.h>
  41
  42 #include "mthca_dev.h"
  43 #include "mthca_config_reg.h"
  44 #include "mthca_cmd.h"
  45 #include "mthca_memfree.h"
  46
  47 #define CMD_POLL_TOKEN 0xffff
  48
  49 enum {
  50         HCR_IN_PARAM_OFFSET    = 0x00,
  51         HCR_IN_MODIFIER_OFFSET = 0x08,
  52         HCR_OUT_PARAM_OFFSET   = 0x0c,
  53         HCR_TOKEN_OFFSET       = 0x14,
  54         HCR_STATUS_OFFSET      = 0x18,
  55
  56         HCR_OPMOD_SHIFT        = 12,
  57         HCA_E_BIT              = 22,
  58         HCR_GO_BIT             = 23
  59 };
  60
  61 enum {
  62         /* initialization and general commands */
  63         CMD_SYS_EN          = 0x1,
  64         CMD_SYS_DIS         = 0x2,
  65         CMD_MAP_FA          = 0xfff,
  66         CMD_UNMAP_FA        = 0xffe,
  67         CMD_RUN_FW          = 0xff6,
  68         CMD_MOD_STAT_CFG    = 0x34,
  69         CMD_QUERY_DEV_LIM   = 0x3,
  70         CMD_QUERY_FW        = 0x4,
  71         CMD_ENABLE_LAM      = 0xff8,
  72         CMD_DISABLE_LAM     = 0xff7,
  73         CMD_QUERY_DDR       = 0x5,
  74         CMD_QUERY_ADAPTER   = 0x6,
  75         CMD_INIT_HCA        = 0x7,
  76         CMD_CLOSE_HCA       = 0x8,
  77         CMD_INIT_IB         = 0x9,
  78         CMD_CLOSE_IB        = 0xa,
  79         CMD_QUERY_HCA       = 0xb,
  80         CMD_SET_IB          = 0xc,
  81         CMD_ACCESS_DDR      = 0x2e,
  82         CMD_MAP_ICM         = 0xffa,
  83         CMD_UNMAP_ICM       = 0xff9,
  84         CMD_MAP_ICM_AUX     = 0xffc,
  85         CMD_UNMAP_ICM_AUX   = 0xffb,
  86         CMD_SET_ICM_SIZE    = 0xffd,
  87
  88         /* TPT commands */
  89         CMD_SW2HW_MPT       = 0xd,
  90         CMD_QUERY_MPT       = 0xe,
  91         CMD_HW2SW_MPT       = 0xf,
  92         CMD_READ_MTT        = 0x10,
  93         CMD_WRITE_MTT       = 0x11,
  94         CMD_SYNC_TPT        = 0x2f,
  95
  96         /* EQ commands */
  97         CMD_MAP_EQ          = 0x12,
  98         CMD_SW2HW_EQ        = 0x13,
  99         CMD_HW2SW_EQ        = 0x14,
 100         CMD_QUERY_EQ        = 0x15,
 101
 102         /* CQ commands */
 103         CMD_SW2HW_CQ        = 0x16,
 104         CMD_HW2SW_CQ        = 0x17,
 105         CMD_QUERY_CQ        = 0x18,
 106         CMD_RESIZE_CQ       = 0x2c,
 107
 108         /* SRQ commands */
 109         CMD_SW2HW_SRQ       = 0x35,
 110         CMD_HW2SW_SRQ       = 0x36,
 111         CMD_QUERY_SRQ       = 0x37,
 112         CMD_ARM_SRQ         = 0x40,
 113
 114         /* QP/EE commands */
 115         CMD_RST2INIT_QPEE   = 0x19,
 116         CMD_INIT2RTR_QPEE   = 0x1a,
 117         CMD_RTR2RTS_QPEE    = 0x1b,
 118         CMD_RTS2RTS_QPEE    = 0x1c,
 119         CMD_SQERR2RTS_QPEE  = 0x1d,
 120         CMD_2ERR_QPEE       = 0x1e,
 121         CMD_RTS2SQD_QPEE    = 0x1f,
 122         CMD_SQD2SQD_QPEE    = 0x38,
 123         CMD_SQD2RTS_QPEE    = 0x20,
 124         CMD_ERR2RST_QPEE    = 0x21,
 125         CMD_QUERY_QPEE      = 0x22,
 126         CMD_INIT2INIT_QPEE  = 0x2d,
 127         CMD_SUSPEND_QPEE    = 0x32,
 128         CMD_UNSUSPEND_QPEE  = 0x33,
 129         /* special QPs and management commands */
 130         CMD_CONF_SPECIAL_QP = 0x23,
 131         CMD_MAD_IFC         = 0x24,
 132
 133         /* multicast commands */
 134         CMD_READ_MGM        = 0x25,
 135         CMD_WRITE_MGM       = 0x26,
 136         CMD_MGID_HASH       = 0x27,
 137
 138         /* miscellaneous commands */
 139         CMD_DIAG_RPRT       = 0x30,
 140         CMD_NOP             = 0x31,
 141
 142         /* debug commands */
 143         CMD_QUERY_DEBUG_MSG = 0x2a,
 144         CMD_SET_DEBUG_MSG   = 0x2b,
 145 };
 146
 147 /*
 148  * According to Mellanox code, FW may be starved and never complete
 149  * commands.  So we can't use strict timeouts described in PRM -- we
 150  * just arbitrarily select 60 seconds for now.
 151  */
 152 #if 0
 153 /*
 154  * Round up and add 1 to make sure we get the full wait time (since we
 155  * will be starting in the middle of a jiffy)
 156  */
 157 enum {
 158         CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
 159         CMD_TIME_CLASS_B = (HZ +  99) /  100 + 1,
 160         CMD_TIME_CLASS_C = (HZ +   9) /   10 + 1
 161 };
 162 #else
 163 enum {
 164         CMD_TIME_CLASS_A = 60 * HZ,
 165         CMD_TIME_CLASS_B = 60 * HZ,
 166         CMD_TIME_CLASS_C = 60 * HZ
 167 };
 168 #endif
 169
 170 enum {
 171         GO_BIT_TIMEOUT = HZ * 10
 172 };
 173
 174 struct mthca_cmd_context {
 175         struct completion done;
 176         struct timer_list timer;
 177         int               result;
 178         int               next;
 179         u64               out_param;
 180         u16               token;
 181         u8                status;
 182 };
 183
 184 static inline int go_bit(struct mthca_dev *dev)
 185 {
 186         return readl(dev->hcr + HCR_STATUS_OFFSET) &
 187                 swab32(1 << HCR_GO_BIT);
 188 }
 189
 190 static int mthca_cmd_post(struct mthca_dev *dev,
 191                           u64 in_param,
 192                           u64 out_param,
 193                           u32 in_modifier,
 194                           u8 op_modifier,
 195                           u16 op,
 196                           u16 token,
 197                           int event)
 198 {
 199         int err = 0;
 200
 201         if (down_interruptible(&dev->cmd.hcr_sem))
 202                 return -EINTR;
 203
 204         if (event) {
 205                 unsigned long end = jiffies + GO_BIT_TIMEOUT;
 206
 207                 while (go_bit(dev) && time_before(jiffies, end)) {
 208                         set_current_state(TASK_RUNNING);
 209                         schedule();
 210                 }
 211         }
 212
 213         if (go_bit(dev)) {
 214                 err = -EAGAIN;
 215                 goto out;
 216         }
 217
 218         /*
 219          * We use writel (instead of something like memcpy_toio)
 220          * because writes of less than 32 bits to the HCR don't work
 221          * (and some architectures such as ia64 implement memcpy_toio
 222          * in terms of writeb).
 223          */
 224         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           dev->hcr + 0 * 4);
 225         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  dev->hcr + 1 * 4);
 226         __raw_writel((__force u32) cpu_to_be32(in_modifier),              dev->hcr + 2 * 4);
 227         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          dev->hcr + 3 * 4);
 228         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
 229         __raw_writel((__force u32) cpu_to_be32(token << 16),              dev->hcr + 5 * 4);
 230
 231         /* __raw_writel may not order writes. */
 232         wmb();
 233
 234         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 235                                                (event ? (1 << HCA_E_BIT) : 0)   |
 236                                                (op_modifier << HCR_OPMOD_SHIFT) |
 237                                                op),                       dev->hcr + 6 * 4);
 238
 239 out:
 240         up(&dev->cmd.hcr_sem);
 241         return err;
 242 }
 243
 244 static int mthca_cmd_poll(struct mthca_dev *dev,
 245                           u64 in_param,
 246                           u64 *out_param,
 247                           int out_is_imm,
 248                           u32 in_modifier,
 249                           u8 op_modifier,
 250                           u16 op,
 251                           unsigned long timeout,
 252                           u8 *status)
 253 {
 254         int err = 0;
 255         unsigned long end;
 256
 257         if (down_interruptible(&dev->cmd.poll_sem))
 258                 return -EINTR;
 259
 260         err = mthca_cmd_post(dev, in_param,
 261                              out_param ? *out_param : 0,
 262                              in_modifier, op_modifier,
 263                              op, CMD_POLL_TOKEN, 0);
 264         if (err)
 265                 goto out;
 266
 267         end = timeout + jiffies;
 268         while (go_bit(dev) && time_before(jiffies, end)) {
 269                 set_current_state(TASK_RUNNING);
 270                 schedule();
 271         }
 272
 273         if (go_bit(dev)) {
 274                 err = -EBUSY;
 275                 goto out;
 276         }
 277
 278         if (out_is_imm)
 279                 *out_param =
 280                         (u64) be32_to_cpu((__force __be32)
 281                                           __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 282                         (u64) be32_to_cpu((__force __be32)
 283                                           __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
 284
 285         *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
 286
 287 out:
 288         up(&dev->cmd.poll_sem);
 289         return err;
 290 }
 291
 292 void mthca_cmd_event(struct mthca_dev *dev,
 293                      u16 token,
 294                      u8  status,
 295                      u64 out_param)
 296 {
 297         struct mthca_cmd_context *context =
 298                 &dev->cmd.context[token & dev->cmd.token_mask];
 299
 300         /* previously timed out command completing at long last */
 301         if (token != context->token)
 302                 return;
 303
 304         context->result    = 0;
 305         context->status    = status;
 306         context->out_param = out_param;
 307
 308         context->token += dev->cmd.token_mask + 1;
 309
 310         complete(&context->done);
 311 }
 312
 313 static void event_timeout(unsigned long context_ptr)
 314 {
 315         struct mthca_cmd_context *context =
 316                 (struct mthca_cmd_context *) context_ptr;
 317
 318         context->result = -EBUSY;
 319         complete(&context->done);
 320 }
 321
 322 static int mthca_cmd_wait(struct mthca_dev *dev,
 323                           u64 in_param,
 324                           u64 *out_param,
 325                           int out_is_imm,
 326                           u32 in_modifier,
 327                           u8 op_modifier,
 328                           u16 op,
 329                           unsigned long timeout,
 330                           u8 *status)
 331 {
 332         int err = 0;
 333         struct mthca_cmd_context *context;
 334
 335         if (down_interruptible(&dev->cmd.event_sem))
 336                 return -EINTR;
 337
 338         spin_lock(&dev->cmd.context_lock);
 339         BUG_ON(dev->cmd.free_head < 0);
 340         context = &dev->cmd.context[dev->cmd.free_head];
 341         dev->cmd.free_head = context->next;
 342         spin_unlock(&dev->cmd.context_lock);
 343
 344         init_completion(&context->done);
 345
 346         err = mthca_cmd_post(dev, in_param,
 347                              out_param ? *out_param : 0,
 348                              in_modifier, op_modifier,
 349                              op, context->token, 1);
 350         if (err)
 351                 goto out;
 352
 353         context->timer.expires  = jiffies + timeout;
 354         add_timer(&context->timer);
 355
 356         wait_for_completion(&context->done);
 357         del_timer_sync(&context->timer);
 358
 359         err = context->result;
 360         if (err)
 361                 goto out;
 362
 363         *status = context->status;
 364         if (*status)
 365                 mthca_dbg(dev, "Command %02x completed with status %02x\n",
 366                           op, *status);
 367
 368         if (out_is_imm)
 369                 *out_param = context->out_param;
 370
 371 out:
 372         spin_lock(&dev->cmd.context_lock);
 373         context->next = dev->cmd.free_head;
 374         dev->cmd.free_head = context - dev->cmd.context;
 375         spin_unlock(&dev->cmd.context_lock);
 376
 377         up(&dev->cmd.event_sem);
 378         return err;
 379 }
 380
 381 /* Invoke a command with an output mailbox */
 382 static int mthca_cmd_box(struct mthca_dev *dev,
 383                          u64 in_param,
 384                          u64 out_param,
 385                          u32 in_modifier,
 386                          u8 op_modifier,
 387                          u16 op,
 388                          unsigned long timeout,
 389                          u8 *status)
 390 {
 391         if (dev->cmd.use_events)
 392                 return mthca_cmd_wait(dev, in_param, &out_param, 0,
 393                                       in_modifier, op_modifier, op,
 394                                       timeout, status);
 395         else
 396                 return mthca_cmd_poll(dev, in_param, &out_param, 0,
 397                                       in_modifier, op_modifier, op,
 398                                       timeout, status);
 399 }
 400
 401 /* Invoke a command with no output parameter */
 402 static int mthca_cmd(struct mthca_dev *dev,
 403                      u64 in_param,
 404                      u32 in_modifier,
 405                      u8 op_modifier,
 406                      u16 op,
 407                      unsigned long timeout,
 408                      u8 *status)
 409 {
 410         return mthca_cmd_box(dev, in_param, 0, in_modifier,
 411                              op_modifier, op, timeout, status);
 412 }
 413
 414 /*
 415  * Invoke a command with an immediate output parameter (and copy the
 416  * output into the caller's out_param pointer after the command
 417  * executes).
 418  */
 419 static int mthca_cmd_imm(struct mthca_dev *dev,
 420                          u64 in_param,
 421                          u64 *out_param,
 422                          u32 in_modifier,
 423                          u8 op_modifier,
 424                          u16 op,
 425                          unsigned long timeout,
 426                          u8 *status)
 427 {
 428         if (dev->cmd.use_events)
 429                 return mthca_cmd_wait(dev, in_param, out_param, 1,
 430                                       in_modifier, op_modifier, op,
 431                                       timeout, status);
 432         else
 433                 return mthca_cmd_poll(dev, in_param, out_param, 1,
 434                                       in_modifier, op_modifier, op,
 435                                       timeout, status);
 436 }
 437
 438 int mthca_cmd_init(struct mthca_dev *dev)
 439 {
 440         sema_init(&dev->cmd.hcr_sem, 1);
 441         sema_init(&dev->cmd.poll_sem, 1);
 442         dev->cmd.use_events = 0;
 443
 444         dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
 445                            MTHCA_HCR_SIZE);
 446         if (!dev->hcr) {
 447                 mthca_err(dev, "Couldn't map command register.");
 448                 return -ENOMEM;
 449         }
 450
 451         dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
 452                                         MTHCA_MAILBOX_SIZE,
 453                                         MTHCA_MAILBOX_SIZE, 0);
 454         if (!dev->cmd.pool) {
 455                 iounmap(dev->hcr);
 456                 return -ENOMEM;
 457         }
 458
 459         return 0;
 460 }
 461
 462 void mthca_cmd_cleanup(struct mthca_dev *dev)
 463 {
 464         pci_pool_destroy(dev->cmd.pool);
 465         iounmap(dev->hcr);
 466 }
 467
 468 /*
 469  * Switch to using events to issue FW commands (should be called after
 470  * event queue to command events has been initialized).
 471  */
 472 int mthca_cmd_use_events(struct mthca_dev *dev)
 473 {
 474         int i;
 475
 476         dev->cmd.context = kmalloc(dev->cmd.max_cmds *
 477                                    sizeof (struct mthca_cmd_context),
 478                                    GFP_KERNEL);
 479         if (!dev->cmd.context)
 480                 return -ENOMEM;
 481
 482         for (i = 0; i < dev->cmd.max_cmds; ++i) {
 483                 dev->cmd.context[i].token = i;
 484                 dev->cmd.context[i].next = i + 1;
 485                 init_timer(&dev->cmd.context[i].timer);
 486                 dev->cmd.context[i].timer.data     =
 487                         (unsigned long) &dev->cmd.context[i];
 488                 dev->cmd.context[i].timer.function = event_timeout;
 489         }
 490
 491         dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
 492         dev->cmd.free_head = 0;
 493
 494         sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
 495         spin_lock_init(&dev->cmd.context_lock);
 496
 497         for (dev->cmd.token_mask = 1;
 498              dev->cmd.token_mask < dev->cmd.max_cmds;
 499              dev->cmd.token_mask <<= 1)
 500                 ; /* nothing */
 501         --dev->cmd.token_mask;
 502
 503         dev->cmd.use_events = 1;
 504         down(&dev->cmd.poll_sem);
 505
 506         return 0;
 507 }
 508
 509 /*
 510  * Switch back to polling (used when shutting down the device)
 511  */
 512 void mthca_cmd_use_polling(struct mthca_dev *dev)
 513 {
 514         int i;
 515
 516         dev->cmd.use_events = 0;
 517
 518         for (i = 0; i < dev->cmd.max_cmds; ++i)
 519                 down(&dev->cmd.event_sem);
 520
 521         kfree(dev->cmd.context);
 522
 523         up(&dev->cmd.poll_sem);
 524 }
 525
 526 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
 527                                           unsigned int gfp_mask)
 528 {
 529         struct mthca_mailbox *mailbox;
 530
 531         mailbox = kmalloc(sizeof *mailbox, gfp_mask);
 532         if (!mailbox)
 533                 return ERR_PTR(-ENOMEM);
 534
 535         mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
 536         if (!mailbox->buf) {
 537                 kfree(mailbox);
 538                 return ERR_PTR(-ENOMEM);
 539         }
 540
 541         return mailbox;
 542 }
 543
 544 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
 545 {
 546         if (!mailbox)
 547                 return;
 548
 549         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 550         kfree(mailbox);
 551 }
 552
 553 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
 554 {
 555         u64 out;
 556         int ret;
 557
 558         ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
 559
 560         if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
 561                 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
 562                            "sladdr=%d, SPD source=%s\n",
 563                            (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
 564                            (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
 565
 566         return ret;
 567 }
 568
 569 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
 570 {
 571         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
 572 }
 573
 574 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
 575                          u64 virt, u8 *status)
 576 {
 577         struct mthca_mailbox *mailbox;
 578         struct mthca_icm_iter iter;
 579         __be64 *pages;
 580         int lg;
 581         int nent = 0;
 582         int i;
 583         int err = 0;
 584         int ts = 0, tc = 0;
 585
 586         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 587         if (IS_ERR(mailbox))
 588                 return PTR_ERR(mailbox);
 589         memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
 590         pages = mailbox->buf;
 591
 592         for (mthca_icm_first(icm, &iter);
 593              !mthca_icm_last(&iter);
 594              mthca_icm_next(&iter)) {
 595                 /*
 596                  * We have to pass pages that are aligned to their
 597                  * size, so find the least significant 1 in the
 598                  * address or size and use that as our log2 size.
 599                  */
 600                 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
 601                 if (lg < 12) {
 602                         mthca_warn(dev, "Got FW area not aligned to 4K (%llx/%lx).\n",
 603                                    (unsigned long long) mthca_icm_addr(&iter),
 604                                    mthca_icm_size(&iter));
 605                         err = -EINVAL;
 606                         goto out;
 607                 }
 608                 for (i = 0; i < mthca_icm_size(&iter) / (1 << lg); ++i) {
 609                         if (virt != -1) {
 610                                 pages[nent * 2] = cpu_to_be64(virt);
 611                                 virt += 1 << lg;
 612                         }
 613
 614                         pages[nent * 2 + 1] = cpu_to_be64((mthca_icm_addr(&iter) +
 615                                                            (i << lg)) | (lg - 12));
 616                         ts += 1 << (lg - 10);
 617                         ++tc;
 618
 619                         if (++nent == MTHCA_MAILBOX_SIZE / 16) {
 620                                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 621                                                 CMD_TIME_CLASS_B, status);
 622                                 if (err || *status)
 623                                         goto out;
 624                                 nent = 0;
 625                         }
 626                 }
 627         }
 628
 629         if (nent)
 630                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 631                                 CMD_TIME_CLASS_B, status);
 632
 633         switch (op) {
 634         case CMD_MAP_FA:
 635                 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
 636                 break;
 637         case CMD_MAP_ICM_AUX:
 638                 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
 639                 break;
 640         case CMD_MAP_ICM:
 641                 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
 642                           tc, ts, (unsigned long long) virt - (ts << 10));
 643                 break;
 644         }
 645
 646 out:
 647         mthca_free_mailbox(dev, mailbox);
 648         return err;
 649 }
 650
 651 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
 652 {
 653         return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
 654 }
 655
 656 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
 657 {
 658         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
 659 }
 660
 661 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
 662 {
 663         return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
 664 }
 665
 666 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
 667 {
 668         struct mthca_mailbox *mailbox;
 669         u32 *outbox;
 670         int err = 0;
 671         u8 lg;
 672
 673 #define QUERY_FW_OUT_SIZE             0x100
 674 #define QUERY_FW_VER_OFFSET            0x00
 675 #define QUERY_FW_MAX_CMD_OFFSET        0x0f
 676 #define QUERY_FW_ERR_START_OFFSET      0x30
 677 #define QUERY_FW_ERR_SIZE_OFFSET       0x38
 678
 679 #define QUERY_FW_START_OFFSET          0x20
 680 #define QUERY_FW_END_OFFSET            0x28
 681
 682 #define QUERY_FW_SIZE_OFFSET           0x00
 683 #define QUERY_FW_CLR_INT_BASE_OFFSET   0x20
 684 #define QUERY_FW_EQ_ARM_BASE_OFFSET    0x40
 685 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
 686
 687         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 688         if (IS_ERR(mailbox))
 689                 return PTR_ERR(mailbox);
 690         outbox = mailbox->buf;
 691
 692         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
 693                             CMD_TIME_CLASS_A, status);
 694
 695         if (err)
 696                 goto out;
 697
 698         MTHCA_GET(dev->fw_ver,   outbox, QUERY_FW_VER_OFFSET);
 699         /*
 700          * FW subminor version is at more signifant bits than minor
 701          * version, so swap here.
 702          */
 703         dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
 704                 ((dev->fw_ver & 0xffff0000ull) >> 16) |
 705                 ((dev->fw_ver & 0x0000ffffull) << 16);
 706
 707         MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
 708         dev->cmd.max_cmds = 1 << lg;
 709
 710         mthca_dbg(dev, "FW version %012llx, max commands %d\n",
 711                   (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
 712
 713         if (mthca_is_memfree(dev)) {
 714                 MTHCA_GET(dev->fw.arbel.fw_pages,       outbox, QUERY_FW_SIZE_OFFSET);
 715                 MTHCA_GET(dev->fw.arbel.clr_int_base,   outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
 716                 MTHCA_GET(dev->fw.arbel.eq_arm_base,    outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
 717                 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
 718                 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
 719
 720                 /*
 721                  * Arbel page size is always 4 KB; round up number of
 722                  * system pages needed.
 723                  */
 724                 dev->fw.arbel.fw_pages =
 725                         (dev->fw.arbel.fw_pages + (1 << (PAGE_SHIFT - 12)) - 1) >>
 726                         (PAGE_SHIFT - 12);
 727
 728                 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
 729                           (unsigned long long) dev->fw.arbel.clr_int_base,
 730                           (unsigned long long) dev->fw.arbel.eq_arm_base,
 731                           (unsigned long long) dev->fw.arbel.eq_set_ci_base);
 732         } else {
 733                 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
 734                 MTHCA_GET(dev->fw.tavor.fw_end,   outbox, QUERY_FW_END_OFFSET);
 735
 736                 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
 737                           (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
 738                           (unsigned long long) dev->fw.tavor.fw_start,
 739                           (unsigned long long) dev->fw.tavor.fw_end);
 740         }
 741
 742 out:
 743         mthca_free_mailbox(dev, mailbox);
 744         return err;
 745 }
 746
 747 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
 748 {
 749         struct mthca_mailbox *mailbox;
 750         u8 info;
 751         u32 *outbox;
 752         int err = 0;
 753
 754 #define ENABLE_LAM_OUT_SIZE         0x100
 755 #define ENABLE_LAM_START_OFFSET     0x00
 756 #define ENABLE_LAM_END_OFFSET       0x08
 757 #define ENABLE_LAM_INFO_OFFSET      0x13
 758
 759 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
 760 #define ENABLE_LAM_INFO_ECC_MASK    0x3
 761
 762         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 763         if (IS_ERR(mailbox))
 764                 return PTR_ERR(mailbox);
 765         outbox = mailbox->buf;
 766
 767         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
 768                             CMD_TIME_CLASS_C, status);
 769
 770         if (err)
 771                 goto out;
 772
 773         if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
 774                 goto out;
 775
 776         MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
 777         MTHCA_GET(dev->ddr_end,   outbox, ENABLE_LAM_END_OFFSET);
 778         MTHCA_GET(info,           outbox, ENABLE_LAM_INFO_OFFSET);
 779
 780         if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
 781             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 782                 mthca_info(dev, "FW reports that HCA-attached memory "
 783                            "is %s hidden; does not match PCI config\n",
 784                            (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
 785                            "" : "not");
 786         }
 787         if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
 788                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
 789
 790         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
 791                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 792                   (unsigned long long) dev->ddr_start,
 793                   (unsigned long long) dev->ddr_end);
 794
 795 out:
 796         mthca_free_mailbox(dev, mailbox);
 797         return err;
 798 }
 799
 800 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
 801 {
 802         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
 803 }
 804
 805 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
 806 {
 807         struct mthca_mailbox *mailbox;
 808         u8 info;
 809         u32 *outbox;
 810         int err = 0;
 811
 812 #define QUERY_DDR_OUT_SIZE         0x100
 813 #define QUERY_DDR_START_OFFSET     0x00
 814 #define QUERY_DDR_END_OFFSET       0x08
 815 #define QUERY_DDR_INFO_OFFSET      0x13
 816
 817 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
 818 #define QUERY_DDR_INFO_ECC_MASK    0x3
 819
 820         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 821         if (IS_ERR(mailbox))
 822                 return PTR_ERR(mailbox);
 823         outbox = mailbox->buf;
 824
 825         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
 826                             CMD_TIME_CLASS_A, status);
 827
 828         if (err)
 829                 goto out;
 830
 831         MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
 832         MTHCA_GET(dev->ddr_end,   outbox, QUERY_DDR_END_OFFSET);
 833         MTHCA_GET(info,           outbox, QUERY_DDR_INFO_OFFSET);
 834
 835         if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
 836             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 837                 mthca_info(dev, "FW reports that HCA-attached memory "
 838                            "is %s hidden; does not match PCI config\n",
 839                            (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
 840                            "" : "not");
 841         }
 842         if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
 843                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
 844
 845         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
 846                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 847                   (unsigned long long) dev->ddr_start,
 848                   (unsigned long long) dev->ddr_end);
 849
 850 out:
 851         mthca_free_mailbox(dev, mailbox);
 852         return err;
 853 }
 854
 855 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
 856                         struct mthca_dev_lim *dev_lim, u8 *status)
 857 {
 858         struct mthca_mailbox *mailbox;
 859         u32 *outbox;
 860         u8 field;
 861         u16 size;
 862         int err;
 863
 864 #define QUERY_DEV_LIM_OUT_SIZE             0x100
 865 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET     0x10
 866 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET      0x11
 867 #define QUERY_DEV_LIM_RSVD_QP_OFFSET        0x12
 868 #define QUERY_DEV_LIM_MAX_QP_OFFSET         0x13
 869 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET       0x14
 870 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET        0x15
 871 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET       0x16
 872 #define QUERY_DEV_LIM_MAX_EEC_OFFSET        0x17
 873 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET      0x19
 874 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET        0x1a
 875 #define QUERY_DEV_LIM_MAX_CQ_OFFSET         0x1b
 876 #define QUERY_DEV_LIM_MAX_MPT_OFFSET        0x1d
 877 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET        0x1e
 878 #define QUERY_DEV_LIM_MAX_EQ_OFFSET         0x1f
 879 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET       0x20
 880 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET     0x21
 881 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET       0x22
 882 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET    0x23
 883 #define QUERY_DEV_LIM_MAX_AV_OFFSET         0x27
 884 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET     0x29
 885 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET     0x2b
 886 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET       0x2f
 887 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET        0x33
 888 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET      0x35
 889 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET      0x36
 890 #define QUERY_DEV_LIM_VL_PORT_OFFSET        0x37
 891 #define QUERY_DEV_LIM_MAX_GID_OFFSET        0x3b
 892 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET       0x3f
 893 #define QUERY_DEV_LIM_FLAGS_OFFSET          0x44
 894 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET       0x48
 895 #define QUERY_DEV_LIM_UAR_SZ_OFFSET         0x49
 896 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET        0x4b
 897 #define QUERY_DEV_LIM_MAX_SG_OFFSET         0x51
 898 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET    0x52
 899 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET      0x55
 900 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
 901 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET     0x61
 902 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET       0x62
 903 #define QUERY_DEV_LIM_MAX_MCG_OFFSET        0x63
 904 #define QUERY_DEV_LIM_RSVD_PD_OFFSET        0x64
 905 #define QUERY_DEV_LIM_MAX_PD_OFFSET         0x65
 906 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET       0x66
 907 #define QUERY_DEV_LIM_MAX_RDD_OFFSET        0x67
 908 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET   0x80
 909 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET   0x82
 910 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET  0x84
 911 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET  0x86
 912 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET   0x88
 913 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET   0x8a
 914 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET   0x8c
 915 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET   0x8e
 916 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET   0x90
 917 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET   0x92
 918 #define QUERY_DEV_LIM_PBL_SZ_OFFSET         0x96
 919 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET     0x97
 920 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET      0x98
 921 #define QUERY_DEV_LIM_LAMR_OFFSET           0x9f
 922 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET     0xa0
 923
 924         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 925         if (IS_ERR(mailbox))
 926                 return PTR_ERR(mailbox);
 927         outbox = mailbox->buf;
 928
 929         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
 930                             CMD_TIME_CLASS_A, status);
 931
 932         if (err)
 933                 goto out;
 934
 935         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
 936         dev_lim->max_srq_sz = (1 << field) - 1;
 937         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
 938         dev_lim->max_qp_sz = (1 << field) - 1;
 939         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
 940         dev_lim->reserved_qps = 1 << (field & 0xf);
 941         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
 942         dev_lim->max_qps = 1 << (field & 0x1f);
 943         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
 944         dev_lim->reserved_srqs = 1 << (field >> 4);
 945         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
 946         dev_lim->max_srqs = 1 << (field & 0x1f);
 947         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
 948         dev_lim->reserved_eecs = 1 << (field & 0xf);
 949         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
 950         dev_lim->max_eecs = 1 << (field & 0x1f);
 951         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
 952         dev_lim->max_cq_sz = 1 << field;
 953         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
 954         dev_lim->reserved_cqs = 1 << (field & 0xf);
 955         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
 956         dev_lim->max_cqs = 1 << (field & 0x1f);
 957         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
 958         dev_lim->max_mpts = 1 << (field & 0x3f);
 959         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
 960         dev_lim->reserved_eqs = 1 << (field & 0xf);
 961         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
 962         dev_lim->max_eqs = 1 << (field & 0x7);
 963         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
 964         dev_lim->reserved_mtts = 1 << (field >> 4);
 965         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
 966         dev_lim->max_mrw_sz = 1 << field;
 967         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
 968         dev_lim->reserved_mrws = 1 << (field & 0xf);
 969         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
 970         dev_lim->max_mtt_seg = 1 << (field & 0x3f);
 971         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
 972         dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
 973         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
 974         dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
 975         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
 976         dev_lim->max_rdma_global = 1 << (field & 0x3f);
 977         MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
 978         dev_lim->local_ca_ack_delay = field & 0x1f;
 979         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
 980         dev_lim->max_mtu        = field >> 4;
 981         dev_lim->max_port_width = field & 0xf;
 982         MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
 983         dev_lim->max_vl    = field >> 4;
 984         dev_lim->num_ports = field & 0xf;
 985         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
 986         dev_lim->max_gids = 1 << (field & 0xf);
 987         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
 988         dev_lim->max_pkeys = 1 << (field & 0xf);
 989         MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
 990         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
 991         dev_lim->reserved_uars = field >> 4;
 992         MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
 993         dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
 994         MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
 995         dev_lim->min_page_sz = 1 << field;
 996         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
 997         dev_lim->max_sg = field;
 998
 999         MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1000         dev_lim->max_desc_sz = size;
1001
1002         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1003         dev_lim->max_qp_per_mcg = 1 << field;
1004         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1005         dev_lim->reserved_mgms = field & 0xf;
1006         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1007         dev_lim->max_mcgs = 1 << field;
1008         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1009         dev_lim->reserved_pds = field >> 4;
1010         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1011         dev_lim->max_pds = 1 << (field & 0x3f);
1012         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1013         dev_lim->reserved_rdds = field >> 4;
1014         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1015         dev_lim->max_rdds = 1 << (field & 0x3f);
1016
1017         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1018         dev_lim->eec_entry_sz = size;
1019         MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1020         dev_lim->qpc_entry_sz = size;
1021         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1022         dev_lim->eeec_entry_sz = size;
1023         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1024         dev_lim->eqpc_entry_sz = size;
1025         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1026         dev_lim->eqc_entry_sz = size;
1027         MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1028         dev_lim->cqc_entry_sz = size;
1029         MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1030         dev_lim->srq_entry_sz = size;
1031         MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1032         dev_lim->uar_scratch_entry_sz = size;
1033
1034         mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1035                   dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1036         mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1037                   dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1038         mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1039                   dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1040         mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1041                   dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1042         mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1043                   dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1044         mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1045                   dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1046         mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1047                   dev_lim->max_pds, dev_lim->reserved_mgms);
1048         mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1049                   dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1050
1051         mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1052
1053         if (mthca_is_memfree(dev)) {
1054                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1055                 dev_lim->hca.arbel.resize_srq = field & 1;
1056                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1057                 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1058                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1059                 dev_lim->mpt_entry_sz = size;
1060                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1061                 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1062                 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1063                           QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1064                 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1065                           QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1066                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1067                 dev_lim->hca.arbel.lam_required = field & 1;
1068                 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1069                           QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1070
1071                 if (dev_lim->hca.arbel.bmme_flags & 1)
1072                         mthca_dbg(dev, "Base MM extensions: yes "
1073                                   "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1074                                   dev_lim->hca.arbel.bmme_flags,
1075                                   dev_lim->hca.arbel.max_pbl_sz,
1076                                   dev_lim->hca.arbel.reserved_lkey);
1077                 else
1078                         mthca_dbg(dev, "Base MM extensions: no\n");
1079
1080                 mthca_dbg(dev, "Max ICM size %lld MB\n",
1081                           (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1082         } else {
1083                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1084                 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1085                 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1086         }
1087
1088 out:
1089         mthca_free_mailbox(dev, mailbox);
1090         return err;
1091 }
1092
1093 static void get_board_id(void *vsd, char *board_id)
1094 {
1095         int i;
1096
1097 #define VSD_OFFSET_SIG1         0x00
1098 #define VSD_OFFSET_SIG2         0xde
1099 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1100 #define VSD_OFFSET_TS_BOARD_ID  0x20
1101
1102 #define VSD_SIGNATURE_TOPSPIN   0x5ad
1103
1104         memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1105
1106         if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1107             be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1108                 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1109         } else {
1110                 /*
1111                  * The board ID is a string but the firmware byte
1112                  * swaps each 4-byte word before passing it back to
1113                  * us.  Therefore we need to swab it before printing.
1114                  */
1115                 for (i = 0; i < 4; ++i)
1116                         ((u32 *) board_id)[i] =
1117                                 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1118         }
1119 }
1120
1121 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1122                         struct mthca_adapter *adapter, u8 *status)
1123 {
1124         struct mthca_mailbox *mailbox;
1125         u32 *outbox;
1126         int err;
1127
1128 #define QUERY_ADAPTER_OUT_SIZE             0x100
1129 #define QUERY_ADAPTER_VENDOR_ID_OFFSET     0x00
1130 #define QUERY_ADAPTER_DEVICE_ID_OFFSET     0x04
1131 #define QUERY_ADAPTER_REVISION_ID_OFFSET   0x08
1132 #define QUERY_ADAPTER_INTA_PIN_OFFSET      0x10
1133 #define QUERY_ADAPTER_VSD_OFFSET           0x20
1134
1135         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1136         if (IS_ERR(mailbox))
1137                 return PTR_ERR(mailbox);
1138         outbox = mailbox->buf;
1139
1140         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1141                             CMD_TIME_CLASS_A, status);
1142
1143         if (err)
1144                 goto out;
1145
1146         MTHCA_GET(adapter->vendor_id, outbox,   QUERY_ADAPTER_VENDOR_ID_OFFSET);
1147         MTHCA_GET(adapter->device_id, outbox,   QUERY_ADAPTER_DEVICE_ID_OFFSET);
1148         MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
1149         MTHCA_GET(adapter->inta_pin, outbox,    QUERY_ADAPTER_INTA_PIN_OFFSET);
1150
1151         get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1152                      adapter->board_id);
1153
1154 out:
1155         mthca_free_mailbox(dev, mailbox);
1156         return err;
1157 }
1158
1159 int mthca_INIT_HCA(struct mthca_dev *dev,
1160                    struct mthca_init_hca_param *param,
1161                    u8 *status)
1162 {
1163         struct mthca_mailbox *mailbox;
1164         __be32 *inbox;
1165         int err;
1166
1167 #define INIT_HCA_IN_SIZE                 0x200
1168 #define INIT_HCA_FLAGS_OFFSET            0x014
1169 #define INIT_HCA_QPC_OFFSET              0x020
1170 #define  INIT_HCA_QPC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x10)
1171 #define  INIT_HCA_LOG_QP_OFFSET          (INIT_HCA_QPC_OFFSET + 0x17)
1172 #define  INIT_HCA_EEC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x20)
1173 #define  INIT_HCA_LOG_EEC_OFFSET         (INIT_HCA_QPC_OFFSET + 0x27)
1174 #define  INIT_HCA_SRQC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x28)
1175 #define  INIT_HCA_LOG_SRQ_OFFSET         (INIT_HCA_QPC_OFFSET + 0x2f)
1176 #define  INIT_HCA_CQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x30)
1177 #define  INIT_HCA_LOG_CQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x37)
1178 #define  INIT_HCA_EQPC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x40)
1179 #define  INIT_HCA_EEEC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x50)
1180 #define  INIT_HCA_EQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x60)
1181 #define  INIT_HCA_LOG_EQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x67)
1182 #define  INIT_HCA_RDB_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x70)
1183 #define INIT_HCA_UDAV_OFFSET             0x0b0
1184 #define  INIT_HCA_UDAV_LKEY_OFFSET       (INIT_HCA_UDAV_OFFSET + 0x0)
1185 #define  INIT_HCA_UDAV_PD_OFFSET         (INIT_HCA_UDAV_OFFSET + 0x4)
1186 #define INIT_HCA_MCAST_OFFSET            0x0c0
1187 #define  INIT_HCA_MC_BASE_OFFSET         (INIT_HCA_MCAST_OFFSET + 0x00)
1188 #define  INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1189 #define  INIT_HCA_MC_HASH_SZ_OFFSET      (INIT_HCA_MCAST_OFFSET + 0x16)
1190 #define  INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1191 #define INIT_HCA_TPT_OFFSET              0x0f0
1192 #define  INIT_HCA_MPT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x00)
1193 #define  INIT_HCA_MTT_SEG_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x09)
1194 #define  INIT_HCA_LOG_MPT_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x0b)
1195 #define  INIT_HCA_MTT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x10)
1196 #define INIT_HCA_UAR_OFFSET              0x120
1197 #define  INIT_HCA_UAR_BASE_OFFSET        (INIT_HCA_UAR_OFFSET + 0x00)
1198 #define  INIT_HCA_UARC_SZ_OFFSET         (INIT_HCA_UAR_OFFSET + 0x09)
1199 #define  INIT_HCA_LOG_UAR_SZ_OFFSET      (INIT_HCA_UAR_OFFSET + 0x0a)
1200 #define  INIT_HCA_UAR_PAGE_SZ_OFFSET     (INIT_HCA_UAR_OFFSET + 0x0b)
1201 #define  INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1202 #define  INIT_HCA_UAR_CTX_BASE_OFFSET    (INIT_HCA_UAR_OFFSET + 0x18)
1203
1204         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1205         if (IS_ERR(mailbox))
1206                 return PTR_ERR(mailbox);
1207         inbox = mailbox->buf;
1208
1209         memset(inbox, 0, INIT_HCA_IN_SIZE);
1210
1211 #if defined(__LITTLE_ENDIAN)
1212         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1213 #elif defined(__BIG_ENDIAN)
1214         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1215 #else
1216 #error Host endianness not defined
1217 #endif
1218         /* Check port for UD address vector: */
1219         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1220
1221         /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1222
1223         /* QPC/EEC/CQC/EQC/RDB attributes */
1224
1225         MTHCA_PUT(inbox, param->qpc_base,     INIT_HCA_QPC_BASE_OFFSET);
1226         MTHCA_PUT(inbox, param->log_num_qps,  INIT_HCA_LOG_QP_OFFSET);
1227         MTHCA_PUT(inbox, param->eec_base,     INIT_HCA_EEC_BASE_OFFSET);
1228         MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1229         MTHCA_PUT(inbox, param->srqc_base,    INIT_HCA_SRQC_BASE_OFFSET);
1230         MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1231         MTHCA_PUT(inbox, param->cqc_base,     INIT_HCA_CQC_BASE_OFFSET);
1232         MTHCA_PUT(inbox, param->log_num_cqs,  INIT_HCA_LOG_CQ_OFFSET);
1233         MTHCA_PUT(inbox, param->eqpc_base,    INIT_HCA_EQPC_BASE_OFFSET);
1234         MTHCA_PUT(inbox, param->eeec_base,    INIT_HCA_EEEC_BASE_OFFSET);
1235         MTHCA_PUT(inbox, param->eqc_base,     INIT_HCA_EQC_BASE_OFFSET);
1236         MTHCA_PUT(inbox, param->log_num_eqs,  INIT_HCA_LOG_EQ_OFFSET);
1237         MTHCA_PUT(inbox, param->rdb_base,     INIT_HCA_RDB_BASE_OFFSET);
1238
1239         /* UD AV attributes */
1240
1241         /* multicast attributes */
1242
1243         MTHCA_PUT(inbox, param->mc_base,         INIT_HCA_MC_BASE_OFFSET);
1244         MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1245         MTHCA_PUT(inbox, param->mc_hash_sz,      INIT_HCA_MC_HASH_SZ_OFFSET);
1246         MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1247
1248         /* TPT attributes */
1249
1250         MTHCA_PUT(inbox, param->mpt_base,   INIT_HCA_MPT_BASE_OFFSET);
1251         if (!mthca_is_memfree(dev))
1252                 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1253         MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1254         MTHCA_PUT(inbox, param->mtt_base,   INIT_HCA_MTT_BASE_OFFSET);
1255
1256         /* UAR attributes */
1257         {
1258                 u8 uar_page_sz = PAGE_SHIFT - 12;
1259                 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1260         }
1261
1262         MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1263
1264         if (mthca_is_memfree(dev)) {
1265                 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1266                 MTHCA_PUT(inbox, param->log_uar_sz,  INIT_HCA_LOG_UAR_SZ_OFFSET);
1267                 MTHCA_PUT(inbox, param->uarc_base,   INIT_HCA_UAR_CTX_BASE_OFFSET);
1268         }
1269
1270         err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status);
1271
1272         mthca_free_mailbox(dev, mailbox);
1273         return err;
1274 }
1275
1276 int mthca_INIT_IB(struct mthca_dev *dev,
1277                   struct mthca_init_ib_param *param,
1278                   int port, u8 *status)
1279 {
1280         struct mthca_mailbox *mailbox;
1281         u32 *inbox;
1282         int err;
1283         u32 flags;
1284
1285 #define INIT_IB_IN_SIZE          56
1286 #define INIT_IB_FLAGS_OFFSET     0x00
1287 #define INIT_IB_FLAG_SIG         (1 << 18)
1288 #define INIT_IB_FLAG_NG          (1 << 17)
1289 #define INIT_IB_FLAG_G0          (1 << 16)
1290 #define INIT_IB_VL_SHIFT         4
1291 #define INIT_IB_PORT_WIDTH_SHIFT 8
1292 #define INIT_IB_MTU_SHIFT        12
1293 #define INIT_IB_MAX_GID_OFFSET   0x06
1294 #define INIT_IB_MAX_PKEY_OFFSET  0x0a
1295 #define INIT_IB_GUID0_OFFSET     0x10
1296 #define INIT_IB_NODE_GUID_OFFSET 0x18
1297 #define INIT_IB_SI_GUID_OFFSET   0x20
1298
1299         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1300         if (IS_ERR(mailbox))
1301                 return PTR_ERR(mailbox);
1302         inbox = mailbox->buf;
1303
1304         memset(inbox, 0, INIT_IB_IN_SIZE);
1305
1306         flags = 0;
1307         flags |= param->set_guid0     ? INIT_IB_FLAG_G0  : 0;
1308         flags |= param->set_node_guid ? INIT_IB_FLAG_NG  : 0;
1309         flags |= param->set_si_guid   ? INIT_IB_FLAG_SIG : 0;
1310         flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1311         flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1312         flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1313         MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1314
1315         MTHCA_PUT(inbox, param->gid_cap,   INIT_IB_MAX_GID_OFFSET);
1316         MTHCA_PUT(inbox, param->pkey_cap,  INIT_IB_MAX_PKEY_OFFSET);
1317         MTHCA_PUT(inbox, param->guid0,     INIT_IB_GUID0_OFFSET);
1318         MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1319         MTHCA_PUT(inbox, param->si_guid,   INIT_IB_SI_GUID_OFFSET);
1320
1321         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1322                         CMD_TIME_CLASS_A, status);
1323
1324         mthca_free_mailbox(dev, mailbox);
1325         return err;
1326 }
1327
1328 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1329 {
1330         return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
1331 }
1332
1333 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1334 {
1335         return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
1336 }
1337
1338 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1339                  int port, u8 *status)
1340 {
1341         struct mthca_mailbox *mailbox;
1342         u32 *inbox;
1343         int err;
1344         u32 flags = 0;
1345
1346 #define SET_IB_IN_SIZE         0x40
1347 #define SET_IB_FLAGS_OFFSET    0x00
1348 #define SET_IB_FLAG_SIG        (1 << 18)
1349 #define SET_IB_FLAG_RQK        (1 <<  0)
1350 #define SET_IB_CAP_MASK_OFFSET 0x04
1351 #define SET_IB_SI_GUID_OFFSET  0x08
1352
1353         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1354         if (IS_ERR(mailbox))
1355                 return PTR_ERR(mailbox);
1356         inbox = mailbox->buf;
1357
1358         memset(inbox, 0, SET_IB_IN_SIZE);
1359
1360         flags |= param->set_si_guid     ? SET_IB_FLAG_SIG : 0;
1361         flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1362         MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1363
1364         MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1365         MTHCA_PUT(inbox, param->si_guid,  SET_IB_SI_GUID_OFFSET);
1366
1367         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1368                         CMD_TIME_CLASS_B, status);
1369
1370         mthca_free_mailbox(dev, mailbox);
1371         return err;
1372 }
1373
1374 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1375 {
1376         return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1377 }
1378
1379 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1380 {
1381         struct mthca_mailbox *mailbox;
1382         __be64 *inbox;
1383         int err;
1384
1385         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1386         if (IS_ERR(mailbox))
1387                 return PTR_ERR(mailbox);
1388         inbox = mailbox->buf;
1389
1390         inbox[0] = cpu_to_be64(virt);
1391         inbox[1] = cpu_to_be64(dma_addr);
1392
1393         err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1394                         CMD_TIME_CLASS_B, status);
1395
1396         mthca_free_mailbox(dev, mailbox);
1397
1398         if (!err)
1399                 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1400                           (unsigned long long) dma_addr, (unsigned long long) virt);
1401
1402         return err;
1403 }
1404
1405 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1406 {
1407         mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1408                   page_count, (unsigned long long) virt);
1409
1410         return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1411 }
1412
1413 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1414 {
1415         return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1416 }
1417
1418 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1419 {
1420         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1421 }
1422
1423 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1424                        u8 *status)
1425 {
1426         int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1427                                 CMD_TIME_CLASS_A, status);
1428
1429         if (ret || status)
1430                 return ret;
1431
1432         /*
1433          * Arbel page size is always 4 KB; round up number of system
1434          * pages needed.
1435          */
1436         *aux_pages = (*aux_pages + (1 << (PAGE_SHIFT - 12)) - 1) >> (PAGE_SHIFT - 12);
1437
1438         return 0;
1439 }
1440
1441 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1442                     int mpt_index, u8 *status)
1443 {
1444         return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1445                          CMD_TIME_CLASS_B, status);
1446 }
1447
1448 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1449                     int mpt_index, u8 *status)
1450 {
1451         return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1452                              !mailbox, CMD_HW2SW_MPT,
1453                              CMD_TIME_CLASS_B, status);
1454 }
1455
1456 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1457                     int num_mtt, u8 *status)
1458 {
1459         return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1460                          CMD_TIME_CLASS_B, status);
1461 }
1462
1463 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1464 {
1465         return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1466 }
1467
1468 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1469                  int eq_num, u8 *status)
1470 {
1471         mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1472                   unmap ? "Clearing" : "Setting",
1473                   (unsigned long long) event_mask, eq_num);
1474         return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1475                          0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1476 }
1477
1478 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1479                    int eq_num, u8 *status)
1480 {
1481         return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1482                          CMD_TIME_CLASS_A, status);
1483 }
1484
1485 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1486                    int eq_num, u8 *status)
1487 {
1488         return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1489                              CMD_HW2SW_EQ,
1490                              CMD_TIME_CLASS_A, status);
1491 }
1492
1493 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1494                    int cq_num, u8 *status)
1495 {
1496         return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1497                         CMD_TIME_CLASS_A, status);
1498 }
1499
1500 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1501                    int cq_num, u8 *status)
1502 {
1503         return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1504                              CMD_HW2SW_CQ,
1505                              CMD_TIME_CLASS_A, status);
1506 }
1507
1508 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1509                     int srq_num, u8 *status)
1510 {
1511         return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1512                         CMD_TIME_CLASS_A, status);
1513 }
1514
1515 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1516                     int srq_num, u8 *status)
1517 {
1518         return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1519                              CMD_HW2SW_SRQ,
1520                              CMD_TIME_CLASS_A, status);
1521 }
1522
1523 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status)
1524 {
1525         return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1526                          CMD_TIME_CLASS_B, status);
1527 }
1528
1529 int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
1530                     int is_ee, struct mthca_mailbox *mailbox, u32 optmask,
1531                     u8 *status)
1532 {
1533         static const u16 op[] = {
1534                 [MTHCA_TRANS_RST2INIT]  = CMD_RST2INIT_QPEE,
1535                 [MTHCA_TRANS_INIT2INIT] = CMD_INIT2INIT_QPEE,
1536                 [MTHCA_TRANS_INIT2RTR]  = CMD_INIT2RTR_QPEE,
1537                 [MTHCA_TRANS_RTR2RTS]   = CMD_RTR2RTS_QPEE,
1538                 [MTHCA_TRANS_RTS2RTS]   = CMD_RTS2RTS_QPEE,
1539                 [MTHCA_TRANS_SQERR2RTS] = CMD_SQERR2RTS_QPEE,
1540                 [MTHCA_TRANS_ANY2ERR]   = CMD_2ERR_QPEE,
1541                 [MTHCA_TRANS_RTS2SQD]   = CMD_RTS2SQD_QPEE,
1542                 [MTHCA_TRANS_SQD2SQD]   = CMD_SQD2SQD_QPEE,
1543                 [MTHCA_TRANS_SQD2RTS]   = CMD_SQD2RTS_QPEE,
1544                 [MTHCA_TRANS_ANY2RST]   = CMD_ERR2RST_QPEE
1545         };
1546         u8 op_mod = 0;
1547         int my_mailbox = 0;
1548         int err;
1549
1550         if (trans < 0 || trans >= ARRAY_SIZE(op))
1551                 return -EINVAL;
1552
1553         if (trans == MTHCA_TRANS_ANY2RST) {
1554                 op_mod = 3;     /* don't write outbox, any->reset */
1555
1556                 /* For debugging */
1557                 if (!mailbox) {
1558                         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1559                         if (!IS_ERR(mailbox)) {
1560                                 my_mailbox = 1;
1561                                 op_mod     = 2; /* write outbox, any->reset */
1562                         } else
1563                                 mailbox = NULL;
1564                 }
1565         } else {
1566                 if (0) {
1567                         int i;
1568                         mthca_dbg(dev, "Dumping QP context:\n");
1569                         printk("  opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1570                         for (i = 0; i < 0x100 / 4; ++i) {
1571                                 if (i % 8 == 0)
1572                                         printk("  [%02x] ", i * 4);
1573                                 printk(" %08x",
1574                                        be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1575                                 if ((i + 1) % 8 == 0)
1576                                         printk("\n");
1577                         }
1578                 }
1579         }
1580
1581         if (trans == MTHCA_TRANS_ANY2RST) {
1582                 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1583                                     (!!is_ee << 24) | num, op_mod,
1584                                     op[trans], CMD_TIME_CLASS_C, status);
1585
1586                 if (0 && mailbox) {
1587                         int i;
1588                         mthca_dbg(dev, "Dumping QP context:\n");
1589                         printk(" %08x\n", be32_to_cpup(mailbox->buf));
1590                         for (i = 0; i < 0x100 / 4; ++i) {
1591                                 if (i % 8 == 0)
1592                                         printk("[%02x] ", i * 4);
1593                                 printk(" %08x",
1594                                        be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1595                                 if ((i + 1) % 8 == 0)
1596                                         printk("\n");
1597                         }
1598                 }
1599
1600         } else
1601                 err = mthca_cmd(dev, mailbox->dma, (!!is_ee << 24) | num,
1602                                 op_mod, op[trans], CMD_TIME_CLASS_C, status);
1603
1604         if (my_mailbox)
1605                 mthca_free_mailbox(dev, mailbox);
1606
1607         return err;
1608 }
1609
1610 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1611                    struct mthca_mailbox *mailbox, u8 *status)
1612 {
1613         return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1614                              CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1615 }
1616
1617 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1618                           u8 *status)
1619 {
1620         u8 op_mod;
1621
1622         switch (type) {
1623         case IB_QPT_SMI:
1624                 op_mod = 0;
1625                 break;
1626         case IB_QPT_GSI:
1627                 op_mod = 1;
1628                 break;
1629         case IB_QPT_RAW_IPV6:
1630                 op_mod = 2;
1631                 break;
1632         case IB_QPT_RAW_ETY:
1633                 op_mod = 3;
1634                 break;
1635         default:
1636                 return -EINVAL;
1637         }
1638
1639         return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1640                          CMD_TIME_CLASS_B, status);
1641 }
1642
1643 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1644                   int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1645                   void *in_mad, void *response_mad, u8 *status)
1646 {
1647         struct mthca_mailbox *inmailbox, *outmailbox;
1648         void *inbox;
1649         int err;
1650         u32 in_modifier = port;
1651         u8 op_modifier = 0;
1652
1653 #define MAD_IFC_BOX_SIZE      0x400
1654 #define MAD_IFC_MY_QPN_OFFSET 0x100
1655 #define MAD_IFC_RQPN_OFFSET   0x104
1656 #define MAD_IFC_SL_OFFSET     0x108
1657 #define MAD_IFC_G_PATH_OFFSET 0x109
1658 #define MAD_IFC_RLID_OFFSET   0x10a
1659 #define MAD_IFC_PKEY_OFFSET   0x10e
1660 #define MAD_IFC_GRH_OFFSET    0x140
1661
1662         inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1663         if (IS_ERR(inmailbox))
1664                 return PTR_ERR(inmailbox);
1665         inbox = inmailbox->buf;
1666
1667         outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1668         if (IS_ERR(outmailbox)) {
1669                 mthca_free_mailbox(dev, inmailbox);
1670                 return PTR_ERR(outmailbox);
1671         }
1672
1673         memcpy(inbox, in_mad, 256);
1674
1675         /*
1676          * Key check traps can't be generated unless we have in_wc to
1677          * tell us where to send the trap.
1678          */
1679         if (ignore_mkey || !in_wc)
1680                 op_modifier |= 0x1;
1681         if (ignore_bkey || !in_wc)
1682                 op_modifier |= 0x2;
1683
1684         if (in_wc) {
1685                 u8 val;
1686
1687                 memset(inbox + 256, 0, 256);
1688
1689                 MTHCA_PUT(inbox, in_wc->qp_num,     MAD_IFC_MY_QPN_OFFSET);
1690                 MTHCA_PUT(inbox, in_wc->src_qp,     MAD_IFC_RQPN_OFFSET);
1691
1692                 val = in_wc->sl << 4;
1693                 MTHCA_PUT(inbox, val,               MAD_IFC_SL_OFFSET);
1694
1695                 val = in_wc->dlid_path_bits |
1696                         (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1697                 MTHCA_PUT(inbox, val,               MAD_IFC_GRH_OFFSET);
1698
1699                 MTHCA_PUT(inbox, in_wc->slid,       MAD_IFC_RLID_OFFSET);
1700                 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1701
1702                 if (in_grh)
1703                         memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1704
1705                 op_modifier |= 0x10;
1706
1707                 in_modifier |= in_wc->slid << 16;
1708         }
1709
1710         err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1711                             in_modifier, op_modifier,
1712                             CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1713
1714         if (!err && !*status)
1715                 memcpy(response_mad, outmailbox->buf, 256);
1716
1717         mthca_free_mailbox(dev, inmailbox);
1718         mthca_free_mailbox(dev, outmailbox);
1719         return err;
1720 }
1721
1722 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1723                    struct mthca_mailbox *mailbox, u8 *status)
1724 {
1725         return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1726                              CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1727 }
1728
1729 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1730                     struct mthca_mailbox *mailbox, u8 *status)
1731 {
1732         return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1733                          CMD_TIME_CLASS_A, status);
1734 }
1735
1736 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1737                     u16 *hash, u8 *status)
1738 {
1739         u64 imm;
1740         int err;
1741
1742         err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1743                             CMD_TIME_CLASS_A, status);
1744
1745         *hash = imm;
1746         return err;
1747 }
1748
1749 int mthca_NOP(struct mthca_dev *dev, u8 *status)
1750 {
1751         return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
1752 }