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   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  *
  33  * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $
  34  */
  35
  36 #include <linux/sched.h>
  37 #include <linux/pci.h>
  38 #include <linux/errno.h>
  39 #include <asm/io.h>
  40 #include <ib_mad.h>
  41
  42 #include "mthca_dev.h"
  43 #include "mthca_config_reg.h"
  44 #include "mthca_cmd.h"
  45 #include "mthca_memfree.h"
  46
  47 #define CMD_POLL_TOKEN 0xffff
  48
  49 enum {
  50         HCR_IN_PARAM_OFFSET    = 0x00,
  51         HCR_IN_MODIFIER_OFFSET = 0x08,
  52         HCR_OUT_PARAM_OFFSET   = 0x0c,
  53         HCR_TOKEN_OFFSET       = 0x14,
  54         HCR_STATUS_OFFSET      = 0x18,
  55
  56         HCR_OPMOD_SHIFT        = 12,
  57         HCA_E_BIT              = 22,
  58         HCR_GO_BIT             = 23
  59 };
  60
  61 enum {
  62         /* initialization and general commands */
  63         CMD_SYS_EN          = 0x1,
  64         CMD_SYS_DIS         = 0x2,
  65         CMD_MAP_FA          = 0xfff,
  66         CMD_UNMAP_FA        = 0xffe,
  67         CMD_RUN_FW          = 0xff6,
  68         CMD_MOD_STAT_CFG    = 0x34,
  69         CMD_QUERY_DEV_LIM   = 0x3,
  70         CMD_QUERY_FW        = 0x4,
  71         CMD_ENABLE_LAM      = 0xff8,
  72         CMD_DISABLE_LAM     = 0xff7,
  73         CMD_QUERY_DDR       = 0x5,
  74         CMD_QUERY_ADAPTER   = 0x6,
  75         CMD_INIT_HCA        = 0x7,
  76         CMD_CLOSE_HCA       = 0x8,
  77         CMD_INIT_IB         = 0x9,
  78         CMD_CLOSE_IB        = 0xa,
  79         CMD_QUERY_HCA       = 0xb,
  80         CMD_SET_IB          = 0xc,
  81         CMD_ACCESS_DDR      = 0x2e,
  82         CMD_MAP_ICM         = 0xffa,
  83         CMD_UNMAP_ICM       = 0xff9,
  84         CMD_MAP_ICM_AUX     = 0xffc,
  85         CMD_UNMAP_ICM_AUX   = 0xffb,
  86         CMD_SET_ICM_SIZE    = 0xffd,
  87
  88         /* TPT commands */
  89         CMD_SW2HW_MPT       = 0xd,
  90         CMD_QUERY_MPT       = 0xe,
  91         CMD_HW2SW_MPT       = 0xf,
  92         CMD_READ_MTT        = 0x10,
  93         CMD_WRITE_MTT       = 0x11,
  94         CMD_SYNC_TPT        = 0x2f,
  95
  96         /* EQ commands */
  97         CMD_MAP_EQ          = 0x12,
  98         CMD_SW2HW_EQ        = 0x13,
  99         CMD_HW2SW_EQ        = 0x14,
 100         CMD_QUERY_EQ        = 0x15,
 101
 102         /* CQ commands */
 103         CMD_SW2HW_CQ        = 0x16,
 104         CMD_HW2SW_CQ        = 0x17,
 105         CMD_QUERY_CQ        = 0x18,
 106         CMD_RESIZE_CQ       = 0x2c,
 107
 108         /* SRQ commands */
 109         CMD_SW2HW_SRQ       = 0x35,
 110         CMD_HW2SW_SRQ       = 0x36,
 111         CMD_QUERY_SRQ       = 0x37,
 112
 113         /* QP/EE commands */
 114         CMD_RST2INIT_QPEE   = 0x19,
 115         CMD_INIT2RTR_QPEE   = 0x1a,
 116         CMD_RTR2RTS_QPEE    = 0x1b,
 117         CMD_RTS2RTS_QPEE    = 0x1c,
 118         CMD_SQERR2RTS_QPEE  = 0x1d,
 119         CMD_2ERR_QPEE       = 0x1e,
 120         CMD_RTS2SQD_QPEE    = 0x1f,
 121         CMD_SQD2SQD_QPEE    = 0x38,
 122         CMD_SQD2RTS_QPEE    = 0x20,
 123         CMD_ERR2RST_QPEE    = 0x21,
 124         CMD_QUERY_QPEE      = 0x22,
 125         CMD_INIT2INIT_QPEE  = 0x2d,
 126         CMD_SUSPEND_QPEE    = 0x32,
 127         CMD_UNSUSPEND_QPEE  = 0x33,
 128         /* special QPs and management commands */
 129         CMD_CONF_SPECIAL_QP = 0x23,
 130         CMD_MAD_IFC         = 0x24,
 131
 132         /* multicast commands */
 133         CMD_READ_MGM        = 0x25,
 134         CMD_WRITE_MGM       = 0x26,
 135         CMD_MGID_HASH       = 0x27,
 136
 137         /* miscellaneous commands */
 138         CMD_DIAG_RPRT       = 0x30,
 139         CMD_NOP             = 0x31,
 140
 141         /* debug commands */
 142         CMD_QUERY_DEBUG_MSG = 0x2a,
 143         CMD_SET_DEBUG_MSG   = 0x2b,
 144 };
 145
 146 /*
 147  * According to Mellanox code, FW may be starved and never complete
 148  * commands.  So we can't use strict timeouts described in PRM -- we
 149  * just arbitrarily select 60 seconds for now.
 150  */
 151 #if 0
 152 /*
 153  * Round up and add 1 to make sure we get the full wait time (since we
 154  * will be starting in the middle of a jiffy)
 155  */
 156 enum {
 157         CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
 158         CMD_TIME_CLASS_B = (HZ +  99) /  100 + 1,
 159         CMD_TIME_CLASS_C = (HZ +   9) /   10 + 1
 160 };
 161 #else
 162 enum {
 163         CMD_TIME_CLASS_A = 60 * HZ,
 164         CMD_TIME_CLASS_B = 60 * HZ,
 165         CMD_TIME_CLASS_C = 60 * HZ
 166 };
 167 #endif
 168
 169 enum {
 170         GO_BIT_TIMEOUT = HZ * 10
 171 };
 172
 173 struct mthca_cmd_context {
 174         struct completion done;
 175         struct timer_list timer;
 176         int               result;
 177         int               next;
 178         u64               out_param;
 179         u16               token;
 180         u8                status;
 181 };
 182
 183 static inline int go_bit(struct mthca_dev *dev)
 184 {
 185         return readl(dev->hcr + HCR_STATUS_OFFSET) &
 186                 swab32(1 << HCR_GO_BIT);
 187 }
 188
 189 static int mthca_cmd_post(struct mthca_dev *dev,
 190                           u64 in_param,
 191                           u64 out_param,
 192                           u32 in_modifier,
 193                           u8 op_modifier,
 194                           u16 op,
 195                           u16 token,
 196                           int event)
 197 {
 198         int err = 0;
 199
 200         if (down_interruptible(&dev->cmd.hcr_sem))
 201                 return -EINTR;
 202
 203         if (event) {
 204                 unsigned long end = jiffies + GO_BIT_TIMEOUT;
 205
 206                 while (go_bit(dev) && time_before(jiffies, end)) {
 207                         set_current_state(TASK_RUNNING);
 208                         schedule();
 209                 }
 210         }
 211
 212         if (go_bit(dev)) {
 213                 err = -EAGAIN;
 214                 goto out;
 215         }
 216
 217         /*
 218          * We use writel (instead of something like memcpy_toio)
 219          * because writes of less than 32 bits to the HCR don't work
 220          * (and some architectures such as ia64 implement memcpy_toio
 221          * in terms of writeb).
 222          */
 223         __raw_writel(cpu_to_be32(in_param >> 32),           dev->hcr + 0 * 4);
 224         __raw_writel(cpu_to_be32(in_param & 0xfffffffful),  dev->hcr + 1 * 4);
 225         __raw_writel(cpu_to_be32(in_modifier),              dev->hcr + 2 * 4);
 226         __raw_writel(cpu_to_be32(out_param >> 32),          dev->hcr + 3 * 4);
 227         __raw_writel(cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
 228         __raw_writel(cpu_to_be32(token << 16),              dev->hcr + 5 * 4);
 229
 230         /* __raw_writel may not order writes. */
 231         wmb();
 232
 233         __raw_writel(cpu_to_be32((1 << HCR_GO_BIT)                |
 234                                  (event ? (1 << HCA_E_BIT) : 0)   |
 235                                  (op_modifier << HCR_OPMOD_SHIFT) |
 236                                  op),                       dev->hcr + 6 * 4);
 237
 238 out:
 239         up(&dev->cmd.hcr_sem);
 240         return err;
 241 }
 242
 243 static int mthca_cmd_poll(struct mthca_dev *dev,
 244                           u64 in_param,
 245                           u64 *out_param,
 246                           int out_is_imm,
 247                           u32 in_modifier,
 248                           u8 op_modifier,
 249                           u16 op,
 250                           unsigned long timeout,
 251                           u8 *status)
 252 {
 253         int err = 0;
 254         unsigned long end;
 255
 256         if (down_interruptible(&dev->cmd.poll_sem))
 257                 return -EINTR;
 258
 259         err = mthca_cmd_post(dev, in_param,
 260                              out_param ? *out_param : 0,
 261                              in_modifier, op_modifier,
 262                              op, CMD_POLL_TOKEN, 0);
 263         if (err)
 264                 goto out;
 265
 266         end = timeout + jiffies;
 267         while (go_bit(dev) && time_before(jiffies, end)) {
 268                 set_current_state(TASK_RUNNING);
 269                 schedule();
 270         }
 271
 272         if (go_bit(dev)) {
 273                 err = -EBUSY;
 274                 goto out;
 275         }
 276
 277         if (out_is_imm) {
 278                 memcpy_fromio(out_param, dev->hcr + HCR_OUT_PARAM_OFFSET, sizeof (u64));
 279                 be64_to_cpus(out_param);
 280         }
 281
 282         *status = be32_to_cpu(__raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
 283
 284 out:
 285         up(&dev->cmd.poll_sem);
 286         return err;
 287 }
 288
 289 void mthca_cmd_event(struct mthca_dev *dev,
 290                      u16 token,
 291                      u8  status,
 292                      u64 out_param)
 293 {
 294         struct mthca_cmd_context *context =
 295                 &dev->cmd.context[token & dev->cmd.token_mask];
 296
 297         /* previously timed out command completing at long last */
 298         if (token != context->token)
 299                 return;
 300
 301         context->result    = 0;
 302         context->status    = status;
 303         context->out_param = out_param;
 304
 305         context->token += dev->cmd.token_mask + 1;
 306
 307         complete(&context->done);
 308 }
 309
 310 static void event_timeout(unsigned long context_ptr)
 311 {
 312         struct mthca_cmd_context *context =
 313                 (struct mthca_cmd_context *) context_ptr;
 314
 315         context->result = -EBUSY;
 316         complete(&context->done);
 317 }
 318
 319 static int mthca_cmd_wait(struct mthca_dev *dev,
 320                           u64 in_param,
 321                           u64 *out_param,
 322                           int out_is_imm,
 323                           u32 in_modifier,
 324                           u8 op_modifier,
 325                           u16 op,
 326                           unsigned long timeout,
 327                           u8 *status)
 328 {
 329         int err = 0;
 330         struct mthca_cmd_context *context;
 331
 332         if (down_interruptible(&dev->cmd.event_sem))
 333                 return -EINTR;
 334
 335         spin_lock(&dev->cmd.context_lock);
 336         BUG_ON(dev->cmd.free_head < 0);
 337         context = &dev->cmd.context[dev->cmd.free_head];
 338         dev->cmd.free_head = context->next;
 339         spin_unlock(&dev->cmd.context_lock);
 340
 341         init_completion(&context->done);
 342
 343         err = mthca_cmd_post(dev, in_param,
 344                              out_param ? *out_param : 0,
 345                              in_modifier, op_modifier,
 346                              op, context->token, 1);
 347         if (err)
 348                 goto out;
 349
 350         context->timer.expires  = jiffies + timeout;
 351         add_timer(&context->timer);
 352
 353         wait_for_completion(&context->done);
 354         del_timer_sync(&context->timer);
 355
 356         err = context->result;
 357         if (err)
 358                 goto out;
 359
 360         *status = context->status;
 361         if (*status)
 362                 mthca_dbg(dev, "Command %02x completed with status %02x\n",
 363                           op, *status);
 364
 365         if (out_is_imm)
 366                 *out_param = context->out_param;
 367
 368 out:
 369         spin_lock(&dev->cmd.context_lock);
 370         context->next = dev->cmd.free_head;
 371         dev->cmd.free_head = context - dev->cmd.context;
 372         spin_unlock(&dev->cmd.context_lock);
 373
 374         up(&dev->cmd.event_sem);
 375         return err;
 376 }
 377
 378 /* Invoke a command with an output mailbox */
 379 static int mthca_cmd_box(struct mthca_dev *dev,
 380                          u64 in_param,
 381                          u64 out_param,
 382                          u32 in_modifier,
 383                          u8 op_modifier,
 384                          u16 op,
 385                          unsigned long timeout,
 386                          u8 *status)
 387 {
 388         if (dev->cmd.use_events)
 389                 return mthca_cmd_wait(dev, in_param, &out_param, 0,
 390                                       in_modifier, op_modifier, op,
 391                                       timeout, status);
 392         else
 393                 return mthca_cmd_poll(dev, in_param, &out_param, 0,
 394                                       in_modifier, op_modifier, op,
 395                                       timeout, status);
 396 }
 397
 398 /* Invoke a command with no output parameter */
 399 static int mthca_cmd(struct mthca_dev *dev,
 400                      u64 in_param,
 401                      u32 in_modifier,
 402                      u8 op_modifier,
 403                      u16 op,
 404                      unsigned long timeout,
 405                      u8 *status)
 406 {
 407         return mthca_cmd_box(dev, in_param, 0, in_modifier,
 408                              op_modifier, op, timeout, status);
 409 }
 410
 411 /*
 412  * Invoke a command with an immediate output parameter (and copy the
 413  * output into the caller's out_param pointer after the command
 414  * executes).
 415  */
 416 static int mthca_cmd_imm(struct mthca_dev *dev,
 417                          u64 in_param,
 418                          u64 *out_param,
 419                          u32 in_modifier,
 420                          u8 op_modifier,
 421                          u16 op,
 422                          unsigned long timeout,
 423                          u8 *status)
 424 {
 425         if (dev->cmd.use_events)
 426                 return mthca_cmd_wait(dev, in_param, out_param, 1,
 427                                       in_modifier, op_modifier, op,
 428                                       timeout, status);
 429         else
 430                 return mthca_cmd_poll(dev, in_param, out_param, 1,
 431                                       in_modifier, op_modifier, op,
 432                                       timeout, status);
 433 }
 434
 435 int mthca_cmd_init(struct mthca_dev *dev)
 436 {
 437         sema_init(&dev->cmd.hcr_sem, 1);
 438         sema_init(&dev->cmd.poll_sem, 1);
 439         dev->cmd.use_events = 0;
 440
 441         dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
 442                            MTHCA_HCR_SIZE);
 443         if (!dev->hcr) {
 444                 mthca_err(dev, "Couldn't map command register.");
 445                 return -ENOMEM;
 446         }
 447
 448         dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
 449                                         MTHCA_MAILBOX_SIZE,
 450                                         MTHCA_MAILBOX_SIZE, 0);
 451         if (!dev->cmd.pool) {
 452                 iounmap(dev->hcr);
 453                 return -ENOMEM;
 454         }
 455
 456         return 0;
 457 }
 458
 459 void mthca_cmd_cleanup(struct mthca_dev *dev)
 460 {
 461         pci_pool_destroy(dev->cmd.pool);
 462         iounmap(dev->hcr);
 463 }
 464
 465 /*
 466  * Switch to using events to issue FW commands (should be called after
 467  * event queue to command events has been initialized).
 468  */
 469 int mthca_cmd_use_events(struct mthca_dev *dev)
 470 {
 471         int i;
 472
 473         dev->cmd.context = kmalloc(dev->cmd.max_cmds *
 474                                    sizeof (struct mthca_cmd_context),
 475                                    GFP_KERNEL);
 476         if (!dev->cmd.context)
 477                 return -ENOMEM;
 478
 479         for (i = 0; i < dev->cmd.max_cmds; ++i) {
 480                 dev->cmd.context[i].token = i;
 481                 dev->cmd.context[i].next = i + 1;
 482                 init_timer(&dev->cmd.context[i].timer);
 483                 dev->cmd.context[i].timer.data     =
 484                         (unsigned long) &dev->cmd.context[i];
 485                 dev->cmd.context[i].timer.function = event_timeout;
 486         }
 487
 488         dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
 489         dev->cmd.free_head = 0;
 490
 491         sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
 492         spin_lock_init(&dev->cmd.context_lock);
 493
 494         for (dev->cmd.token_mask = 1;
 495              dev->cmd.token_mask < dev->cmd.max_cmds;
 496              dev->cmd.token_mask <<= 1)
 497                 ; /* nothing */
 498         --dev->cmd.token_mask;
 499
 500         dev->cmd.use_events = 1;
 501         down(&dev->cmd.poll_sem);
 502
 503         return 0;
 504 }
 505
 506 /*
 507  * Switch back to polling (used when shutting down the device)
 508  */
 509 void mthca_cmd_use_polling(struct mthca_dev *dev)
 510 {
 511         int i;
 512
 513         dev->cmd.use_events = 0;
 514
 515         for (i = 0; i < dev->cmd.max_cmds; ++i)
 516                 down(&dev->cmd.event_sem);
 517
 518         kfree(dev->cmd.context);
 519
 520         up(&dev->cmd.poll_sem);
 521 }
 522
 523 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
 524                                           unsigned int gfp_mask)
 525 {
 526         struct mthca_mailbox *mailbox;
 527
 528         mailbox = kmalloc(sizeof *mailbox, gfp_mask);
 529         if (!mailbox)
 530                 return ERR_PTR(-ENOMEM);
 531
 532         mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
 533         if (!mailbox->buf) {
 534                 kfree(mailbox);
 535                 return ERR_PTR(-ENOMEM);
 536         }
 537
 538         return mailbox;
 539 }
 540
 541 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
 542 {
 543         if (!mailbox)
 544                 return;
 545
 546         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 547         kfree(mailbox);
 548 }
 549
 550 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
 551 {
 552         u64 out;
 553         int ret;
 554
 555         ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
 556
 557         if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
 558                 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
 559                            "sladdr=%d, SPD source=%s\n",
 560                            (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
 561                            (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
 562
 563         return ret;
 564 }
 565
 566 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
 567 {
 568         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
 569 }
 570
 571 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
 572                          u64 virt, u8 *status)
 573 {
 574         struct mthca_mailbox *mailbox;
 575         struct mthca_icm_iter iter;
 576         __be64 *pages;
 577         int lg;
 578         int nent = 0;
 579         int i;
 580         int err = 0;
 581         int ts = 0, tc = 0;
 582
 583         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 584         if (IS_ERR(mailbox))
 585                 return PTR_ERR(mailbox);
 586         memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
 587         pages = mailbox->buf;
 588
 589         for (mthca_icm_first(icm, &iter);
 590              !mthca_icm_last(&iter);
 591              mthca_icm_next(&iter)) {
 592                 /*
 593                  * We have to pass pages that are aligned to their
 594                  * size, so find the least significant 1 in the
 595                  * address or size and use that as our log2 size.
 596                  */
 597                 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
 598                 if (lg < 12) {
 599                         mthca_warn(dev, "Got FW area not aligned to 4K (%llx/%lx).\n",
 600                                    (unsigned long long) mthca_icm_addr(&iter),
 601                                    mthca_icm_size(&iter));
 602                         err = -EINVAL;
 603                         goto out;
 604                 }
 605                 for (i = 0; i < mthca_icm_size(&iter) / (1 << lg); ++i, ++nent) {
 606                         if (virt != -1) {
 607                                 pages[nent * 2] = cpu_to_be64(virt);
 608                                 virt += 1 << lg;
 609                         }
 610
 611                         pages[nent * 2 + 1] = cpu_to_be64((mthca_icm_addr(&iter) +
 612                                                            (i << lg)) | (lg - 12));
 613                         ts += 1 << (lg - 10);
 614                         ++tc;
 615
 616                         if (nent == MTHCA_MAILBOX_SIZE / 16) {
 617                                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 618                                                 CMD_TIME_CLASS_B, status);
 619                                 if (err || *status)
 620                                         goto out;
 621                                 nent = 0;
 622                         }
 623                 }
 624         }
 625
 626         if (nent)
 627                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 628                                 CMD_TIME_CLASS_B, status);
 629
 630         switch (op) {
 631         case CMD_MAP_FA:
 632                 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
 633                 break;
 634         case CMD_MAP_ICM_AUX:
 635                 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
 636                 break;
 637         case CMD_MAP_ICM:
 638                 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
 639                           tc, ts, (unsigned long long) virt - (ts << 10));
 640                 break;
 641         }
 642
 643 out:
 644         mthca_free_mailbox(dev, mailbox);
 645         return err;
 646 }
 647
 648 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
 649 {
 650         return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
 651 }
 652
 653 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
 654 {
 655         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
 656 }
 657
 658 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
 659 {
 660         return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
 661 }
 662
 663 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
 664 {
 665         struct mthca_mailbox *mailbox;
 666         u32 *outbox;
 667         int err = 0;
 668         u8 lg;
 669
 670 #define QUERY_FW_OUT_SIZE             0x100
 671 #define QUERY_FW_VER_OFFSET            0x00
 672 #define QUERY_FW_MAX_CMD_OFFSET        0x0f
 673 #define QUERY_FW_ERR_START_OFFSET      0x30
 674 #define QUERY_FW_ERR_SIZE_OFFSET       0x38
 675
 676 #define QUERY_FW_START_OFFSET          0x20
 677 #define QUERY_FW_END_OFFSET            0x28
 678
 679 #define QUERY_FW_SIZE_OFFSET           0x00
 680 #define QUERY_FW_CLR_INT_BASE_OFFSET   0x20
 681 #define QUERY_FW_EQ_ARM_BASE_OFFSET    0x40
 682 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
 683
 684         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 685         if (IS_ERR(mailbox))
 686                 return PTR_ERR(mailbox);
 687         outbox = mailbox->buf;
 688
 689         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
 690                             CMD_TIME_CLASS_A, status);
 691
 692         if (err)
 693                 goto out;
 694
 695         MTHCA_GET(dev->fw_ver,   outbox, QUERY_FW_VER_OFFSET);
 696         /*
 697          * FW subminor version is at more signifant bits than minor
 698          * version, so swap here.
 699          */
 700         dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
 701                 ((dev->fw_ver & 0xffff0000ull) >> 16) |
 702                 ((dev->fw_ver & 0x0000ffffull) << 16);
 703
 704         MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
 705         dev->cmd.max_cmds = 1 << lg;
 706
 707         mthca_dbg(dev, "FW version %012llx, max commands %d\n",
 708                   (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
 709
 710         if (mthca_is_memfree(dev)) {
 711                 MTHCA_GET(dev->fw.arbel.fw_pages,       outbox, QUERY_FW_SIZE_OFFSET);
 712                 MTHCA_GET(dev->fw.arbel.clr_int_base,   outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
 713                 MTHCA_GET(dev->fw.arbel.eq_arm_base,    outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
 714                 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
 715                 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
 716
 717                 /*
 718                  * Arbel page size is always 4 KB; round up number of
 719                  * system pages needed.
 720                  */
 721                 dev->fw.arbel.fw_pages =
 722                         (dev->fw.arbel.fw_pages + (1 << (PAGE_SHIFT - 12)) - 1) >>
 723                         (PAGE_SHIFT - 12);
 724
 725                 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
 726                           (unsigned long long) dev->fw.arbel.clr_int_base,
 727                           (unsigned long long) dev->fw.arbel.eq_arm_base,
 728                           (unsigned long long) dev->fw.arbel.eq_set_ci_base);
 729         } else {
 730                 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
 731                 MTHCA_GET(dev->fw.tavor.fw_end,   outbox, QUERY_FW_END_OFFSET);
 732
 733                 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
 734                           (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
 735                           (unsigned long long) dev->fw.tavor.fw_start,
 736                           (unsigned long long) dev->fw.tavor.fw_end);
 737         }
 738
 739 out:
 740         mthca_free_mailbox(dev, mailbox);
 741         return err;
 742 }
 743
 744 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
 745 {
 746         struct mthca_mailbox *mailbox;
 747         u8 info;
 748         u32 *outbox;
 749         int err = 0;
 750
 751 #define ENABLE_LAM_OUT_SIZE         0x100
 752 #define ENABLE_LAM_START_OFFSET     0x00
 753 #define ENABLE_LAM_END_OFFSET       0x08
 754 #define ENABLE_LAM_INFO_OFFSET      0x13
 755
 756 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
 757 #define ENABLE_LAM_INFO_ECC_MASK    0x3
 758
 759         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 760         if (IS_ERR(mailbox))
 761                 return PTR_ERR(mailbox);
 762         outbox = mailbox->buf;
 763
 764         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
 765                             CMD_TIME_CLASS_C, status);
 766
 767         if (err)
 768                 goto out;
 769
 770         if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
 771                 goto out;
 772
 773         MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
 774         MTHCA_GET(dev->ddr_end,   outbox, ENABLE_LAM_END_OFFSET);
 775         MTHCA_GET(info,           outbox, ENABLE_LAM_INFO_OFFSET);
 776
 777         if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
 778             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 779                 mthca_info(dev, "FW reports that HCA-attached memory "
 780                            "is %s hidden; does not match PCI config\n",
 781                            (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
 782                            "" : "not");
 783         }
 784         if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
 785                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
 786
 787         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
 788                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 789                   (unsigned long long) dev->ddr_start,
 790                   (unsigned long long) dev->ddr_end);
 791
 792 out:
 793         mthca_free_mailbox(dev, mailbox);
 794         return err;
 795 }
 796
 797 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
 798 {
 799         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
 800 }
 801
 802 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
 803 {
 804         struct mthca_mailbox *mailbox;
 805         u8 info;
 806         u32 *outbox;
 807         int err = 0;
 808
 809 #define QUERY_DDR_OUT_SIZE         0x100
 810 #define QUERY_DDR_START_OFFSET     0x00
 811 #define QUERY_DDR_END_OFFSET       0x08
 812 #define QUERY_DDR_INFO_OFFSET      0x13
 813
 814 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
 815 #define QUERY_DDR_INFO_ECC_MASK    0x3
 816
 817         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 818         if (IS_ERR(mailbox))
 819                 return PTR_ERR(mailbox);
 820         outbox = mailbox->buf;
 821
 822         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
 823                             CMD_TIME_CLASS_A, status);
 824
 825         if (err)
 826                 goto out;
 827
 828         MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
 829         MTHCA_GET(dev->ddr_end,   outbox, QUERY_DDR_END_OFFSET);
 830         MTHCA_GET(info,           outbox, QUERY_DDR_INFO_OFFSET);
 831
 832         if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
 833             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 834                 mthca_info(dev, "FW reports that HCA-attached memory "
 835                            "is %s hidden; does not match PCI config\n",
 836                            (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
 837                            "" : "not");
 838         }
 839         if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
 840                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
 841
 842         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
 843                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 844                   (unsigned long long) dev->ddr_start,
 845                   (unsigned long long) dev->ddr_end);
 846
 847 out:
 848         mthca_free_mailbox(dev, mailbox);
 849         return err;
 850 }
 851
 852 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
 853                         struct mthca_dev_lim *dev_lim, u8 *status)
 854 {
 855         struct mthca_mailbox *mailbox;
 856         u32 *outbox;
 857         u8 field;
 858         u16 size;
 859         int err;
 860
 861 #define QUERY_DEV_LIM_OUT_SIZE             0x100
 862 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET     0x10
 863 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET      0x11
 864 #define QUERY_DEV_LIM_RSVD_QP_OFFSET        0x12
 865 #define QUERY_DEV_LIM_MAX_QP_OFFSET         0x13
 866 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET       0x14
 867 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET        0x15
 868 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET       0x16
 869 #define QUERY_DEV_LIM_MAX_EEC_OFFSET        0x17
 870 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET      0x19
 871 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET        0x1a
 872 #define QUERY_DEV_LIM_MAX_CQ_OFFSET         0x1b
 873 #define QUERY_DEV_LIM_MAX_MPT_OFFSET        0x1d
 874 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET        0x1e
 875 #define QUERY_DEV_LIM_MAX_EQ_OFFSET         0x1f
 876 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET       0x20
 877 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET     0x21
 878 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET       0x22
 879 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET    0x23
 880 #define QUERY_DEV_LIM_MAX_AV_OFFSET         0x27
 881 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET     0x29
 882 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET     0x2b
 883 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET       0x2f
 884 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET        0x33
 885 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET      0x35
 886 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET      0x36
 887 #define QUERY_DEV_LIM_VL_PORT_OFFSET        0x37
 888 #define QUERY_DEV_LIM_MAX_GID_OFFSET        0x3b
 889 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET       0x3f
 890 #define QUERY_DEV_LIM_FLAGS_OFFSET          0x44
 891 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET       0x48
 892 #define QUERY_DEV_LIM_UAR_SZ_OFFSET         0x49
 893 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET        0x4b
 894 #define QUERY_DEV_LIM_MAX_SG_OFFSET         0x51
 895 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET    0x52
 896 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET      0x55
 897 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
 898 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET     0x61
 899 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET       0x62
 900 #define QUERY_DEV_LIM_MAX_MCG_OFFSET        0x63
 901 #define QUERY_DEV_LIM_RSVD_PD_OFFSET        0x64
 902 #define QUERY_DEV_LIM_MAX_PD_OFFSET         0x65
 903 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET       0x66
 904 #define QUERY_DEV_LIM_MAX_RDD_OFFSET        0x67
 905 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET   0x80
 906 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET   0x82
 907 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET  0x84
 908 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET  0x86
 909 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET   0x88
 910 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET   0x8a
 911 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET   0x8c
 912 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET   0x8e
 913 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET   0x90
 914 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET   0x92
 915 #define QUERY_DEV_LIM_PBL_SZ_OFFSET         0x96
 916 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET     0x97
 917 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET      0x98
 918 #define QUERY_DEV_LIM_LAMR_OFFSET           0x9f
 919 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET     0xa0
 920
 921         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 922         if (IS_ERR(mailbox))
 923                 return PTR_ERR(mailbox);
 924         outbox = mailbox->buf;
 925
 926         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
 927                             CMD_TIME_CLASS_A, status);
 928
 929         if (err)
 930                 goto out;
 931
 932         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
 933         dev_lim->max_srq_sz = 1 << field;
 934         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
 935         dev_lim->max_qp_sz = 1 << field;
 936         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
 937         dev_lim->reserved_qps = 1 << (field & 0xf);
 938         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
 939         dev_lim->max_qps = 1 << (field & 0x1f);
 940         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
 941         dev_lim->reserved_srqs = 1 << (field >> 4);
 942         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
 943         dev_lim->max_srqs = 1 << (field & 0x1f);
 944         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
 945         dev_lim->reserved_eecs = 1 << (field & 0xf);
 946         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
 947         dev_lim->max_eecs = 1 << (field & 0x1f);
 948         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
 949         dev_lim->max_cq_sz = 1 << field;
 950         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
 951         dev_lim->reserved_cqs = 1 << (field & 0xf);
 952         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
 953         dev_lim->max_cqs = 1 << (field & 0x1f);
 954         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
 955         dev_lim->max_mpts = 1 << (field & 0x3f);
 956         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
 957         dev_lim->reserved_eqs = 1 << (field & 0xf);
 958         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
 959         dev_lim->max_eqs = 1 << (field & 0x7);
 960         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
 961         dev_lim->reserved_mtts = 1 << (field >> 4);
 962         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
 963         dev_lim->max_mrw_sz = 1 << field;
 964         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
 965         dev_lim->reserved_mrws = 1 << (field & 0xf);
 966         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
 967         dev_lim->max_mtt_seg = 1 << (field & 0x3f);
 968         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
 969         dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
 970         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
 971         dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
 972         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
 973         dev_lim->max_rdma_global = 1 << (field & 0x3f);
 974         MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
 975         dev_lim->local_ca_ack_delay = field & 0x1f;
 976         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
 977         dev_lim->max_mtu        = field >> 4;
 978         dev_lim->max_port_width = field & 0xf;
 979         MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
 980         dev_lim->max_vl    = field >> 4;
 981         dev_lim->num_ports = field & 0xf;
 982         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
 983         dev_lim->max_gids = 1 << (field & 0xf);
 984         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
 985         dev_lim->max_pkeys = 1 << (field & 0xf);
 986         MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
 987         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
 988         dev_lim->reserved_uars = field >> 4;
 989         MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
 990         dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
 991         MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
 992         dev_lim->min_page_sz = 1 << field;
 993         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
 994         dev_lim->max_sg = field;
 995
 996         MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
 997         dev_lim->max_desc_sz = size;
 998
 999         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1000         dev_lim->max_qp_per_mcg = 1 << field;
1001         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1002         dev_lim->reserved_mgms = field & 0xf;
1003         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1004         dev_lim->max_mcgs = 1 << field;
1005         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1006         dev_lim->reserved_pds = field >> 4;
1007         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1008         dev_lim->max_pds = 1 << (field & 0x3f);
1009         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1010         dev_lim->reserved_rdds = field >> 4;
1011         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1012         dev_lim->max_rdds = 1 << (field & 0x3f);
1013
1014         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1015         dev_lim->eec_entry_sz = size;
1016         MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1017         dev_lim->qpc_entry_sz = size;
1018         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1019         dev_lim->eeec_entry_sz = size;
1020         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1021         dev_lim->eqpc_entry_sz = size;
1022         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1023         dev_lim->eqc_entry_sz = size;
1024         MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1025         dev_lim->cqc_entry_sz = size;
1026         MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1027         dev_lim->srq_entry_sz = size;
1028         MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1029         dev_lim->uar_scratch_entry_sz = size;
1030
1031         mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1032                   dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1033         mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1034                   dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1035         mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1036                   dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1037         mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1038                   dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1039         mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1040                   dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1041         mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1042                   dev_lim->max_pds, dev_lim->reserved_mgms);
1043
1044         mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1045
1046         if (mthca_is_memfree(dev)) {
1047                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1048                 dev_lim->hca.arbel.resize_srq = field & 1;
1049                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1050                 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1051                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1052                 dev_lim->mpt_entry_sz = size;
1053                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1054                 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1055                 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1056                           QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1057                 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1058                           QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1059                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1060                 dev_lim->hca.arbel.lam_required = field & 1;
1061                 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1062                           QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1063
1064                 if (dev_lim->hca.arbel.bmme_flags & 1)
1065                         mthca_dbg(dev, "Base MM extensions: yes "
1066                                   "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1067                                   dev_lim->hca.arbel.bmme_flags,
1068                                   dev_lim->hca.arbel.max_pbl_sz,
1069                                   dev_lim->hca.arbel.reserved_lkey);
1070                 else
1071                         mthca_dbg(dev, "Base MM extensions: no\n");
1072
1073                 mthca_dbg(dev, "Max ICM size %lld MB\n",
1074                           (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1075         } else {
1076                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1077                 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1078                 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1079         }
1080
1081 out:
1082         mthca_free_mailbox(dev, mailbox);
1083         return err;
1084 }
1085
1086 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1087                         struct mthca_adapter *adapter, u8 *status)
1088 {
1089         struct mthca_mailbox *mailbox;
1090         u32 *outbox;
1091         int err;
1092
1093 #define QUERY_ADAPTER_OUT_SIZE             0x100
1094 #define QUERY_ADAPTER_VENDOR_ID_OFFSET     0x00
1095 #define QUERY_ADAPTER_DEVICE_ID_OFFSET     0x04
1096 #define QUERY_ADAPTER_REVISION_ID_OFFSET   0x08
1097 #define QUERY_ADAPTER_INTA_PIN_OFFSET      0x10
1098
1099         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1100         if (IS_ERR(mailbox))
1101                 return PTR_ERR(mailbox);
1102         outbox = mailbox->buf;
1103
1104         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1105                             CMD_TIME_CLASS_A, status);
1106
1107         if (err)
1108                 goto out;
1109
1110         MTHCA_GET(adapter->vendor_id, outbox,   QUERY_ADAPTER_VENDOR_ID_OFFSET);
1111         MTHCA_GET(adapter->device_id, outbox,   QUERY_ADAPTER_DEVICE_ID_OFFSET);
1112         MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
1113         MTHCA_GET(adapter->inta_pin, outbox,    QUERY_ADAPTER_INTA_PIN_OFFSET);
1114
1115 out:
1116         mthca_free_mailbox(dev, mailbox);
1117         return err;
1118 }
1119
1120 int mthca_INIT_HCA(struct mthca_dev *dev,
1121                    struct mthca_init_hca_param *param,
1122                    u8 *status)
1123 {
1124         struct mthca_mailbox *mailbox;
1125         u32 *inbox;
1126         int err;
1127
1128 #define INIT_HCA_IN_SIZE                 0x200
1129 #define INIT_HCA_FLAGS_OFFSET            0x014
1130 #define INIT_HCA_QPC_OFFSET              0x020
1131 #define  INIT_HCA_QPC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x10)
1132 #define  INIT_HCA_LOG_QP_OFFSET          (INIT_HCA_QPC_OFFSET + 0x17)
1133 #define  INIT_HCA_EEC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x20)
1134 #define  INIT_HCA_LOG_EEC_OFFSET         (INIT_HCA_QPC_OFFSET + 0x27)
1135 #define  INIT_HCA_SRQC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x28)
1136 #define  INIT_HCA_LOG_SRQ_OFFSET         (INIT_HCA_QPC_OFFSET + 0x2f)
1137 #define  INIT_HCA_CQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x30)
1138 #define  INIT_HCA_LOG_CQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x37)
1139 #define  INIT_HCA_EQPC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x40)
1140 #define  INIT_HCA_EEEC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x50)
1141 #define  INIT_HCA_EQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x60)
1142 #define  INIT_HCA_LOG_EQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x67)
1143 #define  INIT_HCA_RDB_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x70)
1144 #define INIT_HCA_UDAV_OFFSET             0x0b0
1145 #define  INIT_HCA_UDAV_LKEY_OFFSET       (INIT_HCA_UDAV_OFFSET + 0x0)
1146 #define  INIT_HCA_UDAV_PD_OFFSET         (INIT_HCA_UDAV_OFFSET + 0x4)
1147 #define INIT_HCA_MCAST_OFFSET            0x0c0
1148 #define  INIT_HCA_MC_BASE_OFFSET         (INIT_HCA_MCAST_OFFSET + 0x00)
1149 #define  INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1150 #define  INIT_HCA_MC_HASH_SZ_OFFSET      (INIT_HCA_MCAST_OFFSET + 0x16)
1151 #define  INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1152 #define INIT_HCA_TPT_OFFSET              0x0f0
1153 #define  INIT_HCA_MPT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x00)
1154 #define  INIT_HCA_MTT_SEG_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x09)
1155 #define  INIT_HCA_LOG_MPT_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x0b)
1156 #define  INIT_HCA_MTT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x10)
1157 #define INIT_HCA_UAR_OFFSET              0x120
1158 #define  INIT_HCA_UAR_BASE_OFFSET        (INIT_HCA_UAR_OFFSET + 0x00)
1159 #define  INIT_HCA_UARC_SZ_OFFSET         (INIT_HCA_UAR_OFFSET + 0x09)
1160 #define  INIT_HCA_LOG_UAR_SZ_OFFSET      (INIT_HCA_UAR_OFFSET + 0x0a)
1161 #define  INIT_HCA_UAR_PAGE_SZ_OFFSET     (INIT_HCA_UAR_OFFSET + 0x0b)
1162 #define  INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1163 #define  INIT_HCA_UAR_CTX_BASE_OFFSET    (INIT_HCA_UAR_OFFSET + 0x18)
1164
1165         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1166         if (IS_ERR(mailbox))
1167                 return PTR_ERR(mailbox);
1168         inbox = mailbox->buf;
1169
1170         memset(inbox, 0, INIT_HCA_IN_SIZE);
1171
1172 #if defined(__LITTLE_ENDIAN)
1173         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1174 #elif defined(__BIG_ENDIAN)
1175         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1176 #else
1177 #error Host endianness not defined
1178 #endif
1179         /* Check port for UD address vector: */
1180         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1181
1182         /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1183
1184         /* QPC/EEC/CQC/EQC/RDB attributes */
1185
1186         MTHCA_PUT(inbox, param->qpc_base,     INIT_HCA_QPC_BASE_OFFSET);
1187         MTHCA_PUT(inbox, param->log_num_qps,  INIT_HCA_LOG_QP_OFFSET);
1188         MTHCA_PUT(inbox, param->eec_base,     INIT_HCA_EEC_BASE_OFFSET);
1189         MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1190         MTHCA_PUT(inbox, param->srqc_base,    INIT_HCA_SRQC_BASE_OFFSET);
1191         MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1192         MTHCA_PUT(inbox, param->cqc_base,     INIT_HCA_CQC_BASE_OFFSET);
1193         MTHCA_PUT(inbox, param->log_num_cqs,  INIT_HCA_LOG_CQ_OFFSET);
1194         MTHCA_PUT(inbox, param->eqpc_base,    INIT_HCA_EQPC_BASE_OFFSET);
1195         MTHCA_PUT(inbox, param->eeec_base,    INIT_HCA_EEEC_BASE_OFFSET);
1196         MTHCA_PUT(inbox, param->eqc_base,     INIT_HCA_EQC_BASE_OFFSET);
1197         MTHCA_PUT(inbox, param->log_num_eqs,  INIT_HCA_LOG_EQ_OFFSET);
1198         MTHCA_PUT(inbox, param->rdb_base,     INIT_HCA_RDB_BASE_OFFSET);
1199
1200         /* UD AV attributes */
1201
1202         /* multicast attributes */
1203
1204         MTHCA_PUT(inbox, param->mc_base,         INIT_HCA_MC_BASE_OFFSET);
1205         MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1206         MTHCA_PUT(inbox, param->mc_hash_sz,      INIT_HCA_MC_HASH_SZ_OFFSET);
1207         MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1208
1209         /* TPT attributes */
1210
1211         MTHCA_PUT(inbox, param->mpt_base,   INIT_HCA_MPT_BASE_OFFSET);
1212         if (!mthca_is_memfree(dev))
1213                 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1214         MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1215         MTHCA_PUT(inbox, param->mtt_base,   INIT_HCA_MTT_BASE_OFFSET);
1216
1217         /* UAR attributes */
1218         {
1219                 u8 uar_page_sz = PAGE_SHIFT - 12;
1220                 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1221         }
1222
1223         MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1224
1225         if (mthca_is_memfree(dev)) {
1226                 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1227                 MTHCA_PUT(inbox, param->log_uar_sz,  INIT_HCA_LOG_UAR_SZ_OFFSET);
1228                 MTHCA_PUT(inbox, param->uarc_base,   INIT_HCA_UAR_CTX_BASE_OFFSET);
1229         }
1230
1231         err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status);
1232
1233         mthca_free_mailbox(dev, mailbox);
1234         return err;
1235 }
1236
1237 int mthca_INIT_IB(struct mthca_dev *dev,
1238                   struct mthca_init_ib_param *param,
1239                   int port, u8 *status)
1240 {
1241         struct mthca_mailbox *mailbox;
1242         u32 *inbox;
1243         int err;
1244         u32 flags;
1245
1246 #define INIT_IB_IN_SIZE          56
1247 #define INIT_IB_FLAGS_OFFSET     0x00
1248 #define INIT_IB_FLAG_SIG         (1 << 18)
1249 #define INIT_IB_FLAG_NG          (1 << 17)
1250 #define INIT_IB_FLAG_G0          (1 << 16)
1251 #define INIT_IB_FLAG_1X          (1 << 8)
1252 #define INIT_IB_FLAG_4X          (1 << 9)
1253 #define INIT_IB_FLAG_12X         (1 << 11)
1254 #define INIT_IB_VL_SHIFT         4
1255 #define INIT_IB_MTU_SHIFT        12
1256 #define INIT_IB_MAX_GID_OFFSET   0x06
1257 #define INIT_IB_MAX_PKEY_OFFSET  0x0a
1258 #define INIT_IB_GUID0_OFFSET     0x10
1259 #define INIT_IB_NODE_GUID_OFFSET 0x18
1260 #define INIT_IB_SI_GUID_OFFSET   0x20
1261
1262         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1263         if (IS_ERR(mailbox))
1264                 return PTR_ERR(mailbox);
1265         inbox = mailbox->buf;
1266
1267         memset(inbox, 0, INIT_IB_IN_SIZE);
1268
1269         flags = 0;
1270         flags |= param->enable_1x     ? INIT_IB_FLAG_1X  : 0;
1271         flags |= param->enable_4x     ? INIT_IB_FLAG_4X  : 0;
1272         flags |= param->set_guid0     ? INIT_IB_FLAG_G0  : 0;
1273         flags |= param->set_node_guid ? INIT_IB_FLAG_NG  : 0;
1274         flags |= param->set_si_guid   ? INIT_IB_FLAG_SIG : 0;
1275         flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1276         flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1277         MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1278
1279         MTHCA_PUT(inbox, param->gid_cap,   INIT_IB_MAX_GID_OFFSET);
1280         MTHCA_PUT(inbox, param->pkey_cap,  INIT_IB_MAX_PKEY_OFFSET);
1281         MTHCA_PUT(inbox, param->guid0,     INIT_IB_GUID0_OFFSET);
1282         MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1283         MTHCA_PUT(inbox, param->si_guid,   INIT_IB_SI_GUID_OFFSET);
1284
1285         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1286                         CMD_TIME_CLASS_A, status);
1287
1288         mthca_free_mailbox(dev, mailbox);
1289         return err;
1290 }
1291
1292 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1293 {
1294         return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
1295 }
1296
1297 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1298 {
1299         return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
1300 }
1301
1302 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1303                  int port, u8 *status)
1304 {
1305         struct mthca_mailbox *mailbox;
1306         u32 *inbox;
1307         int err;
1308         u32 flags = 0;
1309
1310 #define SET_IB_IN_SIZE         0x40
1311 #define SET_IB_FLAGS_OFFSET    0x00
1312 #define SET_IB_FLAG_SIG        (1 << 18)
1313 #define SET_IB_FLAG_RQK        (1 <<  0)
1314 #define SET_IB_CAP_MASK_OFFSET 0x04
1315 #define SET_IB_SI_GUID_OFFSET  0x08
1316
1317         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1318         if (IS_ERR(mailbox))
1319                 return PTR_ERR(mailbox);
1320         inbox = mailbox->buf;
1321
1322         memset(inbox, 0, SET_IB_IN_SIZE);
1323
1324         flags |= param->set_si_guid     ? SET_IB_FLAG_SIG : 0;
1325         flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1326         MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1327
1328         MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1329         MTHCA_PUT(inbox, param->si_guid,  SET_IB_SI_GUID_OFFSET);
1330
1331         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1332                         CMD_TIME_CLASS_B, status);
1333
1334         mthca_free_mailbox(dev, mailbox);
1335         return err;
1336 }
1337
1338 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1339 {
1340         return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1341 }
1342
1343 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1344 {
1345         struct mthca_mailbox *mailbox;
1346         u64 *inbox;
1347         int err;
1348
1349         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1350         if (IS_ERR(mailbox))
1351                 return PTR_ERR(mailbox);
1352         inbox = mailbox->buf;
1353
1354         inbox[0] = cpu_to_be64(virt);
1355         inbox[1] = cpu_to_be64(dma_addr);
1356
1357         err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1358                         CMD_TIME_CLASS_B, status);
1359
1360         mthca_free_mailbox(dev, mailbox);
1361
1362         if (!err)
1363                 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1364                           (unsigned long long) dma_addr, (unsigned long long) virt);
1365
1366         return err;
1367 }
1368
1369 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1370 {
1371         mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1372                   page_count, (unsigned long long) virt);
1373
1374         return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1375 }
1376
1377 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1378 {
1379         return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1380 }
1381
1382 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1383 {
1384         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1385 }
1386
1387 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1388                        u8 *status)
1389 {
1390         int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1391                                 CMD_TIME_CLASS_A, status);
1392
1393         if (ret || status)
1394                 return ret;
1395
1396         /*
1397          * Arbel page size is always 4 KB; round up number of system
1398          * pages needed.
1399          */
1400         *aux_pages = (*aux_pages + (1 << (PAGE_SHIFT - 12)) - 1) >> (PAGE_SHIFT - 12);
1401
1402         return 0;
1403 }
1404
1405 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1406                     int mpt_index, u8 *status)
1407 {
1408         return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1409                          CMD_TIME_CLASS_B, status);
1410 }
1411
1412 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1413                     int mpt_index, u8 *status)
1414 {
1415         return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1416                              !mailbox, CMD_HW2SW_MPT,
1417                              CMD_TIME_CLASS_B, status);
1418 }
1419
1420 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1421                     int num_mtt, u8 *status)
1422 {
1423         return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1424                          CMD_TIME_CLASS_B, status);
1425 }
1426
1427 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1428 {
1429         return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1430 }
1431
1432 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1433                  int eq_num, u8 *status)
1434 {
1435         mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1436                   unmap ? "Clearing" : "Setting",
1437                   (unsigned long long) event_mask, eq_num);
1438         return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1439                          0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1440 }
1441
1442 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1443                    int eq_num, u8 *status)
1444 {
1445         return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1446                          CMD_TIME_CLASS_A, status);
1447 }
1448
1449 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1450                    int eq_num, u8 *status)
1451 {
1452         return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1453                              CMD_HW2SW_EQ,
1454                              CMD_TIME_CLASS_A, status);
1455 }
1456
1457 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1458                    int cq_num, u8 *status)
1459 {
1460         return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1461                         CMD_TIME_CLASS_A, status);
1462 }
1463
1464 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1465                    int cq_num, u8 *status)
1466 {
1467         return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1468                              CMD_HW2SW_CQ,
1469                              CMD_TIME_CLASS_A, status);
1470 }
1471
1472 int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
1473                     int is_ee, struct mthca_mailbox *mailbox, u32 optmask,
1474                     u8 *status)
1475 {
1476         static const u16 op[] = {
1477                 [MTHCA_TRANS_RST2INIT]  = CMD_RST2INIT_QPEE,
1478                 [MTHCA_TRANS_INIT2INIT] = CMD_INIT2INIT_QPEE,
1479                 [MTHCA_TRANS_INIT2RTR]  = CMD_INIT2RTR_QPEE,
1480                 [MTHCA_TRANS_RTR2RTS]   = CMD_RTR2RTS_QPEE,
1481                 [MTHCA_TRANS_RTS2RTS]   = CMD_RTS2RTS_QPEE,
1482                 [MTHCA_TRANS_SQERR2RTS] = CMD_SQERR2RTS_QPEE,
1483                 [MTHCA_TRANS_ANY2ERR]   = CMD_2ERR_QPEE,
1484                 [MTHCA_TRANS_RTS2SQD]   = CMD_RTS2SQD_QPEE,
1485                 [MTHCA_TRANS_SQD2SQD]   = CMD_SQD2SQD_QPEE,
1486                 [MTHCA_TRANS_SQD2RTS]   = CMD_SQD2RTS_QPEE,
1487                 [MTHCA_TRANS_ANY2RST]   = CMD_ERR2RST_QPEE
1488         };
1489         u8 op_mod = 0;
1490         int my_mailbox = 0;
1491         int err;
1492
1493         if (trans < 0 || trans >= ARRAY_SIZE(op))
1494                 return -EINVAL;
1495
1496         if (trans == MTHCA_TRANS_ANY2RST) {
1497                 op_mod = 3;     /* don't write outbox, any->reset */
1498
1499                 /* For debugging */
1500                 if (!mailbox) {
1501                         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1502                         if (!IS_ERR(mailbox)) {
1503                                 my_mailbox = 1;
1504                                 op_mod     = 2; /* write outbox, any->reset */
1505                         } else
1506                                 mailbox = NULL;
1507                 }
1508         } else {
1509                 if (0) {
1510                         int i;
1511                         mthca_dbg(dev, "Dumping QP context:\n");
1512                         printk("  opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1513                         for (i = 0; i < 0x100 / 4; ++i) {
1514                                 if (i % 8 == 0)
1515                                         printk("  [%02x] ", i * 4);
1516                                 printk(" %08x",
1517                                        be32_to_cpu(((u32 *) mailbox->buf)[i + 2]));
1518                                 if ((i + 1) % 8 == 0)
1519                                         printk("\n");
1520                         }
1521                 }
1522         }
1523
1524         if (trans == MTHCA_TRANS_ANY2RST) {
1525                 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1526                                     (!!is_ee << 24) | num, op_mod,
1527                                     op[trans], CMD_TIME_CLASS_C, status);
1528
1529                 if (0 && mailbox) {
1530                         int i;
1531                         mthca_dbg(dev, "Dumping QP context:\n");
1532                         printk(" %08x\n", be32_to_cpup(mailbox->buf));
1533                         for (i = 0; i < 0x100 / 4; ++i) {
1534                                 if (i % 8 == 0)
1535                                         printk("[%02x] ", i * 4);
1536                                 printk(" %08x",
1537                                        be32_to_cpu(((u32 *) mailbox->buf)[i + 2]));
1538                                 if ((i + 1) % 8 == 0)
1539                                         printk("\n");
1540                         }
1541                 }
1542
1543         } else
1544                 err = mthca_cmd(dev, mailbox->dma, (!!is_ee << 24) | num,
1545                                 op_mod, op[trans], CMD_TIME_CLASS_C, status);
1546
1547         if (my_mailbox)
1548                 mthca_free_mailbox(dev, mailbox);
1549
1550         return err;
1551 }
1552
1553 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1554                    struct mthca_mailbox *mailbox, u8 *status)
1555 {
1556         return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1557                              CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1558 }
1559
1560 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1561                           u8 *status)
1562 {
1563         u8 op_mod;
1564
1565         switch (type) {
1566         case IB_QPT_SMI:
1567                 op_mod = 0;
1568                 break;
1569         case IB_QPT_GSI:
1570                 op_mod = 1;
1571                 break;
1572         case IB_QPT_RAW_IPV6:
1573                 op_mod = 2;
1574                 break;
1575         case IB_QPT_RAW_ETY:
1576                 op_mod = 3;
1577                 break;
1578         default:
1579                 return -EINVAL;
1580         }
1581
1582         return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1583                          CMD_TIME_CLASS_B, status);
1584 }
1585
1586 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1587                   int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1588                   void *in_mad, void *response_mad, u8 *status)
1589 {
1590         struct mthca_mailbox *inmailbox, *outmailbox;
1591         void *inbox;
1592         int err;
1593         u32 in_modifier = port;
1594         u8 op_modifier = 0;
1595
1596 #define MAD_IFC_BOX_SIZE      0x400
1597 #define MAD_IFC_MY_QPN_OFFSET 0x100
1598 #define MAD_IFC_RQPN_OFFSET   0x104
1599 #define MAD_IFC_SL_OFFSET     0x108
1600 #define MAD_IFC_G_PATH_OFFSET 0x109
1601 #define MAD_IFC_RLID_OFFSET   0x10a
1602 #define MAD_IFC_PKEY_OFFSET   0x10e
1603 #define MAD_IFC_GRH_OFFSET    0x140
1604
1605         inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1606         if (IS_ERR(inmailbox))
1607                 return PTR_ERR(inmailbox);
1608         inbox = inmailbox->buf;
1609
1610         outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1611         if (IS_ERR(outmailbox)) {
1612                 mthca_free_mailbox(dev, inmailbox);
1613                 return PTR_ERR(outmailbox);
1614         }
1615
1616         memcpy(inbox, in_mad, 256);
1617
1618         /*
1619          * Key check traps can't be generated unless we have in_wc to
1620          * tell us where to send the trap.
1621          */
1622         if (ignore_mkey || !in_wc)
1623                 op_modifier |= 0x1;
1624         if (ignore_bkey || !in_wc)
1625                 op_modifier |= 0x2;
1626
1627         if (in_wc) {
1628                 u8 val;
1629
1630                 memset(inbox + 256, 0, 256);
1631
1632                 MTHCA_PUT(inbox, in_wc->qp_num,     MAD_IFC_MY_QPN_OFFSET);
1633                 MTHCA_PUT(inbox, in_wc->src_qp,     MAD_IFC_RQPN_OFFSET);
1634
1635                 val = in_wc->sl << 4;
1636                 MTHCA_PUT(inbox, val,               MAD_IFC_SL_OFFSET);
1637
1638                 val = in_wc->dlid_path_bits |
1639                         (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1640                 MTHCA_PUT(inbox, val,               MAD_IFC_GRH_OFFSET);
1641
1642                 MTHCA_PUT(inbox, in_wc->slid,       MAD_IFC_RLID_OFFSET);
1643                 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1644
1645                 if (in_grh)
1646                         memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1647
1648                 op_modifier |= 0x10;
1649
1650                 in_modifier |= in_wc->slid << 16;
1651         }
1652
1653         err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1654                             in_modifier, op_modifier,
1655                             CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1656
1657         if (!err && !*status)
1658                 memcpy(response_mad, outmailbox->buf, 256);
1659
1660         mthca_free_mailbox(dev, inmailbox);
1661         mthca_free_mailbox(dev, outmailbox);
1662         return err;
1663 }
1664
1665 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1666                    struct mthca_mailbox *mailbox, u8 *status)
1667 {
1668         return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1669                              CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1670 }
1671
1672 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1673                     struct mthca_mailbox *mailbox, u8 *status)
1674 {
1675         return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1676                          CMD_TIME_CLASS_A, status);
1677 }
1678
1679 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1680                     u16 *hash, u8 *status)
1681 {
1682         u64 imm;
1683         int err;
1684
1685         err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1686                             CMD_TIME_CLASS_A, status);
1687
1688         *hash = imm;
1689         return err;
1690 }
1691
1692 int mthca_NOP(struct mthca_dev *dev, u8 *status)
1693 {
1694         return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
1695 }