SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/log2.h>
  34
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_pack.h>
  37
  38 #include <linux/mlx4/qp.h>
  39
  40 #include "mlx4_ib.h"
  41 #include "user.h"
  42
  43 enum {
  44         MLX4_IB_ACK_REQ_FREQ    = 8,
  45 };
  46
  47 enum {
  48         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  49         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
  50 };
  51
  52 enum {
  53         /*
  54          * Largest possible UD header: send with GRH and immediate data.
  55          */
  56         MLX4_IB_UD_HEADER_SIZE          = 72
  57 };
  58
  59 struct mlx4_ib_sqp {
  60         struct mlx4_ib_qp       qp;
  61         int                     pkey_index;
  62         u32                     qkey;
  63         u32                     send_psn;
  64         struct ib_ud_header     ud_header;
  65         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  66 };
  67
  68 enum {
  69         MLX4_IB_MIN_SQ_STRIDE = 6
  70 };
  71
  72 static const __be32 mlx4_ib_opcode[] = {
  73         [IB_WR_SEND]                    = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
  74         [IB_WR_SEND_WITH_IMM]           = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  75         [IB_WR_RDMA_WRITE]              = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  76         [IB_WR_RDMA_WRITE_WITH_IMM]     = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  77         [IB_WR_RDMA_READ]               = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  78         [IB_WR_ATOMIC_CMP_AND_SWP]      = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  79         [IB_WR_ATOMIC_FETCH_AND_ADD]    = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  80 };
  81
  82 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
  83 {
  84         return container_of(mqp, struct mlx4_ib_sqp, qp);
  85 }
  86
  87 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  88 {
  89         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  90                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
  91 }
  92
  93 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  94 {
  95         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  96                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
  97 }
  98
  99 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 100 {
 101         return mlx4_buf_offset(&qp->buf, offset);
 102 }
 103
 104 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 105 {
 106         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 107 }
 108
 109 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 110 {
 111         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 112 }
 113
 114 /*
 115  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 116  * first four bytes of every 64 byte chunk with
 117  *     0x7FFFFFF | (invalid_ownership_value << 31).
 118  *
 119  * When the max work request size is less than or equal to the WQE
 120  * basic block size, as an optimization, we can stamp all WQEs with
 121  * 0xffffffff, and skip the very first chunk of each WQE.
 122  */
 123 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 124 {
 125         __be32 *wqe;
 126         int i;
 127         int s;
 128         int ind;
 129         void *buf;
 130         __be32 stamp;
 131
 132         s = roundup(size, 1U << qp->sq.wqe_shift);
 133         if (qp->sq_max_wqes_per_wr > 1) {
 134                 for (i = 0; i < s; i += 64) {
 135                         ind = (i >> qp->sq.wqe_shift) + n;
 136                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 137                                                        cpu_to_be32(0xffffffff);
 138                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 139                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 140                         *wqe = stamp;
 141                 }
 142         } else {
 143                 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 144                 for (i = 64; i < s; i += 64) {
 145                         wqe = buf + i;
 146                         *wqe = cpu_to_be32(0xffffffff);
 147                 }
 148         }
 149 }
 150
 151 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 152 {
 153         struct mlx4_wqe_ctrl_seg *ctrl;
 154         struct mlx4_wqe_inline_seg *inl;
 155         void *wqe;
 156         int s;
 157
 158         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 159         s = sizeof(struct mlx4_wqe_ctrl_seg);
 160
 161         if (qp->ibqp.qp_type == IB_QPT_UD) {
 162                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 163                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 164                 memset(dgram, 0, sizeof *dgram);
 165                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 166                 s += sizeof(struct mlx4_wqe_datagram_seg);
 167         }
 168
 169         /* Pad the remainder of the WQE with an inline data segment. */
 170         if (size > s) {
 171                 inl = wqe + s;
 172                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 173         }
 174         ctrl->srcrb_flags = 0;
 175         ctrl->fence_size = size / 16;
 176         /*
 177          * Make sure descriptor is fully written before setting ownership bit
 178          * (because HW can start executing as soon as we do).
 179          */
 180         wmb();
 181
 182         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 183                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 184
 185         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 186 }
 187
 188 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 189 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 190 {
 191         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 192         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 193                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 194                 ind += s;
 195         }
 196         return ind;
 197 }
 198
 199 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 200 {
 201         struct ib_event event;
 202         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 203
 204         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 205                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 206
 207         if (ibqp->event_handler) {
 208                 event.device     = ibqp->device;
 209                 event.element.qp = ibqp;
 210                 switch (type) {
 211                 case MLX4_EVENT_TYPE_PATH_MIG:
 212                         event.event = IB_EVENT_PATH_MIG;
 213                         break;
 214                 case MLX4_EVENT_TYPE_COMM_EST:
 215                         event.event = IB_EVENT_COMM_EST;
 216                         break;
 217                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 218                         event.event = IB_EVENT_SQ_DRAINED;
 219                         break;
 220                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 221                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 222                         break;
 223                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 224                         event.event = IB_EVENT_QP_FATAL;
 225                         break;
 226                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 227                         event.event = IB_EVENT_PATH_MIG_ERR;
 228                         break;
 229                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 230                         event.event = IB_EVENT_QP_REQ_ERR;
 231                         break;
 232                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 233                         event.event = IB_EVENT_QP_ACCESS_ERR;
 234                         break;
 235                 default:
 236                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
 237                                "on QP %06x\n", type, qp->qpn);
 238                         return;
 239                 }
 240
 241                 ibqp->event_handler(&event, ibqp->qp_context);
 242         }
 243 }
 244
 245 static int send_wqe_overhead(enum ib_qp_type type)
 246 {
 247         /*
 248          * UD WQEs must have a datagram segment.
 249          * RC and UC WQEs might have a remote address segment.
 250          * MLX WQEs need two extra inline data segments (for the UD
 251          * header and space for the ICRC).
 252          */
 253         switch (type) {
 254         case IB_QPT_UD:
 255                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 256                         sizeof (struct mlx4_wqe_datagram_seg);
 257         case IB_QPT_UC:
 258                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 259                         sizeof (struct mlx4_wqe_raddr_seg);
 260         case IB_QPT_RC:
 261                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 262                         sizeof (struct mlx4_wqe_atomic_seg) +
 263                         sizeof (struct mlx4_wqe_raddr_seg);
 264         case IB_QPT_SMI:
 265         case IB_QPT_GSI:
 266                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 267                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 268                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 269                                            MLX4_INLINE_ALIGN) *
 270                               sizeof (struct mlx4_wqe_inline_seg),
 271                               sizeof (struct mlx4_wqe_data_seg)) +
 272                         ALIGN(4 +
 273                               sizeof (struct mlx4_wqe_inline_seg),
 274                               sizeof (struct mlx4_wqe_data_seg));
 275         default:
 276                 return sizeof (struct mlx4_wqe_ctrl_seg);
 277         }
 278 }
 279
 280 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 281                        int is_user, int has_srq, struct mlx4_ib_qp *qp)
 282 {
 283         /* Sanity check RQ size before proceeding */
 284         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
 285             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
 286                 return -EINVAL;
 287
 288         if (has_srq) {
 289                 /* QPs attached to an SRQ should have no RQ */
 290                 if (cap->max_recv_wr)
 291                         return -EINVAL;
 292
 293                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 294         } else {
 295                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 296                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 297                         return -EINVAL;
 298
 299                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 300                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 301                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 302         }
 303
 304         cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 305         cap->max_recv_sge = qp->rq.max_gs;
 306
 307         return 0;
 308 }
 309
 310 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 311                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
 312 {
 313         int s;
 314
 315         /* Sanity check SQ size before proceeding */
 316         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
 317             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
 318             cap->max_inline_data + send_wqe_overhead(type) +
 319             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 320                 return -EINVAL;
 321
 322         /*
 323          * For MLX transport we need 2 extra S/G entries:
 324          * one for the header and one for the checksum at the end
 325          */
 326         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
 327             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 328                 return -EINVAL;
 329
 330         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 331                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 332                 send_wqe_overhead(type);
 333
 334         /*
 335          * Hermon supports shrinking WQEs, such that a single work
 336          * request can include multiple units of 1 << wqe_shift.  This
 337          * way, work requests can differ in size, and do not have to
 338          * be a power of 2 in size, saving memory and speeding up send
 339          * WR posting.  Unfortunately, if we do this then the
 340          * wqe_index field in CQEs can't be used to look up the WR ID
 341          * anymore, so we do this only if selective signaling is off.
 342          *
 343          * Further, on 32-bit platforms, we can't use vmap() to make
 344          * the QP buffer virtually contigious.  Thus we have to use
 345          * constant-sized WRs to make sure a WR is always fully within
 346          * a single page-sized chunk.
 347          *
 348          * Finally, we use NOP work requests to pad the end of the
 349          * work queue, to avoid wrap-around in the middle of WR.  We
 350          * set NEC bit to avoid getting completions with error for
 351          * these NOP WRs, but since NEC is only supported starting
 352          * with firmware 2.2.232, we use constant-sized WRs for older
 353          * firmware.
 354          *
 355          * And, since MLX QPs only support SEND, we use constant-sized
 356          * WRs in this case.
 357          *
 358          * We look for the smallest value of wqe_shift such that the
 359          * resulting number of wqes does not exceed device
 360          * capabilities.
 361          *
 362          * We set WQE size to at least 64 bytes, this way stamping
 363          * invalidates each WQE.
 364          */
 365         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 366             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 367             type != IB_QPT_SMI && type != IB_QPT_GSI)
 368                 qp->sq.wqe_shift = ilog2(64);
 369         else
 370                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 371
 372         for (;;) {
 373                 if (1 << qp->sq.wqe_shift > dev->dev->caps.max_sq_desc_sz)
 374                         return -EINVAL;
 375
 376                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 377
 378                 /*
 379                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 380                  * allow HW to prefetch.
 381                  */
 382                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 383                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 384                                                     qp->sq_max_wqes_per_wr +
 385                                                     qp->sq_spare_wqes);
 386
 387                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 388                         break;
 389
 390                 if (qp->sq_max_wqes_per_wr <= 1)
 391                         return -EINVAL;
 392
 393                 ++qp->sq.wqe_shift;
 394         }
 395
 396         qp->sq.max_gs = ((qp->sq_max_wqes_per_wr << qp->sq.wqe_shift) -
 397                          send_wqe_overhead(type)) / sizeof (struct mlx4_wqe_data_seg);
 398
 399         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 400                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 401         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 402                 qp->rq.offset = 0;
 403                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 404         } else {
 405                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 406                 qp->sq.offset = 0;
 407         }
 408
 409         cap->max_send_wr  = qp->sq.max_post =
 410                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 411         cap->max_send_sge = qp->sq.max_gs;
 412         /* We don't support inline sends for kernel QPs (yet) */
 413         cap->max_inline_data = 0;
 414
 415         return 0;
 416 }
 417
 418 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 419                             struct mlx4_ib_qp *qp,
 420                             struct mlx4_ib_create_qp *ucmd)
 421 {
 422         /* Sanity check SQ size before proceeding */
 423         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 424             ucmd->log_sq_stride >
 425                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 426             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 427                 return -EINVAL;
 428
 429         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 430         qp->sq.wqe_shift = ucmd->log_sq_stride;
 431
 432         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 433                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 434
 435         return 0;
 436 }
 437
 438 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 439                             struct ib_qp_init_attr *init_attr,
 440                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
 441 {
 442         int err;
 443
 444         mutex_init(&qp->mutex);
 445         spin_lock_init(&qp->sq.lock);
 446         spin_lock_init(&qp->rq.lock);
 447
 448         qp->state        = IB_QPS_RESET;
 449         qp->atomic_rd_en = 0;
 450         qp->resp_depth   = 0;
 451
 452         qp->rq.head         = 0;
 453         qp->rq.tail         = 0;
 454         qp->sq.head         = 0;
 455         qp->sq.tail         = 0;
 456         qp->sq_next_wqe     = 0;
 457
 458         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 459                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 460         else
 461                 qp->sq_signal_bits = 0;
 462
 463         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
 464         if (err)
 465                 goto err;
 466
 467         if (pd->uobject) {
 468                 struct mlx4_ib_create_qp ucmd;
 469
 470                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 471                         err = -EFAULT;
 472                         goto err;
 473                 }
 474
 475                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 476
 477                 err = set_user_sq_size(dev, qp, &ucmd);
 478                 if (err)
 479                         goto err;
 480
 481                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 482                                        qp->buf_size, 0);
 483                 if (IS_ERR(qp->umem)) {
 484                         err = PTR_ERR(qp->umem);
 485                         goto err;
 486                 }
 487
 488                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 489                                     ilog2(qp->umem->page_size), &qp->mtt);
 490                 if (err)
 491                         goto err_buf;
 492
 493                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 494                 if (err)
 495                         goto err_mtt;
 496
 497                 if (!init_attr->srq) {
 498                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 499                                                   ucmd.db_addr, &qp->db);
 500                         if (err)
 501                                 goto err_mtt;
 502                 }
 503         } else {
 504                 qp->sq_no_prefetch = 0;
 505
 506                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
 507                 if (err)
 508                         goto err;
 509
 510                 if (!init_attr->srq) {
 511                         err = mlx4_ib_db_alloc(dev, &qp->db, 0);
 512                         if (err)
 513                                 goto err;
 514
 515                         *qp->db.db = 0;
 516                 }
 517
 518                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 519                         err = -ENOMEM;
 520                         goto err_db;
 521                 }
 522
 523                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 524                                     &qp->mtt);
 525                 if (err)
 526                         goto err_buf;
 527
 528                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 529                 if (err)
 530                         goto err_mtt;
 531
 532                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 533                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 534
 535                 if (!qp->sq.wrid || !qp->rq.wrid) {
 536                         err = -ENOMEM;
 537                         goto err_wrid;
 538                 }
 539         }
 540
 541         err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
 542         if (err)
 543                 goto err_wrid;
 544
 545         /*
 546          * Hardware wants QPN written in big-endian order (after
 547          * shifting) for send doorbell.  Precompute this value to save
 548          * a little bit when posting sends.
 549          */
 550         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 551
 552         qp->mqp.event = mlx4_ib_qp_event;
 553
 554         return 0;
 555
 556 err_wrid:
 557         if (pd->uobject) {
 558                 if (!init_attr->srq)
 559                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
 560                                               &qp->db);
 561         } else {
 562                 kfree(qp->sq.wrid);
 563                 kfree(qp->rq.wrid);
 564         }
 565
 566 err_mtt:
 567         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 568
 569 err_buf:
 570         if (pd->uobject)
 571                 ib_umem_release(qp->umem);
 572         else
 573                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 574
 575 err_db:
 576         if (!pd->uobject && !init_attr->srq)
 577                 mlx4_ib_db_free(dev, &qp->db);
 578
 579 err:
 580         return err;
 581 }
 582
 583 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 584 {
 585         switch (state) {
 586         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 587         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 588         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 589         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 590         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 591         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 592         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 593         default:                return -1;
 594         }
 595 }
 596
 597 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 598 {
 599         if (send_cq == recv_cq)
 600                 spin_lock_irq(&send_cq->lock);
 601         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 602                 spin_lock_irq(&send_cq->lock);
 603                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 604         } else {
 605                 spin_lock_irq(&recv_cq->lock);
 606                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 607         }
 608 }
 609
 610 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 611 {
 612         if (send_cq == recv_cq)
 613                 spin_unlock_irq(&send_cq->lock);
 614         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 615                 spin_unlock(&recv_cq->lock);
 616                 spin_unlock_irq(&send_cq->lock);
 617         } else {
 618                 spin_unlock(&send_cq->lock);
 619                 spin_unlock_irq(&recv_cq->lock);
 620         }
 621 }
 622
 623 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 624                               int is_user)
 625 {
 626         struct mlx4_ib_cq *send_cq, *recv_cq;
 627
 628         if (qp->state != IB_QPS_RESET)
 629                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 630                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 631                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
 632                                qp->mqp.qpn);
 633
 634         send_cq = to_mcq(qp->ibqp.send_cq);
 635         recv_cq = to_mcq(qp->ibqp.recv_cq);
 636
 637         mlx4_ib_lock_cqs(send_cq, recv_cq);
 638
 639         if (!is_user) {
 640                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 641                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 642                 if (send_cq != recv_cq)
 643                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 644         }
 645
 646         mlx4_qp_remove(dev->dev, &qp->mqp);
 647
 648         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 649
 650         mlx4_qp_free(dev->dev, &qp->mqp);
 651         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 652
 653         if (is_user) {
 654                 if (!qp->ibqp.srq)
 655                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 656                                               &qp->db);
 657                 ib_umem_release(qp->umem);
 658         } else {
 659                 kfree(qp->sq.wrid);
 660                 kfree(qp->rq.wrid);
 661                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 662                 if (!qp->ibqp.srq)
 663                         mlx4_ib_db_free(dev, &qp->db);
 664         }
 665 }
 666
 667 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 668                                 struct ib_qp_init_attr *init_attr,
 669                                 struct ib_udata *udata)
 670 {
 671         struct mlx4_ib_dev *dev = to_mdev(pd->device);
 672         struct mlx4_ib_sqp *sqp;
 673         struct mlx4_ib_qp *qp;
 674         int err;
 675
 676         if (init_attr->create_flags)
 677                 return ERR_PTR(-EINVAL);
 678
 679         switch (init_attr->qp_type) {
 680         case IB_QPT_RC:
 681         case IB_QPT_UC:
 682         case IB_QPT_UD:
 683         {
 684                 qp = kmalloc(sizeof *qp, GFP_KERNEL);
 685                 if (!qp)
 686                         return ERR_PTR(-ENOMEM);
 687
 688                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
 689                 if (err) {
 690                         kfree(qp);
 691                         return ERR_PTR(err);
 692                 }
 693
 694                 qp->ibqp.qp_num = qp->mqp.qpn;
 695
 696                 break;
 697         }
 698         case IB_QPT_SMI:
 699         case IB_QPT_GSI:
 700         {
 701                 /* Userspace is not allowed to create special QPs: */
 702                 if (pd->uobject)
 703                         return ERR_PTR(-EINVAL);
 704
 705                 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
 706                 if (!sqp)
 707                         return ERR_PTR(-ENOMEM);
 708
 709                 qp = &sqp->qp;
 710
 711                 err = create_qp_common(dev, pd, init_attr, udata,
 712                                        dev->dev->caps.sqp_start +
 713                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 714                                        init_attr->port_num - 1,
 715                                        qp);
 716                 if (err) {
 717                         kfree(sqp);
 718                         return ERR_PTR(err);
 719                 }
 720
 721                 qp->port        = init_attr->port_num;
 722                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
 723
 724                 break;
 725         }
 726         default:
 727                 /* Don't support raw QPs */
 728                 return ERR_PTR(-EINVAL);
 729         }
 730
 731         return &qp->ibqp;
 732 }
 733
 734 int mlx4_ib_destroy_qp(struct ib_qp *qp)
 735 {
 736         struct mlx4_ib_dev *dev = to_mdev(qp->device);
 737         struct mlx4_ib_qp *mqp = to_mqp(qp);
 738
 739         if (is_qp0(dev, mqp))
 740                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
 741
 742         destroy_qp_common(dev, mqp, !!qp->pd->uobject);
 743
 744         if (is_sqp(dev, mqp))
 745                 kfree(to_msqp(mqp));
 746         else
 747                 kfree(mqp);
 748
 749         return 0;
 750 }
 751
 752 static int to_mlx4_st(enum ib_qp_type type)
 753 {
 754         switch (type) {
 755         case IB_QPT_RC:         return MLX4_QP_ST_RC;
 756         case IB_QPT_UC:         return MLX4_QP_ST_UC;
 757         case IB_QPT_UD:         return MLX4_QP_ST_UD;
 758         case IB_QPT_SMI:
 759         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
 760         default:                return -1;
 761         }
 762 }
 763
 764 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
 765                                    int attr_mask)
 766 {
 767         u8 dest_rd_atomic;
 768         u32 access_flags;
 769         u32 hw_access_flags = 0;
 770
 771         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 772                 dest_rd_atomic = attr->max_dest_rd_atomic;
 773         else
 774                 dest_rd_atomic = qp->resp_depth;
 775
 776         if (attr_mask & IB_QP_ACCESS_FLAGS)
 777                 access_flags = attr->qp_access_flags;
 778         else
 779                 access_flags = qp->atomic_rd_en;
 780
 781         if (!dest_rd_atomic)
 782                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 783
 784         if (access_flags & IB_ACCESS_REMOTE_READ)
 785                 hw_access_flags |= MLX4_QP_BIT_RRE;
 786         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 787                 hw_access_flags |= MLX4_QP_BIT_RAE;
 788         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 789                 hw_access_flags |= MLX4_QP_BIT_RWE;
 790
 791         return cpu_to_be32(hw_access_flags);
 792 }
 793
 794 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
 795                             int attr_mask)
 796 {
 797         if (attr_mask & IB_QP_PKEY_INDEX)
 798                 sqp->pkey_index = attr->pkey_index;
 799         if (attr_mask & IB_QP_QKEY)
 800                 sqp->qkey = attr->qkey;
 801         if (attr_mask & IB_QP_SQ_PSN)
 802                 sqp->send_psn = attr->sq_psn;
 803 }
 804
 805 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
 806 {
 807         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
 808 }
 809
 810 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
 811                          struct mlx4_qp_path *path, u8 port)
 812 {
 813         path->grh_mylmc     = ah->src_path_bits & 0x7f;
 814         path->rlid          = cpu_to_be16(ah->dlid);
 815         if (ah->static_rate) {
 816                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
 817                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
 818                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
 819                         --path->static_rate;
 820         } else
 821                 path->static_rate = 0;
 822         path->counter_index = 0xff;
 823
 824         if (ah->ah_flags & IB_AH_GRH) {
 825                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
 826                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
 827                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
 828                         return -1;
 829                 }
 830
 831                 path->grh_mylmc |= 1 << 7;
 832                 path->mgid_index = ah->grh.sgid_index;
 833                 path->hop_limit  = ah->grh.hop_limit;
 834                 path->tclass_flowlabel =
 835                         cpu_to_be32((ah->grh.traffic_class << 20) |
 836                                     (ah->grh.flow_label));
 837                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 838         }
 839
 840         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 841                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
 842
 843         return 0;
 844 }
 845
 846 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
 847                                const struct ib_qp_attr *attr, int attr_mask,
 848                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
 849 {
 850         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 851         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 852         struct mlx4_qp_context *context;
 853         enum mlx4_qp_optpar optpar = 0;
 854         int sqd_event;
 855         int err = -EINVAL;
 856
 857         context = kzalloc(sizeof *context, GFP_KERNEL);
 858         if (!context)
 859                 return -ENOMEM;
 860
 861         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
 862                                      (to_mlx4_st(ibqp->qp_type) << 16));
 863         context->flags     |= cpu_to_be32(1 << 8); /* DE? */
 864
 865         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 866                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 867         else {
 868                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
 869                 switch (attr->path_mig_state) {
 870                 case IB_MIG_MIGRATED:
 871                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 872                         break;
 873                 case IB_MIG_REARM:
 874                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
 875                         break;
 876                 case IB_MIG_ARMED:
 877                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
 878                         break;
 879                 }
 880         }
 881
 882         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
 883             ibqp->qp_type == IB_QPT_UD)
 884                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 885         else if (attr_mask & IB_QP_PATH_MTU) {
 886                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
 887                         printk(KERN_ERR "path MTU (%u) is invalid\n",
 888                                attr->path_mtu);
 889                         goto out;
 890                 }
 891                 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 892         }
 893
 894         if (qp->rq.wqe_cnt)
 895                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
 896         context->rq_size_stride |= qp->rq.wqe_shift - 4;
 897
 898         if (qp->sq.wqe_cnt)
 899                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
 900         context->sq_size_stride |= qp->sq.wqe_shift - 4;
 901
 902         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
 903                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
 904
 905         if (qp->ibqp.uobject)
 906                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
 907         else
 908                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
 909
 910         if (attr_mask & IB_QP_DEST_QPN)
 911                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 912
 913         if (attr_mask & IB_QP_PORT) {
 914                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
 915                     !(attr_mask & IB_QP_AV)) {
 916                         mlx4_set_sched(&context->pri_path, attr->port_num);
 917                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
 918                 }
 919         }
 920
 921         if (attr_mask & IB_QP_PKEY_INDEX) {
 922                 context->pri_path.pkey_index = attr->pkey_index;
 923                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
 924         }
 925
 926         if (attr_mask & IB_QP_AV) {
 927                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
 928                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 929                         goto out;
 930
 931                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
 932                            MLX4_QP_OPTPAR_SCHED_QUEUE);
 933         }
 934
 935         if (attr_mask & IB_QP_TIMEOUT) {
 936                 context->pri_path.ackto = attr->timeout << 3;
 937                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
 938         }
 939
 940         if (attr_mask & IB_QP_ALT_PATH) {
 941                 if (attr->alt_port_num == 0 ||
 942                     attr->alt_port_num > dev->dev->caps.num_ports)
 943                         goto out;
 944
 945                 if (attr->alt_pkey_index >=
 946                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
 947                         goto out;
 948
 949                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
 950                                   attr->alt_port_num))
 951                         goto out;
 952
 953                 context->alt_path.pkey_index = attr->alt_pkey_index;
 954                 context->alt_path.ackto = attr->alt_timeout << 3;
 955                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
 956         }
 957
 958         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
 959         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
 960
 961         if (attr_mask & IB_QP_RNR_RETRY) {
 962                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
 963                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
 964         }
 965
 966         if (attr_mask & IB_QP_RETRY_CNT) {
 967                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 968                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
 969         }
 970
 971         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 972                 if (attr->max_rd_atomic)
 973                         context->params1 |=
 974                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 975                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
 976         }
 977
 978         if (attr_mask & IB_QP_SQ_PSN)
 979                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
 980
 981         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
 982
 983         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 984                 if (attr->max_dest_rd_atomic)
 985                         context->params2 |=
 986                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 987                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
 988         }
 989
 990         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 991                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
 992                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
 993         }
 994
 995         if (ibqp->srq)
 996                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
 997
 998         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 999                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1000                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1001         }
1002         if (attr_mask & IB_QP_RQ_PSN)
1003                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1004
1005         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
1006
1007         if (attr_mask & IB_QP_QKEY) {
1008                 context->qkey = cpu_to_be32(attr->qkey);
1009                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1010         }
1011
1012         if (ibqp->srq)
1013                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1014
1015         if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1016                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1017
1018         if (cur_state == IB_QPS_INIT &&
1019             new_state == IB_QPS_RTR  &&
1020             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1021              ibqp->qp_type == IB_QPT_UD)) {
1022                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1023                 if (is_qp0(dev, qp))
1024                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1025                 else
1026                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1027         }
1028
1029         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1030             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1031                 sqd_event = 1;
1032         else
1033                 sqd_event = 0;
1034
1035         /*
1036          * Before passing a kernel QP to the HW, make sure that the
1037          * ownership bits of the send queue are set and the SQ
1038          * headroom is stamped so that the hardware doesn't start
1039          * processing stale work requests.
1040          */
1041         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1042                 struct mlx4_wqe_ctrl_seg *ctrl;
1043                 int i;
1044
1045                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1046                         ctrl = get_send_wqe(qp, i);
1047                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1048
1049                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1050                 }
1051         }
1052
1053         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1054                              to_mlx4_state(new_state), context, optpar,
1055                              sqd_event, &qp->mqp);
1056         if (err)
1057                 goto out;
1058
1059         qp->state = new_state;
1060
1061         if (attr_mask & IB_QP_ACCESS_FLAGS)
1062                 qp->atomic_rd_en = attr->qp_access_flags;
1063         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1064                 qp->resp_depth = attr->max_dest_rd_atomic;
1065         if (attr_mask & IB_QP_PORT)
1066                 qp->port = attr->port_num;
1067         if (attr_mask & IB_QP_ALT_PATH)
1068                 qp->alt_port = attr->alt_port_num;
1069
1070         if (is_sqp(dev, qp))
1071                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1072
1073         /*
1074          * If we moved QP0 to RTR, bring the IB link up; if we moved
1075          * QP0 to RESET or ERROR, bring the link back down.
1076          */
1077         if (is_qp0(dev, qp)) {
1078                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1079                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1080                                 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1081                                        qp->port);
1082
1083                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1084                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1085                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1086         }
1087
1088         /*
1089          * If we moved a kernel QP to RESET, clean up all old CQ
1090          * entries and reinitialize the QP.
1091          */
1092         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1093                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
1094                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
1095                 if (ibqp->send_cq != ibqp->recv_cq)
1096                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
1097
1098                 qp->rq.head = 0;
1099                 qp->rq.tail = 0;
1100                 qp->sq.head = 0;
1101                 qp->sq.tail = 0;
1102                 qp->sq_next_wqe = 0;
1103                 if (!ibqp->srq)
1104                         *qp->db.db  = 0;
1105         }
1106
1107 out:
1108         kfree(context);
1109         return err;
1110 }
1111
1112 static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
1113 static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
1114                 [IB_QPT_UD]  = (IB_QP_PKEY_INDEX                |
1115                                 IB_QP_PORT                      |
1116                                 IB_QP_QKEY),
1117                 [IB_QPT_UC]  = (IB_QP_PKEY_INDEX                |
1118                                 IB_QP_PORT                      |
1119                                 IB_QP_ACCESS_FLAGS),
1120                 [IB_QPT_RC]  = (IB_QP_PKEY_INDEX                |
1121                                 IB_QP_PORT                      |
1122                                 IB_QP_ACCESS_FLAGS),
1123                 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX                |
1124                                 IB_QP_QKEY),
1125                 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX                |
1126                                 IB_QP_QKEY),
1127 };
1128
1129 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1130                       int attr_mask, struct ib_udata *udata)
1131 {
1132         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1133         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1134         enum ib_qp_state cur_state, new_state;
1135         int err = -EINVAL;
1136
1137         mutex_lock(&qp->mutex);
1138
1139         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1140         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1141
1142         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1143                 goto out;
1144
1145         if ((attr_mask & IB_QP_PORT) &&
1146             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1147                 goto out;
1148         }
1149
1150         if (attr_mask & IB_QP_PKEY_INDEX) {
1151                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1152                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1153                         goto out;
1154         }
1155
1156         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1157             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1158                 goto out;
1159         }
1160
1161         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1162             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1163                 goto out;
1164         }
1165
1166         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1167                 err = 0;
1168                 goto out;
1169         }
1170
1171         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
1172                 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
1173                                           mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
1174                                           IB_QPS_RESET, IB_QPS_INIT);
1175                 if (err)
1176                         goto out;
1177                 cur_state = IB_QPS_INIT;
1178         }
1179
1180         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1181
1182 out:
1183         mutex_unlock(&qp->mutex);
1184         return err;
1185 }
1186
1187 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1188                             void *wqe)
1189 {
1190         struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1191         struct mlx4_wqe_mlx_seg *mlx = wqe;
1192         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1193         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1194         u16 pkey;
1195         int send_size;
1196         int header_size;
1197         int spc;
1198         int i;
1199
1200         send_size = 0;
1201         for (i = 0; i < wr->num_sge; ++i)
1202                 send_size += wr->sg_list[i].length;
1203
1204         ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1205
1206         sqp->ud_header.lrh.service_level   =
1207                 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1208         sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1209         sqp->ud_header.lrh.source_lid      = cpu_to_be16(ah->av.g_slid & 0x7f);
1210         if (mlx4_ib_ah_grh_present(ah)) {
1211                 sqp->ud_header.grh.traffic_class =
1212                         (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1213                 sqp->ud_header.grh.flow_label    =
1214                         ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1215                 sqp->ud_header.grh.hop_limit     = ah->av.hop_limit;
1216                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1217                                   ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1218                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1219                        ah->av.dgid, 16);
1220         }
1221
1222         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1223         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1224                                   (sqp->ud_header.lrh.destination_lid ==
1225                                    IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1226                                   (sqp->ud_header.lrh.service_level << 8));
1227         mlx->rlid   = sqp->ud_header.lrh.destination_lid;
1228
1229         switch (wr->opcode) {
1230         case IB_WR_SEND:
1231                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1232                 sqp->ud_header.immediate_present = 0;
1233                 break;
1234         case IB_WR_SEND_WITH_IMM:
1235                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1236                 sqp->ud_header.immediate_present = 1;
1237                 sqp->ud_header.immediate_data    = wr->imm_data;
1238                 break;
1239         default:
1240                 return -EINVAL;
1241         }
1242
1243         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1244         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1245                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1246         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1247         if (!sqp->qp.ibqp.qp_num)
1248                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1249         else
1250                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1251         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1252         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1253         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1254         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1255                                                sqp->qkey : wr->wr.ud.remote_qkey);
1256         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1257
1258         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1259
1260         if (0) {
1261                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1262                 for (i = 0; i < header_size / 4; ++i) {
1263                         if (i % 8 == 0)
1264                                 printk("  [%02x] ", i * 4);
1265                         printk(" %08x",
1266                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1267                         if ((i + 1) % 8 == 0)
1268                                 printk("\n");
1269                 }
1270                 printk("\n");
1271         }
1272
1273         /*
1274          * Inline data segments may not cross a 64 byte boundary.  If
1275          * our UD header is bigger than the space available up to the
1276          * next 64 byte boundary in the WQE, use two inline data
1277          * segments to hold the UD header.
1278          */
1279         spc = MLX4_INLINE_ALIGN -
1280                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1281         if (header_size <= spc) {
1282                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1283                 memcpy(inl + 1, sqp->header_buf, header_size);
1284                 i = 1;
1285         } else {
1286                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1287                 memcpy(inl + 1, sqp->header_buf, spc);
1288
1289                 inl = (void *) (inl + 1) + spc;
1290                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1291                 /*
1292                  * Need a barrier here to make sure all the data is
1293                  * visible before the byte_count field is set.
1294                  * Otherwise the HCA prefetcher could grab the 64-byte
1295                  * chunk with this inline segment and get a valid (!=
1296                  * 0xffffffff) byte count but stale data, and end up
1297                  * generating a packet with bad headers.
1298                  *
1299                  * The first inline segment's byte_count field doesn't
1300                  * need a barrier, because it comes after a
1301                  * control/MLX segment and therefore is at an offset
1302                  * of 16 mod 64.
1303                  */
1304                 wmb();
1305                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1306                 i = 2;
1307         }
1308
1309         return ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1310 }
1311
1312 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1313 {
1314         unsigned cur;
1315         struct mlx4_ib_cq *cq;
1316
1317         cur = wq->head - wq->tail;
1318         if (likely(cur + nreq < wq->max_post))
1319                 return 0;
1320
1321         cq = to_mcq(ib_cq);
1322         spin_lock(&cq->lock);
1323         cur = wq->head - wq->tail;
1324         spin_unlock(&cq->lock);
1325
1326         return cur + nreq >= wq->max_post;
1327 }
1328
1329 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1330                                           u64 remote_addr, u32 rkey)
1331 {
1332         rseg->raddr    = cpu_to_be64(remote_addr);
1333         rseg->rkey     = cpu_to_be32(rkey);
1334         rseg->reserved = 0;
1335 }
1336
1337 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1338 {
1339         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1340                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1341                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
1342         } else {
1343                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1344                 aseg->compare  = 0;
1345         }
1346
1347 }
1348
1349 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1350                              struct ib_send_wr *wr)
1351 {
1352         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1353         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1354         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1355 }
1356
1357 static void set_mlx_icrc_seg(void *dseg)
1358 {
1359         u32 *t = dseg;
1360         struct mlx4_wqe_inline_seg *iseg = dseg;
1361
1362         t[1] = 0;
1363
1364         /*
1365          * Need a barrier here before writing the byte_count field to
1366          * make sure that all the data is visible before the
1367          * byte_count field is set.  Otherwise, if the segment begins
1368          * a new cacheline, the HCA prefetcher could grab the 64-byte
1369          * chunk and get a valid (!= * 0xffffffff) byte count but
1370          * stale data, and end up sending the wrong data.
1371          */
1372         wmb();
1373
1374         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1375 }
1376
1377 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1378 {
1379         dseg->lkey       = cpu_to_be32(sg->lkey);
1380         dseg->addr       = cpu_to_be64(sg->addr);
1381
1382         /*
1383          * Need a barrier here before writing the byte_count field to
1384          * make sure that all the data is visible before the
1385          * byte_count field is set.  Otherwise, if the segment begins
1386          * a new cacheline, the HCA prefetcher could grab the 64-byte
1387          * chunk and get a valid (!= * 0xffffffff) byte count but
1388          * stale data, and end up sending the wrong data.
1389          */
1390         wmb();
1391
1392         dseg->byte_count = cpu_to_be32(sg->length);
1393 }
1394
1395 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1396 {
1397         dseg->byte_count = cpu_to_be32(sg->length);
1398         dseg->lkey       = cpu_to_be32(sg->lkey);
1399         dseg->addr       = cpu_to_be64(sg->addr);
1400 }
1401
1402 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1403                       struct ib_send_wr **bad_wr)
1404 {
1405         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1406         void *wqe;
1407         struct mlx4_wqe_ctrl_seg *ctrl;
1408         struct mlx4_wqe_data_seg *dseg;
1409         unsigned long flags;
1410         int nreq;
1411         int err = 0;
1412         unsigned ind;
1413         int uninitialized_var(stamp);
1414         int uninitialized_var(size);
1415         int i;
1416
1417         spin_lock_irqsave(&qp->sq.lock, flags);
1418
1419         ind = qp->sq_next_wqe;
1420
1421         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1422                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1423                         err = -ENOMEM;
1424                         *bad_wr = wr;
1425                         goto out;
1426                 }
1427
1428                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1429                         err = -EINVAL;
1430                         *bad_wr = wr;
1431                         goto out;
1432                 }
1433
1434                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1435                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1436
1437                 ctrl->srcrb_flags =
1438                         (wr->send_flags & IB_SEND_SIGNALED ?
1439                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1440                         (wr->send_flags & IB_SEND_SOLICITED ?
1441                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1442                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
1443                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1444                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
1445                         qp->sq_signal_bits;
1446
1447                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1448                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1449                         ctrl->imm = wr->imm_data;
1450                 else
1451                         ctrl->imm = 0;
1452
1453                 wqe += sizeof *ctrl;
1454                 size = sizeof *ctrl / 16;
1455
1456                 switch (ibqp->qp_type) {
1457                 case IB_QPT_RC:
1458                 case IB_QPT_UC:
1459                         switch (wr->opcode) {
1460                         case IB_WR_ATOMIC_CMP_AND_SWP:
1461                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1462                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1463                                               wr->wr.atomic.rkey);
1464                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1465
1466                                 set_atomic_seg(wqe, wr);
1467                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1468
1469                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1470                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1471
1472                                 break;
1473
1474                         case IB_WR_RDMA_READ:
1475                         case IB_WR_RDMA_WRITE:
1476                         case IB_WR_RDMA_WRITE_WITH_IMM:
1477                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1478                                               wr->wr.rdma.rkey);
1479                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1480                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1481                                 break;
1482
1483                         default:
1484                                 /* No extra segments required for sends */
1485                                 break;
1486                         }
1487                         break;
1488
1489                 case IB_QPT_UD:
1490                         set_datagram_seg(wqe, wr);
1491                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1492                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1493                         break;
1494
1495                 case IB_QPT_SMI:
1496                 case IB_QPT_GSI:
1497                         err = build_mlx_header(to_msqp(qp), wr, ctrl);
1498                         if (err < 0) {
1499                                 *bad_wr = wr;
1500                                 goto out;
1501                         }
1502                         wqe  += err;
1503                         size += err / 16;
1504
1505                         err = 0;
1506                         break;
1507
1508                 default:
1509                         break;
1510                 }
1511
1512                 /*
1513                  * Write data segments in reverse order, so as to
1514                  * overwrite cacheline stamp last within each
1515                  * cacheline.  This avoids issues with WQE
1516                  * prefetching.
1517                  */
1518
1519                 dseg = wqe;
1520                 dseg += wr->num_sge - 1;
1521                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1522
1523                 /* Add one more inline data segment for ICRC for MLX sends */
1524                 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1525                              qp->ibqp.qp_type == IB_QPT_GSI)) {
1526                         set_mlx_icrc_seg(dseg + 1);
1527                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1528                 }
1529
1530                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1531                         set_data_seg(dseg, wr->sg_list + i);
1532
1533                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1534                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1535
1536                 /*
1537                  * Make sure descriptor is fully written before
1538                  * setting ownership bit (because HW can start
1539                  * executing as soon as we do).
1540                  */
1541                 wmb();
1542
1543                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1544                         err = -EINVAL;
1545                         goto out;
1546                 }
1547
1548                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1549                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1550
1551                 stamp = ind + qp->sq_spare_wqes;
1552                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1553
1554                 /*
1555                  * We can improve latency by not stamping the last
1556                  * send queue WQE until after ringing the doorbell, so
1557                  * only stamp here if there are still more WQEs to post.
1558                  *
1559                  * Same optimization applies to padding with NOP wqe
1560                  * in case of WQE shrinking (used to prevent wrap-around
1561                  * in the middle of WR).
1562                  */
1563                 if (wr->next) {
1564                         stamp_send_wqe(qp, stamp, size * 16);
1565                         ind = pad_wraparound(qp, ind);
1566                 }
1567
1568         }
1569
1570 out:
1571         if (likely(nreq)) {
1572                 qp->sq.head += nreq;
1573
1574                 /*
1575                  * Make sure that descriptors are written before
1576                  * doorbell record.
1577                  */
1578                 wmb();
1579
1580                 writel(qp->doorbell_qpn,
1581                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1582
1583                 /*
1584                  * Make sure doorbells don't leak out of SQ spinlock
1585                  * and reach the HCA out of order.
1586                  */
1587                 mmiowb();
1588
1589                 stamp_send_wqe(qp, stamp, size * 16);
1590
1591                 ind = pad_wraparound(qp, ind);
1592                 qp->sq_next_wqe = ind;
1593         }
1594
1595         spin_unlock_irqrestore(&qp->sq.lock, flags);
1596
1597         return err;
1598 }
1599
1600 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1601                       struct ib_recv_wr **bad_wr)
1602 {
1603         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1604         struct mlx4_wqe_data_seg *scat;
1605         unsigned long flags;
1606         int err = 0;
1607         int nreq;
1608         int ind;
1609         int i;
1610
1611         spin_lock_irqsave(&qp->rq.lock, flags);
1612
1613         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1614
1615         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1616                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1617                         err = -ENOMEM;
1618                         *bad_wr = wr;
1619                         goto out;
1620                 }
1621
1622                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1623                         err = -EINVAL;
1624                         *bad_wr = wr;
1625                         goto out;
1626                 }
1627
1628                 scat = get_recv_wqe(qp, ind);
1629
1630                 for (i = 0; i < wr->num_sge; ++i)
1631                         __set_data_seg(scat + i, wr->sg_list + i);
1632
1633                 if (i < qp->rq.max_gs) {
1634                         scat[i].byte_count = 0;
1635                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1636                         scat[i].addr       = 0;
1637                 }
1638
1639                 qp->rq.wrid[ind] = wr->wr_id;
1640
1641                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1642         }
1643
1644 out:
1645         if (likely(nreq)) {
1646                 qp->rq.head += nreq;
1647
1648                 /*
1649                  * Make sure that descriptors are written before
1650                  * doorbell record.
1651                  */
1652                 wmb();
1653
1654                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1655         }
1656
1657         spin_unlock_irqrestore(&qp->rq.lock, flags);
1658
1659         return err;
1660 }
1661
1662 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1663 {
1664         switch (mlx4_state) {
1665         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
1666         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
1667         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
1668         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
1669         case MLX4_QP_STATE_SQ_DRAINING:
1670         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
1671         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
1672         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
1673         default:                     return -1;
1674         }
1675 }
1676
1677 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1678 {
1679         switch (mlx4_mig_state) {
1680         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
1681         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
1682         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
1683         default: return -1;
1684         }
1685 }
1686
1687 static int to_ib_qp_access_flags(int mlx4_flags)
1688 {
1689         int ib_flags = 0;
1690
1691         if (mlx4_flags & MLX4_QP_BIT_RRE)
1692                 ib_flags |= IB_ACCESS_REMOTE_READ;
1693         if (mlx4_flags & MLX4_QP_BIT_RWE)
1694                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1695         if (mlx4_flags & MLX4_QP_BIT_RAE)
1696                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1697
1698         return ib_flags;
1699 }
1700
1701 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1702                                 struct mlx4_qp_path *path)
1703 {
1704         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
1705         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
1706
1707         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1708                 return;
1709
1710         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
1711         ib_ah_attr->sl            = (path->sched_queue >> 2) & 0xf;
1712         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1713         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
1714         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1715         if (ib_ah_attr->ah_flags) {
1716                 ib_ah_attr->grh.sgid_index = path->mgid_index;
1717                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
1718                 ib_ah_attr->grh.traffic_class =
1719                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1720                 ib_ah_attr->grh.flow_label =
1721                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
1722                 memcpy(ib_ah_attr->grh.dgid.raw,
1723                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1724         }
1725 }
1726
1727 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1728                      struct ib_qp_init_attr *qp_init_attr)
1729 {
1730         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1731         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1732         struct mlx4_qp_context context;
1733         int mlx4_state;
1734         int err;
1735
1736         if (qp->state == IB_QPS_RESET) {
1737                 qp_attr->qp_state = IB_QPS_RESET;
1738                 goto done;
1739         }
1740
1741         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
1742         if (err)
1743                 return -EINVAL;
1744
1745         mlx4_state = be32_to_cpu(context.flags) >> 28;
1746
1747         qp_attr->qp_state            = to_ib_qp_state(mlx4_state);
1748         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
1749         qp_attr->path_mig_state      =
1750                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1751         qp_attr->qkey                = be32_to_cpu(context.qkey);
1752         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1753         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
1754         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
1755         qp_attr->qp_access_flags     =
1756                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1757
1758         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1759                 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1760                 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1761                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1762                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
1763         }
1764
1765         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1766         if (qp_attr->qp_state == IB_QPS_INIT)
1767                 qp_attr->port_num = qp->port;
1768         else
1769                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
1770
1771         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1772         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1773
1774         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1775
1776         qp_attr->max_dest_rd_atomic =
1777                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1778         qp_attr->min_rnr_timer      =
1779                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1780         qp_attr->timeout            = context.pri_path.ackto >> 3;
1781         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
1782         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
1783         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
1784
1785 done:
1786         qp_attr->cur_qp_state        = qp_attr->qp_state;
1787         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
1788         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
1789
1790         if (!ibqp->uobject) {
1791                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
1792                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1793         } else {
1794                 qp_attr->cap.max_send_wr  = 0;
1795                 qp_attr->cap.max_send_sge = 0;
1796         }
1797
1798         /*
1799          * We don't support inline sends for kernel QPs (yet), and we
1800          * don't know what userspace's value should be.
1801          */
1802         qp_attr->cap.max_inline_data = 0;
1803
1804         qp_init_attr->cap            = qp_attr->cap;
1805
1806         return 0;
1807 }
1808