SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <rdma/ib_cache.h>
  34 #include <rdma/ib_pack.h>
  35
  36 #include <linux/mlx4/qp.h>
  37
  38 #include "mlx4_ib.h"
  39 #include "user.h"
  40
  41 enum {
  42         MLX4_IB_ACK_REQ_FREQ    = 8,
  43 };
  44
  45 enum {
  46         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  47         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
  48 };
  49
  50 enum {
  51         /*
  52          * Largest possible UD header: send with GRH and immediate data.
  53          */
  54         MLX4_IB_UD_HEADER_SIZE          = 72
  55 };
  56
  57 struct mlx4_ib_sqp {
  58         struct mlx4_ib_qp       qp;
  59         int                     pkey_index;
  60         u32                     qkey;
  61         u32                     send_psn;
  62         struct ib_ud_header     ud_header;
  63         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  64 };
  65
  66 static const __be32 mlx4_ib_opcode[] = {
  67         [IB_WR_SEND]                    = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
  68         [IB_WR_SEND_WITH_IMM]           = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  69         [IB_WR_RDMA_WRITE]              = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  70         [IB_WR_RDMA_WRITE_WITH_IMM]     = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  71         [IB_WR_RDMA_READ]               = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  72         [IB_WR_ATOMIC_CMP_AND_SWP]      = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  73         [IB_WR_ATOMIC_FETCH_AND_ADD]    = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  74 };
  75
  76 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
  77 {
  78         return container_of(mqp, struct mlx4_ib_sqp, qp);
  79 }
  80
  81 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  82 {
  83         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  84                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
  85 }
  86
  87 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  88 {
  89         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  90                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
  91 }
  92
  93 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
  94 {
  95         if (qp->buf.nbufs == 1)
  96                 return qp->buf.u.direct.buf + offset;
  97         else
  98                 return qp->buf.u.page_list[offset >> PAGE_SHIFT].buf +
  99                         (offset & (PAGE_SIZE - 1));
 100 }
 101
 102 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 103 {
 104         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 105 }
 106
 107 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 108 {
 109         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 110 }
 111
 112 /*
 113  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 114  * first four bytes of every 64 byte chunk with 0xffffffff, except for
 115  * the very first chunk of the WQE.
 116  */
 117 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
 118 {
 119         u32 *wqe = get_send_wqe(qp, n);
 120         int i;
 121
 122         for (i = 16; i < 1 << (qp->sq.wqe_shift - 2); i += 16)
 123                 wqe[i] = 0xffffffff;
 124 }
 125
 126 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 127 {
 128         struct ib_event event;
 129         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 130
 131         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 132                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 133
 134         if (ibqp->event_handler) {
 135                 event.device     = ibqp->device;
 136                 event.element.qp = ibqp;
 137                 switch (type) {
 138                 case MLX4_EVENT_TYPE_PATH_MIG:
 139                         event.event = IB_EVENT_PATH_MIG;
 140                         break;
 141                 case MLX4_EVENT_TYPE_COMM_EST:
 142                         event.event = IB_EVENT_COMM_EST;
 143                         break;
 144                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 145                         event.event = IB_EVENT_SQ_DRAINED;
 146                         break;
 147                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 148                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 149                         break;
 150                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 151                         event.event = IB_EVENT_QP_FATAL;
 152                         break;
 153                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 154                         event.event = IB_EVENT_PATH_MIG_ERR;
 155                         break;
 156                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 157                         event.event = IB_EVENT_QP_REQ_ERR;
 158                         break;
 159                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 160                         event.event = IB_EVENT_QP_ACCESS_ERR;
 161                         break;
 162                 default:
 163                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
 164                                "on QP %06x\n", type, qp->qpn);
 165                         return;
 166                 }
 167
 168                 ibqp->event_handler(&event, ibqp->qp_context);
 169         }
 170 }
 171
 172 static int send_wqe_overhead(enum ib_qp_type type)
 173 {
 174         /*
 175          * UD WQEs must have a datagram segment.
 176          * RC and UC WQEs might have a remote address segment.
 177          * MLX WQEs need two extra inline data segments (for the UD
 178          * header and space for the ICRC).
 179          */
 180         switch (type) {
 181         case IB_QPT_UD:
 182                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 183                         sizeof (struct mlx4_wqe_datagram_seg);
 184         case IB_QPT_UC:
 185                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 186                         sizeof (struct mlx4_wqe_raddr_seg);
 187         case IB_QPT_RC:
 188                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 189                         sizeof (struct mlx4_wqe_atomic_seg) +
 190                         sizeof (struct mlx4_wqe_raddr_seg);
 191         case IB_QPT_SMI:
 192         case IB_QPT_GSI:
 193                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 194                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 195                               sizeof (struct mlx4_wqe_inline_seg),
 196                               sizeof (struct mlx4_wqe_data_seg)) +
 197                         ALIGN(4 +
 198                               sizeof (struct mlx4_wqe_inline_seg),
 199                               sizeof (struct mlx4_wqe_data_seg));
 200         default:
 201                 return sizeof (struct mlx4_wqe_ctrl_seg);
 202         }
 203 }
 204
 205 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 206                        int is_user, int has_srq, struct mlx4_ib_qp *qp)
 207 {
 208         /* Sanity check RQ size before proceeding */
 209         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
 210             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
 211                 return -EINVAL;
 212
 213         if (has_srq) {
 214                 /* QPs attached to an SRQ should have no RQ */
 215                 if (cap->max_recv_wr)
 216                         return -EINVAL;
 217
 218                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 219         } else {
 220                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 221                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 222                         return -EINVAL;
 223
 224                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 225                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 226                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 227         }
 228
 229         cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 230         cap->max_recv_sge = qp->rq.max_gs;
 231
 232         return 0;
 233 }
 234
 235 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 236                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
 237 {
 238         /* Sanity check SQ size before proceeding */
 239         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
 240             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
 241             cap->max_inline_data + send_wqe_overhead(type) +
 242             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 243                 return -EINVAL;
 244
 245         /*
 246          * For MLX transport we need 2 extra S/G entries:
 247          * one for the header and one for the checksum at the end
 248          */
 249         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
 250             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 251                 return -EINVAL;
 252
 253         qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
 254                                                         sizeof (struct mlx4_wqe_data_seg),
 255                                                         cap->max_inline_data +
 256                                                         sizeof (struct mlx4_wqe_inline_seg)) +
 257                                                     send_wqe_overhead(type)));
 258         qp->sq.max_gs    = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
 259                 sizeof (struct mlx4_wqe_data_seg);
 260
 261         /*
 262          * We need to leave 2 KB + 1 WQE of headroom in the SQ to
 263          * allow HW to prefetch.
 264          */
 265         qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + 1;
 266         qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + qp->sq_spare_wqes);
 267
 268         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 269                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 270         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 271                 qp->rq.offset = 0;
 272                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 273         } else {
 274                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 275                 qp->sq.offset = 0;
 276         }
 277
 278         cap->max_send_wr  = qp->sq.max_post = qp->sq.wqe_cnt - qp->sq_spare_wqes;
 279         cap->max_send_sge = qp->sq.max_gs;
 280         /* We don't support inline sends for kernel QPs (yet) */
 281         cap->max_inline_data = 0;
 282
 283         return 0;
 284 }
 285
 286 static int set_user_sq_size(struct mlx4_ib_qp *qp,
 287                             struct mlx4_ib_create_qp *ucmd)
 288 {
 289         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 290         qp->sq.wqe_shift = ucmd->log_sq_stride;
 291
 292         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 293                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 294
 295         return 0;
 296 }
 297
 298 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 299                             struct ib_qp_init_attr *init_attr,
 300                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
 301 {
 302         int err;
 303
 304         mutex_init(&qp->mutex);
 305         spin_lock_init(&qp->sq.lock);
 306         spin_lock_init(&qp->rq.lock);
 307
 308         qp->state        = IB_QPS_RESET;
 309         qp->atomic_rd_en = 0;
 310         qp->resp_depth   = 0;
 311
 312         qp->rq.head         = 0;
 313         qp->rq.tail         = 0;
 314         qp->sq.head         = 0;
 315         qp->sq.tail         = 0;
 316
 317         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
 318         if (err)
 319                 goto err;
 320
 321         if (pd->uobject) {
 322                 struct mlx4_ib_create_qp ucmd;
 323
 324                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 325                         err = -EFAULT;
 326                         goto err;
 327                 }
 328
 329                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 330
 331                 err = set_user_sq_size(qp, &ucmd);
 332                 if (err)
 333                         goto err;
 334
 335                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 336                                        qp->buf_size, 0);
 337                 if (IS_ERR(qp->umem)) {
 338                         err = PTR_ERR(qp->umem);
 339                         goto err;
 340                 }
 341
 342                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 343                                     ilog2(qp->umem->page_size), &qp->mtt);
 344                 if (err)
 345                         goto err_buf;
 346
 347                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 348                 if (err)
 349                         goto err_mtt;
 350
 351                 if (!init_attr->srq) {
 352                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 353                                                   ucmd.db_addr, &qp->db);
 354                         if (err)
 355                                 goto err_mtt;
 356                 }
 357         } else {
 358                 qp->sq_no_prefetch = 0;
 359
 360                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
 361                 if (err)
 362                         goto err;
 363
 364                 if (!init_attr->srq) {
 365                         err = mlx4_ib_db_alloc(dev, &qp->db, 0);
 366                         if (err)
 367                                 goto err;
 368
 369                         *qp->db.db = 0;
 370                 }
 371
 372                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 373                         err = -ENOMEM;
 374                         goto err_db;
 375                 }
 376
 377                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 378                                     &qp->mtt);
 379                 if (err)
 380                         goto err_buf;
 381
 382                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 383                 if (err)
 384                         goto err_mtt;
 385
 386                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 387                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 388
 389                 if (!qp->sq.wrid || !qp->rq.wrid) {
 390                         err = -ENOMEM;
 391                         goto err_wrid;
 392                 }
 393         }
 394
 395         err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
 396         if (err)
 397                 goto err_wrid;
 398
 399         /*
 400          * Hardware wants QPN written in big-endian order (after
 401          * shifting) for send doorbell.  Precompute this value to save
 402          * a little bit when posting sends.
 403          */
 404         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 405
 406         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 407                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 408         else
 409                 qp->sq_signal_bits = 0;
 410
 411         qp->mqp.event = mlx4_ib_qp_event;
 412
 413         return 0;
 414
 415 err_wrid:
 416         if (pd->uobject && !init_attr->srq)
 417                 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 418         else {
 419                 kfree(qp->sq.wrid);
 420                 kfree(qp->rq.wrid);
 421         }
 422
 423 err_mtt:
 424         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 425
 426 err_buf:
 427         if (pd->uobject)
 428                 ib_umem_release(qp->umem);
 429         else
 430                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 431
 432 err_db:
 433         if (!pd->uobject && !init_attr->srq)
 434                 mlx4_ib_db_free(dev, &qp->db);
 435
 436 err:
 437         return err;
 438 }
 439
 440 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 441 {
 442         switch (state) {
 443         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 444         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 445         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 446         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 447         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 448         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 449         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 450         default:                return -1;
 451         }
 452 }
 453
 454 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 455 {
 456         if (send_cq == recv_cq)
 457                 spin_lock_irq(&send_cq->lock);
 458         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 459                 spin_lock_irq(&send_cq->lock);
 460                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 461         } else {
 462                 spin_lock_irq(&recv_cq->lock);
 463                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 464         }
 465 }
 466
 467 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 468 {
 469         if (send_cq == recv_cq)
 470                 spin_unlock_irq(&send_cq->lock);
 471         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 472                 spin_unlock(&recv_cq->lock);
 473                 spin_unlock_irq(&send_cq->lock);
 474         } else {
 475                 spin_unlock(&send_cq->lock);
 476                 spin_unlock_irq(&recv_cq->lock);
 477         }
 478 }
 479
 480 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 481                               int is_user)
 482 {
 483         struct mlx4_ib_cq *send_cq, *recv_cq;
 484
 485         if (qp->state != IB_QPS_RESET)
 486                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 487                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 488                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
 489                                qp->mqp.qpn);
 490
 491         send_cq = to_mcq(qp->ibqp.send_cq);
 492         recv_cq = to_mcq(qp->ibqp.recv_cq);
 493
 494         mlx4_ib_lock_cqs(send_cq, recv_cq);
 495
 496         if (!is_user) {
 497                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 498                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 499                 if (send_cq != recv_cq)
 500                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 501         }
 502
 503         mlx4_qp_remove(dev->dev, &qp->mqp);
 504
 505         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 506
 507         mlx4_qp_free(dev->dev, &qp->mqp);
 508         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 509
 510         if (is_user) {
 511                 if (!qp->ibqp.srq)
 512                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 513                                               &qp->db);
 514                 ib_umem_release(qp->umem);
 515         } else {
 516                 kfree(qp->sq.wrid);
 517                 kfree(qp->rq.wrid);
 518                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 519                 if (!qp->ibqp.srq)
 520                         mlx4_ib_db_free(dev, &qp->db);
 521         }
 522 }
 523
 524 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 525                                 struct ib_qp_init_attr *init_attr,
 526                                 struct ib_udata *udata)
 527 {
 528         struct mlx4_ib_dev *dev = to_mdev(pd->device);
 529         struct mlx4_ib_sqp *sqp;
 530         struct mlx4_ib_qp *qp;
 531         int err;
 532
 533         switch (init_attr->qp_type) {
 534         case IB_QPT_RC:
 535         case IB_QPT_UC:
 536         case IB_QPT_UD:
 537         {
 538                 qp = kmalloc(sizeof *qp, GFP_KERNEL);
 539                 if (!qp)
 540                         return ERR_PTR(-ENOMEM);
 541
 542                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
 543                 if (err) {
 544                         kfree(qp);
 545                         return ERR_PTR(err);
 546                 }
 547
 548                 qp->ibqp.qp_num = qp->mqp.qpn;
 549
 550                 break;
 551         }
 552         case IB_QPT_SMI:
 553         case IB_QPT_GSI:
 554         {
 555                 /* Userspace is not allowed to create special QPs: */
 556                 if (pd->uobject)
 557                         return ERR_PTR(-EINVAL);
 558
 559                 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
 560                 if (!sqp)
 561                         return ERR_PTR(-ENOMEM);
 562
 563                 qp = &sqp->qp;
 564
 565                 err = create_qp_common(dev, pd, init_attr, udata,
 566                                        dev->dev->caps.sqp_start +
 567                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 568                                        init_attr->port_num - 1,
 569                                        qp);
 570                 if (err) {
 571                         kfree(sqp);
 572                         return ERR_PTR(err);
 573                 }
 574
 575                 qp->port        = init_attr->port_num;
 576                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
 577
 578                 break;
 579         }
 580         default:
 581                 /* Don't support raw QPs */
 582                 return ERR_PTR(-EINVAL);
 583         }
 584
 585         return &qp->ibqp;
 586 }
 587
 588 int mlx4_ib_destroy_qp(struct ib_qp *qp)
 589 {
 590         struct mlx4_ib_dev *dev = to_mdev(qp->device);
 591         struct mlx4_ib_qp *mqp = to_mqp(qp);
 592
 593         if (is_qp0(dev, mqp))
 594                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
 595
 596         destroy_qp_common(dev, mqp, !!qp->pd->uobject);
 597
 598         if (is_sqp(dev, mqp))
 599                 kfree(to_msqp(mqp));
 600         else
 601                 kfree(mqp);
 602
 603         return 0;
 604 }
 605
 606 static void init_port(struct mlx4_ib_dev *dev, int port)
 607 {
 608         struct mlx4_init_port_param param;
 609         int err;
 610
 611         memset(&param, 0, sizeof param);
 612
 613         param.port_width_cap = dev->dev->caps.port_width_cap;
 614         param.vl_cap         = dev->dev->caps.vl_cap;
 615         param.mtu            = ib_mtu_enum_to_int(dev->dev->caps.mtu_cap);
 616         param.max_gid        = dev->dev->caps.gid_table_len;
 617         param.max_pkey       = dev->dev->caps.pkey_table_len;
 618
 619         err = mlx4_INIT_PORT(dev->dev, &param, port);
 620         if (err)
 621                 printk(KERN_WARNING "INIT_PORT failed, return code %d.\n", err);
 622 }
 623
 624 static int to_mlx4_st(enum ib_qp_type type)
 625 {
 626         switch (type) {
 627         case IB_QPT_RC:         return MLX4_QP_ST_RC;
 628         case IB_QPT_UC:         return MLX4_QP_ST_UC;
 629         case IB_QPT_UD:         return MLX4_QP_ST_UD;
 630         case IB_QPT_SMI:
 631         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
 632         default:                return -1;
 633         }
 634 }
 635
 636 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
 637                                    int attr_mask)
 638 {
 639         u8 dest_rd_atomic;
 640         u32 access_flags;
 641         u32 hw_access_flags = 0;
 642
 643         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 644                 dest_rd_atomic = attr->max_dest_rd_atomic;
 645         else
 646                 dest_rd_atomic = qp->resp_depth;
 647
 648         if (attr_mask & IB_QP_ACCESS_FLAGS)
 649                 access_flags = attr->qp_access_flags;
 650         else
 651                 access_flags = qp->atomic_rd_en;
 652
 653         if (!dest_rd_atomic)
 654                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 655
 656         if (access_flags & IB_ACCESS_REMOTE_READ)
 657                 hw_access_flags |= MLX4_QP_BIT_RRE;
 658         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 659                 hw_access_flags |= MLX4_QP_BIT_RAE;
 660         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 661                 hw_access_flags |= MLX4_QP_BIT_RWE;
 662
 663         return cpu_to_be32(hw_access_flags);
 664 }
 665
 666 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
 667                             int attr_mask)
 668 {
 669         if (attr_mask & IB_QP_PKEY_INDEX)
 670                 sqp->pkey_index = attr->pkey_index;
 671         if (attr_mask & IB_QP_QKEY)
 672                 sqp->qkey = attr->qkey;
 673         if (attr_mask & IB_QP_SQ_PSN)
 674                 sqp->send_psn = attr->sq_psn;
 675 }
 676
 677 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
 678 {
 679         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
 680 }
 681
 682 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
 683                          struct mlx4_qp_path *path, u8 port)
 684 {
 685         path->grh_mylmc     = ah->src_path_bits & 0x7f;
 686         path->rlid          = cpu_to_be16(ah->dlid);
 687         if (ah->static_rate) {
 688                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
 689                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
 690                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
 691                         --path->static_rate;
 692         } else
 693                 path->static_rate = 0;
 694         path->counter_index = 0xff;
 695
 696         if (ah->ah_flags & IB_AH_GRH) {
 697                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len) {
 698                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
 699                                ah->grh.sgid_index, dev->dev->caps.gid_table_len - 1);
 700                         return -1;
 701                 }
 702
 703                 path->grh_mylmc |= 1 << 7;
 704                 path->mgid_index = ah->grh.sgid_index;
 705                 path->hop_limit  = ah->grh.hop_limit;
 706                 path->tclass_flowlabel =
 707                         cpu_to_be32((ah->grh.traffic_class << 20) |
 708                                     (ah->grh.flow_label));
 709                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 710         }
 711
 712         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 713                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
 714
 715         return 0;
 716 }
 717
 718 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
 719                                const struct ib_qp_attr *attr, int attr_mask,
 720                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
 721 {
 722         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 723         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 724         struct mlx4_qp_context *context;
 725         enum mlx4_qp_optpar optpar = 0;
 726         int sqd_event;
 727         int err = -EINVAL;
 728
 729         context = kzalloc(sizeof *context, GFP_KERNEL);
 730         if (!context)
 731                 return -ENOMEM;
 732
 733         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
 734                                      (to_mlx4_st(ibqp->qp_type) << 16));
 735         context->flags     |= cpu_to_be32(1 << 8); /* DE? */
 736
 737         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 738                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 739         else {
 740                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
 741                 switch (attr->path_mig_state) {
 742                 case IB_MIG_MIGRATED:
 743                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 744                         break;
 745                 case IB_MIG_REARM:
 746                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
 747                         break;
 748                 case IB_MIG_ARMED:
 749                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
 750                         break;
 751                 }
 752         }
 753
 754         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
 755             ibqp->qp_type == IB_QPT_UD)
 756                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 757         else if (attr_mask & IB_QP_PATH_MTU) {
 758                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
 759                         printk(KERN_ERR "path MTU (%u) is invalid\n",
 760                                attr->path_mtu);
 761                         return -EINVAL;
 762                 }
 763                 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 764         }
 765
 766         if (qp->rq.wqe_cnt)
 767                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
 768         context->rq_size_stride |= qp->rq.wqe_shift - 4;
 769
 770         if (qp->sq.wqe_cnt)
 771                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
 772         context->sq_size_stride |= qp->sq.wqe_shift - 4;
 773
 774         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
 775                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
 776
 777         if (qp->ibqp.uobject)
 778                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
 779         else
 780                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
 781
 782         if (attr_mask & IB_QP_DEST_QPN)
 783                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 784
 785         if (attr_mask & IB_QP_PORT) {
 786                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
 787                     !(attr_mask & IB_QP_AV)) {
 788                         mlx4_set_sched(&context->pri_path, attr->port_num);
 789                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
 790                 }
 791         }
 792
 793         if (attr_mask & IB_QP_PKEY_INDEX) {
 794                 context->pri_path.pkey_index = attr->pkey_index;
 795                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
 796         }
 797
 798         if (attr_mask & IB_QP_AV) {
 799                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
 800                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) {
 801                         err = -EINVAL;
 802                         goto out;
 803                 }
 804
 805                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
 806                            MLX4_QP_OPTPAR_SCHED_QUEUE);
 807         }
 808
 809         if (attr_mask & IB_QP_TIMEOUT) {
 810                 context->pri_path.ackto = attr->timeout << 3;
 811                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
 812         }
 813
 814         if (attr_mask & IB_QP_ALT_PATH) {
 815                 if (attr->alt_pkey_index >= dev->dev->caps.pkey_table_len)
 816                         return -EINVAL;
 817
 818                 if (attr->alt_port_num == 0 ||
 819                     attr->alt_port_num > dev->dev->caps.num_ports)
 820                         return -EINVAL;
 821
 822                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
 823                                   attr->alt_port_num))
 824                         return -EINVAL;
 825
 826                 context->alt_path.pkey_index = attr->alt_pkey_index;
 827                 context->alt_path.ackto = attr->alt_timeout << 3;
 828                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
 829         }
 830
 831         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
 832         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
 833
 834         if (attr_mask & IB_QP_RNR_RETRY) {
 835                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
 836                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
 837         }
 838
 839         if (attr_mask & IB_QP_RETRY_CNT) {
 840                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 841                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
 842         }
 843
 844         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 845                 if (attr->max_rd_atomic)
 846                         context->params1 |=
 847                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 848                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
 849         }
 850
 851         if (attr_mask & IB_QP_SQ_PSN)
 852                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
 853
 854         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
 855
 856         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 857                 if (attr->max_dest_rd_atomic)
 858                         context->params2 |=
 859                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 860                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
 861         }
 862
 863         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 864                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
 865                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
 866         }
 867
 868         if (ibqp->srq)
 869                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
 870
 871         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 872                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 873                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
 874         }
 875         if (attr_mask & IB_QP_RQ_PSN)
 876                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 877
 878         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
 879
 880         if (attr_mask & IB_QP_QKEY) {
 881                 context->qkey = cpu_to_be32(attr->qkey);
 882                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
 883         }
 884
 885         if (ibqp->srq)
 886                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
 887
 888         if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
 889                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
 890
 891         if (cur_state == IB_QPS_INIT &&
 892             new_state == IB_QPS_RTR  &&
 893             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
 894              ibqp->qp_type == IB_QPT_UD)) {
 895                 context->pri_path.sched_queue = (qp->port - 1) << 6;
 896                 if (is_qp0(dev, qp))
 897                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
 898                 else
 899                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
 900         }
 901
 902         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 903             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
 904                 sqd_event = 1;
 905         else
 906                 sqd_event = 0;
 907
 908         /*
 909          * Before passing a kernel QP to the HW, make sure that the
 910          * ownership bits of the send queue are set and the SQ
 911          * headroom is stamped so that the hardware doesn't start
 912          * processing stale work requests.
 913          */
 914         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
 915                 struct mlx4_wqe_ctrl_seg *ctrl;
 916                 int i;
 917
 918                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
 919                         ctrl = get_send_wqe(qp, i);
 920                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
 921
 922                         stamp_send_wqe(qp, i);
 923                 }
 924         }
 925
 926         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
 927                              to_mlx4_state(new_state), context, optpar,
 928                              sqd_event, &qp->mqp);
 929         if (err)
 930                 goto out;
 931
 932         qp->state = new_state;
 933
 934         if (attr_mask & IB_QP_ACCESS_FLAGS)
 935                 qp->atomic_rd_en = attr->qp_access_flags;
 936         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 937                 qp->resp_depth = attr->max_dest_rd_atomic;
 938         if (attr_mask & IB_QP_PORT)
 939                 qp->port = attr->port_num;
 940         if (attr_mask & IB_QP_ALT_PATH)
 941                 qp->alt_port = attr->alt_port_num;
 942
 943         if (is_sqp(dev, qp))
 944                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
 945
 946         /*
 947          * If we moved QP0 to RTR, bring the IB link up; if we moved
 948          * QP0 to RESET or ERROR, bring the link back down.
 949          */
 950         if (is_qp0(dev, qp)) {
 951                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
 952                         init_port(dev, qp->port);
 953
 954                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
 955                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
 956                         mlx4_CLOSE_PORT(dev->dev, qp->port);
 957         }
 958
 959         /*
 960          * If we moved a kernel QP to RESET, clean up all old CQ
 961          * entries and reinitialize the QP.
 962          */
 963         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
 964                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
 965                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
 966                 if (ibqp->send_cq != ibqp->recv_cq)
 967                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
 968
 969                 qp->rq.head = 0;
 970                 qp->rq.tail = 0;
 971                 qp->sq.head = 0;
 972                 qp->sq.tail = 0;
 973                 if (!ibqp->srq)
 974                         *qp->db.db  = 0;
 975         }
 976
 977 out:
 978         kfree(context);
 979         return err;
 980 }
 981
 982 static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
 983 static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
 984                 [IB_QPT_UD]  = (IB_QP_PKEY_INDEX                |
 985                                 IB_QP_PORT                      |
 986                                 IB_QP_QKEY),
 987                 [IB_QPT_UC]  = (IB_QP_PKEY_INDEX                |
 988                                 IB_QP_PORT                      |
 989                                 IB_QP_ACCESS_FLAGS),
 990                 [IB_QPT_RC]  = (IB_QP_PKEY_INDEX                |
 991                                 IB_QP_PORT                      |
 992                                 IB_QP_ACCESS_FLAGS),
 993                 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX                |
 994                                 IB_QP_QKEY),
 995                 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX                |
 996                                 IB_QP_QKEY),
 997 };
 998
 999 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1000                       int attr_mask, struct ib_udata *udata)
1001 {
1002         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1003         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1004         enum ib_qp_state cur_state, new_state;
1005         int err = -EINVAL;
1006
1007         mutex_lock(&qp->mutex);
1008
1009         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1010         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1011
1012         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1013                 goto out;
1014
1015         if ((attr_mask & IB_QP_PKEY_INDEX) &&
1016              attr->pkey_index >= dev->dev->caps.pkey_table_len) {
1017                 goto out;
1018         }
1019
1020         if ((attr_mask & IB_QP_PORT) &&
1021             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1022                 goto out;
1023         }
1024
1025         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1026             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1027                 goto out;
1028         }
1029
1030         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1031             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1032                 goto out;
1033         }
1034
1035         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1036                 err = 0;
1037                 goto out;
1038         }
1039
1040         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
1041                 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
1042                                           mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
1043                                           IB_QPS_RESET, IB_QPS_INIT);
1044                 if (err)
1045                         goto out;
1046                 cur_state = IB_QPS_INIT;
1047         }
1048
1049         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1050
1051 out:
1052         mutex_unlock(&qp->mutex);
1053         return err;
1054 }
1055
1056 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1057                             void *wqe)
1058 {
1059         struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1060         struct mlx4_wqe_mlx_seg *mlx = wqe;
1061         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1062         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1063         u16 pkey;
1064         int send_size;
1065         int header_size;
1066         int i;
1067
1068         send_size = 0;
1069         for (i = 0; i < wr->num_sge; ++i)
1070                 send_size += wr->sg_list[i].length;
1071
1072         ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1073
1074         sqp->ud_header.lrh.service_level   =
1075                 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1076         sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1077         sqp->ud_header.lrh.source_lid      = cpu_to_be16(ah->av.g_slid & 0x7f);
1078         if (mlx4_ib_ah_grh_present(ah)) {
1079                 sqp->ud_header.grh.traffic_class =
1080                         (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1081                 sqp->ud_header.grh.flow_label    =
1082                         ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1083                 sqp->ud_header.grh.hop_limit     = ah->av.hop_limit;
1084                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1085                                   ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1086                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1087                        ah->av.dgid, 16);
1088         }
1089
1090         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1091         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1092                                   (sqp->ud_header.lrh.destination_lid ==
1093                                    IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1094                                   (sqp->ud_header.lrh.service_level << 8));
1095         mlx->rlid   = sqp->ud_header.lrh.destination_lid;
1096
1097         switch (wr->opcode) {
1098         case IB_WR_SEND:
1099                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1100                 sqp->ud_header.immediate_present = 0;
1101                 break;
1102         case IB_WR_SEND_WITH_IMM:
1103                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1104                 sqp->ud_header.immediate_present = 1;
1105                 sqp->ud_header.immediate_data    = wr->imm_data;
1106                 break;
1107         default:
1108                 return -EINVAL;
1109         }
1110
1111         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1112         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1113                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1114         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1115         if (!sqp->qp.ibqp.qp_num)
1116                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1117         else
1118                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1119         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1120         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1121         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1122         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1123                                                sqp->qkey : wr->wr.ud.remote_qkey);
1124         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1125
1126         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1127
1128         if (0) {
1129                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1130                 for (i = 0; i < header_size / 4; ++i) {
1131                         if (i % 8 == 0)
1132                                 printk("  [%02x] ", i * 4);
1133                         printk(" %08x",
1134                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1135                         if ((i + 1) % 8 == 0)
1136                                 printk("\n");
1137                 }
1138                 printk("\n");
1139         }
1140
1141         inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1142         memcpy(inl + 1, sqp->header_buf, header_size);
1143
1144         return ALIGN(sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1145 }
1146
1147 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1148 {
1149         unsigned cur;
1150         struct mlx4_ib_cq *cq;
1151
1152         cur = wq->head - wq->tail;
1153         if (likely(cur + nreq < wq->max_post))
1154                 return 0;
1155
1156         cq = to_mcq(ib_cq);
1157         spin_lock(&cq->lock);
1158         cur = wq->head - wq->tail;
1159         spin_unlock(&cq->lock);
1160
1161         return cur + nreq >= wq->max_post;
1162 }
1163
1164 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1165                       struct ib_send_wr **bad_wr)
1166 {
1167         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1168         void *wqe;
1169         struct mlx4_wqe_ctrl_seg *ctrl;
1170         unsigned long flags;
1171         int nreq;
1172         int err = 0;
1173         int ind;
1174         int size;
1175         int i;
1176
1177         spin_lock_irqsave(&qp->rq.lock, flags);
1178
1179         ind = qp->sq.head;
1180
1181         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1182                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1183                         err = -ENOMEM;
1184                         *bad_wr = wr;
1185                         goto out;
1186                 }
1187
1188                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1189                         err = -EINVAL;
1190                         *bad_wr = wr;
1191                         goto out;
1192                 }
1193
1194                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1195                 qp->sq.wrid[ind & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1196
1197                 ctrl->srcrb_flags =
1198                         (wr->send_flags & IB_SEND_SIGNALED ?
1199                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1200                         (wr->send_flags & IB_SEND_SOLICITED ?
1201                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1202                         qp->sq_signal_bits;
1203
1204                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1205                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1206                         ctrl->imm = wr->imm_data;
1207                 else
1208                         ctrl->imm = 0;
1209
1210                 wqe += sizeof *ctrl;
1211                 size = sizeof *ctrl / 16;
1212
1213                 switch (ibqp->qp_type) {
1214                 case IB_QPT_RC:
1215                 case IB_QPT_UC:
1216                         switch (wr->opcode) {
1217                         case IB_WR_ATOMIC_CMP_AND_SWP:
1218                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1219                                 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1220                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1221                                 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1222                                         cpu_to_be32(wr->wr.atomic.rkey);
1223                                 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1224
1225                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1226
1227                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1228                                         ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1229                                                 cpu_to_be64(wr->wr.atomic.swap);
1230                                         ((struct mlx4_wqe_atomic_seg *) wqe)->compare =
1231                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1232                                 } else {
1233                                         ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1234                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1235                                         ((struct mlx4_wqe_atomic_seg *) wqe)->compare = 0;
1236                                 }
1237
1238                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1239                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1240                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1241
1242                                 break;
1243
1244                         case IB_WR_RDMA_READ:
1245                         case IB_WR_RDMA_WRITE:
1246                         case IB_WR_RDMA_WRITE_WITH_IMM:
1247                                 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1248                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1249                                 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1250                                         cpu_to_be32(wr->wr.rdma.rkey);
1251                                 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1252
1253                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1254                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1255
1256                                 break;
1257
1258                         default:
1259                                 /* No extra segments required for sends */
1260                                 break;
1261                         }
1262                         break;
1263
1264                 case IB_QPT_UD:
1265                         memcpy(((struct mlx4_wqe_datagram_seg *) wqe)->av,
1266                                &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1267                         ((struct mlx4_wqe_datagram_seg *) wqe)->dqpn =
1268                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1269                         ((struct mlx4_wqe_datagram_seg *) wqe)->qkey =
1270                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1271
1272                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1273                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1274                         break;
1275
1276                 case IB_QPT_SMI:
1277                 case IB_QPT_GSI:
1278                         err = build_mlx_header(to_msqp(qp), wr, ctrl);
1279                         if (err < 0) {
1280                                 *bad_wr = wr;
1281                                 goto out;
1282                         }
1283                         wqe  += err;
1284                         size += err / 16;
1285
1286                         err = 0;
1287                         break;
1288
1289                 default:
1290                         break;
1291                 }
1292
1293                 for (i = 0; i < wr->num_sge; ++i) {
1294                         ((struct mlx4_wqe_data_seg *) wqe)->byte_count =
1295                                 cpu_to_be32(wr->sg_list[i].length);
1296                         ((struct mlx4_wqe_data_seg *) wqe)->lkey =
1297                                 cpu_to_be32(wr->sg_list[i].lkey);
1298                         ((struct mlx4_wqe_data_seg *) wqe)->addr =
1299                                 cpu_to_be64(wr->sg_list[i].addr);
1300
1301                         wqe  += sizeof (struct mlx4_wqe_data_seg);
1302                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1303                 }
1304
1305                 /* Add one more inline data segment for ICRC for MLX sends */
1306                 if (qp->ibqp.qp_type == IB_QPT_SMI || qp->ibqp.qp_type == IB_QPT_GSI) {
1307                         ((struct mlx4_wqe_inline_seg *) wqe)->byte_count =
1308                                 cpu_to_be32((1 << 31) | 4);
1309                         ((u32 *) wqe)[1] = 0;
1310                         wqe  += sizeof (struct mlx4_wqe_data_seg);
1311                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1312                 }
1313
1314                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1315                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1316
1317                 /*
1318                  * Make sure descriptor is fully written before
1319                  * setting ownership bit (because HW can start
1320                  * executing as soon as we do).
1321                  */
1322                 wmb();
1323
1324                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1325                         err = -EINVAL;
1326                         goto out;
1327                 }
1328
1329                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1330                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1331
1332                 /*
1333                  * We can improve latency by not stamping the last
1334                  * send queue WQE until after ringing the doorbell, so
1335                  * only stamp here if there are still more WQEs to post.
1336                  */
1337                 if (wr->next)
1338                         stamp_send_wqe(qp, (ind + qp->sq_spare_wqes) &
1339                                        (qp->sq.wqe_cnt - 1));
1340
1341                 ++ind;
1342         }
1343
1344 out:
1345         if (likely(nreq)) {
1346                 qp->sq.head += nreq;
1347
1348                 /*
1349                  * Make sure that descriptors are written before
1350                  * doorbell record.
1351                  */
1352                 wmb();
1353
1354                 writel(qp->doorbell_qpn,
1355                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1356
1357                 /*
1358                  * Make sure doorbells don't leak out of SQ spinlock
1359                  * and reach the HCA out of order.
1360                  */
1361                 mmiowb();
1362
1363                 stamp_send_wqe(qp, (ind + qp->sq_spare_wqes - 1) &
1364                                (qp->sq.wqe_cnt - 1));
1365         }
1366
1367         spin_unlock_irqrestore(&qp->rq.lock, flags);
1368
1369         return err;
1370 }
1371
1372 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1373                       struct ib_recv_wr **bad_wr)
1374 {
1375         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1376         struct mlx4_wqe_data_seg *scat;
1377         unsigned long flags;
1378         int err = 0;
1379         int nreq;
1380         int ind;
1381         int i;
1382
1383         spin_lock_irqsave(&qp->rq.lock, flags);
1384
1385         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1386
1387         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1388                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1389                         err = -ENOMEM;
1390                         *bad_wr = wr;
1391                         goto out;
1392                 }
1393
1394                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1395                         err = -EINVAL;
1396                         *bad_wr = wr;
1397                         goto out;
1398                 }
1399
1400                 scat = get_recv_wqe(qp, ind);
1401
1402                 for (i = 0; i < wr->num_sge; ++i) {
1403                         scat[i].byte_count = cpu_to_be32(wr->sg_list[i].length);
1404                         scat[i].lkey       = cpu_to_be32(wr->sg_list[i].lkey);
1405                         scat[i].addr       = cpu_to_be64(wr->sg_list[i].addr);
1406                 }
1407
1408                 if (i < qp->rq.max_gs) {
1409                         scat[i].byte_count = 0;
1410                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1411                         scat[i].addr       = 0;
1412                 }
1413
1414                 qp->rq.wrid[ind] = wr->wr_id;
1415
1416                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1417         }
1418
1419 out:
1420         if (likely(nreq)) {
1421                 qp->rq.head += nreq;
1422
1423                 /*
1424                  * Make sure that descriptors are written before
1425                  * doorbell record.
1426                  */
1427                 wmb();
1428
1429                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1430         }
1431
1432         spin_unlock_irqrestore(&qp->rq.lock, flags);
1433
1434         return err;
1435 }