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   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/log2.h>
  34
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_pack.h>
  37
  38 #include <linux/mlx4/qp.h>
  39
  40 #include "mlx4_ib.h"
  41 #include "user.h"
  42
  43 enum {
  44         MLX4_IB_ACK_REQ_FREQ    = 8,
  45 };
  46
  47 enum {
  48         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  49         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
  50 };
  51
  52 enum {
  53         /*
  54          * Largest possible UD header: send with GRH and immediate data.
  55          */
  56         MLX4_IB_UD_HEADER_SIZE          = 72
  57 };
  58
  59 struct mlx4_ib_sqp {
  60         struct mlx4_ib_qp       qp;
  61         int                     pkey_index;
  62         u32                     qkey;
  63         u32                     send_psn;
  64         struct ib_ud_header     ud_header;
  65         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  66 };
  67
  68 enum {
  69         MLX4_IB_MIN_SQ_STRIDE = 6
  70 };
  71
  72 static const __be32 mlx4_ib_opcode[] = {
  73         [IB_WR_SEND]                    = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
  74         [IB_WR_LSO]                     = __constant_cpu_to_be32(MLX4_OPCODE_LSO),
  75         [IB_WR_SEND_WITH_IMM]           = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  76         [IB_WR_RDMA_WRITE]              = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  77         [IB_WR_RDMA_WRITE_WITH_IMM]     = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  78         [IB_WR_RDMA_READ]               = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  79         [IB_WR_ATOMIC_CMP_AND_SWP]      = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  80         [IB_WR_ATOMIC_FETCH_AND_ADD]    = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  81 };
  82
  83 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
  84 {
  85         return container_of(mqp, struct mlx4_ib_sqp, qp);
  86 }
  87
  88 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  89 {
  90         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  91                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
  92 }
  93
  94 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  95 {
  96         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  97                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
  98 }
  99
 100 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 101 {
 102         return mlx4_buf_offset(&qp->buf, offset);
 103 }
 104
 105 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 106 {
 107         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 108 }
 109
 110 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 111 {
 112         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 113 }
 114
 115 /*
 116  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 117  * first four bytes of every 64 byte chunk with
 118  *     0x7FFFFFF | (invalid_ownership_value << 31).
 119  *
 120  * When the max work request size is less than or equal to the WQE
 121  * basic block size, as an optimization, we can stamp all WQEs with
 122  * 0xffffffff, and skip the very first chunk of each WQE.
 123  */
 124 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 125 {
 126         __be32 *wqe;
 127         int i;
 128         int s;
 129         int ind;
 130         void *buf;
 131         __be32 stamp;
 132         struct mlx4_wqe_ctrl_seg *ctrl;
 133
 134         if (qp->sq_max_wqes_per_wr > 1) {
 135                 s = roundup(size, 1U << qp->sq.wqe_shift);
 136                 for (i = 0; i < s; i += 64) {
 137                         ind = (i >> qp->sq.wqe_shift) + n;
 138                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 139                                                        cpu_to_be32(0xffffffff);
 140                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 141                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 142                         *wqe = stamp;
 143                 }
 144         } else {
 145                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 146                 s = (ctrl->fence_size & 0x3f) << 4;
 147                 for (i = 64; i < s; i += 64) {
 148                         wqe = buf + i;
 149                         *wqe = cpu_to_be32(0xffffffff);
 150                 }
 151         }
 152 }
 153
 154 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 155 {
 156         struct mlx4_wqe_ctrl_seg *ctrl;
 157         struct mlx4_wqe_inline_seg *inl;
 158         void *wqe;
 159         int s;
 160
 161         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 162         s = sizeof(struct mlx4_wqe_ctrl_seg);
 163
 164         if (qp->ibqp.qp_type == IB_QPT_UD) {
 165                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 166                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 167                 memset(dgram, 0, sizeof *dgram);
 168                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 169                 s += sizeof(struct mlx4_wqe_datagram_seg);
 170         }
 171
 172         /* Pad the remainder of the WQE with an inline data segment. */
 173         if (size > s) {
 174                 inl = wqe + s;
 175                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 176         }
 177         ctrl->srcrb_flags = 0;
 178         ctrl->fence_size = size / 16;
 179         /*
 180          * Make sure descriptor is fully written before setting ownership bit
 181          * (because HW can start executing as soon as we do).
 182          */
 183         wmb();
 184
 185         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 186                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 187
 188         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 189 }
 190
 191 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 192 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 193 {
 194         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 195         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 196                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 197                 ind += s;
 198         }
 199         return ind;
 200 }
 201
 202 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 203 {
 204         struct ib_event event;
 205         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 206
 207         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 208                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 209
 210         if (ibqp->event_handler) {
 211                 event.device     = ibqp->device;
 212                 event.element.qp = ibqp;
 213                 switch (type) {
 214                 case MLX4_EVENT_TYPE_PATH_MIG:
 215                         event.event = IB_EVENT_PATH_MIG;
 216                         break;
 217                 case MLX4_EVENT_TYPE_COMM_EST:
 218                         event.event = IB_EVENT_COMM_EST;
 219                         break;
 220                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 221                         event.event = IB_EVENT_SQ_DRAINED;
 222                         break;
 223                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 224                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 225                         break;
 226                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 227                         event.event = IB_EVENT_QP_FATAL;
 228                         break;
 229                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 230                         event.event = IB_EVENT_PATH_MIG_ERR;
 231                         break;
 232                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 233                         event.event = IB_EVENT_QP_REQ_ERR;
 234                         break;
 235                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 236                         event.event = IB_EVENT_QP_ACCESS_ERR;
 237                         break;
 238                 default:
 239                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
 240                                "on QP %06x\n", type, qp->qpn);
 241                         return;
 242                 }
 243
 244                 ibqp->event_handler(&event, ibqp->qp_context);
 245         }
 246 }
 247
 248 static int send_wqe_overhead(enum ib_qp_type type, u32 flags)
 249 {
 250         /*
 251          * UD WQEs must have a datagram segment.
 252          * RC and UC WQEs might have a remote address segment.
 253          * MLX WQEs need two extra inline data segments (for the UD
 254          * header and space for the ICRC).
 255          */
 256         switch (type) {
 257         case IB_QPT_UD:
 258                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 259                         sizeof (struct mlx4_wqe_datagram_seg) +
 260                         ((flags & MLX4_IB_QP_LSO) ? 64 : 0);
 261         case IB_QPT_UC:
 262                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 263                         sizeof (struct mlx4_wqe_raddr_seg);
 264         case IB_QPT_RC:
 265                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 266                         sizeof (struct mlx4_wqe_atomic_seg) +
 267                         sizeof (struct mlx4_wqe_raddr_seg);
 268         case IB_QPT_SMI:
 269         case IB_QPT_GSI:
 270                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 271                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 272                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 273                                            MLX4_INLINE_ALIGN) *
 274                               sizeof (struct mlx4_wqe_inline_seg),
 275                               sizeof (struct mlx4_wqe_data_seg)) +
 276                         ALIGN(4 +
 277                               sizeof (struct mlx4_wqe_inline_seg),
 278                               sizeof (struct mlx4_wqe_data_seg));
 279         default:
 280                 return sizeof (struct mlx4_wqe_ctrl_seg);
 281         }
 282 }
 283
 284 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 285                        int is_user, int has_srq, struct mlx4_ib_qp *qp)
 286 {
 287         /* Sanity check RQ size before proceeding */
 288         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
 289             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
 290                 return -EINVAL;
 291
 292         if (has_srq) {
 293                 /* QPs attached to an SRQ should have no RQ */
 294                 if (cap->max_recv_wr)
 295                         return -EINVAL;
 296
 297                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 298         } else {
 299                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 300                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 301                         return -EINVAL;
 302
 303                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 304                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 305                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 306         }
 307
 308         cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 309         cap->max_recv_sge = qp->rq.max_gs;
 310
 311         return 0;
 312 }
 313
 314 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 315                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
 316 {
 317         int s;
 318
 319         /* Sanity check SQ size before proceeding */
 320         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
 321             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
 322             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 323             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 324                 return -EINVAL;
 325
 326         /*
 327          * For MLX transport we need 2 extra S/G entries:
 328          * one for the header and one for the checksum at the end
 329          */
 330         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
 331             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 332                 return -EINVAL;
 333
 334         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 335                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 336                 send_wqe_overhead(type, qp->flags);
 337
 338         if (s > dev->dev->caps.max_sq_desc_sz)
 339                 return -EINVAL;
 340
 341         /*
 342          * Hermon supports shrinking WQEs, such that a single work
 343          * request can include multiple units of 1 << wqe_shift.  This
 344          * way, work requests can differ in size, and do not have to
 345          * be a power of 2 in size, saving memory and speeding up send
 346          * WR posting.  Unfortunately, if we do this then the
 347          * wqe_index field in CQEs can't be used to look up the WR ID
 348          * anymore, so we do this only if selective signaling is off.
 349          *
 350          * Further, on 32-bit platforms, we can't use vmap() to make
 351          * the QP buffer virtually contigious.  Thus we have to use
 352          * constant-sized WRs to make sure a WR is always fully within
 353          * a single page-sized chunk.
 354          *
 355          * Finally, we use NOP work requests to pad the end of the
 356          * work queue, to avoid wrap-around in the middle of WR.  We
 357          * set NEC bit to avoid getting completions with error for
 358          * these NOP WRs, but since NEC is only supported starting
 359          * with firmware 2.2.232, we use constant-sized WRs for older
 360          * firmware.
 361          *
 362          * And, since MLX QPs only support SEND, we use constant-sized
 363          * WRs in this case.
 364          *
 365          * We look for the smallest value of wqe_shift such that the
 366          * resulting number of wqes does not exceed device
 367          * capabilities.
 368          *
 369          * We set WQE size to at least 64 bytes, this way stamping
 370          * invalidates each WQE.
 371          */
 372         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 373             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 374             type != IB_QPT_SMI && type != IB_QPT_GSI)
 375                 qp->sq.wqe_shift = ilog2(64);
 376         else
 377                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 378
 379         for (;;) {
 380                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 381
 382                 /*
 383                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 384                  * allow HW to prefetch.
 385                  */
 386                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 387                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 388                                                     qp->sq_max_wqes_per_wr +
 389                                                     qp->sq_spare_wqes);
 390
 391                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 392                         break;
 393
 394                 if (qp->sq_max_wqes_per_wr <= 1)
 395                         return -EINVAL;
 396
 397                 ++qp->sq.wqe_shift;
 398         }
 399
 400         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 401                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 402                          send_wqe_overhead(type, qp->flags)) /
 403                 sizeof (struct mlx4_wqe_data_seg);
 404
 405         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 406                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 407         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 408                 qp->rq.offset = 0;
 409                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 410         } else {
 411                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 412                 qp->sq.offset = 0;
 413         }
 414
 415         cap->max_send_wr  = qp->sq.max_post =
 416                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 417         cap->max_send_sge = min(qp->sq.max_gs,
 418                                 min(dev->dev->caps.max_sq_sg,
 419                                     dev->dev->caps.max_rq_sg));
 420         /* We don't support inline sends for kernel QPs (yet) */
 421         cap->max_inline_data = 0;
 422
 423         return 0;
 424 }
 425
 426 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 427                             struct mlx4_ib_qp *qp,
 428                             struct mlx4_ib_create_qp *ucmd)
 429 {
 430         /* Sanity check SQ size before proceeding */
 431         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 432             ucmd->log_sq_stride >
 433                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 434             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 435                 return -EINVAL;
 436
 437         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 438         qp->sq.wqe_shift = ucmd->log_sq_stride;
 439
 440         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 441                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 442
 443         return 0;
 444 }
 445
 446 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 447                             struct ib_qp_init_attr *init_attr,
 448                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
 449 {
 450         int err;
 451
 452         mutex_init(&qp->mutex);
 453         spin_lock_init(&qp->sq.lock);
 454         spin_lock_init(&qp->rq.lock);
 455
 456         qp->state        = IB_QPS_RESET;
 457         qp->atomic_rd_en = 0;
 458         qp->resp_depth   = 0;
 459
 460         qp->rq.head         = 0;
 461         qp->rq.tail         = 0;
 462         qp->sq.head         = 0;
 463         qp->sq.tail         = 0;
 464         qp->sq_next_wqe     = 0;
 465
 466         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 467                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 468         else
 469                 qp->sq_signal_bits = 0;
 470
 471         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
 472         if (err)
 473                 goto err;
 474
 475         if (pd->uobject) {
 476                 struct mlx4_ib_create_qp ucmd;
 477
 478                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 479                         err = -EFAULT;
 480                         goto err;
 481                 }
 482
 483                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 484
 485                 err = set_user_sq_size(dev, qp, &ucmd);
 486                 if (err)
 487                         goto err;
 488
 489                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 490                                        qp->buf_size, 0, 0);
 491                 if (IS_ERR(qp->umem)) {
 492                         err = PTR_ERR(qp->umem);
 493                         goto err;
 494                 }
 495
 496                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 497                                     ilog2(qp->umem->page_size), &qp->mtt);
 498                 if (err)
 499                         goto err_buf;
 500
 501                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 502                 if (err)
 503                         goto err_mtt;
 504
 505                 if (!init_attr->srq) {
 506                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 507                                                   ucmd.db_addr, &qp->db);
 508                         if (err)
 509                                 goto err_mtt;
 510                 }
 511         } else {
 512                 qp->sq_no_prefetch = 0;
 513
 514                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 515                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 516
 517                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 518                         qp->flags |= MLX4_IB_QP_LSO;
 519
 520                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
 521                 if (err)
 522                         goto err;
 523
 524                 if (!init_attr->srq) {
 525                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 526                         if (err)
 527                                 goto err;
 528
 529                         *qp->db.db = 0;
 530                 }
 531
 532                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 533                         err = -ENOMEM;
 534                         goto err_db;
 535                 }
 536
 537                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 538                                     &qp->mtt);
 539                 if (err)
 540                         goto err_buf;
 541
 542                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 543                 if (err)
 544                         goto err_mtt;
 545
 546                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 547                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 548
 549                 if (!qp->sq.wrid || !qp->rq.wrid) {
 550                         err = -ENOMEM;
 551                         goto err_wrid;
 552                 }
 553         }
 554
 555         err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
 556         if (err)
 557                 goto err_wrid;
 558
 559         /*
 560          * Hardware wants QPN written in big-endian order (after
 561          * shifting) for send doorbell.  Precompute this value to save
 562          * a little bit when posting sends.
 563          */
 564         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 565
 566         qp->mqp.event = mlx4_ib_qp_event;
 567
 568         return 0;
 569
 570 err_wrid:
 571         if (pd->uobject) {
 572                 if (!init_attr->srq)
 573                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
 574                                               &qp->db);
 575         } else {
 576                 kfree(qp->sq.wrid);
 577                 kfree(qp->rq.wrid);
 578         }
 579
 580 err_mtt:
 581         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 582
 583 err_buf:
 584         if (pd->uobject)
 585                 ib_umem_release(qp->umem);
 586         else
 587                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 588
 589 err_db:
 590         if (!pd->uobject && !init_attr->srq)
 591                 mlx4_db_free(dev->dev, &qp->db);
 592
 593 err:
 594         return err;
 595 }
 596
 597 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 598 {
 599         switch (state) {
 600         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 601         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 602         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 603         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 604         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 605         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 606         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 607         default:                return -1;
 608         }
 609 }
 610
 611 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 612 {
 613         if (send_cq == recv_cq)
 614                 spin_lock_irq(&send_cq->lock);
 615         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 616                 spin_lock_irq(&send_cq->lock);
 617                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 618         } else {
 619                 spin_lock_irq(&recv_cq->lock);
 620                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 621         }
 622 }
 623
 624 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 625 {
 626         if (send_cq == recv_cq)
 627                 spin_unlock_irq(&send_cq->lock);
 628         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 629                 spin_unlock(&recv_cq->lock);
 630                 spin_unlock_irq(&send_cq->lock);
 631         } else {
 632                 spin_unlock(&send_cq->lock);
 633                 spin_unlock_irq(&recv_cq->lock);
 634         }
 635 }
 636
 637 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 638                               int is_user)
 639 {
 640         struct mlx4_ib_cq *send_cq, *recv_cq;
 641
 642         if (qp->state != IB_QPS_RESET)
 643                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 644                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 645                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
 646                                qp->mqp.qpn);
 647
 648         send_cq = to_mcq(qp->ibqp.send_cq);
 649         recv_cq = to_mcq(qp->ibqp.recv_cq);
 650
 651         mlx4_ib_lock_cqs(send_cq, recv_cq);
 652
 653         if (!is_user) {
 654                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 655                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 656                 if (send_cq != recv_cq)
 657                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 658         }
 659
 660         mlx4_qp_remove(dev->dev, &qp->mqp);
 661
 662         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 663
 664         mlx4_qp_free(dev->dev, &qp->mqp);
 665         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 666
 667         if (is_user) {
 668                 if (!qp->ibqp.srq)
 669                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 670                                               &qp->db);
 671                 ib_umem_release(qp->umem);
 672         } else {
 673                 kfree(qp->sq.wrid);
 674                 kfree(qp->rq.wrid);
 675                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 676                 if (!qp->ibqp.srq)
 677                         mlx4_db_free(dev->dev, &qp->db);
 678         }
 679 }
 680
 681 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 682                                 struct ib_qp_init_attr *init_attr,
 683                                 struct ib_udata *udata)
 684 {
 685         struct mlx4_ib_dev *dev = to_mdev(pd->device);
 686         struct mlx4_ib_sqp *sqp;
 687         struct mlx4_ib_qp *qp;
 688         int err;
 689
 690         /*
 691          * We only support LSO and multicast loopback blocking, and
 692          * only for kernel UD QPs.
 693          */
 694         if (init_attr->create_flags & ~(IB_QP_CREATE_IPOIB_UD_LSO |
 695                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
 696                 return ERR_PTR(-EINVAL);
 697
 698         if (init_attr->create_flags &&
 699             (pd->uobject || init_attr->qp_type != IB_QPT_UD))
 700                 return ERR_PTR(-EINVAL);
 701
 702         switch (init_attr->qp_type) {
 703         case IB_QPT_RC:
 704         case IB_QPT_UC:
 705         case IB_QPT_UD:
 706         {
 707                 qp = kmalloc(sizeof *qp, GFP_KERNEL);
 708                 if (!qp)
 709                         return ERR_PTR(-ENOMEM);
 710
 711                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
 712                 if (err) {
 713                         kfree(qp);
 714                         return ERR_PTR(err);
 715                 }
 716
 717                 qp->ibqp.qp_num = qp->mqp.qpn;
 718
 719                 break;
 720         }
 721         case IB_QPT_SMI:
 722         case IB_QPT_GSI:
 723         {
 724                 /* Userspace is not allowed to create special QPs: */
 725                 if (pd->uobject)
 726                         return ERR_PTR(-EINVAL);
 727
 728                 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
 729                 if (!sqp)
 730                         return ERR_PTR(-ENOMEM);
 731
 732                 qp = &sqp->qp;
 733
 734                 err = create_qp_common(dev, pd, init_attr, udata,
 735                                        dev->dev->caps.sqp_start +
 736                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 737                                        init_attr->port_num - 1,
 738                                        qp);
 739                 if (err) {
 740                         kfree(sqp);
 741                         return ERR_PTR(err);
 742                 }
 743
 744                 qp->port        = init_attr->port_num;
 745                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
 746
 747                 break;
 748         }
 749         default:
 750                 /* Don't support raw QPs */
 751                 return ERR_PTR(-EINVAL);
 752         }
 753
 754         return &qp->ibqp;
 755 }
 756
 757 int mlx4_ib_destroy_qp(struct ib_qp *qp)
 758 {
 759         struct mlx4_ib_dev *dev = to_mdev(qp->device);
 760         struct mlx4_ib_qp *mqp = to_mqp(qp);
 761
 762         if (is_qp0(dev, mqp))
 763                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
 764
 765         destroy_qp_common(dev, mqp, !!qp->pd->uobject);
 766
 767         if (is_sqp(dev, mqp))
 768                 kfree(to_msqp(mqp));
 769         else
 770                 kfree(mqp);
 771
 772         return 0;
 773 }
 774
 775 static int to_mlx4_st(enum ib_qp_type type)
 776 {
 777         switch (type) {
 778         case IB_QPT_RC:         return MLX4_QP_ST_RC;
 779         case IB_QPT_UC:         return MLX4_QP_ST_UC;
 780         case IB_QPT_UD:         return MLX4_QP_ST_UD;
 781         case IB_QPT_SMI:
 782         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
 783         default:                return -1;
 784         }
 785 }
 786
 787 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
 788                                    int attr_mask)
 789 {
 790         u8 dest_rd_atomic;
 791         u32 access_flags;
 792         u32 hw_access_flags = 0;
 793
 794         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 795                 dest_rd_atomic = attr->max_dest_rd_atomic;
 796         else
 797                 dest_rd_atomic = qp->resp_depth;
 798
 799         if (attr_mask & IB_QP_ACCESS_FLAGS)
 800                 access_flags = attr->qp_access_flags;
 801         else
 802                 access_flags = qp->atomic_rd_en;
 803
 804         if (!dest_rd_atomic)
 805                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 806
 807         if (access_flags & IB_ACCESS_REMOTE_READ)
 808                 hw_access_flags |= MLX4_QP_BIT_RRE;
 809         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 810                 hw_access_flags |= MLX4_QP_BIT_RAE;
 811         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 812                 hw_access_flags |= MLX4_QP_BIT_RWE;
 813
 814         return cpu_to_be32(hw_access_flags);
 815 }
 816
 817 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
 818                             int attr_mask)
 819 {
 820         if (attr_mask & IB_QP_PKEY_INDEX)
 821                 sqp->pkey_index = attr->pkey_index;
 822         if (attr_mask & IB_QP_QKEY)
 823                 sqp->qkey = attr->qkey;
 824         if (attr_mask & IB_QP_SQ_PSN)
 825                 sqp->send_psn = attr->sq_psn;
 826 }
 827
 828 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
 829 {
 830         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
 831 }
 832
 833 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
 834                          struct mlx4_qp_path *path, u8 port)
 835 {
 836         path->grh_mylmc     = ah->src_path_bits & 0x7f;
 837         path->rlid          = cpu_to_be16(ah->dlid);
 838         if (ah->static_rate) {
 839                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
 840                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
 841                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
 842                         --path->static_rate;
 843         } else
 844                 path->static_rate = 0;
 845         path->counter_index = 0xff;
 846
 847         if (ah->ah_flags & IB_AH_GRH) {
 848                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
 849                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
 850                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
 851                         return -1;
 852                 }
 853
 854                 path->grh_mylmc |= 1 << 7;
 855                 path->mgid_index = ah->grh.sgid_index;
 856                 path->hop_limit  = ah->grh.hop_limit;
 857                 path->tclass_flowlabel =
 858                         cpu_to_be32((ah->grh.traffic_class << 20) |
 859                                     (ah->grh.flow_label));
 860                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 861         }
 862
 863         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 864                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
 865
 866         return 0;
 867 }
 868
 869 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
 870                                const struct ib_qp_attr *attr, int attr_mask,
 871                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
 872 {
 873         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 874         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 875         struct mlx4_qp_context *context;
 876         enum mlx4_qp_optpar optpar = 0;
 877         int sqd_event;
 878         int err = -EINVAL;
 879
 880         context = kzalloc(sizeof *context, GFP_KERNEL);
 881         if (!context)
 882                 return -ENOMEM;
 883
 884         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
 885                                      (to_mlx4_st(ibqp->qp_type) << 16));
 886         context->flags     |= cpu_to_be32(1 << 8); /* DE? */
 887
 888         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 889                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 890         else {
 891                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
 892                 switch (attr->path_mig_state) {
 893                 case IB_MIG_MIGRATED:
 894                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 895                         break;
 896                 case IB_MIG_REARM:
 897                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
 898                         break;
 899                 case IB_MIG_ARMED:
 900                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
 901                         break;
 902                 }
 903         }
 904
 905         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
 906                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 907         else if (ibqp->qp_type == IB_QPT_UD) {
 908                 if (qp->flags & MLX4_IB_QP_LSO)
 909                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
 910                                               ilog2(dev->dev->caps.max_gso_sz);
 911                 else
 912                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 913         } else if (attr_mask & IB_QP_PATH_MTU) {
 914                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
 915                         printk(KERN_ERR "path MTU (%u) is invalid\n",
 916                                attr->path_mtu);
 917                         goto out;
 918                 }
 919                 context->mtu_msgmax = (attr->path_mtu << 5) |
 920                         ilog2(dev->dev->caps.max_msg_sz);
 921         }
 922
 923         if (qp->rq.wqe_cnt)
 924                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
 925         context->rq_size_stride |= qp->rq.wqe_shift - 4;
 926
 927         if (qp->sq.wqe_cnt)
 928                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
 929         context->sq_size_stride |= qp->sq.wqe_shift - 4;
 930
 931         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
 932                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
 933
 934         if (qp->ibqp.uobject)
 935                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
 936         else
 937                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
 938
 939         if (attr_mask & IB_QP_DEST_QPN)
 940                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 941
 942         if (attr_mask & IB_QP_PORT) {
 943                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
 944                     !(attr_mask & IB_QP_AV)) {
 945                         mlx4_set_sched(&context->pri_path, attr->port_num);
 946                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
 947                 }
 948         }
 949
 950         if (attr_mask & IB_QP_PKEY_INDEX) {
 951                 context->pri_path.pkey_index = attr->pkey_index;
 952                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
 953         }
 954
 955         if (attr_mask & IB_QP_AV) {
 956                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
 957                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 958                         goto out;
 959
 960                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
 961                            MLX4_QP_OPTPAR_SCHED_QUEUE);
 962         }
 963
 964         if (attr_mask & IB_QP_TIMEOUT) {
 965                 context->pri_path.ackto = attr->timeout << 3;
 966                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
 967         }
 968
 969         if (attr_mask & IB_QP_ALT_PATH) {
 970                 if (attr->alt_port_num == 0 ||
 971                     attr->alt_port_num > dev->dev->caps.num_ports)
 972                         goto out;
 973
 974                 if (attr->alt_pkey_index >=
 975                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
 976                         goto out;
 977
 978                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
 979                                   attr->alt_port_num))
 980                         goto out;
 981
 982                 context->alt_path.pkey_index = attr->alt_pkey_index;
 983                 context->alt_path.ackto = attr->alt_timeout << 3;
 984                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
 985         }
 986
 987         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
 988         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
 989
 990         if (attr_mask & IB_QP_RNR_RETRY) {
 991                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
 992                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
 993         }
 994
 995         if (attr_mask & IB_QP_RETRY_CNT) {
 996                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 997                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
 998         }
 999
1000         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1001                 if (attr->max_rd_atomic)
1002                         context->params1 |=
1003                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1004                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1005         }
1006
1007         if (attr_mask & IB_QP_SQ_PSN)
1008                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1009
1010         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
1011
1012         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1013                 if (attr->max_dest_rd_atomic)
1014                         context->params2 |=
1015                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1016                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1017         }
1018
1019         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1020                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1021                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1022         }
1023
1024         if (ibqp->srq)
1025                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1026
1027         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1028                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1029                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1030         }
1031         if (attr_mask & IB_QP_RQ_PSN)
1032                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1033
1034         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
1035
1036         if (attr_mask & IB_QP_QKEY) {
1037                 context->qkey = cpu_to_be32(attr->qkey);
1038                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1039         }
1040
1041         if (ibqp->srq)
1042                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1043
1044         if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1045                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1046
1047         if (cur_state == IB_QPS_INIT &&
1048             new_state == IB_QPS_RTR  &&
1049             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1050              ibqp->qp_type == IB_QPT_UD)) {
1051                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1052                 if (is_qp0(dev, qp))
1053                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1054                 else
1055                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1056         }
1057
1058         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1059             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1060                 sqd_event = 1;
1061         else
1062                 sqd_event = 0;
1063
1064         /*
1065          * Before passing a kernel QP to the HW, make sure that the
1066          * ownership bits of the send queue are set and the SQ
1067          * headroom is stamped so that the hardware doesn't start
1068          * processing stale work requests.
1069          */
1070         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1071                 struct mlx4_wqe_ctrl_seg *ctrl;
1072                 int i;
1073
1074                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1075                         ctrl = get_send_wqe(qp, i);
1076                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1077                         if (qp->sq_max_wqes_per_wr == 1)
1078                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1079
1080                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1081                 }
1082         }
1083
1084         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1085                              to_mlx4_state(new_state), context, optpar,
1086                              sqd_event, &qp->mqp);
1087         if (err)
1088                 goto out;
1089
1090         qp->state = new_state;
1091
1092         if (attr_mask & IB_QP_ACCESS_FLAGS)
1093                 qp->atomic_rd_en = attr->qp_access_flags;
1094         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1095                 qp->resp_depth = attr->max_dest_rd_atomic;
1096         if (attr_mask & IB_QP_PORT)
1097                 qp->port = attr->port_num;
1098         if (attr_mask & IB_QP_ALT_PATH)
1099                 qp->alt_port = attr->alt_port_num;
1100
1101         if (is_sqp(dev, qp))
1102                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1103
1104         /*
1105          * If we moved QP0 to RTR, bring the IB link up; if we moved
1106          * QP0 to RESET or ERROR, bring the link back down.
1107          */
1108         if (is_qp0(dev, qp)) {
1109                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1110                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1111                                 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1112                                        qp->port);
1113
1114                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1115                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1116                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1117         }
1118
1119         /*
1120          * If we moved a kernel QP to RESET, clean up all old CQ
1121          * entries and reinitialize the QP.
1122          */
1123         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1124                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
1125                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
1126                 if (ibqp->send_cq != ibqp->recv_cq)
1127                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
1128
1129                 qp->rq.head = 0;
1130                 qp->rq.tail = 0;
1131                 qp->sq.head = 0;
1132                 qp->sq.tail = 0;
1133                 qp->sq_next_wqe = 0;
1134                 if (!ibqp->srq)
1135                         *qp->db.db  = 0;
1136         }
1137
1138 out:
1139         kfree(context);
1140         return err;
1141 }
1142
1143 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1144                       int attr_mask, struct ib_udata *udata)
1145 {
1146         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1147         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1148         enum ib_qp_state cur_state, new_state;
1149         int err = -EINVAL;
1150
1151         mutex_lock(&qp->mutex);
1152
1153         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1154         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1155
1156         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1157                 goto out;
1158
1159         if ((attr_mask & IB_QP_PORT) &&
1160             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1161                 goto out;
1162         }
1163
1164         if (attr_mask & IB_QP_PKEY_INDEX) {
1165                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1166                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1167                         goto out;
1168         }
1169
1170         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1171             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1172                 goto out;
1173         }
1174
1175         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1176             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1177                 goto out;
1178         }
1179
1180         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1181                 err = 0;
1182                 goto out;
1183         }
1184
1185         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1186
1187 out:
1188         mutex_unlock(&qp->mutex);
1189         return err;
1190 }
1191
1192 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1193                             void *wqe, unsigned *mlx_seg_len)
1194 {
1195         struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1196         struct mlx4_wqe_mlx_seg *mlx = wqe;
1197         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1198         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1199         u16 pkey;
1200         int send_size;
1201         int header_size;
1202         int spc;
1203         int i;
1204
1205         send_size = 0;
1206         for (i = 0; i < wr->num_sge; ++i)
1207                 send_size += wr->sg_list[i].length;
1208
1209         ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1210
1211         sqp->ud_header.lrh.service_level   =
1212                 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1213         sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1214         sqp->ud_header.lrh.source_lid      = cpu_to_be16(ah->av.g_slid & 0x7f);
1215         if (mlx4_ib_ah_grh_present(ah)) {
1216                 sqp->ud_header.grh.traffic_class =
1217                         (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1218                 sqp->ud_header.grh.flow_label    =
1219                         ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1220                 sqp->ud_header.grh.hop_limit     = ah->av.hop_limit;
1221                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1222                                   ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1223                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1224                        ah->av.dgid, 16);
1225         }
1226
1227         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1228         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1229                                   (sqp->ud_header.lrh.destination_lid ==
1230                                    IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1231                                   (sqp->ud_header.lrh.service_level << 8));
1232         mlx->rlid   = sqp->ud_header.lrh.destination_lid;
1233
1234         switch (wr->opcode) {
1235         case IB_WR_SEND:
1236                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1237                 sqp->ud_header.immediate_present = 0;
1238                 break;
1239         case IB_WR_SEND_WITH_IMM:
1240                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1241                 sqp->ud_header.immediate_present = 1;
1242                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
1243                 break;
1244         default:
1245                 return -EINVAL;
1246         }
1247
1248         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1249         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1250                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1251         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1252         if (!sqp->qp.ibqp.qp_num)
1253                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1254         else
1255                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1256         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1257         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1258         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1259         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1260                                                sqp->qkey : wr->wr.ud.remote_qkey);
1261         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1262
1263         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1264
1265         if (0) {
1266                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1267                 for (i = 0; i < header_size / 4; ++i) {
1268                         if (i % 8 == 0)
1269                                 printk("  [%02x] ", i * 4);
1270                         printk(" %08x",
1271                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1272                         if ((i + 1) % 8 == 0)
1273                                 printk("\n");
1274                 }
1275                 printk("\n");
1276         }
1277
1278         /*
1279          * Inline data segments may not cross a 64 byte boundary.  If
1280          * our UD header is bigger than the space available up to the
1281          * next 64 byte boundary in the WQE, use two inline data
1282          * segments to hold the UD header.
1283          */
1284         spc = MLX4_INLINE_ALIGN -
1285                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1286         if (header_size <= spc) {
1287                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1288                 memcpy(inl + 1, sqp->header_buf, header_size);
1289                 i = 1;
1290         } else {
1291                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1292                 memcpy(inl + 1, sqp->header_buf, spc);
1293
1294                 inl = (void *) (inl + 1) + spc;
1295                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1296                 /*
1297                  * Need a barrier here to make sure all the data is
1298                  * visible before the byte_count field is set.
1299                  * Otherwise the HCA prefetcher could grab the 64-byte
1300                  * chunk with this inline segment and get a valid (!=
1301                  * 0xffffffff) byte count but stale data, and end up
1302                  * generating a packet with bad headers.
1303                  *
1304                  * The first inline segment's byte_count field doesn't
1305                  * need a barrier, because it comes after a
1306                  * control/MLX segment and therefore is at an offset
1307                  * of 16 mod 64.
1308                  */
1309                 wmb();
1310                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1311                 i = 2;
1312         }
1313
1314         *mlx_seg_len =
1315                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1316         return 0;
1317 }
1318
1319 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1320 {
1321         unsigned cur;
1322         struct mlx4_ib_cq *cq;
1323
1324         cur = wq->head - wq->tail;
1325         if (likely(cur + nreq < wq->max_post))
1326                 return 0;
1327
1328         cq = to_mcq(ib_cq);
1329         spin_lock(&cq->lock);
1330         cur = wq->head - wq->tail;
1331         spin_unlock(&cq->lock);
1332
1333         return cur + nreq >= wq->max_post;
1334 }
1335
1336 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1337                                           u64 remote_addr, u32 rkey)
1338 {
1339         rseg->raddr    = cpu_to_be64(remote_addr);
1340         rseg->rkey     = cpu_to_be32(rkey);
1341         rseg->reserved = 0;
1342 }
1343
1344 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1345 {
1346         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1347                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1348                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
1349         } else {
1350                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1351                 aseg->compare  = 0;
1352         }
1353
1354 }
1355
1356 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1357                              struct ib_send_wr *wr)
1358 {
1359         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1360         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1361         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1362 }
1363
1364 static void set_mlx_icrc_seg(void *dseg)
1365 {
1366         u32 *t = dseg;
1367         struct mlx4_wqe_inline_seg *iseg = dseg;
1368
1369         t[1] = 0;
1370
1371         /*
1372          * Need a barrier here before writing the byte_count field to
1373          * make sure that all the data is visible before the
1374          * byte_count field is set.  Otherwise, if the segment begins
1375          * a new cacheline, the HCA prefetcher could grab the 64-byte
1376          * chunk and get a valid (!= * 0xffffffff) byte count but
1377          * stale data, and end up sending the wrong data.
1378          */
1379         wmb();
1380
1381         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1382 }
1383
1384 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1385 {
1386         dseg->lkey       = cpu_to_be32(sg->lkey);
1387         dseg->addr       = cpu_to_be64(sg->addr);
1388
1389         /*
1390          * Need a barrier here before writing the byte_count field to
1391          * make sure that all the data is visible before the
1392          * byte_count field is set.  Otherwise, if the segment begins
1393          * a new cacheline, the HCA prefetcher could grab the 64-byte
1394          * chunk and get a valid (!= * 0xffffffff) byte count but
1395          * stale data, and end up sending the wrong data.
1396          */
1397         wmb();
1398
1399         dseg->byte_count = cpu_to_be32(sg->length);
1400 }
1401
1402 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1403 {
1404         dseg->byte_count = cpu_to_be32(sg->length);
1405         dseg->lkey       = cpu_to_be32(sg->lkey);
1406         dseg->addr       = cpu_to_be64(sg->addr);
1407 }
1408
1409 static int build_lso_seg(struct mlx4_lso_seg *wqe, struct ib_send_wr *wr,
1410                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len)
1411 {
1412         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
1413
1414         /*
1415          * This is a temporary limitation and will be removed in
1416          * a forthcoming FW release:
1417          */
1418         if (unlikely(halign > 64))
1419                 return -EINVAL;
1420
1421         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
1422                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
1423                 return -EINVAL;
1424
1425         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
1426
1427         /* make sure LSO header is written before overwriting stamping */
1428         wmb();
1429
1430         wqe->mss_hdr_size = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
1431                                         wr->wr.ud.hlen);
1432
1433         *lso_seg_len = halign;
1434         return 0;
1435 }
1436
1437 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1438                       struct ib_send_wr **bad_wr)
1439 {
1440         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1441         void *wqe;
1442         struct mlx4_wqe_ctrl_seg *ctrl;
1443         struct mlx4_wqe_data_seg *dseg;
1444         unsigned long flags;
1445         int nreq;
1446         int err = 0;
1447         unsigned ind;
1448         int uninitialized_var(stamp);
1449         int uninitialized_var(size);
1450         unsigned uninitialized_var(seglen);
1451         int i;
1452
1453         spin_lock_irqsave(&qp->sq.lock, flags);
1454
1455         ind = qp->sq_next_wqe;
1456
1457         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1458                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1459                         err = -ENOMEM;
1460                         *bad_wr = wr;
1461                         goto out;
1462                 }
1463
1464                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1465                         err = -EINVAL;
1466                         *bad_wr = wr;
1467                         goto out;
1468                 }
1469
1470                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1471                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1472
1473                 ctrl->srcrb_flags =
1474                         (wr->send_flags & IB_SEND_SIGNALED ?
1475                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1476                         (wr->send_flags & IB_SEND_SOLICITED ?
1477                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1478                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
1479                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1480                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
1481                         qp->sq_signal_bits;
1482
1483                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1484                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1485                         ctrl->imm = wr->ex.imm_data;
1486                 else
1487                         ctrl->imm = 0;
1488
1489                 wqe += sizeof *ctrl;
1490                 size = sizeof *ctrl / 16;
1491
1492                 switch (ibqp->qp_type) {
1493                 case IB_QPT_RC:
1494                 case IB_QPT_UC:
1495                         switch (wr->opcode) {
1496                         case IB_WR_ATOMIC_CMP_AND_SWP:
1497                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1498                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1499                                               wr->wr.atomic.rkey);
1500                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1501
1502                                 set_atomic_seg(wqe, wr);
1503                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1504
1505                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1506                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1507
1508                                 break;
1509
1510                         case IB_WR_RDMA_READ:
1511                         case IB_WR_RDMA_WRITE:
1512                         case IB_WR_RDMA_WRITE_WITH_IMM:
1513                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1514                                               wr->wr.rdma.rkey);
1515                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1516                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1517                                 break;
1518
1519                         default:
1520                                 /* No extra segments required for sends */
1521                                 break;
1522                         }
1523                         break;
1524
1525                 case IB_QPT_UD:
1526                         set_datagram_seg(wqe, wr);
1527                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1528                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1529
1530                         if (wr->opcode == IB_WR_LSO) {
1531                                 err = build_lso_seg(wqe, wr, qp, &seglen);
1532                                 if (unlikely(err)) {
1533                                         *bad_wr = wr;
1534                                         goto out;
1535                                 }
1536                                 wqe  += seglen;
1537                                 size += seglen / 16;
1538                         }
1539                         break;
1540
1541                 case IB_QPT_SMI:
1542                 case IB_QPT_GSI:
1543                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
1544                         if (unlikely(err)) {
1545                                 *bad_wr = wr;
1546                                 goto out;
1547                         }
1548                         wqe  += seglen;
1549                         size += seglen / 16;
1550                         break;
1551
1552                 default:
1553                         break;
1554                 }
1555
1556                 /*
1557                  * Write data segments in reverse order, so as to
1558                  * overwrite cacheline stamp last within each
1559                  * cacheline.  This avoids issues with WQE
1560                  * prefetching.
1561                  */
1562
1563                 dseg = wqe;
1564                 dseg += wr->num_sge - 1;
1565                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1566
1567                 /* Add one more inline data segment for ICRC for MLX sends */
1568                 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1569                              qp->ibqp.qp_type == IB_QPT_GSI)) {
1570                         set_mlx_icrc_seg(dseg + 1);
1571                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1572                 }
1573
1574                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1575                         set_data_seg(dseg, wr->sg_list + i);
1576
1577                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1578                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1579
1580                 /*
1581                  * Make sure descriptor is fully written before
1582                  * setting ownership bit (because HW can start
1583                  * executing as soon as we do).
1584                  */
1585                 wmb();
1586
1587                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1588                         err = -EINVAL;
1589                         goto out;
1590                 }
1591
1592                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1593                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1594
1595                 stamp = ind + qp->sq_spare_wqes;
1596                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1597
1598                 /*
1599                  * We can improve latency by not stamping the last
1600                  * send queue WQE until after ringing the doorbell, so
1601                  * only stamp here if there are still more WQEs to post.
1602                  *
1603                  * Same optimization applies to padding with NOP wqe
1604                  * in case of WQE shrinking (used to prevent wrap-around
1605                  * in the middle of WR).
1606                  */
1607                 if (wr->next) {
1608                         stamp_send_wqe(qp, stamp, size * 16);
1609                         ind = pad_wraparound(qp, ind);
1610                 }
1611
1612         }
1613
1614 out:
1615         if (likely(nreq)) {
1616                 qp->sq.head += nreq;
1617
1618                 /*
1619                  * Make sure that descriptors are written before
1620                  * doorbell record.
1621                  */
1622                 wmb();
1623
1624                 writel(qp->doorbell_qpn,
1625                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1626
1627                 /*
1628                  * Make sure doorbells don't leak out of SQ spinlock
1629                  * and reach the HCA out of order.
1630                  */
1631                 mmiowb();
1632
1633                 stamp_send_wqe(qp, stamp, size * 16);
1634
1635                 ind = pad_wraparound(qp, ind);
1636                 qp->sq_next_wqe = ind;
1637         }
1638
1639         spin_unlock_irqrestore(&qp->sq.lock, flags);
1640
1641         return err;
1642 }
1643
1644 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1645                       struct ib_recv_wr **bad_wr)
1646 {
1647         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1648         struct mlx4_wqe_data_seg *scat;
1649         unsigned long flags;
1650         int err = 0;
1651         int nreq;
1652         int ind;
1653         int i;
1654
1655         spin_lock_irqsave(&qp->rq.lock, flags);
1656
1657         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1658
1659         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1660                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1661                         err = -ENOMEM;
1662                         *bad_wr = wr;
1663                         goto out;
1664                 }
1665
1666                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1667                         err = -EINVAL;
1668                         *bad_wr = wr;
1669                         goto out;
1670                 }
1671
1672                 scat = get_recv_wqe(qp, ind);
1673
1674                 for (i = 0; i < wr->num_sge; ++i)
1675                         __set_data_seg(scat + i, wr->sg_list + i);
1676
1677                 if (i < qp->rq.max_gs) {
1678                         scat[i].byte_count = 0;
1679                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1680                         scat[i].addr       = 0;
1681                 }
1682
1683                 qp->rq.wrid[ind] = wr->wr_id;
1684
1685                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1686         }
1687
1688 out:
1689         if (likely(nreq)) {
1690                 qp->rq.head += nreq;
1691
1692                 /*
1693                  * Make sure that descriptors are written before
1694                  * doorbell record.
1695                  */
1696                 wmb();
1697
1698                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1699         }
1700
1701         spin_unlock_irqrestore(&qp->rq.lock, flags);
1702
1703         return err;
1704 }
1705
1706 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1707 {
1708         switch (mlx4_state) {
1709         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
1710         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
1711         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
1712         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
1713         case MLX4_QP_STATE_SQ_DRAINING:
1714         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
1715         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
1716         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
1717         default:                     return -1;
1718         }
1719 }
1720
1721 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1722 {
1723         switch (mlx4_mig_state) {
1724         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
1725         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
1726         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
1727         default: return -1;
1728         }
1729 }
1730
1731 static int to_ib_qp_access_flags(int mlx4_flags)
1732 {
1733         int ib_flags = 0;
1734
1735         if (mlx4_flags & MLX4_QP_BIT_RRE)
1736                 ib_flags |= IB_ACCESS_REMOTE_READ;
1737         if (mlx4_flags & MLX4_QP_BIT_RWE)
1738                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1739         if (mlx4_flags & MLX4_QP_BIT_RAE)
1740                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1741
1742         return ib_flags;
1743 }
1744
1745 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1746                                 struct mlx4_qp_path *path)
1747 {
1748         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
1749         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
1750
1751         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1752                 return;
1753
1754         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
1755         ib_ah_attr->sl            = (path->sched_queue >> 2) & 0xf;
1756         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1757         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
1758         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1759         if (ib_ah_attr->ah_flags) {
1760                 ib_ah_attr->grh.sgid_index = path->mgid_index;
1761                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
1762                 ib_ah_attr->grh.traffic_class =
1763                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1764                 ib_ah_attr->grh.flow_label =
1765                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
1766                 memcpy(ib_ah_attr->grh.dgid.raw,
1767                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1768         }
1769 }
1770
1771 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1772                      struct ib_qp_init_attr *qp_init_attr)
1773 {
1774         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1775         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1776         struct mlx4_qp_context context;
1777         int mlx4_state;
1778         int err = 0;
1779
1780         mutex_lock(&qp->mutex);
1781
1782         if (qp->state == IB_QPS_RESET) {
1783                 qp_attr->qp_state = IB_QPS_RESET;
1784                 goto done;
1785         }
1786
1787         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
1788         if (err) {
1789                 err = -EINVAL;
1790                 goto out;
1791         }
1792
1793         mlx4_state = be32_to_cpu(context.flags) >> 28;
1794
1795         qp->state                    = to_ib_qp_state(mlx4_state);
1796         qp_attr->qp_state            = qp->state;
1797         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
1798         qp_attr->path_mig_state      =
1799                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1800         qp_attr->qkey                = be32_to_cpu(context.qkey);
1801         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1802         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
1803         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
1804         qp_attr->qp_access_flags     =
1805                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1806
1807         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1808                 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1809                 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1810                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1811                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
1812         }
1813
1814         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1815         if (qp_attr->qp_state == IB_QPS_INIT)
1816                 qp_attr->port_num = qp->port;
1817         else
1818                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
1819
1820         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1821         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1822
1823         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1824
1825         qp_attr->max_dest_rd_atomic =
1826                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1827         qp_attr->min_rnr_timer      =
1828                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1829         qp_attr->timeout            = context.pri_path.ackto >> 3;
1830         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
1831         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
1832         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
1833
1834 done:
1835         qp_attr->cur_qp_state        = qp_attr->qp_state;
1836         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
1837         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
1838
1839         if (!ibqp->uobject) {
1840                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
1841                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1842         } else {
1843                 qp_attr->cap.max_send_wr  = 0;
1844                 qp_attr->cap.max_send_sge = 0;
1845         }
1846
1847         /*
1848          * We don't support inline sends for kernel QPs (yet), and we
1849          * don't know what userspace's value should be.
1850          */
1851         qp_attr->cap.max_inline_data = 0;
1852
1853         qp_init_attr->cap            = qp_attr->cap;
1854
1855         qp_init_attr->create_flags = 0;
1856         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1857                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
1858
1859         if (qp->flags & MLX4_IB_QP_LSO)
1860                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
1861
1862 out:
1863         mutex_unlock(&qp->mutex);
1864         return err;
1865 }
1866