SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <rdma/ib_cache.h>
  34 #include <rdma/ib_pack.h>
  35
  36 #include <linux/mlx4/qp.h>
  37
  38 #include "mlx4_ib.h"
  39 #include "user.h"
  40
  41 enum {
  42         MLX4_IB_ACK_REQ_FREQ    = 8,
  43 };
  44
  45 enum {
  46         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  47         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
  48 };
  49
  50 enum {
  51         /*
  52          * Largest possible UD header: send with GRH and immediate data.
  53          */
  54         MLX4_IB_UD_HEADER_SIZE          = 72
  55 };
  56
  57 struct mlx4_ib_sqp {
  58         struct mlx4_ib_qp       qp;
  59         int                     pkey_index;
  60         u32                     qkey;
  61         u32                     send_psn;
  62         struct ib_ud_header     ud_header;
  63         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  64 };
  65
  66 static const __be32 mlx4_ib_opcode[] = {
  67         [IB_WR_SEND]                    = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
  68         [IB_WR_SEND_WITH_IMM]           = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  69         [IB_WR_RDMA_WRITE]              = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  70         [IB_WR_RDMA_WRITE_WITH_IMM]     = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  71         [IB_WR_RDMA_READ]               = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  72         [IB_WR_ATOMIC_CMP_AND_SWP]      = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  73         [IB_WR_ATOMIC_FETCH_AND_ADD]    = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  74 };
  75
  76 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
  77 {
  78         return container_of(mqp, struct mlx4_ib_sqp, qp);
  79 }
  80
  81 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  82 {
  83         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  84                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
  85 }
  86
  87 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  88 {
  89         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  90                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
  91 }
  92
  93 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
  94 {
  95         if (qp->buf.nbufs == 1)
  96                 return qp->buf.u.direct.buf + offset;
  97         else
  98                 return qp->buf.u.page_list[offset >> PAGE_SHIFT].buf +
  99                         (offset & (PAGE_SIZE - 1));
 100 }
 101
 102 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 103 {
 104         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 105 }
 106
 107 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 108 {
 109         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 110 }
 111
 112 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 113 {
 114         struct ib_event event;
 115         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 116
 117         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 118                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 119
 120         if (ibqp->event_handler) {
 121                 event.device     = ibqp->device;
 122                 event.element.qp = ibqp;
 123                 switch (type) {
 124                 case MLX4_EVENT_TYPE_PATH_MIG:
 125                         event.event = IB_EVENT_PATH_MIG;
 126                         break;
 127                 case MLX4_EVENT_TYPE_COMM_EST:
 128                         event.event = IB_EVENT_COMM_EST;
 129                         break;
 130                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 131                         event.event = IB_EVENT_SQ_DRAINED;
 132                         break;
 133                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 134                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 135                         break;
 136                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 137                         event.event = IB_EVENT_QP_FATAL;
 138                         break;
 139                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 140                         event.event = IB_EVENT_PATH_MIG_ERR;
 141                         break;
 142                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 143                         event.event = IB_EVENT_QP_REQ_ERR;
 144                         break;
 145                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 146                         event.event = IB_EVENT_QP_ACCESS_ERR;
 147                         break;
 148                 default:
 149                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
 150                                "on QP %06x\n", type, qp->qpn);
 151                         return;
 152                 }
 153
 154                 ibqp->event_handler(&event, ibqp->qp_context);
 155         }
 156 }
 157
 158 static int send_wqe_overhead(enum ib_qp_type type)
 159 {
 160         /*
 161          * UD WQEs must have a datagram segment.
 162          * RC and UC WQEs might have a remote address segment.
 163          * MLX WQEs need two extra inline data segments (for the UD
 164          * header and space for the ICRC).
 165          */
 166         switch (type) {
 167         case IB_QPT_UD:
 168                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 169                         sizeof (struct mlx4_wqe_datagram_seg);
 170         case IB_QPT_UC:
 171                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 172                         sizeof (struct mlx4_wqe_raddr_seg);
 173         case IB_QPT_RC:
 174                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 175                         sizeof (struct mlx4_wqe_atomic_seg) +
 176                         sizeof (struct mlx4_wqe_raddr_seg);
 177         case IB_QPT_SMI:
 178         case IB_QPT_GSI:
 179                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 180                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 181                               sizeof (struct mlx4_wqe_inline_seg),
 182                               sizeof (struct mlx4_wqe_data_seg)) +
 183                         ALIGN(4 +
 184                               sizeof (struct mlx4_wqe_inline_seg),
 185                               sizeof (struct mlx4_wqe_data_seg));
 186         default:
 187                 return sizeof (struct mlx4_wqe_ctrl_seg);
 188         }
 189 }
 190
 191 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 192                        struct mlx4_ib_qp *qp)
 193 {
 194         /* Sanity check RQ size before proceeding */
 195         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
 196             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
 197                 return -EINVAL;
 198
 199         qp->rq.max = cap->max_recv_wr ? roundup_pow_of_two(cap->max_recv_wr) : 0;
 200
 201         qp->rq.wqe_shift = ilog2(roundup_pow_of_two(cap->max_recv_sge *
 202                                                     sizeof (struct mlx4_wqe_data_seg)));
 203         qp->rq.max_gs    = (1 << qp->rq.wqe_shift) / sizeof (struct mlx4_wqe_data_seg);
 204
 205         cap->max_recv_wr  = qp->rq.max;
 206         cap->max_recv_sge = qp->rq.max_gs;
 207
 208         return 0;
 209 }
 210
 211 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 212                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
 213 {
 214         /* Sanity check SQ size before proceeding */
 215         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
 216             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
 217             cap->max_inline_data + send_wqe_overhead(type) +
 218             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 219                 return -EINVAL;
 220
 221         /*
 222          * For MLX transport we need 2 extra S/G entries:
 223          * one for the header and one for the checksum at the end
 224          */
 225         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
 226             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 227                 return -EINVAL;
 228
 229         qp->sq.max = cap->max_send_wr ? roundup_pow_of_two(cap->max_send_wr) : 1;
 230
 231         qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
 232                                                         sizeof (struct mlx4_wqe_data_seg),
 233                                                         cap->max_inline_data +
 234                                                         sizeof (struct mlx4_wqe_inline_seg)) +
 235                                                     send_wqe_overhead(type)));
 236         qp->sq.max_gs    = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
 237                 sizeof (struct mlx4_wqe_data_seg);
 238
 239         qp->buf_size = (qp->rq.max << qp->rq.wqe_shift) +
 240                 (qp->sq.max << qp->sq.wqe_shift);
 241         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 242                 qp->rq.offset = 0;
 243                 qp->sq.offset = qp->rq.max << qp->rq.wqe_shift;
 244         } else {
 245                 qp->rq.offset = qp->sq.max << qp->sq.wqe_shift;
 246                 qp->sq.offset = 0;
 247         }
 248
 249         cap->max_send_wr     = qp->sq.max;
 250         cap->max_send_sge    = qp->sq.max_gs;
 251         cap->max_inline_data = (1 << qp->sq.wqe_shift) - send_wqe_overhead(type) -
 252                 sizeof (struct mlx4_wqe_inline_seg);
 253
 254         return 0;
 255 }
 256
 257 static int set_user_sq_size(struct mlx4_ib_qp *qp,
 258                             struct mlx4_ib_create_qp *ucmd)
 259 {
 260         qp->sq.max       = 1 << ucmd->log_sq_bb_count;
 261         qp->sq.wqe_shift = ucmd->log_sq_stride;
 262
 263         qp->buf_size = (qp->rq.max << qp->rq.wqe_shift) +
 264                 (qp->sq.max << qp->sq.wqe_shift);
 265
 266         return 0;
 267 }
 268
 269 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 270                             struct ib_qp_init_attr *init_attr,
 271                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
 272 {
 273         struct mlx4_wqe_ctrl_seg *ctrl;
 274         int err;
 275         int i;
 276
 277         mutex_init(&qp->mutex);
 278         spin_lock_init(&qp->sq.lock);
 279         spin_lock_init(&qp->rq.lock);
 280
 281         qp->state        = IB_QPS_RESET;
 282         qp->atomic_rd_en = 0;
 283         qp->resp_depth   = 0;
 284
 285         qp->rq.head         = 0;
 286         qp->rq.tail         = 0;
 287         qp->sq.head         = 0;
 288         qp->sq.tail         = 0;
 289
 290         err = set_rq_size(dev, &init_attr->cap, qp);
 291         if (err)
 292                 goto err;
 293
 294         if (pd->uobject) {
 295                 struct mlx4_ib_create_qp ucmd;
 296
 297                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 298                         err = -EFAULT;
 299                         goto err;
 300                 }
 301
 302                 err = set_user_sq_size(qp, &ucmd);
 303                 if (err)
 304                         goto err;
 305
 306                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 307                                        qp->buf_size, 0);
 308                 if (IS_ERR(qp->umem)) {
 309                         err = PTR_ERR(qp->umem);
 310                         goto err;
 311                 }
 312
 313                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 314                                     ilog2(qp->umem->page_size), &qp->mtt);
 315                 if (err)
 316                         goto err_buf;
 317
 318                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 319                 if (err)
 320                         goto err_mtt;
 321
 322                 if (!init_attr->srq) {
 323                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 324                                                   ucmd.db_addr, &qp->db);
 325                         if (err)
 326                                 goto err_mtt;
 327                 }
 328         } else {
 329                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
 330                 if (err)
 331                         goto err;
 332
 333                 if (!init_attr->srq) {
 334                         err = mlx4_ib_db_alloc(dev, &qp->db, 0);
 335                         if (err)
 336                                 goto err;
 337
 338                         *qp->db.db = 0;
 339                 }
 340
 341                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 342                         err = -ENOMEM;
 343                         goto err_db;
 344                 }
 345
 346                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 347                                     &qp->mtt);
 348                 if (err)
 349                         goto err_buf;
 350
 351                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 352                 if (err)
 353                         goto err_mtt;
 354
 355                 for (i = 0; i < qp->sq.max; ++i) {
 356                         ctrl = get_send_wqe(qp, i);
 357                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
 358                 }
 359
 360                 qp->sq.wrid  = kmalloc(qp->sq.max * sizeof (u64), GFP_KERNEL);
 361                 qp->rq.wrid  = kmalloc(qp->rq.max * sizeof (u64), GFP_KERNEL);
 362
 363                 if (!qp->sq.wrid || !qp->rq.wrid) {
 364                         err = -ENOMEM;
 365                         goto err_wrid;
 366                 }
 367
 368                 /* We don't support inline sends for kernel QPs (yet) */
 369                 init_attr->cap.max_inline_data = 0;
 370         }
 371
 372         err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
 373         if (err)
 374                 goto err_wrid;
 375
 376         /*
 377          * Hardware wants QPN written in big-endian order (after
 378          * shifting) for send doorbell.  Precompute this value to save
 379          * a little bit when posting sends.
 380          */
 381         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 382
 383         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 384                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 385         else
 386                 qp->sq_signal_bits = 0;
 387
 388         qp->mqp.event = mlx4_ib_qp_event;
 389
 390         return 0;
 391
 392 err_wrid:
 393         if (pd->uobject && !init_attr->srq)
 394                 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 395         else {
 396                 kfree(qp->sq.wrid);
 397                 kfree(qp->rq.wrid);
 398         }
 399
 400 err_mtt:
 401         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 402
 403 err_buf:
 404         if (pd->uobject)
 405                 ib_umem_release(qp->umem);
 406         else
 407                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 408
 409 err_db:
 410         if (!pd->uobject && !init_attr->srq)
 411                 mlx4_ib_db_free(dev, &qp->db);
 412
 413 err:
 414         return err;
 415 }
 416
 417 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 418 {
 419         switch (state) {
 420         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 421         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 422         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 423         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 424         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 425         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 426         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 427         default:                return -1;
 428         }
 429 }
 430
 431 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 432 {
 433         if (send_cq == recv_cq)
 434                 spin_lock_irq(&send_cq->lock);
 435         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 436                 spin_lock_irq(&send_cq->lock);
 437                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 438         } else {
 439                 spin_lock_irq(&recv_cq->lock);
 440                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 441         }
 442 }
 443
 444 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 445 {
 446         if (send_cq == recv_cq)
 447                 spin_unlock_irq(&send_cq->lock);
 448         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 449                 spin_unlock(&recv_cq->lock);
 450                 spin_unlock_irq(&send_cq->lock);
 451         } else {
 452                 spin_unlock(&send_cq->lock);
 453                 spin_unlock_irq(&recv_cq->lock);
 454         }
 455 }
 456
 457 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 458                               int is_user)
 459 {
 460         struct mlx4_ib_cq *send_cq, *recv_cq;
 461
 462         if (qp->state != IB_QPS_RESET)
 463                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 464                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 465                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
 466                                qp->mqp.qpn);
 467
 468         send_cq = to_mcq(qp->ibqp.send_cq);
 469         recv_cq = to_mcq(qp->ibqp.recv_cq);
 470
 471         mlx4_ib_lock_cqs(send_cq, recv_cq);
 472
 473         if (!is_user) {
 474                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 475                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 476                 if (send_cq != recv_cq)
 477                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 478         }
 479
 480         mlx4_qp_remove(dev->dev, &qp->mqp);
 481
 482         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 483
 484         mlx4_qp_free(dev->dev, &qp->mqp);
 485         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 486
 487         if (is_user) {
 488                 if (!qp->ibqp.srq)
 489                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 490                                               &qp->db);
 491                 ib_umem_release(qp->umem);
 492         } else {
 493                 kfree(qp->sq.wrid);
 494                 kfree(qp->rq.wrid);
 495                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 496                 if (!qp->ibqp.srq)
 497                         mlx4_ib_db_free(dev, &qp->db);
 498         }
 499 }
 500
 501 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 502                                 struct ib_qp_init_attr *init_attr,
 503                                 struct ib_udata *udata)
 504 {
 505         struct mlx4_ib_dev *dev = to_mdev(pd->device);
 506         struct mlx4_ib_sqp *sqp;
 507         struct mlx4_ib_qp *qp;
 508         int err;
 509
 510         switch (init_attr->qp_type) {
 511         case IB_QPT_RC:
 512         case IB_QPT_UC:
 513         case IB_QPT_UD:
 514         {
 515                 qp = kmalloc(sizeof *qp, GFP_KERNEL);
 516                 if (!qp)
 517                         return ERR_PTR(-ENOMEM);
 518
 519                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
 520                 if (err) {
 521                         kfree(qp);
 522                         return ERR_PTR(err);
 523                 }
 524
 525                 qp->ibqp.qp_num = qp->mqp.qpn;
 526
 527                 break;
 528         }
 529         case IB_QPT_SMI:
 530         case IB_QPT_GSI:
 531         {
 532                 /* Userspace is not allowed to create special QPs: */
 533                 if (pd->uobject)
 534                         return ERR_PTR(-EINVAL);
 535
 536                 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
 537                 if (!sqp)
 538                         return ERR_PTR(-ENOMEM);
 539
 540                 qp = &sqp->qp;
 541
 542                 err = create_qp_common(dev, pd, init_attr, udata,
 543                                        dev->dev->caps.sqp_start +
 544                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 545                                        init_attr->port_num - 1,
 546                                        qp);
 547                 if (err) {
 548                         kfree(sqp);
 549                         return ERR_PTR(err);
 550                 }
 551
 552                 qp->port        = init_attr->port_num;
 553                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
 554
 555                 break;
 556         }
 557         default:
 558                 /* Don't support raw QPs */
 559                 return ERR_PTR(-EINVAL);
 560         }
 561
 562         return &qp->ibqp;
 563 }
 564
 565 int mlx4_ib_destroy_qp(struct ib_qp *qp)
 566 {
 567         struct mlx4_ib_dev *dev = to_mdev(qp->device);
 568         struct mlx4_ib_qp *mqp = to_mqp(qp);
 569
 570         if (is_qp0(dev, mqp))
 571                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
 572
 573         destroy_qp_common(dev, mqp, !!qp->pd->uobject);
 574
 575         if (is_sqp(dev, mqp))
 576                 kfree(to_msqp(mqp));
 577         else
 578                 kfree(mqp);
 579
 580         return 0;
 581 }
 582
 583 static void init_port(struct mlx4_ib_dev *dev, int port)
 584 {
 585         struct mlx4_init_port_param param;
 586         int err;
 587
 588         memset(&param, 0, sizeof param);
 589
 590         param.port_width_cap = dev->dev->caps.port_width_cap;
 591         param.vl_cap         = dev->dev->caps.vl_cap;
 592         param.mtu            = ib_mtu_enum_to_int(dev->dev->caps.mtu_cap);
 593         param.max_gid        = dev->dev->caps.gid_table_len;
 594         param.max_pkey       = dev->dev->caps.pkey_table_len;
 595
 596         err = mlx4_INIT_PORT(dev->dev, &param, port);
 597         if (err)
 598                 printk(KERN_WARNING "INIT_PORT failed, return code %d.\n", err);
 599 }
 600
 601 static int to_mlx4_st(enum ib_qp_type type)
 602 {
 603         switch (type) {
 604         case IB_QPT_RC:         return MLX4_QP_ST_RC;
 605         case IB_QPT_UC:         return MLX4_QP_ST_UC;
 606         case IB_QPT_UD:         return MLX4_QP_ST_UD;
 607         case IB_QPT_SMI:
 608         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
 609         default:                return -1;
 610         }
 611 }
 612
 613 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
 614                                    int attr_mask)
 615 {
 616         u8 dest_rd_atomic;
 617         u32 access_flags;
 618         u32 hw_access_flags = 0;
 619
 620         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 621                 dest_rd_atomic = attr->max_dest_rd_atomic;
 622         else
 623                 dest_rd_atomic = qp->resp_depth;
 624
 625         if (attr_mask & IB_QP_ACCESS_FLAGS)
 626                 access_flags = attr->qp_access_flags;
 627         else
 628                 access_flags = qp->atomic_rd_en;
 629
 630         if (!dest_rd_atomic)
 631                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 632
 633         if (access_flags & IB_ACCESS_REMOTE_READ)
 634                 hw_access_flags |= MLX4_QP_BIT_RRE;
 635         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 636                 hw_access_flags |= MLX4_QP_BIT_RAE;
 637         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 638                 hw_access_flags |= MLX4_QP_BIT_RWE;
 639
 640         return cpu_to_be32(hw_access_flags);
 641 }
 642
 643 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
 644                             int attr_mask)
 645 {
 646         if (attr_mask & IB_QP_PKEY_INDEX)
 647                 sqp->pkey_index = attr->pkey_index;
 648         if (attr_mask & IB_QP_QKEY)
 649                 sqp->qkey = attr->qkey;
 650         if (attr_mask & IB_QP_SQ_PSN)
 651                 sqp->send_psn = attr->sq_psn;
 652 }
 653
 654 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
 655 {
 656         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
 657 }
 658
 659 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
 660                          struct mlx4_qp_path *path, u8 port)
 661 {
 662         path->grh_mylmc     = ah->src_path_bits & 0x7f;
 663         path->rlid          = cpu_to_be16(ah->dlid);
 664         if (ah->static_rate) {
 665                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
 666                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
 667                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
 668                         --path->static_rate;
 669         } else
 670                 path->static_rate = 0;
 671         path->counter_index = 0xff;
 672
 673         if (ah->ah_flags & IB_AH_GRH) {
 674                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len) {
 675                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
 676                                ah->grh.sgid_index, dev->dev->caps.gid_table_len - 1);
 677                         return -1;
 678                 }
 679
 680                 path->grh_mylmc |= 1 << 7;
 681                 path->mgid_index = ah->grh.sgid_index;
 682                 path->hop_limit  = ah->grh.hop_limit;
 683                 path->tclass_flowlabel =
 684                         cpu_to_be32((ah->grh.traffic_class << 20) |
 685                                     (ah->grh.flow_label));
 686                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 687         }
 688
 689         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 690                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
 691
 692         return 0;
 693 }
 694
 695 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
 696                                const struct ib_qp_attr *attr, int attr_mask,
 697                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
 698 {
 699         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 700         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 701         struct mlx4_qp_context *context;
 702         enum mlx4_qp_optpar optpar = 0;
 703         int sqd_event;
 704         int err = -EINVAL;
 705
 706         context = kzalloc(sizeof *context, GFP_KERNEL);
 707         if (!context)
 708                 return -ENOMEM;
 709
 710         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
 711                                      (to_mlx4_st(ibqp->qp_type) << 16));
 712         context->flags     |= cpu_to_be32(1 << 8); /* DE? */
 713
 714         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 715                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 716         else {
 717                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
 718                 switch (attr->path_mig_state) {
 719                 case IB_MIG_MIGRATED:
 720                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 721                         break;
 722                 case IB_MIG_REARM:
 723                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
 724                         break;
 725                 case IB_MIG_ARMED:
 726                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
 727                         break;
 728                 }
 729         }
 730
 731         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
 732             ibqp->qp_type == IB_QPT_UD)
 733                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 734         else if (attr_mask & IB_QP_PATH_MTU) {
 735                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
 736                         printk(KERN_ERR "path MTU (%u) is invalid\n",
 737                                attr->path_mtu);
 738                         return -EINVAL;
 739                 }
 740                 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 741         }
 742
 743         if (qp->rq.max)
 744                 context->rq_size_stride = ilog2(qp->rq.max) << 3;
 745         context->rq_size_stride |= qp->rq.wqe_shift - 4;
 746
 747         if (qp->sq.max)
 748                 context->sq_size_stride = ilog2(qp->sq.max) << 3;
 749         context->sq_size_stride |= qp->sq.wqe_shift - 4;
 750
 751         if (qp->ibqp.uobject)
 752                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
 753         else
 754                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
 755
 756         if (attr_mask & IB_QP_DEST_QPN)
 757                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 758
 759         if (attr_mask & IB_QP_PORT) {
 760                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
 761                     !(attr_mask & IB_QP_AV)) {
 762                         mlx4_set_sched(&context->pri_path, attr->port_num);
 763                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
 764                 }
 765         }
 766
 767         if (attr_mask & IB_QP_PKEY_INDEX) {
 768                 context->pri_path.pkey_index = attr->pkey_index;
 769                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
 770         }
 771
 772         if (attr_mask & IB_QP_RNR_RETRY) {
 773                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
 774                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
 775         }
 776
 777         if (attr_mask & IB_QP_AV) {
 778                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
 779                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) {
 780                         err = -EINVAL;
 781                         goto out;
 782                 }
 783
 784                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
 785                            MLX4_QP_OPTPAR_SCHED_QUEUE);
 786         }
 787
 788         if (attr_mask & IB_QP_TIMEOUT) {
 789                 context->pri_path.ackto = attr->timeout << 3;
 790                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
 791         }
 792
 793         if (attr_mask & IB_QP_ALT_PATH) {
 794                 if (attr->alt_pkey_index >= dev->dev->caps.pkey_table_len)
 795                         return -EINVAL;
 796
 797                 if (attr->alt_port_num == 0 ||
 798                     attr->alt_port_num > dev->dev->caps.num_ports)
 799                         return -EINVAL;
 800
 801                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
 802                                   attr->alt_port_num))
 803                         return -EINVAL;
 804
 805                 context->alt_path.pkey_index = attr->alt_pkey_index;
 806                 context->alt_path.ackto = attr->alt_timeout << 3;
 807                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
 808         }
 809
 810         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
 811         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
 812         if (attr_mask & IB_QP_RETRY_CNT) {
 813                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 814                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
 815         }
 816
 817         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 818                 if (attr->max_rd_atomic)
 819                         context->params1 |=
 820                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 821                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
 822         }
 823
 824         if (attr_mask & IB_QP_SQ_PSN)
 825                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
 826
 827         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
 828
 829         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 830                 if (attr->max_dest_rd_atomic)
 831                         context->params2 |=
 832                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 833                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
 834         }
 835
 836         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 837                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
 838                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
 839         }
 840
 841         if (ibqp->srq)
 842                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
 843
 844         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 845                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 846                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
 847         }
 848         if (attr_mask & IB_QP_RQ_PSN)
 849                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 850
 851         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
 852
 853         if (attr_mask & IB_QP_QKEY) {
 854                 context->qkey = cpu_to_be32(attr->qkey);
 855                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
 856         }
 857
 858         if (ibqp->srq)
 859                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
 860
 861         if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
 862                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
 863
 864         if (cur_state == IB_QPS_INIT &&
 865             new_state == IB_QPS_RTR  &&
 866             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
 867              ibqp->qp_type == IB_QPT_UD)) {
 868                 context->pri_path.sched_queue = (qp->port - 1) << 6;
 869                 if (is_qp0(dev, qp))
 870                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
 871                 else
 872                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
 873         }
 874
 875         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 876             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
 877                 sqd_event = 1;
 878         else
 879                 sqd_event = 0;
 880
 881         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
 882                              to_mlx4_state(new_state), context, optpar,
 883                              sqd_event, &qp->mqp);
 884         if (err)
 885                 goto out;
 886
 887         qp->state = new_state;
 888
 889         if (attr_mask & IB_QP_ACCESS_FLAGS)
 890                 qp->atomic_rd_en = attr->qp_access_flags;
 891         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 892                 qp->resp_depth = attr->max_dest_rd_atomic;
 893         if (attr_mask & IB_QP_PORT)
 894                 qp->port = attr->port_num;
 895         if (attr_mask & IB_QP_ALT_PATH)
 896                 qp->alt_port = attr->alt_port_num;
 897
 898         if (is_sqp(dev, qp))
 899                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
 900
 901         /*
 902          * If we moved QP0 to RTR, bring the IB link up; if we moved
 903          * QP0 to RESET or ERROR, bring the link back down.
 904          */
 905         if (is_qp0(dev, qp)) {
 906                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
 907                         init_port(dev, qp->port);
 908
 909                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
 910                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
 911                         mlx4_CLOSE_PORT(dev->dev, qp->port);
 912         }
 913
 914         /*
 915          * If we moved a kernel QP to RESET, clean up all old CQ
 916          * entries and reinitialize the QP.
 917          */
 918         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
 919                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
 920                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
 921                 if (ibqp->send_cq != ibqp->recv_cq)
 922                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
 923
 924                 qp->rq.head = 0;
 925                 qp->rq.tail = 0;
 926                 qp->sq.head = 0;
 927                 qp->sq.tail = 0;
 928                 if (!ibqp->srq)
 929                         *qp->db.db  = 0;
 930         }
 931
 932 out:
 933         kfree(context);
 934         return err;
 935 }
 936
 937 static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
 938 static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
 939                 [IB_QPT_UD]  = (IB_QP_PKEY_INDEX                |
 940                                 IB_QP_PORT                      |
 941                                 IB_QP_QKEY),
 942                 [IB_QPT_UC]  = (IB_QP_PKEY_INDEX                |
 943                                 IB_QP_PORT                      |
 944                                 IB_QP_ACCESS_FLAGS),
 945                 [IB_QPT_RC]  = (IB_QP_PKEY_INDEX                |
 946                                 IB_QP_PORT                      |
 947                                 IB_QP_ACCESS_FLAGS),
 948                 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX                |
 949                                 IB_QP_QKEY),
 950                 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX                |
 951                                 IB_QP_QKEY),
 952 };
 953
 954 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 955                       int attr_mask, struct ib_udata *udata)
 956 {
 957         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 958         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 959         enum ib_qp_state cur_state, new_state;
 960         int err = -EINVAL;
 961
 962         mutex_lock(&qp->mutex);
 963
 964         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
 965         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 966
 967         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
 968                 goto out;
 969
 970         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 971              attr->pkey_index >= dev->dev->caps.pkey_table_len) {
 972                 goto out;
 973         }
 974
 975         if ((attr_mask & IB_QP_PORT) &&
 976             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
 977                 goto out;
 978         }
 979
 980         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 981             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
 982                 goto out;
 983         }
 984
 985         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 986             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
 987                 goto out;
 988         }
 989
 990         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
 991                 err = 0;
 992                 goto out;
 993         }
 994
 995         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
 996                 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
 997                                           mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
 998                                           IB_QPS_RESET, IB_QPS_INIT);
 999                 if (err)
1000                         goto out;
1001                 cur_state = IB_QPS_INIT;
1002         }
1003
1004         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1005
1006 out:
1007         mutex_unlock(&qp->mutex);
1008         return err;
1009 }
1010
1011 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1012                             void *wqe)
1013 {
1014         struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1015         struct mlx4_wqe_mlx_seg *mlx = wqe;
1016         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1017         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1018         u16 pkey;
1019         int send_size;
1020         int header_size;
1021         int i;
1022
1023         send_size = 0;
1024         for (i = 0; i < wr->num_sge; ++i)
1025                 send_size += wr->sg_list[i].length;
1026
1027         ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1028
1029         sqp->ud_header.lrh.service_level   =
1030                 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1031         sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1032         sqp->ud_header.lrh.source_lid      = cpu_to_be16(ah->av.g_slid & 0x7f);
1033         if (mlx4_ib_ah_grh_present(ah)) {
1034                 sqp->ud_header.grh.traffic_class =
1035                         (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1036                 sqp->ud_header.grh.flow_label    =
1037                         ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1038                 sqp->ud_header.grh.hop_limit     = ah->av.hop_limit;
1039                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1040                                   ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1041                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1042                        ah->av.dgid, 16);
1043         }
1044
1045         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1046         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1047                                   (sqp->ud_header.lrh.destination_lid ==
1048                                    IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1049                                   (sqp->ud_header.lrh.service_level << 8));
1050         mlx->rlid   = sqp->ud_header.lrh.destination_lid;
1051
1052         switch (wr->opcode) {
1053         case IB_WR_SEND:
1054                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1055                 sqp->ud_header.immediate_present = 0;
1056                 break;
1057         case IB_WR_SEND_WITH_IMM:
1058                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1059                 sqp->ud_header.immediate_present = 1;
1060                 sqp->ud_header.immediate_data    = wr->imm_data;
1061                 break;
1062         default:
1063                 return -EINVAL;
1064         }
1065
1066         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1067         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1068                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1069         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1070         if (!sqp->qp.ibqp.qp_num)
1071                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1072         else
1073                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1074         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1075         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1076         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1077         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1078                                                sqp->qkey : wr->wr.ud.remote_qkey);
1079         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1080
1081         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1082
1083         if (0) {
1084                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1085                 for (i = 0; i < header_size / 4; ++i) {
1086                         if (i % 8 == 0)
1087                                 printk("  [%02x] ", i * 4);
1088                         printk(" %08x",
1089                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1090                         if ((i + 1) % 8 == 0)
1091                                 printk("\n");
1092                 }
1093                 printk("\n");
1094         }
1095
1096         inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1097         memcpy(inl + 1, sqp->header_buf, header_size);
1098
1099         return ALIGN(sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1100 }
1101
1102 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1103 {
1104         unsigned cur;
1105         struct mlx4_ib_cq *cq;
1106
1107         cur = wq->head - wq->tail;
1108         if (likely(cur + nreq < wq->max))
1109                 return 0;
1110
1111         cq = to_mcq(ib_cq);
1112         spin_lock(&cq->lock);
1113         cur = wq->head - wq->tail;
1114         spin_unlock(&cq->lock);
1115
1116         return cur + nreq >= wq->max;
1117 }
1118
1119 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1120                       struct ib_send_wr **bad_wr)
1121 {
1122         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1123         void *wqe;
1124         struct mlx4_wqe_ctrl_seg *ctrl;
1125         unsigned long flags;
1126         int nreq;
1127         int err = 0;
1128         int ind;
1129         int size;
1130         int i;
1131
1132         spin_lock_irqsave(&qp->rq.lock, flags);
1133
1134         ind = qp->sq.head;
1135
1136         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1137                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1138                         err = -ENOMEM;
1139                         *bad_wr = wr;
1140                         goto out;
1141                 }
1142
1143                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1144                         err = -EINVAL;
1145                         *bad_wr = wr;
1146                         goto out;
1147                 }
1148
1149                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.max - 1));
1150                 qp->sq.wrid[ind & (qp->sq.max - 1)] = wr->wr_id;
1151
1152                 ctrl->srcrb_flags =
1153                         (wr->send_flags & IB_SEND_SIGNALED ?
1154                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1155                         (wr->send_flags & IB_SEND_SOLICITED ?
1156                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1157                         qp->sq_signal_bits;
1158
1159                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1160                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1161                         ctrl->imm = wr->imm_data;
1162                 else
1163                         ctrl->imm = 0;
1164
1165                 wqe += sizeof *ctrl;
1166                 size = sizeof *ctrl / 16;
1167
1168                 switch (ibqp->qp_type) {
1169                 case IB_QPT_RC:
1170                 case IB_QPT_UC:
1171                         switch (wr->opcode) {
1172                         case IB_WR_ATOMIC_CMP_AND_SWP:
1173                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1174                                 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1175                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1176                                 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1177                                         cpu_to_be32(wr->wr.atomic.rkey);
1178                                 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1179
1180                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1181
1182                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1183                                         ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1184                                                 cpu_to_be64(wr->wr.atomic.swap);
1185                                         ((struct mlx4_wqe_atomic_seg *) wqe)->compare =
1186                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1187                                 } else {
1188                                         ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1189                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1190                                         ((struct mlx4_wqe_atomic_seg *) wqe)->compare = 0;
1191                                 }
1192
1193                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1194                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1195                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1196
1197                                 break;
1198
1199                         case IB_WR_RDMA_READ:
1200                         case IB_WR_RDMA_WRITE:
1201                         case IB_WR_RDMA_WRITE_WITH_IMM:
1202                                 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1203                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1204                                 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1205                                         cpu_to_be32(wr->wr.rdma.rkey);
1206                                 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1207
1208                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1209                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1210
1211                                 break;
1212
1213                         default:
1214                                 /* No extra segments required for sends */
1215                                 break;
1216                         }
1217                         break;
1218
1219                 case IB_QPT_UD:
1220                         memcpy(((struct mlx4_wqe_datagram_seg *) wqe)->av,
1221                                &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1222                         ((struct mlx4_wqe_datagram_seg *) wqe)->dqpn =
1223                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1224                         ((struct mlx4_wqe_datagram_seg *) wqe)->qkey =
1225                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1226
1227                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1228                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1229                         break;
1230
1231                 case IB_QPT_SMI:
1232                 case IB_QPT_GSI:
1233                         err = build_mlx_header(to_msqp(qp), wr, ctrl);
1234                         if (err < 0) {
1235                                 *bad_wr = wr;
1236                                 goto out;
1237                         }
1238                         wqe  += err;
1239                         size += err / 16;
1240
1241                         err = 0;
1242                         break;
1243
1244                 default:
1245                         break;
1246                 }
1247
1248                 for (i = 0; i < wr->num_sge; ++i) {
1249                         ((struct mlx4_wqe_data_seg *) wqe)->byte_count =
1250                                 cpu_to_be32(wr->sg_list[i].length);
1251                         ((struct mlx4_wqe_data_seg *) wqe)->lkey =
1252                                 cpu_to_be32(wr->sg_list[i].lkey);
1253                         ((struct mlx4_wqe_data_seg *) wqe)->addr =
1254                                 cpu_to_be64(wr->sg_list[i].addr);
1255
1256                         wqe  += sizeof (struct mlx4_wqe_data_seg);
1257                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1258                 }
1259
1260                 /* Add one more inline data segment for ICRC for MLX sends */
1261                 if (qp->ibqp.qp_type == IB_QPT_SMI || qp->ibqp.qp_type == IB_QPT_GSI) {
1262                         ((struct mlx4_wqe_inline_seg *) wqe)->byte_count =
1263                                 cpu_to_be32((1 << 31) | 4);
1264                         ((u32 *) wqe)[1] = 0;
1265                         wqe  += sizeof (struct mlx4_wqe_data_seg);
1266                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1267                 }
1268
1269                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1270                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1271
1272                 /*
1273                  * Make sure descriptor is fully written before
1274                  * setting ownership bit (because HW can start
1275                  * executing as soon as we do).
1276                  */
1277                 wmb();
1278
1279                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1280                         err = -EINVAL;
1281                         goto out;
1282                 }
1283
1284                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1285                         (ind & qp->sq.max ? cpu_to_be32(1 << 31) : 0);
1286
1287                 ++ind;
1288         }
1289
1290 out:
1291         if (likely(nreq)) {
1292                 qp->sq.head += nreq;
1293
1294                 /*
1295                  * Make sure that descriptors are written before
1296                  * doorbell record.
1297                  */
1298                 wmb();
1299
1300                 writel(qp->doorbell_qpn,
1301                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1302
1303                 /*
1304                  * Make sure doorbells don't leak out of SQ spinlock
1305                  * and reach the HCA out of order.
1306                  */
1307                 mmiowb();
1308         }
1309
1310         spin_unlock_irqrestore(&qp->rq.lock, flags);
1311
1312         return err;
1313 }
1314
1315 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1316                       struct ib_recv_wr **bad_wr)
1317 {
1318         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1319         struct mlx4_wqe_data_seg *scat;
1320         unsigned long flags;
1321         int err = 0;
1322         int nreq;
1323         int ind;
1324         int i;
1325
1326         spin_lock_irqsave(&qp->rq.lock, flags);
1327
1328         ind = qp->rq.head & (qp->rq.max - 1);
1329
1330         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1331                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1332                         err = -ENOMEM;
1333                         *bad_wr = wr;
1334                         goto out;
1335                 }
1336
1337                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1338                         err = -EINVAL;
1339                         *bad_wr = wr;
1340                         goto out;
1341                 }
1342
1343                 scat = get_recv_wqe(qp, ind);
1344
1345                 for (i = 0; i < wr->num_sge; ++i) {
1346                         scat[i].byte_count = cpu_to_be32(wr->sg_list[i].length);
1347                         scat[i].lkey       = cpu_to_be32(wr->sg_list[i].lkey);
1348                         scat[i].addr       = cpu_to_be64(wr->sg_list[i].addr);
1349                 }
1350
1351                 if (i < qp->rq.max_gs) {
1352                         scat[i].byte_count = 0;
1353                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1354                         scat[i].addr       = 0;
1355                 }
1356
1357                 qp->rq.wrid[ind] = wr->wr_id;
1358
1359                 ind = (ind + 1) & (qp->rq.max - 1);
1360         }
1361
1362 out:
1363         if (likely(nreq)) {
1364                 qp->rq.head += nreq;
1365
1366                 /*
1367                  * Make sure that descriptors are written before
1368                  * doorbell record.
1369                  */
1370                 wmb();
1371
1372                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1373         }
1374
1375         spin_unlock_irqrestore(&qp->rq.lock, flags);
1376
1377         return err;
1378 }