SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_init_chip.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/vmalloc.h>
  37
  38 #include "ipath_kernel.h"
  39 #include "ipath_common.h"
  40
  41 /*
  42  * min buffers we want to have per port, after driver
  43  */
  44 #define IPATH_MIN_USER_PORT_BUFCNT 8
  45
  46 /*
  47  * Number of ports we are configured to use (to allow for more pio
  48  * buffers per port, etc.)  Zero means use chip value.
  49  */
  50 static ushort ipath_cfgports;
  51
  52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
  53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
  54
  55 /*
  56  * Number of buffers reserved for driver (verbs and layered drivers.)
  57  * Reserved at end of buffer list.   Initialized based on
  58  * number of PIO buffers if not set via module interface.
  59  * The problem with this is that it's global, but we'll use different
  60  * numbers for different chip types.  So the default value is not
  61  * very useful.  I've redefined it for the 1.3 release so that it's
  62  * zero unless set by the user to something else, in which case we
  63  * try to respect it.
  64  */
  65 static ushort ipath_kpiobufs;
  66
  67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
  68
  69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
  70                   &ipath_kpiobufs, S_IWUSR | S_IRUGO);
  71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
  72
  73 /**
  74  * create_port0_egr - allocate the eager TID buffers
  75  * @dd: the infinipath device
  76  *
  77  * This code is now quite different for user and kernel, because
  78  * the kernel uses skb's, for the accelerated network performance.
  79  * This is the kernel (port0) version.
  80  *
  81  * Allocate the eager TID buffers and program them into infinipath.
  82  * We use the network layer alloc_skb() allocator to allocate the
  83  * memory, and either use the buffers as is for things like verbs
  84  * packets, or pass the buffers up to the ipath layered driver and
  85  * thence the network layer, replacing them as we do so (see
  86  * ipath_rcv_layer()).
  87  */
  88 static int create_port0_egr(struct ipath_devdata *dd)
  89 {
  90         unsigned e, egrcnt;
  91         struct ipath_skbinfo *skbinfo;
  92         int ret;
  93
  94         egrcnt = dd->ipath_p0_rcvegrcnt;
  95
  96         skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
  97         if (skbinfo == NULL) {
  98                 ipath_dev_err(dd, "allocation error for eager TID "
  99                               "skb array\n");
 100                 ret = -ENOMEM;
 101                 goto bail;
 102         }
 103         for (e = 0; e < egrcnt; e++) {
 104                 /*
 105                  * This is a bit tricky in that we allocate extra
 106                  * space for 2 bytes of the 14 byte ethernet header.
 107                  * These two bytes are passed in the ipath header so
 108                  * the rest of the data is word aligned.  We allocate
 109                  * 4 bytes so that the data buffer stays word aligned.
 110                  * See ipath_kreceive() for more details.
 111                  */
 112                 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
 113                 if (!skbinfo[e].skb) {
 114                         ipath_dev_err(dd, "SKB allocation error for "
 115                                       "eager TID %u\n", e);
 116                         while (e != 0)
 117                                 dev_kfree_skb(skbinfo[--e].skb);
 118                         vfree(skbinfo);
 119                         ret = -ENOMEM;
 120                         goto bail;
 121                 }
 122         }
 123         /*
 124          * After loop above, so we can test non-NULL to see if ready
 125          * to use at receive, etc.
 126          */
 127         dd->ipath_port0_skbinfo = skbinfo;
 128
 129         for (e = 0; e < egrcnt; e++) {
 130                 dd->ipath_port0_skbinfo[e].phys =
 131                   ipath_map_single(dd->pcidev,
 132                                    dd->ipath_port0_skbinfo[e].skb->data,
 133                                    dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
 134                 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
 135                                     ((char __iomem *) dd->ipath_kregbase +
 136                                      dd->ipath_rcvegrbase),
 137                                     RCVHQ_RCV_TYPE_EAGER,
 138                                     dd->ipath_port0_skbinfo[e].phys);
 139         }
 140
 141         ret = 0;
 142
 143 bail:
 144         return ret;
 145 }
 146
 147 static int bringup_link(struct ipath_devdata *dd)
 148 {
 149         u64 val, ibc;
 150         int ret = 0;
 151
 152         /* hold IBC in reset */
 153         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
 154         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 155                          dd->ipath_control);
 156
 157         /*
 158          * set initial max size pkt IBC will send, including ICRC; it's the
 159          * PIO buffer size in dwords, less 1; also see ipath_set_mtu()
 160          */
 161         val = (dd->ipath_ibmaxlen >> 2) + 1;
 162         ibc = val << dd->ibcc_mpl_shift;
 163
 164         /* flowcontrolwatermark is in units of KBytes */
 165         ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
 166         /*
 167          * How often flowctrl sent.  More or less in usecs; balance against
 168          * watermark value, so that in theory senders always get a flow
 169          * control update in time to not let the IB link go idle.
 170          */
 171         ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
 172         /* max error tolerance */
 173         ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
 174         /* use "real" buffer space for */
 175         ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
 176         /* IB credit flow control. */
 177         ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
 178         /* initially come up waiting for TS1, without sending anything. */
 179         dd->ipath_ibcctrl = ibc;
 180         /*
 181          * Want to start out with both LINKCMD and LINKINITCMD in NOP
 182          * (0 and 0).  Don't put linkinitcmd in ipath_ibcctrl, want that
 183          * to stay a NOP
 184          */
 185         ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
 186                 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
 187         ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
 188                    (unsigned long long) ibc);
 189         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
 190
 191         // be sure chip saw it
 192         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 193
 194         ret = dd->ipath_f_bringup_serdes(dd);
 195
 196         if (ret)
 197                 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
 198                          "not usable\n");
 199         else {
 200                 /* enable IBC */
 201                 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
 202                 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 203                                  dd->ipath_control);
 204         }
 205
 206         return ret;
 207 }
 208
 209 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
 210 {
 211         struct ipath_portdata *pd = NULL;
 212
 213         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 214         if (pd) {
 215                 pd->port_dd = dd;
 216                 pd->port_cnt = 1;
 217                 /* The port 0 pkey table is used by the layer interface. */
 218                 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
 219         }
 220         return pd;
 221 }
 222
 223 static int init_chip_first(struct ipath_devdata *dd,
 224                            struct ipath_portdata **pdp)
 225 {
 226         struct ipath_portdata *pd = NULL;
 227         int ret = 0;
 228         u64 val;
 229
 230         /*
 231          * skip cfgports stuff because we are not allocating memory,
 232          * and we don't want problems if the portcnt changed due to
 233          * cfgports.  We do still check and report a difference, if
 234          * not same (should be impossible).
 235          */
 236         dd->ipath_f_config_ports(dd, ipath_cfgports);
 237         if (!ipath_cfgports)
 238                 dd->ipath_cfgports = dd->ipath_portcnt;
 239         else if (ipath_cfgports <= dd->ipath_portcnt) {
 240                 dd->ipath_cfgports = ipath_cfgports;
 241                 ipath_dbg("Configured to use %u ports out of %u in chip\n",
 242                           dd->ipath_cfgports, dd->ipath_portcnt);
 243         } else {
 244                 dd->ipath_cfgports = dd->ipath_portcnt;
 245                 ipath_dbg("Tried to configured to use %u ports; chip "
 246                           "only supports %u\n", ipath_cfgports,
 247                           dd->ipath_portcnt);
 248         }
 249         /*
 250          * Allocate full portcnt array, rather than just cfgports, because
 251          * cleanup iterates across all possible ports.
 252          */
 253         dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
 254                                GFP_KERNEL);
 255
 256         if (!dd->ipath_pd) {
 257                 ipath_dev_err(dd, "Unable to allocate portdata array, "
 258                               "failing\n");
 259                 ret = -ENOMEM;
 260                 goto done;
 261         }
 262
 263         pd = create_portdata0(dd);
 264         if (!pd) {
 265                 ipath_dev_err(dd, "Unable to allocate portdata for port "
 266                               "0, failing\n");
 267                 ret = -ENOMEM;
 268                 goto done;
 269         }
 270         dd->ipath_pd[0] = pd;
 271
 272         dd->ipath_rcvtidcnt =
 273                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 274         dd->ipath_rcvtidbase =
 275                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 276         dd->ipath_rcvegrcnt =
 277                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 278         dd->ipath_rcvegrbase =
 279                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 280         dd->ipath_palign =
 281                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 282         dd->ipath_piobufbase =
 283                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
 284         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
 285         dd->ipath_piosize2k = val & ~0U;
 286         dd->ipath_piosize4k = val >> 32;
 287         if (dd->ipath_piosize4k == 0 && ipath_mtu4096)
 288                 ipath_mtu4096 = 0; /* 4KB not supported by this chip */
 289         dd->ipath_ibmtu = ipath_mtu4096 ? 4096 : 2048;
 290         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
 291         dd->ipath_piobcnt2k = val & ~0U;
 292         dd->ipath_piobcnt4k = val >> 32;
 293         dd->ipath_pio2kbase =
 294                 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
 295                                  (dd->ipath_piobufbase & 0xffffffff));
 296         if (dd->ipath_piobcnt4k) {
 297                 dd->ipath_pio4kbase = (u32 __iomem *)
 298                         (((char __iomem *) dd->ipath_kregbase) +
 299                          (dd->ipath_piobufbase >> 32));
 300                 /*
 301                  * 4K buffers take 2 pages; we use roundup just to be
 302                  * paranoid; we calculate it once here, rather than on
 303                  * ever buf allocate
 304                  */
 305                 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
 306                                           dd->ipath_palign);
 307                 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
 308                           "(%x aligned)\n",
 309                           dd->ipath_piobcnt2k, dd->ipath_piosize2k,
 310                           dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
 311                           dd->ipath_piosize4k, dd->ipath_pio4kbase,
 312                           dd->ipath_4kalign);
 313         }
 314         else ipath_dbg("%u 2k piobufs @ %p\n",
 315                        dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
 316
 317         spin_lock_init(&dd->ipath_tid_lock);
 318         spin_lock_init(&dd->ipath_sendctrl_lock);
 319         spin_lock_init(&dd->ipath_gpio_lock);
 320         spin_lock_init(&dd->ipath_eep_st_lock);
 321         mutex_init(&dd->ipath_eep_lock);
 322
 323 done:
 324         *pdp = pd;
 325         return ret;
 326 }
 327
 328 /**
 329  * init_chip_reset - re-initialize after a reset, or enable
 330  * @dd: the infinipath device
 331  * @pdp: output for port data
 332  *
 333  * sanity check at least some of the values after reset, and
 334  * ensure no receive or transmit (explictly, in case reset
 335  * failed
 336  */
 337 static int init_chip_reset(struct ipath_devdata *dd,
 338                            struct ipath_portdata **pdp)
 339 {
 340         u32 rtmp;
 341
 342         *pdp = dd->ipath_pd[0];
 343         /* ensure chip does no sends or receives while we re-initialize */
 344         dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U;
 345         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, dd->ipath_rcvctrl);
 346         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 347         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, dd->ipath_control);
 348
 349         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
 350         if (dd->ipath_portcnt != rtmp)
 351                 dev_info(&dd->pcidev->dev, "portcnt was %u before "
 352                          "reset, now %u, using original\n",
 353                          dd->ipath_portcnt, rtmp);
 354         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 355         if (rtmp != dd->ipath_rcvtidcnt)
 356                 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
 357                          "reset, now %u, using original\n",
 358                          dd->ipath_rcvtidcnt, rtmp);
 359         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 360         if (rtmp != dd->ipath_rcvtidbase)
 361                 dev_info(&dd->pcidev->dev, "tidbase was %u before "
 362                          "reset, now %u, using original\n",
 363                          dd->ipath_rcvtidbase, rtmp);
 364         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 365         if (rtmp != dd->ipath_rcvegrcnt)
 366                 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
 367                          "reset, now %u, using original\n",
 368                          dd->ipath_rcvegrcnt, rtmp);
 369         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 370         if (rtmp != dd->ipath_rcvegrbase)
 371                 dev_info(&dd->pcidev->dev, "egrbase was %u before "
 372                          "reset, now %u, using original\n",
 373                          dd->ipath_rcvegrbase, rtmp);
 374
 375         return 0;
 376 }
 377
 378 static int init_pioavailregs(struct ipath_devdata *dd)
 379 {
 380         int ret;
 381
 382         dd->ipath_pioavailregs_dma = dma_alloc_coherent(
 383                 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
 384                 GFP_KERNEL);
 385         if (!dd->ipath_pioavailregs_dma) {
 386                 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
 387                               "in memory\n");
 388                 ret = -ENOMEM;
 389                 goto done;
 390         }
 391
 392         /*
 393          * we really want L2 cache aligned, but for current CPUs of
 394          * interest, they are the same.
 395          */
 396         dd->ipath_statusp = (u64 *)
 397                 ((char *)dd->ipath_pioavailregs_dma +
 398                  ((2 * L1_CACHE_BYTES +
 399                    dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
 400         /* copy the current value now that it's really allocated */
 401         *dd->ipath_statusp = dd->_ipath_status;
 402         /*
 403          * setup buffer to hold freeze msg, accessible to apps,
 404          * following statusp
 405          */
 406         dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
 407         /* and its length */
 408         dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
 409
 410         ret = 0;
 411
 412 done:
 413         return ret;
 414 }
 415
 416 /**
 417  * init_shadow_tids - allocate the shadow TID array
 418  * @dd: the infinipath device
 419  *
 420  * allocate the shadow TID array, so we can ipath_munlock previous
 421  * entries.  It may make more sense to move the pageshadow to the
 422  * port data structure, so we only allocate memory for ports actually
 423  * in use, since we at 8k per port, now.
 424  */
 425 static void init_shadow_tids(struct ipath_devdata *dd)
 426 {
 427         struct page **pages;
 428         dma_addr_t *addrs;
 429
 430         pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 431                         sizeof(struct page *));
 432         if (!pages) {
 433                 ipath_dev_err(dd, "failed to allocate shadow page * "
 434                               "array, no expected sends!\n");
 435                 dd->ipath_pageshadow = NULL;
 436                 return;
 437         }
 438
 439         addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 440                         sizeof(dma_addr_t));
 441         if (!addrs) {
 442                 ipath_dev_err(dd, "failed to allocate shadow dma handle "
 443                               "array, no expected sends!\n");
 444                 vfree(dd->ipath_pageshadow);
 445                 dd->ipath_pageshadow = NULL;
 446                 return;
 447         }
 448
 449         memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 450                sizeof(struct page *));
 451
 452         dd->ipath_pageshadow = pages;
 453         dd->ipath_physshadow = addrs;
 454 }
 455
 456 static void enable_chip(struct ipath_devdata *dd,
 457                         struct ipath_portdata *pd, int reinit)
 458 {
 459         u32 val;
 460         unsigned long flags;
 461         int i;
 462
 463         if (!reinit)
 464                 init_waitqueue_head(&ipath_state_wait);
 465
 466         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 467                          dd->ipath_rcvctrl);
 468
 469         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 470         /* Enable PIO send, and update of PIOavail regs to memory. */
 471         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
 472                 INFINIPATH_S_PIOBUFAVAILUPD;
 473         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 474         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 475         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 476
 477         /*
 478          * enable port 0 receive, and receive interrupt.  other ports
 479          * done as user opens and inits them.
 480          */
 481         dd->ipath_rcvctrl = (1ULL << dd->ipath_r_tailupd_shift) |
 482                 (1ULL << dd->ipath_r_portenable_shift) |
 483                 (1ULL << dd->ipath_r_intravail_shift);
 484         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 485                          dd->ipath_rcvctrl);
 486
 487         /*
 488          * now ready for use.  this should be cleared whenever we
 489          * detect a reset, or initiate one.
 490          */
 491         dd->ipath_flags |= IPATH_INITTED;
 492
 493         /*
 494          * init our shadow copies of head from tail values, and write
 495          * head values to match.
 496          */
 497         val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
 498         (void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
 499
 500         /* Initialize so we interrupt on next packet received */
 501         (void)ipath_write_ureg(dd, ur_rcvhdrhead,
 502                                dd->ipath_rhdrhead_intr_off |
 503                                dd->ipath_pd[0]->port_head, 0);
 504
 505         /*
 506          * by now pioavail updates to memory should have occurred, so
 507          * copy them into our working/shadow registers; this is in
 508          * case something went wrong with abort, but mostly to get the
 509          * initial values of the generation bit correct.
 510          */
 511         for (i = 0; i < dd->ipath_pioavregs; i++) {
 512                 __le64 pioavail;
 513
 514                 /*
 515                  * Chip Errata bug 6641; even and odd qwords>3 are swapped.
 516                  */
 517                 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
 518                         pioavail = dd->ipath_pioavailregs_dma[i ^ 1];
 519                 else
 520                         pioavail = dd->ipath_pioavailregs_dma[i];
 521                 dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail);
 522         }
 523         /* can get counters, stats, etc. */
 524         dd->ipath_flags |= IPATH_PRESENT;
 525 }
 526
 527 static int init_housekeeping(struct ipath_devdata *dd,
 528                              struct ipath_portdata **pdp, int reinit)
 529 {
 530         char boardn[32];
 531         int ret = 0;
 532
 533         /*
 534          * have to clear shadow copies of registers at init that are
 535          * not otherwise set here, or all kinds of bizarre things
 536          * happen with driver on chip reset
 537          */
 538         dd->ipath_rcvhdrsize = 0;
 539
 540         /*
 541          * Don't clear ipath_flags as 8bit mode was set before
 542          * entering this func. However, we do set the linkstate to
 543          * unknown, so we can watch for a transition.
 544          * PRESENT is set because we want register reads to work,
 545          * and the kernel infrastructure saw it in config space;
 546          * We clear it if we have failures.
 547          */
 548         dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
 549         dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
 550                              IPATH_LINKDOWN | IPATH_LINKINIT);
 551
 552         ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
 553         dd->ipath_revision =
 554                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
 555
 556         /*
 557          * set up fundamental info we need to use the chip; we assume
 558          * if the revision reg and these regs are OK, we don't need to
 559          * special case the rest
 560          */
 561         dd->ipath_sregbase =
 562                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
 563         dd->ipath_cregbase =
 564                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
 565         dd->ipath_uregbase =
 566                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
 567         ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
 568                    "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
 569                    dd->ipath_uregbase, dd->ipath_cregbase);
 570         if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
 571             || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
 572             || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
 573             || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
 574                 ipath_dev_err(dd, "Register read failures from chip, "
 575                               "giving up initialization\n");
 576                 dd->ipath_flags &= ~IPATH_PRESENT;
 577                 ret = -ENODEV;
 578                 goto done;
 579         }
 580
 581
 582         /* clear diagctrl register, in case diags were running and crashed */
 583         ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
 584
 585         /* clear the initial reset flag, in case first driver load */
 586         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
 587                          INFINIPATH_E_RESET);
 588
 589         if (reinit)
 590                 ret = init_chip_reset(dd, pdp);
 591         else
 592                 ret = init_chip_first(dd, pdp);
 593
 594         if (ret)
 595                 goto done;
 596
 597         ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, "
 598                    "%u egrtids\n", (unsigned long long) dd->ipath_revision,
 599                    dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt,
 600                    dd->ipath_rcvegrcnt);
 601
 602         if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
 603              INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
 604                 ipath_dev_err(dd, "Driver only handles version %d, "
 605                               "chip swversion is %d (%llx), failng\n",
 606                               IPATH_CHIP_SWVERSION,
 607                               (int)(dd->ipath_revision >>
 608                                     INFINIPATH_R_SOFTWARE_SHIFT) &
 609                               INFINIPATH_R_SOFTWARE_MASK,
 610                               (unsigned long long) dd->ipath_revision);
 611                 ret = -ENOSYS;
 612                 goto done;
 613         }
 614         dd->ipath_majrev = (u8) ((dd->ipath_revision >>
 615                                   INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
 616                                  INFINIPATH_R_CHIPREVMAJOR_MASK);
 617         dd->ipath_minrev = (u8) ((dd->ipath_revision >>
 618                                   INFINIPATH_R_CHIPREVMINOR_SHIFT) &
 619                                  INFINIPATH_R_CHIPREVMINOR_MASK);
 620         dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
 621                                     INFINIPATH_R_BOARDID_SHIFT) &
 622                                    INFINIPATH_R_BOARDID_MASK);
 623
 624         ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
 625
 626         snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
 627                  "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
 628                  "SW Compat %u\n",
 629                  IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
 630                  (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
 631                  INFINIPATH_R_ARCH_MASK,
 632                  dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
 633                  (unsigned)(dd->ipath_revision >>
 634                             INFINIPATH_R_SOFTWARE_SHIFT) &
 635                  INFINIPATH_R_SOFTWARE_MASK);
 636
 637         ipath_dbg("%s", dd->ipath_boardversion);
 638
 639 done:
 640         return ret;
 641 }
 642
 643
 644 /**
 645  * ipath_init_chip - do the actual initialization sequence on the chip
 646  * @dd: the infinipath device
 647  * @reinit: reinitializing, so don't allocate new memory
 648  *
 649  * Do the actual initialization sequence on the chip.  This is done
 650  * both from the init routine called from the PCI infrastructure, and
 651  * when we reset the chip, or detect that it was reset internally,
 652  * or it's administratively re-enabled.
 653  *
 654  * Memory allocation here and in called routines is only done in
 655  * the first case (reinit == 0).  We have to be careful, because even
 656  * without memory allocation, we need to re-write all the chip registers
 657  * TIDs, etc. after the reset or enable has completed.
 658  */
 659 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
 660 {
 661         int ret = 0;
 662         u32 val32, kpiobufs;
 663         u32 piobufs, uports;
 664         u64 val;
 665         struct ipath_portdata *pd = NULL; /* keep gcc4 happy */
 666         gfp_t gfp_flags = GFP_USER | __GFP_COMP;
 667         unsigned long flags;
 668
 669         ret = init_housekeeping(dd, &pd, reinit);
 670         if (ret)
 671                 goto done;
 672
 673         /*
 674          * we ignore most issues after reporting them, but have to specially
 675          * handle hardware-disabled chips.
 676          */
 677         if (ret == 2) {
 678                 /* unique error, known to ipath_init_one */
 679                 ret = -EPERM;
 680                 goto done;
 681         }
 682
 683         /*
 684          * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
 685          * but then it no longer nicely fits power of two, and since
 686          * we now use routines that backend onto __get_free_pages, the
 687          * rest would be wasted.
 688          */
 689         dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt;
 690         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
 691                          dd->ipath_rcvhdrcnt);
 692
 693         /*
 694          * Set up the shadow copies of the piobufavail registers,
 695          * which we compare against the chip registers for now, and
 696          * the in memory DMA'ed copies of the registers.  This has to
 697          * be done early, before we calculate lastport, etc.
 698          */
 699         piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
 700         /*
 701          * calc number of pioavail registers, and save it; we have 2
 702          * bits per buffer.
 703          */
 704         dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
 705                 / (sizeof(u64) * BITS_PER_BYTE / 2);
 706         uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
 707         if (ipath_kpiobufs == 0) {
 708                 /* not set by user (this is default) */
 709                 if (piobufs > 144)
 710                         kpiobufs = 32;
 711                 else
 712                         kpiobufs = 16;
 713         }
 714         else
 715                 kpiobufs = ipath_kpiobufs;
 716
 717         if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) {
 718                 int i = (int) piobufs -
 719                         (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
 720                 if (i < 0)
 721                         i = 0;
 722                 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
 723                          "%d for kernel leaves too few for %d user ports "
 724                          "(%d each); using %u\n", kpiobufs,
 725                          piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
 726                 /*
 727                  * shouldn't change ipath_kpiobufs, because could be
 728                  * different for different devices...
 729                  */
 730                 kpiobufs = i;
 731         }
 732         dd->ipath_lastport_piobuf = piobufs - kpiobufs;
 733         dd->ipath_pbufsport =
 734                 uports ? dd->ipath_lastport_piobuf / uports : 0;
 735         val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports);
 736         if (val32 > 0) {
 737                 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
 738                           "add to kernel\n", dd->ipath_pbufsport, val32);
 739                 dd->ipath_lastport_piobuf -= val32;
 740                 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
 741                           dd->ipath_pbufsport, val32);
 742         }
 743         dd->ipath_lastpioindex = dd->ipath_lastport_piobuf;
 744         ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
 745                    "each for %u user ports\n", kpiobufs,
 746                    piobufs, dd->ipath_pbufsport, uports);
 747
 748         dd->ipath_f_early_init(dd);
 749         /*
 750          * cancel any possible active sends from early driver load.
 751          * Follows early_init because some chips have to initialize
 752          * PIO buffers in early_init to avoid false parity errors.
 753          */
 754         ipath_cancel_sends(dd, 0);
 755
 756         /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
 757          * done after early_init */
 758         dd->ipath_hdrqlast =
 759                 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
 760         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
 761                          dd->ipath_rcvhdrentsize);
 762         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
 763                          dd->ipath_rcvhdrsize);
 764
 765         if (!reinit) {
 766                 ret = init_pioavailregs(dd);
 767                 init_shadow_tids(dd);
 768                 if (ret)
 769                         goto done;
 770         }
 771
 772         (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
 773                                dd->ipath_pioavailregs_phys);
 774         /*
 775          * this is to detect s/w errors, which the h/w works around by
 776          * ignoring the low 6 bits of address, if it wasn't aligned.
 777          */
 778         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
 779         if (val != dd->ipath_pioavailregs_phys) {
 780                 ipath_dev_err(dd, "Catastrophic software error, "
 781                               "SendPIOAvailAddr written as %lx, "
 782                               "read back as %llx\n",
 783                               (unsigned long) dd->ipath_pioavailregs_phys,
 784                               (unsigned long long) val);
 785                 ret = -EINVAL;
 786                 goto done;
 787         }
 788
 789         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
 790
 791         /*
 792          * make sure we are not in freeze, and PIO send enabled, so
 793          * writes to pbc happen
 794          */
 795         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
 796         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 797                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 798         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 799
 800         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 801         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE;
 802         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 803         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 804         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 805
 806         /*
 807          * before error clears, since we expect serdes pll errors during
 808          * this, the first time after reset
 809          */
 810         if (bringup_link(dd)) {
 811                 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
 812                 ret = -ENETDOWN;
 813                 goto done;
 814         }
 815
 816         /*
 817          * clear any "expected" hwerrs from reset and/or initialization
 818          * clear any that aren't enabled (at least this once), and then
 819          * set the enable mask
 820          */
 821         dd->ipath_f_init_hwerrors(dd);
 822         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 823                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 824         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 825                          dd->ipath_hwerrmask);
 826
 827         /* clear all */
 828         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
 829         /* enable errors that are masked, at least this first time. */
 830         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
 831                          ~dd->ipath_maskederrs);
 832         dd->ipath_errormask = ipath_read_kreg64(dd,
 833                 dd->ipath_kregs->kr_errormask);
 834         /* clear any interrupts up to this point (ints still not enabled) */
 835         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
 836
 837         /*
 838          * Set up the port 0 (kernel) rcvhdr q and egr TIDs.  If doing
 839          * re-init, the simplest way to handle this is to free
 840          * existing, and re-allocate.
 841          * Need to re-create rest of port 0 portdata as well.
 842          */
 843         if (reinit) {
 844                 /* Alloc and init new ipath_portdata for port0,
 845                  * Then free old pd. Could lead to fragmentation, but also
 846                  * makes later support for hot-swap easier.
 847                  */
 848                 struct ipath_portdata *npd;
 849                 npd = create_portdata0(dd);
 850                 if (npd) {
 851                         ipath_free_pddata(dd, pd);
 852                         dd->ipath_pd[0] = pd = npd;
 853                 } else {
 854                         ipath_dev_err(dd, "Unable to allocate portdata for"
 855                                       "  port 0, failing\n");
 856                         ret = -ENOMEM;
 857                         goto done;
 858                 }
 859         }
 860         dd->ipath_f_tidtemplate(dd);
 861         ret = ipath_create_rcvhdrq(dd, pd);
 862         if (!ret) {
 863                 dd->ipath_hdrqtailptr =
 864                         (volatile __le64 *)pd->port_rcvhdrtail_kvaddr;
 865                 ret = create_port0_egr(dd);
 866         }
 867         if (ret)
 868                 ipath_dev_err(dd, "failed to allocate port 0 (kernel) "
 869                               "rcvhdrq and/or egr bufs\n");
 870         else
 871                 enable_chip(dd, pd, reinit);
 872
 873
 874         if (!ret && !reinit) {
 875             /* used when we close a port, for DMA already in flight at close */
 876                 dd->ipath_dummy_hdrq = dma_alloc_coherent(
 877                         &dd->pcidev->dev, pd->port_rcvhdrq_size,
 878                         &dd->ipath_dummy_hdrq_phys,
 879                         gfp_flags);
 880                 if (!dd->ipath_dummy_hdrq ) {
 881                         dev_info(&dd->pcidev->dev,
 882                                 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
 883                                 pd->port_rcvhdrq_size);
 884                         /* fallback to just 0'ing */
 885                         dd->ipath_dummy_hdrq_phys = 0UL;
 886                 }
 887         }
 888
 889         /*
 890          * cause retrigger of pending interrupts ignored during init,
 891          * even if we had errors
 892          */
 893         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
 894
 895         if(!dd->ipath_stats_timer_active) {
 896                 /*
 897                  * first init, or after an admin disable/enable
 898                  * set up stats retrieval timer, even if we had errors
 899                  * in last portion of setup
 900                  */
 901                 init_timer(&dd->ipath_stats_timer);
 902                 dd->ipath_stats_timer.function = ipath_get_faststats;
 903                 dd->ipath_stats_timer.data = (unsigned long) dd;
 904                 /* every 5 seconds; */
 905                 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
 906                 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
 907                 add_timer(&dd->ipath_stats_timer);
 908                 dd->ipath_stats_timer_active = 1;
 909         }
 910
 911         /* Set up HoL state */
 912         init_timer(&dd->ipath_hol_timer);
 913         dd->ipath_hol_timer.function = ipath_hol_event;
 914         dd->ipath_hol_timer.data = (unsigned long)dd;
 915         dd->ipath_hol_state = IPATH_HOL_UP;
 916
 917 done:
 918         if (!ret) {
 919                 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
 920                 if (!dd->ipath_f_intrsetup(dd)) {
 921                         /* now we can enable all interrupts from the chip */
 922                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
 923                                          -1LL);
 924                         /* force re-interrupt of any pending interrupts. */
 925                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
 926                                          0ULL);
 927                         /* chip is usable; mark it as initialized */
 928                         *dd->ipath_statusp |= IPATH_STATUS_INITTED;
 929                 } else
 930                         ipath_dev_err(dd, "No interrupts enabled, couldn't "
 931                                       "setup interrupt address\n");
 932
 933                 if (dd->ipath_cfgports > ipath_stats.sps_nports)
 934                         /*
 935                          * sps_nports is a global, so, we set it to
 936                          * the highest number of ports of any of the
 937                          * chips we find; we never decrement it, at
 938                          * least for now.  Since this might have changed
 939                          * over disable/enable or prior to reset, always
 940                          * do the check and potentially adjust.
 941                          */
 942                         ipath_stats.sps_nports = dd->ipath_cfgports;
 943         } else
 944                 ipath_dbg("Failed (%d) to initialize chip\n", ret);
 945
 946         /* if ret is non-zero, we probably should do some cleanup
 947            here... */
 948         return ret;
 949 }
 950
 951 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
 952 {
 953         struct ipath_devdata *dd;
 954         unsigned long flags;
 955         unsigned short val;
 956         int ret;
 957
 958         ret = ipath_parse_ushort(str, &val);
 959
 960         spin_lock_irqsave(&ipath_devs_lock, flags);
 961
 962         if (ret < 0)
 963                 goto bail;
 964
 965         if (val == 0) {
 966                 ret = -EINVAL;
 967                 goto bail;
 968         }
 969
 970         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
 971                 if (dd->ipath_kregbase)
 972                         continue;
 973                 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
 974                            (dd->ipath_cfgports *
 975                             IPATH_MIN_USER_PORT_BUFCNT)))
 976                 {
 977                         ipath_dev_err(
 978                                 dd,
 979                                 "Allocating %d PIO bufs for kernel leaves "
 980                                 "too few for %d user ports (%d each)\n",
 981                                 val, dd->ipath_cfgports - 1,
 982                                 IPATH_MIN_USER_PORT_BUFCNT);
 983                         ret = -EINVAL;
 984                         goto bail;
 985                 }
 986                 dd->ipath_lastport_piobuf =
 987                         dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
 988         }
 989
 990         ipath_kpiobufs = val;
 991         ret = 0;
 992 bail:
 993         spin_unlock_irqrestore(&ipath_devs_lock, flags);
 994
 995         return ret;
 996 }