2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/vmalloc.h>
38 #include "ipath_kernel.h"
39 #include "ipath_common.h"
42 * min buffers we want to have per port, after driver
44 #define IPATH_MIN_USER_PORT_BUFCNT 8
47 * Number of ports we are configured to use (to allow for more pio
48 * buffers per port, etc.) Zero means use chip value.
50 static ushort ipath_cfgports;
52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
56 * Number of buffers reserved for driver (verbs and layered drivers.)
57 * Reserved at end of buffer list. Initialized based on
58 * number of PIO buffers if not set via module interface.
59 * The problem with this is that it's global, but we'll use different
60 * numbers for different chip types. So the default value is not
61 * very useful. I've redefined it for the 1.3 release so that it's
62 * zero unless set by the user to something else, in which case we
65 static ushort ipath_kpiobufs;
67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
70 &ipath_kpiobufs, S_IWUSR | S_IRUGO);
71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
74 * create_port0_egr - allocate the eager TID buffers
75 * @dd: the infinipath device
77 * This code is now quite different for user and kernel, because
78 * the kernel uses skb's, for the accelerated network performance.
79 * This is the kernel (port0) version.
81 * Allocate the eager TID buffers and program them into infinipath.
82 * We use the network layer alloc_skb() allocator to allocate the
83 * memory, and either use the buffers as is for things like verbs
84 * packets, or pass the buffers up to the ipath layered driver and
85 * thence the network layer, replacing them as we do so (see
88 static int create_port0_egr(struct ipath_devdata *dd)
91 struct ipath_skbinfo *skbinfo;
94 egrcnt = dd->ipath_rcvegrcnt;
96 skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
97 if (skbinfo == NULL) {
98 ipath_dev_err(dd, "allocation error for eager TID "
103 for (e = 0; e < egrcnt; e++) {
105 * This is a bit tricky in that we allocate extra
106 * space for 2 bytes of the 14 byte ethernet header.
107 * These two bytes are passed in the ipath header so
108 * the rest of the data is word aligned. We allocate
109 * 4 bytes so that the data buffer stays word aligned.
110 * See ipath_kreceive() for more details.
112 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
113 if (!skbinfo[e].skb) {
114 ipath_dev_err(dd, "SKB allocation error for "
115 "eager TID %u\n", e);
117 dev_kfree_skb(skbinfo[--e].skb);
124 * After loop above, so we can test non-NULL to see if ready
125 * to use at receive, etc.
127 dd->ipath_port0_skbinfo = skbinfo;
129 for (e = 0; e < egrcnt; e++) {
130 dd->ipath_port0_skbinfo[e].phys =
131 ipath_map_single(dd->pcidev,
132 dd->ipath_port0_skbinfo[e].skb->data,
133 dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
134 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
135 ((char __iomem *) dd->ipath_kregbase +
136 dd->ipath_rcvegrbase),
137 RCVHQ_RCV_TYPE_EAGER,
138 dd->ipath_port0_skbinfo[e].phys);
147 static int bringup_link(struct ipath_devdata *dd)
152 /* hold IBC in reset */
153 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
154 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
158 * Note that prior to try 14 or 15 of IB, the credit scaling
159 * wasn't working, because it was swapped for writes with the
160 * 1 bit default linkstate field
163 /* ignore pbc and align word */
164 val = dd->ipath_piosize2k - 2 * sizeof(u32);
166 * for ICRC, which we only send in diag test pkt mode, and we
167 * don't need to worry about that for mtu
171 * Set the IBC maxpktlength to the size of our pio buffers the
172 * maxpktlength is in words. This is *not* the IB data MTU.
174 ibc = (val / sizeof(u32)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
176 ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
178 * How often flowctrl sent. More or less in usecs; balance against
179 * watermark value, so that in theory senders always get a flow
180 * control update in time to not let the IB link go idle.
182 ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
183 /* max error tolerance */
184 ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
185 /* use "real" buffer space for */
186 ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
187 /* IB credit flow control. */
188 ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
189 /* initially come up waiting for TS1, without sending anything. */
190 dd->ipath_ibcctrl = ibc;
192 * Want to start out with both LINKCMD and LINKINITCMD in NOP
193 * (0 and 0). Don't put linkinitcmd in ipath_ibcctrl, want that
196 ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
197 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
198 ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
199 (unsigned long long) ibc);
200 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
202 // be sure chip saw it
203 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
205 ret = dd->ipath_f_bringup_serdes(dd);
208 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
212 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
213 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
220 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
222 struct ipath_portdata *pd = NULL;
224 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
228 /* The port 0 pkey table is used by the layer interface. */
229 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
234 static int init_chip_first(struct ipath_devdata *dd,
235 struct ipath_portdata **pdp)
237 struct ipath_portdata *pd = NULL;
242 * skip cfgports stuff because we are not allocating memory,
243 * and we don't want problems if the portcnt changed due to
244 * cfgports. We do still check and report a difference, if
245 * not same (should be impossible).
248 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
250 dd->ipath_cfgports = dd->ipath_portcnt;
251 else if (ipath_cfgports <= dd->ipath_portcnt) {
252 dd->ipath_cfgports = ipath_cfgports;
253 ipath_dbg("Configured to use %u ports out of %u in chip\n",
254 dd->ipath_cfgports, dd->ipath_portcnt);
256 dd->ipath_cfgports = dd->ipath_portcnt;
257 ipath_dbg("Tried to configured to use %u ports; chip "
258 "only supports %u\n", ipath_cfgports,
262 * Allocate full portcnt array, rather than just cfgports, because
263 * cleanup iterates across all possible ports.
265 dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
269 ipath_dev_err(dd, "Unable to allocate portdata array, "
275 pd = create_portdata0(dd);
277 ipath_dev_err(dd, "Unable to allocate portdata for port "
282 dd->ipath_pd[0] = pd;
284 dd->ipath_rcvtidcnt =
285 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
286 dd->ipath_rcvtidbase =
287 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
288 dd->ipath_rcvegrcnt =
289 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
290 dd->ipath_rcvegrbase =
291 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
293 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
294 dd->ipath_piobufbase =
295 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
296 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
297 dd->ipath_piosize2k = val & ~0U;
298 dd->ipath_piosize4k = val >> 32;
300 * Note: the chips support a maximum MTU of 4096, but the driver
301 * hasn't implemented this feature yet, so set the initial value
304 dd->ipath_ibmtu = 2048;
305 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
306 dd->ipath_piobcnt2k = val & ~0U;
307 dd->ipath_piobcnt4k = val >> 32;
308 dd->ipath_pio2kbase =
309 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
310 (dd->ipath_piobufbase & 0xffffffff));
311 if (dd->ipath_piobcnt4k) {
312 dd->ipath_pio4kbase = (u32 __iomem *)
313 (((char __iomem *) dd->ipath_kregbase) +
314 (dd->ipath_piobufbase >> 32));
316 * 4K buffers take 2 pages; we use roundup just to be
317 * paranoid; we calculate it once here, rather than on
320 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
322 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
324 dd->ipath_piobcnt2k, dd->ipath_piosize2k,
325 dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
326 dd->ipath_piosize4k, dd->ipath_pio4kbase,
329 else ipath_dbg("%u 2k piobufs @ %p\n",
330 dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
332 spin_lock_init(&dd->ipath_tid_lock);
333 spin_lock_init(&dd->ipath_sendctrl_lock);
334 spin_lock_init(&dd->ipath_gpio_lock);
335 spin_lock_init(&dd->ipath_eep_st_lock);
336 mutex_init(&dd->ipath_eep_lock);
344 * init_chip_reset - re-initialize after a reset, or enable
345 * @dd: the infinipath device
346 * @pdp: output for port data
348 * sanity check at least some of the values after reset, and
349 * ensure no receive or transmit (explictly, in case reset
352 static int init_chip_reset(struct ipath_devdata *dd,
353 struct ipath_portdata **pdp)
357 *pdp = dd->ipath_pd[0];
358 /* ensure chip does no sends or receives while we re-initialize */
359 dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U;
360 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, dd->ipath_rcvctrl);
361 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
362 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, dd->ipath_control);
364 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
365 if (dd->ipath_portcnt != rtmp)
366 dev_info(&dd->pcidev->dev, "portcnt was %u before "
367 "reset, now %u, using original\n",
368 dd->ipath_portcnt, rtmp);
369 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
370 if (rtmp != dd->ipath_rcvtidcnt)
371 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
372 "reset, now %u, using original\n",
373 dd->ipath_rcvtidcnt, rtmp);
374 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
375 if (rtmp != dd->ipath_rcvtidbase)
376 dev_info(&dd->pcidev->dev, "tidbase was %u before "
377 "reset, now %u, using original\n",
378 dd->ipath_rcvtidbase, rtmp);
379 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
380 if (rtmp != dd->ipath_rcvegrcnt)
381 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
382 "reset, now %u, using original\n",
383 dd->ipath_rcvegrcnt, rtmp);
384 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
385 if (rtmp != dd->ipath_rcvegrbase)
386 dev_info(&dd->pcidev->dev, "egrbase was %u before "
387 "reset, now %u, using original\n",
388 dd->ipath_rcvegrbase, rtmp);
393 static int init_pioavailregs(struct ipath_devdata *dd)
397 dd->ipath_pioavailregs_dma = dma_alloc_coherent(
398 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
400 if (!dd->ipath_pioavailregs_dma) {
401 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
408 * we really want L2 cache aligned, but for current CPUs of
409 * interest, they are the same.
411 dd->ipath_statusp = (u64 *)
412 ((char *)dd->ipath_pioavailregs_dma +
413 ((2 * L1_CACHE_BYTES +
414 dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
415 /* copy the current value now that it's really allocated */
416 *dd->ipath_statusp = dd->_ipath_status;
418 * setup buffer to hold freeze msg, accessible to apps,
421 dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
423 dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
432 * init_shadow_tids - allocate the shadow TID array
433 * @dd: the infinipath device
435 * allocate the shadow TID array, so we can ipath_munlock previous
436 * entries. It may make more sense to move the pageshadow to the
437 * port data structure, so we only allocate memory for ports actually
438 * in use, since we at 8k per port, now.
440 static void init_shadow_tids(struct ipath_devdata *dd)
445 pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
446 sizeof(struct page *));
448 ipath_dev_err(dd, "failed to allocate shadow page * "
449 "array, no expected sends!\n");
450 dd->ipath_pageshadow = NULL;
454 addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
457 ipath_dev_err(dd, "failed to allocate shadow dma handle "
458 "array, no expected sends!\n");
459 vfree(dd->ipath_pageshadow);
460 dd->ipath_pageshadow = NULL;
464 memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt *
465 sizeof(struct page *));
467 dd->ipath_pageshadow = pages;
468 dd->ipath_physshadow = addrs;
471 static void enable_chip(struct ipath_devdata *dd,
472 struct ipath_portdata *pd, int reinit)
479 init_waitqueue_head(&ipath_state_wait);
481 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
484 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
485 /* Enable PIO send, and update of PIOavail regs to memory. */
486 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
487 INFINIPATH_S_PIOBUFAVAILUPD;
488 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
489 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
490 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
493 * enable port 0 receive, and receive interrupt. other ports
494 * done as user opens and inits them.
496 dd->ipath_rcvctrl = (1ULL << dd->ipath_r_tailupd_shift) |
497 (1ULL << dd->ipath_r_portenable_shift) |
498 (1ULL << dd->ipath_r_intravail_shift);
499 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
503 * now ready for use. this should be cleared whenever we
504 * detect a reset, or initiate one.
506 dd->ipath_flags |= IPATH_INITTED;
509 * init our shadow copies of head from tail values, and write
510 * head values to match.
512 val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
513 (void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
515 /* Initialize so we interrupt on next packet received */
516 (void)ipath_write_ureg(dd, ur_rcvhdrhead,
517 dd->ipath_rhdrhead_intr_off |
518 dd->ipath_pd[0]->port_head, 0);
521 * by now pioavail updates to memory should have occurred, so
522 * copy them into our working/shadow registers; this is in
523 * case something went wrong with abort, but mostly to get the
524 * initial values of the generation bit correct.
526 for (i = 0; i < dd->ipath_pioavregs; i++) {
530 * Chip Errata bug 6641; even and odd qwords>3 are swapped.
534 val = dd->ipath_pioavailregs_dma[i - 1];
536 val = dd->ipath_pioavailregs_dma[i + 1];
539 val = dd->ipath_pioavailregs_dma[i];
540 dd->ipath_pioavailshadow[i] = le64_to_cpu(val);
542 /* can get counters, stats, etc. */
543 dd->ipath_flags |= IPATH_PRESENT;
546 static int init_housekeeping(struct ipath_devdata *dd,
547 struct ipath_portdata **pdp, int reinit)
553 * have to clear shadow copies of registers at init that are
554 * not otherwise set here, or all kinds of bizarre things
555 * happen with driver on chip reset
557 dd->ipath_rcvhdrsize = 0;
560 * Don't clear ipath_flags as 8bit mode was set before
561 * entering this func. However, we do set the linkstate to
562 * unknown, so we can watch for a transition.
563 * PRESENT is set because we want register reads to work,
564 * and the kernel infrastructure saw it in config space;
565 * We clear it if we have failures.
567 dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
568 dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
569 IPATH_LINKDOWN | IPATH_LINKINIT);
571 ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
573 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
576 * set up fundamental info we need to use the chip; we assume
577 * if the revision reg and these regs are OK, we don't need to
578 * special case the rest
581 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
583 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
585 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
586 ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
587 "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
588 dd->ipath_uregbase, dd->ipath_cregbase);
589 if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
590 || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
591 || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
592 || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
593 ipath_dev_err(dd, "Register read failures from chip, "
594 "giving up initialization\n");
595 dd->ipath_flags &= ~IPATH_PRESENT;
601 /* clear diagctrl register, in case diags were running and crashed */
602 ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
604 /* clear the initial reset flag, in case first driver load */
605 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
609 ret = init_chip_reset(dd, pdp);
611 ret = init_chip_first(dd, pdp);
616 ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, "
617 "%u egrtids\n", (unsigned long long) dd->ipath_revision,
618 dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt,
619 dd->ipath_rcvegrcnt);
621 if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
622 INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
623 ipath_dev_err(dd, "Driver only handles version %d, "
624 "chip swversion is %d (%llx), failng\n",
625 IPATH_CHIP_SWVERSION,
626 (int)(dd->ipath_revision >>
627 INFINIPATH_R_SOFTWARE_SHIFT) &
628 INFINIPATH_R_SOFTWARE_MASK,
629 (unsigned long long) dd->ipath_revision);
633 dd->ipath_majrev = (u8) ((dd->ipath_revision >>
634 INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
635 INFINIPATH_R_CHIPREVMAJOR_MASK);
636 dd->ipath_minrev = (u8) ((dd->ipath_revision >>
637 INFINIPATH_R_CHIPREVMINOR_SHIFT) &
638 INFINIPATH_R_CHIPREVMINOR_MASK);
639 dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
640 INFINIPATH_R_BOARDID_SHIFT) &
641 INFINIPATH_R_BOARDID_MASK);
643 ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
645 snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
646 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
648 IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
649 (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
650 INFINIPATH_R_ARCH_MASK,
651 dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
652 (unsigned)(dd->ipath_revision >>
653 INFINIPATH_R_SOFTWARE_SHIFT) &
654 INFINIPATH_R_SOFTWARE_MASK);
656 ipath_dbg("%s", dd->ipath_boardversion);
664 * ipath_init_chip - do the actual initialization sequence on the chip
665 * @dd: the infinipath device
666 * @reinit: reinitializing, so don't allocate new memory
668 * Do the actual initialization sequence on the chip. This is done
669 * both from the init routine called from the PCI infrastructure, and
670 * when we reset the chip, or detect that it was reset internally,
671 * or it's administratively re-enabled.
673 * Memory allocation here and in called routines is only done in
674 * the first case (reinit == 0). We have to be careful, because even
675 * without memory allocation, we need to re-write all the chip registers
676 * TIDs, etc. after the reset or enable has completed.
678 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
684 struct ipath_portdata *pd = NULL; /* keep gcc4 happy */
685 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
688 ret = init_housekeeping(dd, &pd, reinit);
693 * we ignore most issues after reporting them, but have to specially
694 * handle hardware-disabled chips.
697 /* unique error, known to ipath_init_one */
703 * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
704 * but then it no longer nicely fits power of two, and since
705 * we now use routines that backend onto __get_free_pages, the
706 * rest would be wasted.
708 dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt;
709 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
710 dd->ipath_rcvhdrcnt);
713 * Set up the shadow copies of the piobufavail registers,
714 * which we compare against the chip registers for now, and
715 * the in memory DMA'ed copies of the registers. This has to
716 * be done early, before we calculate lastport, etc.
718 piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
720 * calc number of pioavail registers, and save it; we have 2
723 dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
724 / (sizeof(u64) * BITS_PER_BYTE / 2);
725 uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
726 if (ipath_kpiobufs == 0) {
727 /* not set by user (this is default) */
734 kpiobufs = ipath_kpiobufs;
736 if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) {
737 int i = (int) piobufs -
738 (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
741 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
742 "%d for kernel leaves too few for %d user ports "
743 "(%d each); using %u\n", kpiobufs,
744 piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
746 * shouldn't change ipath_kpiobufs, because could be
747 * different for different devices...
751 dd->ipath_lastport_piobuf = piobufs - kpiobufs;
752 dd->ipath_pbufsport =
753 uports ? dd->ipath_lastport_piobuf / uports : 0;
754 val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports);
756 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
757 "add to kernel\n", dd->ipath_pbufsport, val32);
758 dd->ipath_lastport_piobuf -= val32;
759 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
760 dd->ipath_pbufsport, val32);
762 dd->ipath_lastpioindex = dd->ipath_lastport_piobuf;
763 ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
764 "each for %u user ports\n", kpiobufs,
765 piobufs, dd->ipath_pbufsport, uports);
767 dd->ipath_f_early_init(dd);
769 * cancel any possible active sends from early driver load.
770 * Follows early_init because some chips have to initialize
771 * PIO buffers in early_init to avoid false parity errors.
773 ipath_cancel_sends(dd, 0);
775 /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
776 * done after early_init */
778 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
779 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
780 dd->ipath_rcvhdrentsize);
781 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
782 dd->ipath_rcvhdrsize);
785 ret = init_pioavailregs(dd);
786 init_shadow_tids(dd);
791 (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
792 dd->ipath_pioavailregs_phys);
794 * this is to detect s/w errors, which the h/w works around by
795 * ignoring the low 6 bits of address, if it wasn't aligned.
797 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
798 if (val != dd->ipath_pioavailregs_phys) {
799 ipath_dev_err(dd, "Catastrophic software error, "
800 "SendPIOAvailAddr written as %lx, "
801 "read back as %llx\n",
802 (unsigned long) dd->ipath_pioavailregs_phys,
803 (unsigned long long) val);
808 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
811 * make sure we are not in freeze, and PIO send enabled, so
812 * writes to pbc happen
814 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
815 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
816 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
817 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
819 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
820 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE;
821 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
822 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
823 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
826 * before error clears, since we expect serdes pll errors during
827 * this, the first time after reset
829 if (bringup_link(dd)) {
830 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
836 * clear any "expected" hwerrs from reset and/or initialization
837 * clear any that aren't enabled (at least this once), and then
838 * set the enable mask
840 dd->ipath_f_init_hwerrors(dd);
841 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
842 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
843 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
844 dd->ipath_hwerrmask);
847 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
848 /* enable errors that are masked, at least this first time. */
849 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
850 ~dd->ipath_maskederrs);
851 dd->ipath_errormask = ipath_read_kreg64(dd,
852 dd->ipath_kregs->kr_errormask);
853 /* clear any interrupts up to this point (ints still not enabled) */
854 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
857 * Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing
858 * re-init, the simplest way to handle this is to free
859 * existing, and re-allocate.
860 * Need to re-create rest of port 0 portdata as well.
863 /* Alloc and init new ipath_portdata for port0,
864 * Then free old pd. Could lead to fragmentation, but also
865 * makes later support for hot-swap easier.
867 struct ipath_portdata *npd;
868 npd = create_portdata0(dd);
870 ipath_free_pddata(dd, pd);
871 dd->ipath_pd[0] = pd = npd;
873 ipath_dev_err(dd, "Unable to allocate portdata for"
874 " port 0, failing\n");
879 dd->ipath_f_tidtemplate(dd);
880 ret = ipath_create_rcvhdrq(dd, pd);
882 dd->ipath_hdrqtailptr =
883 (volatile __le64 *)pd->port_rcvhdrtail_kvaddr;
884 ret = create_port0_egr(dd);
887 ipath_dev_err(dd, "failed to allocate port 0 (kernel) "
888 "rcvhdrq and/or egr bufs\n");
890 enable_chip(dd, pd, reinit);
893 if (!ret && !reinit) {
894 /* used when we close a port, for DMA already in flight at close */
895 dd->ipath_dummy_hdrq = dma_alloc_coherent(
896 &dd->pcidev->dev, pd->port_rcvhdrq_size,
897 &dd->ipath_dummy_hdrq_phys,
899 if (!dd->ipath_dummy_hdrq ) {
900 dev_info(&dd->pcidev->dev,
901 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
902 pd->port_rcvhdrq_size);
903 /* fallback to just 0'ing */
904 dd->ipath_dummy_hdrq_phys = 0UL;
909 * cause retrigger of pending interrupts ignored during init,
910 * even if we had errors
912 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
914 if(!dd->ipath_stats_timer_active) {
916 * first init, or after an admin disable/enable
917 * set up stats retrieval timer, even if we had errors
918 * in last portion of setup
920 init_timer(&dd->ipath_stats_timer);
921 dd->ipath_stats_timer.function = ipath_get_faststats;
922 dd->ipath_stats_timer.data = (unsigned long) dd;
923 /* every 5 seconds; */
924 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
925 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
926 add_timer(&dd->ipath_stats_timer);
927 dd->ipath_stats_timer_active = 1;
932 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
933 if (!dd->ipath_f_intrsetup(dd)) {
934 /* now we can enable all interrupts from the chip */
935 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
937 /* force re-interrupt of any pending interrupts. */
938 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
940 /* chip is usable; mark it as initialized */
941 *dd->ipath_statusp |= IPATH_STATUS_INITTED;
943 ipath_dev_err(dd, "No interrupts enabled, couldn't "
944 "setup interrupt address\n");
946 if (dd->ipath_cfgports > ipath_stats.sps_nports)
948 * sps_nports is a global, so, we set it to
949 * the highest number of ports of any of the
950 * chips we find; we never decrement it, at
951 * least for now. Since this might have changed
952 * over disable/enable or prior to reset, always
953 * do the check and potentially adjust.
955 ipath_stats.sps_nports = dd->ipath_cfgports;
957 ipath_dbg("Failed (%d) to initialize chip\n", ret);
959 /* if ret is non-zero, we probably should do some cleanup
964 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
966 struct ipath_devdata *dd;
971 ret = ipath_parse_ushort(str, &val);
973 spin_lock_irqsave(&ipath_devs_lock, flags);
983 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
984 if (dd->ipath_kregbase)
986 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
987 (dd->ipath_cfgports *
988 IPATH_MIN_USER_PORT_BUFCNT)))
992 "Allocating %d PIO bufs for kernel leaves "
993 "too few for %d user ports (%d each)\n",
994 val, dd->ipath_cfgports - 1,
995 IPATH_MIN_USER_PORT_BUFCNT);
999 dd->ipath_lastport_piobuf =
1000 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
1003 ipath_kpiobufs = val;
1006 spin_unlock_irqrestore(&ipath_devs_lock, flags);