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   1 /*
   2  * linux/drivers/ide/pci/sis5513.c      Version 0.16ac+vp       Jun 18, 2003
   3  *
   4  * Copyright (C) 1999-2000      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2002           Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
   6  * Copyright (C) 2003           Vojtech Pavlik <vojtech@suse.cz>
   7  * May be copied or modified under the terms of the GNU General Public License
   8  *
   9  *
  10  * Thanks :
  11  *
  12  * SiS Taiwan           : for direct support and hardware.
  13  * Daniela Engert       : for initial ATA100 advices and numerous others.
  14  * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt        :
  15  *                        for checking code correctness, providing patches.
  16  *
  17  *
  18  * Original tests and design on the SiS620 chipset.
  19  * ATA100 tests and design on the SiS735 chipset.
  20  * ATA16/33 support from specs
  21  * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
  22  * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
  23  *
  24  * Documentation:
  25  *      SiS chipset documentation available under NDA to companies only
  26  *      (not to individuals).
  27  */
  28
  29 /*
  30  * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
  31  * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
  32  * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
  33  *
  34  * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
  35  * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
  36  * can figure out that we have a more modern and more capable 5513 by looking
  37  * for the respective NorthBridge IDs.
  38  *
  39  * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
  40  * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
  41  * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
  42  * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
  43  * bits, changing its device id to the true one - 5517 for 961 and 5518 for
  44  * 962/963.
  45  */
  46
  47 #include <linux/config.h>
  48 #include <linux/types.h>
  49 #include <linux/module.h>
  50 #include <linux/kernel.h>
  51 #include <linux/delay.h>
  52 #include <linux/timer.h>
  53 #include <linux/mm.h>
  54 #include <linux/ioport.h>
  55 #include <linux/blkdev.h>
  56 #include <linux/hdreg.h>
  57
  58 #include <linux/interrupt.h>
  59 #include <linux/pci.h>
  60 #include <linux/init.h>
  61 #include <linux/ide.h>
  62
  63 #include <asm/irq.h>
  64
  65 #include "ide-timing.h"
  66
  67 #define DISPLAY_SIS_TIMINGS
  68
  69 /* registers layout and init values are chipset family dependant */
  70
  71 #define ATA_16          0x01
  72 #define ATA_33          0x02
  73 #define ATA_66          0x03
  74 #define ATA_100a        0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
  75 #define ATA_100         0x05
  76 #define ATA_133a        0x06 // SiS961b with 133 support
  77 #define ATA_133         0x07 // SiS962/963
  78
  79 static u8 chipset_family;
  80
  81 /*
  82  * Devices supported
  83  */
  84 static const struct {
  85         const char *name;
  86         u16 host_id;
  87         u8 chipset_family;
  88         u8 flags;
  89 } SiSHostChipInfo[] = {
  90         { "SiS965",     PCI_DEVICE_ID_SI_965,   ATA_133  },
  91         { "SiS745",     PCI_DEVICE_ID_SI_745,   ATA_100  },
  92         { "SiS735",     PCI_DEVICE_ID_SI_735,   ATA_100  },
  93         { "SiS733",     PCI_DEVICE_ID_SI_733,   ATA_100  },
  94         { "SiS635",     PCI_DEVICE_ID_SI_635,   ATA_100  },
  95         { "SiS633",     PCI_DEVICE_ID_SI_633,   ATA_100  },
  96
  97         { "SiS730",     PCI_DEVICE_ID_SI_730,   ATA_100a },
  98         { "SiS550",     PCI_DEVICE_ID_SI_550,   ATA_100a },
  99
 100         { "SiS640",     PCI_DEVICE_ID_SI_640,   ATA_66   },
 101         { "SiS630",     PCI_DEVICE_ID_SI_630,   ATA_66   },
 102         { "SiS620",     PCI_DEVICE_ID_SI_620,   ATA_66   },
 103         { "SiS540",     PCI_DEVICE_ID_SI_540,   ATA_66   },
 104         { "SiS530",     PCI_DEVICE_ID_SI_530,   ATA_66   },
 105
 106         { "SiS5600",    PCI_DEVICE_ID_SI_5600,  ATA_33   },
 107         { "SiS5598",    PCI_DEVICE_ID_SI_5598,  ATA_33   },
 108         { "SiS5597",    PCI_DEVICE_ID_SI_5597,  ATA_33   },
 109         { "SiS5591/2",  PCI_DEVICE_ID_SI_5591,  ATA_33   },
 110         { "SiS5582",    PCI_DEVICE_ID_SI_5582,  ATA_33   },
 111         { "SiS5581",    PCI_DEVICE_ID_SI_5581,  ATA_33   },
 112
 113         { "SiS5596",    PCI_DEVICE_ID_SI_5596,  ATA_16   },
 114         { "SiS5571",    PCI_DEVICE_ID_SI_5571,  ATA_16   },
 115         { "SiS5517",    PCI_DEVICE_ID_SI_5517,  ATA_16   },
 116         { "SiS551x",    PCI_DEVICE_ID_SI_5511,  ATA_16   },
 117 };
 118
 119 /* Cycle time bits and values vary across chip dma capabilities
 120    These three arrays hold the register layout and the values to set.
 121    Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
 122
 123 /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
 124 static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
 125 static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
 126 static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
 127         {0,0,0,0,0,0,0}, /* no udma */
 128         {0,0,0,0,0,0,0}, /* no udma */
 129         {3,2,1,0,0,0,0}, /* ATA_33 */
 130         {7,5,3,2,1,0,0}, /* ATA_66 */
 131         {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
 132         {11,7,5,4,2,1,0}, /* ATA_100 */
 133         {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
 134         {15,10,7,5,3,2,1}, /* ATA_133 */
 135 };
 136 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
 137    See SiS962 data sheet for more detail */
 138 static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
 139         {0,0,0,0,0,0,0}, /* no udma */
 140         {0,0,0,0,0,0,0}, /* no udma */
 141         {2,1,1,0,0,0,0},
 142         {4,3,2,1,0,0,0},
 143         {4,3,2,1,0,0,0},
 144         {6,4,3,1,1,1,0},
 145         {9,6,4,2,2,2,2},
 146         {9,6,4,2,2,2,2},
 147 };
 148 /* Initialize time, Active time, Recovery time vary across
 149    IDE clock settings. These 3 arrays hold the register value
 150    for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
 151 static u8 ini_time_value[][8] = {
 152         {0,0,0,0,0,0,0,0},
 153         {0,0,0,0,0,0,0,0},
 154         {2,1,0,0,0,1,0,0},
 155         {4,3,1,1,1,3,1,1},
 156         {4,3,1,1,1,3,1,1},
 157         {6,4,2,2,2,4,2,2},
 158         {9,6,3,3,3,6,3,3},
 159         {9,6,3,3,3,6,3,3},
 160 };
 161 static u8 act_time_value[][8] = {
 162         {0,0,0,0,0,0,0,0},
 163         {0,0,0,0,0,0,0,0},
 164         {9,9,9,2,2,7,2,2},
 165         {19,19,19,5,4,14,5,4},
 166         {19,19,19,5,4,14,5,4},
 167         {28,28,28,7,6,21,7,6},
 168         {38,38,38,10,9,28,10,9},
 169         {38,38,38,10,9,28,10,9},
 170 };
 171 static u8 rco_time_value[][8] = {
 172         {0,0,0,0,0,0,0,0},
 173         {0,0,0,0,0,0,0,0},
 174         {9,2,0,2,0,7,1,1},
 175         {19,5,1,5,2,16,3,2},
 176         {19,5,1,5,2,16,3,2},
 177         {30,9,3,9,4,25,6,4},
 178         {40,12,4,12,5,34,12,5},
 179         {40,12,4,12,5,34,12,5},
 180 };
 181
 182 /*
 183  * Printing configuration
 184  */
 185 /* Used for chipset type printing at boot time */
 186 static char* chipset_capability[] = {
 187         "ATA", "ATA 16",
 188         "ATA 33", "ATA 66",
 189         "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
 190         "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
 191 };
 192
 193 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
 194 #include <linux/stat.h>
 195 #include <linux/proc_fs.h>
 196
 197 static u8 sis_proc = 0;
 198
 199 static struct pci_dev *bmide_dev;
 200
 201 static char* cable_type[] = {
 202         "80 pins",
 203         "40 pins"
 204 };
 205
 206 static char* recovery_time[] ={
 207         "12 PCICLK", "1 PCICLK",
 208         "2 PCICLK", "3 PCICLK",
 209         "4 PCICLK", "5 PCICLCK",
 210         "6 PCICLK", "7 PCICLCK",
 211         "8 PCICLK", "9 PCICLCK",
 212         "10 PCICLK", "11 PCICLK",
 213         "13 PCICLK", "14 PCICLK",
 214         "15 PCICLK", "15 PCICLK"
 215 };
 216
 217 static char* active_time[] = {
 218         "8 PCICLK", "1 PCICLCK",
 219         "2 PCICLK", "3 PCICLK",
 220         "4 PCICLK", "5 PCICLK",
 221         "6 PCICLK", "12 PCICLK"
 222 };
 223
 224 static char* cycle_time[] = {
 225         "Reserved", "2 CLK",
 226         "3 CLK", "4 CLK",
 227         "5 CLK", "6 CLK",
 228         "7 CLK", "8 CLK",
 229         "9 CLK", "10 CLK",
 230         "11 CLK", "12 CLK",
 231         "13 CLK", "14 CLK",
 232         "15 CLK", "16 CLK"
 233 };
 234
 235 /* Generic add master or slave info function */
 236 static char* get_drives_info (char *buffer, u8 pos)
 237 {
 238         u8 reg00, reg01, reg10, reg11; /* timing registers */
 239         u32 regdw0, regdw1;
 240         char* p = buffer;
 241
 242 /* Postwrite/Prefetch */
 243         if (chipset_family < ATA_133) {
 244                 pci_read_config_byte(bmide_dev, 0x4b, &reg00);
 245                 p += sprintf(p, "Drive %d:        Postwrite %s \t \t Postwrite %s\n",
 246                              pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
 247                              (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
 248                 p += sprintf(p, "                Prefetch  %s \t \t Prefetch  %s\n",
 249                              (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
 250                              (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
 251                 pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
 252                 pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
 253                 pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
 254                 pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
 255         } else {
 256                 u32 reg54h;
 257                 u8 drive_pci = 0x40;
 258                 pci_read_config_dword(bmide_dev, 0x54, &reg54h);
 259                 if (reg54h & 0x40000000) {
 260                         // Configuration space remapped to 0x70
 261                         drive_pci = 0x70;
 262                 }
 263                 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, &regdw0);
 264                 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, &regdw1);
 265
 266                 p += sprintf(p, "Drive %d:\n", pos);
 267         }
 268
 269
 270 /* UDMA */
 271         if (chipset_family >= ATA_133) {
 272                 p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
 273                              (regdw0 & 0x04) ? "Enabled" : "Disabled",
 274                              (regdw1 & 0x04) ? "Enabled" : "Disabled");
 275                 p += sprintf(p, "                UDMA Cycle Time    %s \t UDMA Cycle Time    %s\n",
 276                              cycle_time[(regdw0 & 0xF0) >> 4],
 277                              cycle_time[(regdw1 & 0xF0) >> 4]);
 278         } else if (chipset_family >= ATA_33) {
 279                 p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
 280                              (reg01 & 0x80) ? "Enabled" : "Disabled",
 281                              (reg11 & 0x80) ? "Enabled" : "Disabled");
 282
 283                 p += sprintf(p, "                UDMA Cycle Time    ");
 284                 switch(chipset_family) {
 285                         case ATA_33:    p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
 286                         case ATA_66:
 287                         case ATA_100a:  p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
 288                         case ATA_100:
 289                         case ATA_133a:  p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
 290                         default:        p += sprintf(p, "?"); break;
 291                 }
 292                 p += sprintf(p, " \t UDMA Cycle Time    ");
 293                 switch(chipset_family) {
 294                         case ATA_33:    p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
 295                         case ATA_66:
 296                         case ATA_100a:  p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
 297                         case ATA_100:
 298                         case ATA_133a:  p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
 299                         default:        p += sprintf(p, "?"); break;
 300                 }
 301                 p += sprintf(p, "\n");
 302         }
 303
 304
 305         if (chipset_family < ATA_133) { /* else case TODO */
 306
 307 /* Data Active */
 308                 p += sprintf(p, "                Data Active Time   ");
 309                 switch(chipset_family) {
 310                         case ATA_16: /* confirmed */
 311                         case ATA_33:
 312                         case ATA_66:
 313                         case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
 314                         case ATA_100:
 315                         case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
 316                         default: p += sprintf(p, "?"); break;
 317                 }
 318                 p += sprintf(p, " \t Data Active Time   ");
 319                 switch(chipset_family) {
 320                         case ATA_16:
 321                         case ATA_33:
 322                         case ATA_66:
 323                         case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
 324                         case ATA_100:
 325                         case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
 326                         default: p += sprintf(p, "?"); break;
 327                 }
 328                 p += sprintf(p, "\n");
 329
 330 /* Data Recovery */
 331         /* warning: may need (reg&0x07) for pre ATA66 chips */
 332                 p += sprintf(p, "                Data Recovery Time %s \t Data Recovery Time %s\n",
 333                              recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
 334         }
 335
 336         return p;
 337 }
 338
 339 static char* get_masters_info(char* buffer)
 340 {
 341         return get_drives_info(buffer, 0);
 342 }
 343
 344 static char* get_slaves_info(char* buffer)
 345 {
 346         return get_drives_info(buffer, 1);
 347 }
 348
 349 /* Main get_info, called on /proc/ide/sis reads */
 350 static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
 351 {
 352         char *p = buffer;
 353         int len;
 354         u8 reg;
 355         u16 reg2, reg3;
 356
 357         p += sprintf(p, "\nSiS 5513 ");
 358         switch(chipset_family) {
 359                 case ATA_16: p += sprintf(p, "DMA 16"); break;
 360                 case ATA_33: p += sprintf(p, "Ultra 33"); break;
 361                 case ATA_66: p += sprintf(p, "Ultra 66"); break;
 362                 case ATA_100a:
 363                 case ATA_100: p += sprintf(p, "Ultra 100"); break;
 364                 case ATA_133a:
 365                 case ATA_133: p += sprintf(p, "Ultra 133"); break;
 366                 default: p+= sprintf(p, "Unknown???"); break;
 367         }
 368         p += sprintf(p, " chipset\n");
 369         p += sprintf(p, "--------------- Primary Channel "
 370                      "---------------- Secondary Channel "
 371                      "-------------\n");
 372
 373 /* Status */
 374         pci_read_config_byte(bmide_dev, 0x4a, &reg);
 375         if (chipset_family == ATA_133) {
 376                 pci_read_config_word(bmide_dev, 0x50, &reg2);
 377                 pci_read_config_word(bmide_dev, 0x52, &reg3);
 378         }
 379         p += sprintf(p, "Channel Status: ");
 380         if (chipset_family < ATA_66) {
 381                 p += sprintf(p, "%s \t \t \t \t %s\n",
 382                              (reg & 0x04) ? "On" : "Off",
 383                              (reg & 0x02) ? "On" : "Off");
 384         } else if (chipset_family < ATA_133) {
 385                 p += sprintf(p, "%s \t \t \t \t %s \n",
 386                              (reg & 0x02) ? "On" : "Off",
 387                              (reg & 0x04) ? "On" : "Off");
 388         } else { /* ATA_133 */
 389                 p += sprintf(p, "%s \t \t \t \t %s \n",
 390                              (reg2 & 0x02) ? "On" : "Off",
 391                              (reg3 & 0x02) ? "On" : "Off");
 392         }
 393
 394 /* Operation Mode */
 395         pci_read_config_byte(bmide_dev, 0x09, &reg);
 396         p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
 397                      (reg & 0x01) ? "Native" : "Compatible",
 398                      (reg & 0x04) ? "Native" : "Compatible");
 399
 400 /* 80-pin cable ? */
 401         if (chipset_family >= ATA_133) {
 402                 p += sprintf(p, "Cable Type:     %s \t \t \t %s\n",
 403                              (reg2 & 0x01) ? cable_type[1] : cable_type[0],
 404                              (reg3 & 0x01) ? cable_type[1] : cable_type[0]);
 405         } else if (chipset_family > ATA_33) {
 406                 pci_read_config_byte(bmide_dev, 0x48, &reg);
 407                 p += sprintf(p, "Cable Type:     %s \t \t \t %s\n",
 408                              (reg & 0x10) ? cable_type[1] : cable_type[0],
 409                              (reg & 0x20) ? cable_type[1] : cable_type[0]);
 410         }
 411
 412 /* Prefetch Count */
 413         if (chipset_family < ATA_133) {
 414                 pci_read_config_word(bmide_dev, 0x4c, &reg2);
 415                 pci_read_config_word(bmide_dev, 0x4e, &reg3);
 416                 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
 417                              reg2, reg3);
 418         }
 419
 420         p = get_masters_info(p);
 421         p = get_slaves_info(p);
 422
 423         len = (p - buffer) - offset;
 424         *addr = buffer + offset;
 425
 426         return len > count ? count : len;
 427 }
 428 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
 429
 430 static u8 sis5513_ratemask (ide_drive_t *drive)
 431 {
 432         u8 rates[] = { 0, 0, 1, 2, 3, 3, 4, 4 };
 433         u8 mode = rates[chipset_family];
 434
 435         if (!eighty_ninty_three(drive))
 436                 mode = min(mode, (u8)1);
 437         return mode;
 438 }
 439
 440 /*
 441  * Configuration functions
 442  */
 443 /* Enables per-drive prefetch and postwrite */
 444 static void config_drive_art_rwp (ide_drive_t *drive)
 445 {
 446         ide_hwif_t *hwif        = HWIF(drive);
 447         struct pci_dev *dev     = hwif->pci_dev;
 448
 449         u8 reg4bh               = 0;
 450         u8 rw_prefetch          = (0x11 << drive->dn);
 451
 452         if (drive->media != ide_disk)
 453                 return;
 454         pci_read_config_byte(dev, 0x4b, &reg4bh);
 455
 456         if ((reg4bh & rw_prefetch) != rw_prefetch)
 457                 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
 458 }
 459
 460
 461 /* Set per-drive active and recovery time */
 462 static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
 463 {
 464         ide_hwif_t *hwif        = HWIF(drive);
 465         struct pci_dev *dev     = hwif->pci_dev;
 466
 467         u8                      timing, drive_pci, test1, test2;
 468
 469         u16 eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
 470         u16 xfer_pio = drive->id->eide_pio_modes;
 471
 472         config_drive_art_rwp(drive);
 473         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 474
 475         if (xfer_pio> 4)
 476                 xfer_pio = 0;
 477
 478         if (drive->id->eide_pio_iordy > 0) {
 479                 for (xfer_pio = 5;
 480                         (xfer_pio > 0) &&
 481                         (drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]);
 482                         xfer_pio--);
 483         } else {
 484                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
 485                            (drive->id->eide_pio_modes & 2) ? 0x04 :
 486                            (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
 487         }
 488
 489         timing = (xfer_pio >= pio) ? xfer_pio : pio;
 490
 491         /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
 492         drive_pci = 0x40;
 493         /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
 494         if (chipset_family >= ATA_133) {
 495                 u32 reg54h;
 496                 pci_read_config_dword(dev, 0x54, &reg54h);
 497                 if (reg54h & 0x40000000) drive_pci = 0x70;
 498                 drive_pci += ((drive->dn)*0x4);
 499         } else {
 500                 drive_pci += ((drive->dn)*0x2);
 501         }
 502
 503         /* register layout changed with newer ATA100 chips */
 504         if (chipset_family < ATA_100) {
 505                 pci_read_config_byte(dev, drive_pci, &test1);
 506                 pci_read_config_byte(dev, drive_pci+1, &test2);
 507
 508                 /* Clear active and recovery timings */
 509                 test1 &= ~0x0F;
 510                 test2 &= ~0x07;
 511
 512                 switch(timing) {
 513                         case 4:         test1 |= 0x01; test2 |= 0x03; break;
 514                         case 3:         test1 |= 0x03; test2 |= 0x03; break;
 515                         case 2:         test1 |= 0x04; test2 |= 0x04; break;
 516                         case 1:         test1 |= 0x07; test2 |= 0x06; break;
 517                         default:        break;
 518                 }
 519                 pci_write_config_byte(dev, drive_pci, test1);
 520                 pci_write_config_byte(dev, drive_pci+1, test2);
 521         } else if (chipset_family < ATA_133) {
 522                 switch(timing) { /*             active  recovery
 523                                                   v     v */
 524                         case 4:         test1 = 0x30|0x01; break;
 525                         case 3:         test1 = 0x30|0x03; break;
 526                         case 2:         test1 = 0x40|0x04; break;
 527                         case 1:         test1 = 0x60|0x07; break;
 528                         case 0:         test1 = 0x00; break;
 529                         default:        break;
 530                 }
 531                 pci_write_config_byte(dev, drive_pci, test1);
 532         } else { /* ATA_133 */
 533                 u32 test3;
 534                 pci_read_config_dword(dev, drive_pci, &test3);
 535                 test3 &= 0xc0c00fff;
 536                 if (test3 & 0x08) {
 537                         test3 |= (unsigned long)ini_time_value[ATA_133][timing] << 12;
 538                         test3 |= (unsigned long)act_time_value[ATA_133][timing] << 16;
 539                         test3 |= (unsigned long)rco_time_value[ATA_133][timing] << 24;
 540                 } else {
 541                         test3 |= (unsigned long)ini_time_value[ATA_100][timing] << 12;
 542                         test3 |= (unsigned long)act_time_value[ATA_100][timing] << 16;
 543                         test3 |= (unsigned long)rco_time_value[ATA_100][timing] << 24;
 544                 }
 545                 pci_write_config_dword(dev, drive_pci, test3);
 546         }
 547 }
 548
 549 static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 550 {
 551         if (pio == 255)
 552                 pio = ide_find_best_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 553         config_art_rwp_pio(drive, pio);
 554         return ide_config_drive_speed(drive, XFER_PIO_0 + min_t(u8, pio, 4));
 555 }
 556
 557 static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 558 {
 559         ide_hwif_t *hwif        = HWIF(drive);
 560         struct pci_dev *dev     = hwif->pci_dev;
 561
 562         u8 drive_pci, reg, speed;
 563         u32 regdw;
 564
 565         speed = ide_rate_filter(sis5513_ratemask(drive), xferspeed);
 566
 567         /* See config_art_rwp_pio for drive pci config registers */
 568         drive_pci = 0x40;
 569         if (chipset_family >= ATA_133) {
 570                 u32 reg54h;
 571                 pci_read_config_dword(dev, 0x54, &reg54h);
 572                 if (reg54h & 0x40000000) drive_pci = 0x70;
 573                 drive_pci += ((drive->dn)*0x4);
 574                 pci_read_config_dword(dev, (unsigned long)drive_pci, &regdw);
 575                 /* Disable UDMA bit for non UDMA modes on UDMA chips */
 576                 if (speed < XFER_UDMA_0) {
 577                         regdw &= 0xfffffffb;
 578                         pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
 579                 }
 580
 581         } else {
 582                 drive_pci += ((drive->dn)*0x2);
 583                 pci_read_config_byte(dev, drive_pci+1, &reg);
 584                 /* Disable UDMA bit for non UDMA modes on UDMA chips */
 585                 if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
 586                         reg &= 0x7F;
 587                         pci_write_config_byte(dev, drive_pci+1, reg);
 588                 }
 589         }
 590
 591         /* Config chip for mode */
 592         switch(speed) {
 593                 case XFER_UDMA_6:
 594                 case XFER_UDMA_5:
 595                 case XFER_UDMA_4:
 596                 case XFER_UDMA_3:
 597                 case XFER_UDMA_2:
 598                 case XFER_UDMA_1:
 599                 case XFER_UDMA_0:
 600                         if (chipset_family >= ATA_133) {
 601                                 regdw |= 0x04;
 602                                 regdw &= 0xfffff00f;
 603                                 /* check if ATA133 enable */
 604                                 if (regdw & 0x08) {
 605                                         regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
 606                                         regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
 607                                 } else {
 608                                 /* if ATA133 disable, we should not set speed above UDMA5 */
 609                                         if (speed > XFER_UDMA_5)
 610                                                 speed = XFER_UDMA_5;
 611                                         regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
 612                                         regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
 613                                 }
 614                                 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
 615                         } else {
 616                                 /* Force the UDMA bit on if we want to use UDMA */
 617                                 reg |= 0x80;
 618                                 /* clean reg cycle time bits */
 619                                 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
 620                                          << cycle_time_offset[chipset_family]);
 621                                 /* set reg cycle time bits */
 622                                 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
 623                                         << cycle_time_offset[chipset_family];
 624                                 pci_write_config_byte(dev, drive_pci+1, reg);
 625                         }
 626                         break;
 627                 case XFER_MW_DMA_2:
 628                 case XFER_MW_DMA_1:
 629                 case XFER_MW_DMA_0:
 630                 case XFER_SW_DMA_2:
 631                 case XFER_SW_DMA_1:
 632                 case XFER_SW_DMA_0:
 633                         break;
 634                 case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
 635                 case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
 636                 case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
 637                 case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
 638                 case XFER_PIO_0:
 639                 default:         return((int) config_chipset_for_pio(drive, 0));
 640         }
 641
 642         return ((int) ide_config_drive_speed(drive, speed));
 643 }
 644
 645 static void sis5513_tune_drive (ide_drive_t *drive, u8 pio)
 646 {
 647         (void) config_chipset_for_pio(drive, pio);
 648 }
 649
 650 /*
 651  * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
 652  */
 653 static int config_chipset_for_dma (ide_drive_t *drive)
 654 {
 655         u8 speed        = ide_dma_speed(drive, sis5513_ratemask(drive));
 656
 657 #ifdef DEBUG
 658         printk("SIS5513: config_chipset_for_dma, drive %d, ultra %x\n",
 659                drive->dn, drive->id->dma_ultra);
 660 #endif
 661
 662         if (!(speed))
 663                 return 0;
 664
 665         sis5513_tune_chipset(drive, speed);
 666         return ide_dma_enable(drive);
 667 }
 668
 669 static int sis5513_config_drive_xfer_rate (ide_drive_t *drive)
 670 {
 671         ide_hwif_t *hwif        = HWIF(drive);
 672         struct hd_driveid *id   = drive->id;
 673
 674         drive->init_speed = 0;
 675
 676         if (id && (id->capability & 1) && drive->autodma) {
 677
 678                 if (ide_use_dma(drive)) {
 679                         if (config_chipset_for_dma(drive))
 680                                 return hwif->ide_dma_on(drive);
 681                 }
 682
 683                 goto fast_ata_pio;
 684
 685         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 686 fast_ata_pio:
 687                 sis5513_tune_drive(drive, 5);
 688                 return hwif->ide_dma_off_quietly(drive);
 689         }
 690         /* IORDY not supported */
 691         return 0;
 692 }
 693
 694 /* initiates/aborts (U)DMA read/write operations on a drive. */
 695 static int sis5513_config_xfer_rate (ide_drive_t *drive)
 696 {
 697         config_drive_art_rwp(drive);
 698         config_art_rwp_pio(drive, 5);
 699         return sis5513_config_drive_xfer_rate(drive);
 700 }
 701
 702 /*
 703   Future simpler config_xfer_rate :
 704    When ide_find_best_mode is made bad-drive aware
 705    - remove config_drive_xfer_rate and config_chipset_for_dma,
 706    - replace config_xfer_rate with the following
 707
 708 static int sis5513_config_xfer_rate (ide_drive_t *drive)
 709 {
 710         u16 w80 = HWIF(drive)->udma_four;
 711         u16 speed;
 712
 713         config_drive_art_rwp(drive);
 714         config_art_rwp_pio(drive, 5);
 715
 716         speed = ide_find_best_mode(drive,
 717                 XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
 718                 (chipset_family >= ATA_33 ? XFER_UDMA : 0) |
 719                 (w80 && chipset_family >= ATA_66 ? XFER_UDMA_66 : 0) |
 720                 (w80 && chipset_family >= ATA_100a ? XFER_UDMA_100 : 0) |
 721                 (w80 && chipset_family >= ATA_133a ? XFER_UDMA_133 : 0));
 722
 723         sis5513_tune_chipset(drive, speed);
 724
 725         if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
 726                 return HWIF(drive)->ide_dma_on(drive);
 727         return HWIF(drive)->ide_dma_off_quietly(drive);
 728 }
 729 */
 730
 731 /* Chip detection and general config */
 732 static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
 733 {
 734         struct pci_dev *host;
 735         int i = 0;
 736
 737         chipset_family = 0;
 738
 739         for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
 740
 741                 host = pci_find_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
 742
 743                 if (!host)
 744                         continue;
 745
 746                 chipset_family = SiSHostChipInfo[i].chipset_family;
 747
 748                 /* Special case for SiS630 : 630S/ET is ATA_100a */
 749                 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
 750                         u8 hostrev;
 751                         pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
 752                         if (hostrev >= 0x30)
 753                                 chipset_family = ATA_100a;
 754                 }
 755
 756                 printk(KERN_INFO "SIS5513: %s %s controller\n",
 757                          SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
 758         }
 759
 760         if (!chipset_family) { /* Belongs to pci-quirks */
 761
 762                         u32 idemisc;
 763                         u16 trueid;
 764
 765                         /* Disable ID masking and register remapping */
 766                         pci_read_config_dword(dev, 0x54, &idemisc);
 767                         pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
 768                         pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
 769                         pci_write_config_dword(dev, 0x54, idemisc);
 770
 771                         if (trueid == 0x5518) {
 772                                 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
 773                                 chipset_family = ATA_133;
 774
 775                                 /* Check for 5513 compability mapping
 776                                  * We must use this, else the port enabled code will fail,
 777                                  * as it expects the enablebits at 0x4a.
 778                                  */
 779                                 if ((idemisc & 0x40000000) == 0) {
 780                                         pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
 781                                         printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
 782                                 }
 783                         }
 784         }
 785
 786         if (!chipset_family) { /* Belongs to pci-quirks */
 787
 788                         struct pci_dev *lpc_bridge;
 789                         u16 trueid;
 790                         u8 prefctl;
 791                         u8 idecfg;
 792                         u8 sbrev;
 793
 794                         pci_read_config_byte(dev, 0x4a, &idecfg);
 795                         pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
 796                         pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
 797                         pci_write_config_byte(dev, 0x4a, idecfg);
 798
 799                         if (trueid == 0x5517) { /* SiS 961/961B */
 800
 801                                 lpc_bridge = pci_find_slot(0x00, 0x10); /* Bus 0, Dev 2, Fn 0 */
 802                                 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
 803                                 pci_read_config_byte(dev, 0x49, &prefctl);
 804
 805                                 if (sbrev == 0x10 && (prefctl & 0x80)) {
 806                                         printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
 807                                         chipset_family = ATA_133a;
 808                                 } else {
 809                                         printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
 810                                         chipset_family = ATA_100;
 811                                 }
 812                         }
 813         }
 814
 815         if (!chipset_family)
 816                 return -1;
 817
 818         /* Make general config ops here
 819            1/ tell IDE channels to operate in Compatibility mode only
 820            2/ tell old chips to allow per drive IDE timings */
 821
 822         {
 823                 u8 reg;
 824                 u16 regw;
 825
 826                 switch(chipset_family) {
 827                         case ATA_133:
 828                                 /* SiS962 operation mode */
 829                                 pci_read_config_word(dev, 0x50, &regw);
 830                                 if (regw & 0x08)
 831                                         pci_write_config_word(dev, 0x50, regw&0xfff7);
 832                                 pci_read_config_word(dev, 0x52, &regw);
 833                                 if (regw & 0x08)
 834                                         pci_write_config_word(dev, 0x52, regw&0xfff7);
 835                                 break;
 836                         case ATA_133a:
 837                         case ATA_100:
 838                                 /* Fixup latency */
 839                                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
 840                                 /* Set compatibility bit */
 841                                 pci_read_config_byte(dev, 0x49, &reg);
 842                                 if (!(reg & 0x01)) {
 843                                         pci_write_config_byte(dev, 0x49, reg|0x01);
 844                                 }
 845                                 break;
 846                         case ATA_100a:
 847                         case ATA_66:
 848                                 /* Fixup latency */
 849                                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
 850
 851                                 /* On ATA_66 chips the bit was elsewhere */
 852                                 pci_read_config_byte(dev, 0x52, &reg);
 853                                 if (!(reg & 0x04)) {
 854                                         pci_write_config_byte(dev, 0x52, reg|0x04);
 855                                 }
 856                                 break;
 857                         case ATA_33:
 858                                 /* On ATA_33 we didn't have a single bit to set */
 859                                 pci_read_config_byte(dev, 0x09, &reg);
 860                                 if ((reg & 0x0f) != 0x00) {
 861                                         pci_write_config_byte(dev, 0x09, reg&0xf0);
 862                                 }
 863                         case ATA_16:
 864                                 /* force per drive recovery and active timings
 865                                    needed on ATA_33 and below chips */
 866                                 pci_read_config_byte(dev, 0x52, &reg);
 867                                 if (!(reg & 0x08)) {
 868                                         pci_write_config_byte(dev, 0x52, reg|0x08);
 869                                 }
 870                                 break;
 871                 }
 872
 873 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
 874                 if (!sis_proc) {
 875                         sis_proc = 1;
 876                         bmide_dev = dev;
 877                         ide_pci_create_host_proc("sis", sis_get_info);
 878                 }
 879 #endif
 880         }
 881
 882         return 0;
 883 }
 884
 885 static unsigned int __devinit ata66_sis5513 (ide_hwif_t *hwif)
 886 {
 887         u8 ata66 = 0;
 888
 889         if (chipset_family >= ATA_133) {
 890                 u16 regw = 0;
 891                 u16 reg_addr = hwif->channel ? 0x52: 0x50;
 892                 pci_read_config_word(hwif->pci_dev, reg_addr, &regw);
 893                 ata66 = (regw & 0x8000) ? 0 : 1;
 894         } else if (chipset_family >= ATA_66) {
 895                 u8 reg48h = 0;
 896                 u8 mask = hwif->channel ? 0x20 : 0x10;
 897                 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
 898                 ata66 = (reg48h & mask) ? 0 : 1;
 899         }
 900         return ata66;
 901 }
 902
 903 static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
 904 {
 905         hwif->autodma = 0;
 906
 907         if (!hwif->irq)
 908                 hwif->irq = hwif->channel ? 15 : 14;
 909
 910         hwif->tuneproc = &sis5513_tune_drive;
 911         hwif->speedproc = &sis5513_tune_chipset;
 912
 913         if (!(hwif->dma_base)) {
 914                 hwif->drives[0].autotune = 1;
 915                 hwif->drives[1].autotune = 1;
 916                 return;
 917         }
 918
 919         hwif->atapi_dma = 1;
 920         hwif->ultra_mask = 0x7f;
 921         hwif->mwdma_mask = 0x07;
 922         hwif->swdma_mask = 0x07;
 923
 924         if (!chipset_family)
 925                 return;
 926
 927         if (!(hwif->udma_four))
 928                 hwif->udma_four = ata66_sis5513(hwif);
 929
 930         if (chipset_family > ATA_16) {
 931                 hwif->ide_dma_check = &sis5513_config_xfer_rate;
 932                 if (!noautodma)
 933                         hwif->autodma = 1;
 934         }
 935         hwif->drives[0].autodma = hwif->autodma;
 936         hwif->drives[1].autodma = hwif->autodma;
 937         return;
 938 }
 939
 940 static ide_pci_device_t sis5513_chipset __devinitdata = {
 941         .name           = "SIS5513",
 942         .init_chipset   = init_chipset_sis5513,
 943         .init_hwif      = init_hwif_sis5513,
 944         .channels       = 2,
 945         .autodma        = NOAUTODMA,
 946         .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 947         .bootable       = ON_BOARD,
 948 };
 949
 950 static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 951 {
 952         return ide_setup_pci_device(dev, &sis5513_chipset);
 953 }
 954
 955 static struct pci_device_id sis5513_pci_tbl[] = {
 956         { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 957         { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 958         { 0, },
 959 };
 960 MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
 961
 962 static struct pci_driver driver = {
 963         .name           = "SIS_IDE",
 964         .id_table       = sis5513_pci_tbl,
 965         .probe          = sis5513_init_one,
 966 };
 967
 968 static int sis5513_ide_init(void)
 969 {
 970         return ide_pci_register_driver(&driver);
 971 }
 972
 973 module_init(sis5513_ide_init);
 974
 975 MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
 976 MODULE_DESCRIPTION("PCI driver module for SIS IDE");
 977 MODULE_LICENSE("GPL");
 978
 979 /*
 980  * TODO:
 981  *      - CLEANUP
 982  *      - Use drivers/ide/ide-timing.h !
 983  *      - More checks in the config registers (force values instead of
 984  *        relying on the BIOS setting them correctly).
 985  *      - Further optimisations ?
 986  *        . for example ATA66+ regs 0x48 & 0x4A
 987  */