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   1 /*
   2  *  i2c_adap_pxa.c
   3  *
   4  *  I2C adapter for the PXA I2C bus access.
   5  *
   6  *  Copyright (C) 2002 Intrinsyc Software Inc.
   7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  History:
  14  *    Apr 2002: Initial version [CS]
  15  *    Jun 2002: Properly seperated algo/adap [FB]
  16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  20  *    Feb 2005: Rework slave mode handling [RMK]
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/i2c-id.h>
  26 #include <linux/init.h>
  27 #include <linux/time.h>
  28 #include <linux/sched.h>
  29 #include <linux/delay.h>
  30 #include <linux/errno.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/i2c-pxa.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/err.h>
  35 #include <linux/clk.h>
  36
  37 #include <mach/hardware.h>
  38 #include <asm/irq.h>
  39 #include <asm/io.h>
  40 #include <mach/i2c.h>
  41 #include <mach/pxa-regs.h>
  42
  43 struct pxa_i2c {
  44         spinlock_t              lock;
  45         wait_queue_head_t       wait;
  46         struct i2c_msg          *msg;
  47         unsigned int            msg_num;
  48         unsigned int            msg_idx;
  49         unsigned int            msg_ptr;
  50         unsigned int            slave_addr;
  51
  52         struct i2c_adapter      adap;
  53         struct clk              *clk;
  54 #ifdef CONFIG_I2C_PXA_SLAVE
  55         struct i2c_slave_client *slave;
  56 #endif
  57
  58         unsigned int            irqlogidx;
  59         u32                     isrlog[32];
  60         u32                     icrlog[32];
  61
  62         void __iomem            *reg_base;
  63         unsigned int            reg_shift;
  64
  65         unsigned long           iobase;
  66         unsigned long           iosize;
  67
  68         int                     irq;
  69         unsigned int            use_pio :1;
  70         unsigned int            fast_mode :1;
  71 };
  72
  73 #define _IBMR(i2c)      ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
  74 #define _IDBR(i2c)      ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
  75 #define _ICR(i2c)       ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
  76 #define _ISR(i2c)       ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
  77 #define _ISAR(i2c)      ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
  78
  79 /*
  80  * I2C Slave mode address
  81  */
  82 #define I2C_PXA_SLAVE_ADDR      0x1
  83
  84 #ifdef DEBUG
  85
  86 struct bits {
  87         u32     mask;
  88         const char *set;
  89         const char *unset;
  90 };
  91 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
  92
  93 static inline void
  94 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
  95 {
  96         printk("%s %08x: ", prefix, val);
  97         while (num--) {
  98                 const char *str = val & bits->mask ? bits->set : bits->unset;
  99                 if (str)
 100                         printk("%s ", str);
 101                 bits++;
 102         }
 103 }
 104
 105 static const struct bits isr_bits[] = {
 106         PXA_BIT(ISR_RWM,        "RX",           "TX"),
 107         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
 108         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
 109         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
 110         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
 111         PXA_BIT(ISR_ALD,        "ALD",          NULL),
 112         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
 113         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
 114         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
 115         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
 116         PXA_BIT(ISR_BED,        "BusErr",       NULL),
 117 };
 118
 119 static void decode_ISR(unsigned int val)
 120 {
 121         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 122         printk("\n");
 123 }
 124
 125 static const struct bits icr_bits[] = {
 126         PXA_BIT(ICR_START,  "START",    NULL),
 127         PXA_BIT(ICR_STOP,   "STOP",     NULL),
 128         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
 129         PXA_BIT(ICR_TB,     "TB",       NULL),
 130         PXA_BIT(ICR_MA,     "MA",       NULL),
 131         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
 132         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
 133         PXA_BIT(ICR_GCD,    "GCD",      NULL),
 134         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
 135         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
 136         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
 137         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
 138         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
 139         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
 140         PXA_BIT(ICR_UR,     "UR",               "ur"),
 141 };
 142
 143 #ifdef CONFIG_I2C_PXA_SLAVE
 144 static void decode_ICR(unsigned int val)
 145 {
 146         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 147         printk("\n");
 148 }
 149 #endif
 150
 151 static unsigned int i2c_debug = DEBUG;
 152
 153 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 154 {
 155         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
 156                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 157 }
 158
 159 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
 160 #else
 161 #define i2c_debug       0
 162
 163 #define show_state(i2c) do { } while (0)
 164 #define decode_ISR(val) do { } while (0)
 165 #define decode_ICR(val) do { } while (0)
 166 #endif
 167
 168 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
 169
 170 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 171 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
 172
 173 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 174 {
 175         unsigned int i;
 176         printk("i2c: error: %s\n", why);
 177         printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
 178                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 179         printk("i2c: ICR: %08x ISR: %08x\n"
 180                "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c)));
 181         for (i = 0; i < i2c->irqlogidx; i++)
 182                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
 183         printk("\n");
 184 }
 185
 186 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 187 {
 188         return !(readl(_ICR(i2c)) & ICR_SCLE);
 189 }
 190
 191 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 192 {
 193         int i = 250;
 194
 195         if (i2c_pxa_is_slavemode(i2c)) {
 196                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 197                 return;
 198         }
 199
 200         while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
 201                 unsigned long icr = readl(_ICR(i2c));
 202
 203                 icr &= ~ICR_START;
 204                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 205
 206                 writel(icr, _ICR(i2c));
 207
 208                 show_state(i2c);
 209
 210                 mdelay(1);
 211                 i --;
 212         }
 213
 214         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
 215                _ICR(i2c));
 216 }
 217
 218 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 219 {
 220         int timeout = DEF_TIMEOUT;
 221
 222         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 223                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
 224                         timeout += 4;
 225
 226                 msleep(2);
 227                 show_state(i2c);
 228         }
 229
 230         if (timeout <= 0)
 231                 show_state(i2c);
 232
 233         return timeout <= 0 ? I2C_RETRY : 0;
 234 }
 235
 236 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 237 {
 238         unsigned long timeout = jiffies + HZ*4;
 239
 240         while (time_before(jiffies, timeout)) {
 241                 if (i2c_debug > 1)
 242                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 243                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 244
 245                 if (readl(_ISR(i2c)) & ISR_SAD) {
 246                         if (i2c_debug > 0)
 247                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 248                         goto out;
 249                 }
 250
 251                 /* wait for unit and bus being not busy, and we also do a
 252                  * quick check of the i2c lines themselves to ensure they've
 253                  * gone high...
 254                  */
 255                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
 256                         if (i2c_debug > 0)
 257                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 258                         return 1;
 259                 }
 260
 261                 msleep(1);
 262         }
 263
 264         if (i2c_debug > 0)
 265                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 266  out:
 267         return 0;
 268 }
 269
 270 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 271 {
 272         if (i2c_debug)
 273                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 274
 275         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
 276                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 277                 if (!i2c_pxa_wait_master(i2c)) {
 278                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 279                         return I2C_RETRY;
 280                 }
 281         }
 282
 283         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 284         return 0;
 285 }
 286
 287 #ifdef CONFIG_I2C_PXA_SLAVE
 288 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 289 {
 290         unsigned long timeout = jiffies + HZ*1;
 291
 292         /* wait for stop */
 293
 294         show_state(i2c);
 295
 296         while (time_before(jiffies, timeout)) {
 297                 if (i2c_debug > 1)
 298                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 299                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 300
 301                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
 302                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
 303                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
 304                         if (i2c_debug > 1)
 305                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 306                         return 1;
 307                 }
 308
 309                 msleep(1);
 310         }
 311
 312         if (i2c_debug > 0)
 313                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 314         return 0;
 315 }
 316
 317 /*
 318  * clear the hold on the bus, and take of anything else
 319  * that has been configured
 320  */
 321 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 322 {
 323         show_state(i2c);
 324
 325         if (errcode < 0) {
 326                 udelay(100);   /* simple delay */
 327         } else {
 328                 /* we need to wait for the stop condition to end */
 329
 330                 /* if we where in stop, then clear... */
 331                 if (readl(_ICR(i2c)) & ICR_STOP) {
 332                         udelay(100);
 333                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
 334                 }
 335
 336                 if (!i2c_pxa_wait_slave(i2c)) {
 337                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 338                                 __func__);
 339                         return;
 340                 }
 341         }
 342
 343         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
 344         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 345
 346         if (i2c_debug) {
 347                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
 348                 decode_ICR(readl(_ICR(i2c)));
 349         }
 350 }
 351 #else
 352 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 353 #endif
 354
 355 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 356 {
 357         pr_debug("Resetting I2C Controller Unit\n");
 358
 359         /* abort any transfer currently under way */
 360         i2c_pxa_abort(i2c);
 361
 362         /* reset according to 9.8 */
 363         writel(ICR_UR, _ICR(i2c));
 364         writel(I2C_ISR_INIT, _ISR(i2c));
 365         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
 366
 367         writel(i2c->slave_addr, _ISAR(i2c));
 368
 369         /* set control register values */
 370         writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
 371
 372 #ifdef CONFIG_I2C_PXA_SLAVE
 373         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 374         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
 375 #endif
 376
 377         i2c_pxa_set_slave(i2c, 0);
 378
 379         /* enable unit */
 380         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
 381         udelay(100);
 382 }
 383
 384
 385 #ifdef CONFIG_I2C_PXA_SLAVE
 386 /*
 387  * PXA I2C Slave mode
 388  */
 389
 390 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 391 {
 392         if (isr & ISR_BED) {
 393                 /* what should we do here? */
 394         } else {
 395                 int ret = 0;
 396
 397                 if (i2c->slave != NULL)
 398                         ret = i2c->slave->read(i2c->slave->data);
 399
 400                 writel(ret, _IDBR(i2c));
 401                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
 402         }
 403 }
 404
 405 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 406 {
 407         unsigned int byte = readl(_IDBR(i2c));
 408
 409         if (i2c->slave != NULL)
 410                 i2c->slave->write(i2c->slave->data, byte);
 411
 412         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 413 }
 414
 415 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 416 {
 417         int timeout;
 418
 419         if (i2c_debug > 0)
 420                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 421                        (isr & ISR_RWM) ? 'r' : 't');
 422
 423         if (i2c->slave != NULL)
 424                 i2c->slave->event(i2c->slave->data,
 425                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
 426
 427         /*
 428          * slave could interrupt in the middle of us generating a
 429          * start condition... if this happens, we'd better back off
 430          * and stop holding the poor thing up
 431          */
 432         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 433         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 434
 435         timeout = 0x10000;
 436
 437         while (1) {
 438                 if ((readl(_IBMR(i2c)) & 2) == 2)
 439                         break;
 440
 441                 timeout--;
 442
 443                 if (timeout <= 0) {
 444                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 445                         break;
 446                 }
 447         }
 448
 449         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 450 }
 451
 452 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 453 {
 454         if (i2c_debug > 2)
 455                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 456
 457         if (i2c->slave != NULL)
 458                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
 459
 460         if (i2c_debug > 2)
 461                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 462
 463         /*
 464          * If we have a master-mode message waiting,
 465          * kick it off now that the slave has completed.
 466          */
 467         if (i2c->msg)
 468                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 469 }
 470 #else
 471 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 472 {
 473         if (isr & ISR_BED) {
 474                 /* what should we do here? */
 475         } else {
 476                 writel(0, _IDBR(i2c));
 477                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 478         }
 479 }
 480
 481 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 482 {
 483         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 484 }
 485
 486 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 487 {
 488         int timeout;
 489
 490         /*
 491          * slave could interrupt in the middle of us generating a
 492          * start condition... if this happens, we'd better back off
 493          * and stop holding the poor thing up
 494          */
 495         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 496         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 497
 498         timeout = 0x10000;
 499
 500         while (1) {
 501                 if ((readl(_IBMR(i2c)) & 2) == 2)
 502                         break;
 503
 504                 timeout--;
 505
 506                 if (timeout <= 0) {
 507                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 508                         break;
 509                 }
 510         }
 511
 512         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 513 }
 514
 515 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 516 {
 517         if (i2c->msg)
 518                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 519 }
 520 #endif
 521
 522 /*
 523  * PXA I2C Master mode
 524  */
 525
 526 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
 527 {
 528         unsigned int addr = (msg->addr & 0x7f) << 1;
 529
 530         if (msg->flags & I2C_M_RD)
 531                 addr |= 1;
 532
 533         return addr;
 534 }
 535
 536 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 537 {
 538         u32 icr;
 539
 540         /*
 541          * Step 1: target slave address into IDBR
 542          */
 543         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 544
 545         /*
 546          * Step 2: initiate the write.
 547          */
 548         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 549         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
 550 }
 551
 552 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 553 {
 554         u32 icr;
 555
 556         /*
 557          * Clear the STOP and ACK flags
 558          */
 559         icr = readl(_ICR(i2c));
 560         icr &= ~(ICR_STOP | ICR_ACKNAK);
 561         writel(icr, _ICR(i2c));
 562 }
 563
 564 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
 565 {
 566         /* make timeout the same as for interrupt based functions */
 567         long timeout = 2 * DEF_TIMEOUT;
 568
 569         /*
 570          * Wait for the bus to become free.
 571          */
 572         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 573                 udelay(1000);
 574                 show_state(i2c);
 575         }
 576
 577         if (timeout <= 0) {
 578                 show_state(i2c);
 579                 dev_err(&i2c->adap.dev,
 580                         "i2c_pxa: timeout waiting for bus free\n");
 581                 return I2C_RETRY;
 582         }
 583
 584         /*
 585          * Set master mode.
 586          */
 587         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 588
 589         return 0;
 590 }
 591
 592 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
 593                                struct i2c_msg *msg, int num)
 594 {
 595         unsigned long timeout = 500000; /* 5 seconds */
 596         int ret = 0;
 597
 598         ret = i2c_pxa_pio_set_master(i2c);
 599         if (ret)
 600                 goto out;
 601
 602         i2c->msg = msg;
 603         i2c->msg_num = num;
 604         i2c->msg_idx = 0;
 605         i2c->msg_ptr = 0;
 606         i2c->irqlogidx = 0;
 607
 608         i2c_pxa_start_message(i2c);
 609
 610         while (timeout-- && i2c->msg_num > 0) {
 611                 i2c_pxa_handler(0, i2c);
 612                 udelay(10);
 613         }
 614
 615         i2c_pxa_stop_message(i2c);
 616
 617         /*
 618          * We place the return code in i2c->msg_idx.
 619          */
 620         ret = i2c->msg_idx;
 621
 622 out:
 623         if (timeout == 0)
 624                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 625
 626         return ret;
 627 }
 628
 629 /*
 630  * We are protected by the adapter bus mutex.
 631  */
 632 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
 633 {
 634         long timeout;
 635         int ret;
 636
 637         /*
 638          * Wait for the bus to become free.
 639          */
 640         ret = i2c_pxa_wait_bus_not_busy(i2c);
 641         if (ret) {
 642                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
 643                 goto out;
 644         }
 645
 646         /*
 647          * Set master mode.
 648          */
 649         ret = i2c_pxa_set_master(i2c);
 650         if (ret) {
 651                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
 652                 goto out;
 653         }
 654
 655         spin_lock_irq(&i2c->lock);
 656
 657         i2c->msg = msg;
 658         i2c->msg_num = num;
 659         i2c->msg_idx = 0;
 660         i2c->msg_ptr = 0;
 661         i2c->irqlogidx = 0;
 662
 663         i2c_pxa_start_message(i2c);
 664
 665         spin_unlock_irq(&i2c->lock);
 666
 667         /*
 668          * The rest of the processing occurs in the interrupt handler.
 669          */
 670         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 671         i2c_pxa_stop_message(i2c);
 672
 673         /*
 674          * We place the return code in i2c->msg_idx.
 675          */
 676         ret = i2c->msg_idx;
 677
 678         if (timeout == 0)
 679                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 680
 681  out:
 682         return ret;
 683 }
 684
 685 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
 686                             struct i2c_msg msgs[], int num)
 687 {
 688         struct pxa_i2c *i2c = adap->algo_data;
 689         int ret, i;
 690
 691         /* If the I2C controller is disabled we need to reset it
 692           (probably due to a suspend/resume destroying state). We do
 693           this here as we can then avoid worrying about resuming the
 694           controller before its users. */
 695         if (!(readl(_ICR(i2c)) & ICR_IUE))
 696                 i2c_pxa_reset(i2c);
 697
 698         for (i = adap->retries; i >= 0; i--) {
 699                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
 700                 if (ret != I2C_RETRY)
 701                         goto out;
 702
 703                 if (i2c_debug)
 704                         dev_dbg(&adap->dev, "Retrying transmission\n");
 705                 udelay(100);
 706         }
 707         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 708         ret = -EREMOTEIO;
 709  out:
 710         i2c_pxa_set_slave(i2c, ret);
 711         return ret;
 712 }
 713
 714 /*
 715  * i2c_pxa_master_complete - complete the message and wake up.
 716  */
 717 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 718 {
 719         i2c->msg_ptr = 0;
 720         i2c->msg = NULL;
 721         i2c->msg_idx ++;
 722         i2c->msg_num = 0;
 723         if (ret)
 724                 i2c->msg_idx = ret;
 725         if (!i2c->use_pio)
 726                 wake_up(&i2c->wait);
 727 }
 728
 729 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 730 {
 731         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 732
 733  again:
 734         /*
 735          * If ISR_ALD is set, we lost arbitration.
 736          */
 737         if (isr & ISR_ALD) {
 738                 /*
 739                  * Do we need to do anything here?  The PXA docs
 740                  * are vague about what happens.
 741                  */
 742                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 743
 744                 /*
 745                  * We ignore this error.  We seem to see spurious ALDs
 746                  * for seemingly no reason.  If we handle them as I think
 747                  * they should, we end up causing an I2C error, which
 748                  * is painful for some systems.
 749                  */
 750                 return; /* ignore */
 751         }
 752
 753         if (isr & ISR_BED) {
 754                 int ret = BUS_ERROR;
 755
 756                 /*
 757                  * I2C bus error - either the device NAK'd us, or
 758                  * something more serious happened.  If we were NAK'd
 759                  * on the initial address phase, we can retry.
 760                  */
 761                 if (isr & ISR_ACKNAK) {
 762                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 763                                 ret = I2C_RETRY;
 764                         else
 765                                 ret = XFER_NAKED;
 766                 }
 767                 i2c_pxa_master_complete(i2c, ret);
 768         } else if (isr & ISR_RWM) {
 769                 /*
 770                  * Read mode.  We have just sent the address byte, and
 771                  * now we must initiate the transfer.
 772                  */
 773                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 774                     i2c->msg_idx == i2c->msg_num - 1)
 775                         icr |= ICR_STOP | ICR_ACKNAK;
 776
 777                 icr |= ICR_ALDIE | ICR_TB;
 778         } else if (i2c->msg_ptr < i2c->msg->len) {
 779                 /*
 780                  * Write mode.  Write the next data byte.
 781                  */
 782                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
 783
 784                 icr |= ICR_ALDIE | ICR_TB;
 785
 786                 /*
 787                  * If this is the last byte of the last message, send
 788                  * a STOP.
 789                  */
 790                 if (i2c->msg_ptr == i2c->msg->len &&
 791                     i2c->msg_idx == i2c->msg_num - 1)
 792                         icr |= ICR_STOP;
 793         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 794                 /*
 795                  * Next segment of the message.
 796                  */
 797                 i2c->msg_ptr = 0;
 798                 i2c->msg_idx ++;
 799                 i2c->msg++;
 800
 801                 /*
 802                  * If we aren't doing a repeated start and address,
 803                  * go back and try to send the next byte.  Note that
 804                  * we do not support switching the R/W direction here.
 805                  */
 806                 if (i2c->msg->flags & I2C_M_NOSTART)
 807                         goto again;
 808
 809                 /*
 810                  * Write the next address.
 811                  */
 812                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 813
 814                 /*
 815                  * And trigger a repeated start, and send the byte.
 816                  */
 817                 icr &= ~ICR_ALDIE;
 818                 icr |= ICR_START | ICR_TB;
 819         } else {
 820                 if (i2c->msg->len == 0) {
 821                         /*
 822                          * Device probes have a message length of zero
 823                          * and need the bus to be reset before it can
 824                          * be used again.
 825                          */
 826                         i2c_pxa_reset(i2c);
 827                 }
 828                 i2c_pxa_master_complete(i2c, 0);
 829         }
 830
 831         i2c->icrlog[i2c->irqlogidx-1] = icr;
 832
 833         writel(icr, _ICR(i2c));
 834         show_state(i2c);
 835 }
 836
 837 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 838 {
 839         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 840
 841         /*
 842          * Read the byte.
 843          */
 844         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
 845
 846         if (i2c->msg_ptr < i2c->msg->len) {
 847                 /*
 848                  * If this is the last byte of the last
 849                  * message, send a STOP.
 850                  */
 851                 if (i2c->msg_ptr == i2c->msg->len - 1)
 852                         icr |= ICR_STOP | ICR_ACKNAK;
 853
 854                 icr |= ICR_ALDIE | ICR_TB;
 855         } else {
 856                 i2c_pxa_master_complete(i2c, 0);
 857         }
 858
 859         i2c->icrlog[i2c->irqlogidx-1] = icr;
 860
 861         writel(icr, _ICR(i2c));
 862 }
 863
 864 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
 865 {
 866         struct pxa_i2c *i2c = dev_id;
 867         u32 isr = readl(_ISR(i2c));
 868
 869         if (i2c_debug > 2 && 0) {
 870                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 871                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
 872                 decode_ISR(isr);
 873         }
 874
 875         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
 876                 i2c->isrlog[i2c->irqlogidx++] = isr;
 877
 878         show_state(i2c);
 879
 880         /*
 881          * Always clear all pending IRQs.
 882          */
 883         writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
 884
 885         if (isr & ISR_SAD)
 886                 i2c_pxa_slave_start(i2c, isr);
 887         if (isr & ISR_SSD)
 888                 i2c_pxa_slave_stop(i2c);
 889
 890         if (i2c_pxa_is_slavemode(i2c)) {
 891                 if (isr & ISR_ITE)
 892                         i2c_pxa_slave_txempty(i2c, isr);
 893                 if (isr & ISR_IRF)
 894                         i2c_pxa_slave_rxfull(i2c, isr);
 895         } else if (i2c->msg) {
 896                 if (isr & ISR_ITE)
 897                         i2c_pxa_irq_txempty(i2c, isr);
 898                 if (isr & ISR_IRF)
 899                         i2c_pxa_irq_rxfull(i2c, isr);
 900         } else {
 901                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
 902         }
 903
 904         return IRQ_HANDLED;
 905 }
 906
 907
 908 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 909 {
 910         struct pxa_i2c *i2c = adap->algo_data;
 911         int ret, i;
 912
 913         for (i = adap->retries; i >= 0; i--) {
 914                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
 915                 if (ret != I2C_RETRY)
 916                         goto out;
 917
 918                 if (i2c_debug)
 919                         dev_dbg(&adap->dev, "Retrying transmission\n");
 920                 udelay(100);
 921         }
 922         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 923         ret = -EREMOTEIO;
 924  out:
 925         i2c_pxa_set_slave(i2c, ret);
 926         return ret;
 927 }
 928
 929 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
 930 {
 931         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 932 }
 933
 934 static const struct i2c_algorithm i2c_pxa_algorithm = {
 935         .master_xfer    = i2c_pxa_xfer,
 936         .functionality  = i2c_pxa_functionality,
 937 };
 938
 939 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
 940         .master_xfer    = i2c_pxa_pio_xfer,
 941         .functionality  = i2c_pxa_functionality,
 942 };
 943
 944 #define res_len(r)              ((r)->end - (r)->start + 1)
 945 static int i2c_pxa_probe(struct platform_device *dev)
 946 {
 947         struct pxa_i2c *i2c;
 948         struct resource *res;
 949         struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
 950         int ret;
 951         int irq;
 952
 953         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 954         irq = platform_get_irq(dev, 0);
 955         if (res == NULL || irq < 0)
 956                 return -ENODEV;
 957
 958         if (!request_mem_region(res->start, res_len(res), res->name))
 959                 return -ENOMEM;
 960
 961         i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
 962         if (!i2c) {
 963                 ret = -ENOMEM;
 964                 goto emalloc;
 965         }
 966
 967         i2c->adap.owner   = THIS_MODULE;
 968         i2c->adap.retries = 5;
 969
 970         spin_lock_init(&i2c->lock);
 971         init_waitqueue_head(&i2c->wait);
 972
 973         /*
 974          * If "dev->id" is negative we consider it as zero.
 975          * The reason to do so is to avoid sysfs names that only make
 976          * sense when there are multiple adapters.
 977          */
 978         i2c->adap.nr = dev->id != -1 ? dev->id : 0;
 979         snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
 980                  i2c->adap.nr);
 981
 982         i2c->clk = clk_get(&dev->dev, "I2CCLK");
 983         if (IS_ERR(i2c->clk)) {
 984                 ret = PTR_ERR(i2c->clk);
 985                 goto eclk;
 986         }
 987
 988         i2c->reg_base = ioremap(res->start, res_len(res));
 989         if (!i2c->reg_base) {
 990                 ret = -EIO;
 991                 goto eremap;
 992         }
 993         i2c->reg_shift = (cpu_is_pxa3xx() && (dev->id == 1)) ? 0 : 1;
 994
 995         i2c->iobase = res->start;
 996         i2c->iosize = res_len(res);
 997
 998         i2c->irq = irq;
 999
1000         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1001
1002 #ifdef CONFIG_I2C_PXA_SLAVE
1003         if (plat) {
1004                 i2c->slave_addr = plat->slave_addr;
1005                 i2c->slave = plat->slave;
1006         }
1007 #endif
1008
1009         clk_enable(i2c->clk);
1010
1011         if (plat) {
1012                 i2c->adap.class = plat->class;
1013                 i2c->use_pio = plat->use_pio;
1014                 i2c->fast_mode = plat->fast_mode;
1015         }
1016
1017         if (i2c->use_pio) {
1018                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1019         } else {
1020                 i2c->adap.algo = &i2c_pxa_algorithm;
1021                 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1022                                   i2c->adap.name, i2c);
1023                 if (ret)
1024                         goto ereqirq;
1025         }
1026
1027         i2c_pxa_reset(i2c);
1028
1029         i2c->adap.algo_data = i2c;
1030         i2c->adap.dev.parent = &dev->dev;
1031
1032         ret = i2c_add_numbered_adapter(&i2c->adap);
1033         if (ret < 0) {
1034                 printk(KERN_INFO "I2C: Failed to add bus\n");
1035                 goto eadapt;
1036         }
1037
1038         platform_set_drvdata(dev, i2c);
1039
1040 #ifdef CONFIG_I2C_PXA_SLAVE
1041         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1042                i2c->adap.dev.bus_id, i2c->slave_addr);
1043 #else
1044         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1045                i2c->adap.dev.bus_id);
1046 #endif
1047         return 0;
1048
1049 eadapt:
1050         if (!i2c->use_pio)
1051                 free_irq(irq, i2c);
1052 ereqirq:
1053         clk_disable(i2c->clk);
1054         iounmap(i2c->reg_base);
1055 eremap:
1056         clk_put(i2c->clk);
1057 eclk:
1058         kfree(i2c);
1059 emalloc:
1060         release_mem_region(res->start, res_len(res));
1061         return ret;
1062 }
1063
1064 static int __exit i2c_pxa_remove(struct platform_device *dev)
1065 {
1066         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1067
1068         platform_set_drvdata(dev, NULL);
1069
1070         i2c_del_adapter(&i2c->adap);
1071         if (!i2c->use_pio)
1072                 free_irq(i2c->irq, i2c);
1073
1074         clk_disable(i2c->clk);
1075         clk_put(i2c->clk);
1076
1077         iounmap(i2c->reg_base);
1078         release_mem_region(i2c->iobase, i2c->iosize);
1079         kfree(i2c);
1080
1081         return 0;
1082 }
1083
1084 #ifdef CONFIG_PM
1085 static int i2c_pxa_suspend_late(struct platform_device *dev, pm_message_t state)
1086 {
1087         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1088         clk_disable(i2c->clk);
1089         return 0;
1090 }
1091
1092 static int i2c_pxa_resume_early(struct platform_device *dev)
1093 {
1094         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1095
1096         clk_enable(i2c->clk);
1097         i2c_pxa_reset(i2c);
1098
1099         return 0;
1100 }
1101 #else
1102 #define i2c_pxa_suspend_late NULL
1103 #define i2c_pxa_resume_early NULL
1104 #endif
1105
1106 static struct platform_driver i2c_pxa_driver = {
1107         .probe          = i2c_pxa_probe,
1108         .remove         = __exit_p(i2c_pxa_remove),
1109         .suspend_late   = i2c_pxa_suspend_late,
1110         .resume_early   = i2c_pxa_resume_early,
1111         .driver         = {
1112                 .name   = "pxa2xx-i2c",
1113                 .owner  = THIS_MODULE,
1114         },
1115 };
1116
1117 static int __init i2c_adap_pxa_init(void)
1118 {
1119         return platform_driver_register(&i2c_pxa_driver);
1120 }
1121
1122 static void __exit i2c_adap_pxa_exit(void)
1123 {
1124         platform_driver_unregister(&i2c_pxa_driver);
1125 }
1126
1127 MODULE_LICENSE("GPL");
1128 MODULE_ALIAS("platform:pxa2xx-i2c");
1129
1130 subsys_initcall(i2c_adap_pxa_init);
1131 module_exit(i2c_adap_pxa_exit);