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   1 /*
   2  *  i2c_adap_pxa.c
   3  *
   4  *  I2C adapter for the PXA I2C bus access.
   5  *
   6  *  Copyright (C) 2002 Intrinsyc Software Inc.
   7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  History:
  14  *    Apr 2002: Initial version [CS]
  15  *    Jun 2002: Properly seperated algo/adap [FB]
  16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  20  *    Feb 2005: Rework slave mode handling [RMK]
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/i2c-id.h>
  26 #include <linux/init.h>
  27 #include <linux/time.h>
  28 #include <linux/sched.h>
  29 #include <linux/delay.h>
  30 #include <linux/errno.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/i2c-pxa.h>
  33
  34 #include <asm/hardware.h>
  35 #include <asm/irq.h>
  36 #include <asm/arch/i2c.h>
  37 #include <asm/arch/pxa-regs.h>
  38
  39 struct pxa_i2c {
  40         spinlock_t              lock;
  41         wait_queue_head_t       wait;
  42         struct i2c_msg          *msg;
  43         unsigned int            msg_num;
  44         unsigned int            msg_idx;
  45         unsigned int            msg_ptr;
  46         unsigned int            slave_addr;
  47
  48         struct i2c_adapter      adap;
  49 #ifdef CONFIG_I2C_PXA_SLAVE
  50         struct i2c_slave_client *slave;
  51 #endif
  52
  53         unsigned int            irqlogidx;
  54         u32                     isrlog[32];
  55         u32                     icrlog[32];
  56 };
  57
  58 /*
  59  * I2C Slave mode address
  60  */
  61 #define I2C_PXA_SLAVE_ADDR      0x1
  62
  63 /*
  64  * Set this to zero to remove all debug statements via dead code elimination.
  65  */
  66 #undef DEBUG
  67
  68 #if 0
  69 #define DBGLVL KERN_INFO
  70 #else
  71 #define DBGLVL KERN_DEBUG
  72 #endif
  73
  74 #ifdef DEBUG
  75
  76 struct bits {
  77         u32     mask;
  78         const char *set;
  79         const char *unset;
  80 };
  81 #define BIT(m, s, u)    { .mask = m, .set = s, .unset = u }
  82
  83 static inline void
  84 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
  85 {
  86         printk("%s %08x: ", prefix, val);
  87         while (num--) {
  88                 const char *str = val & bits->mask ? bits->set : bits->unset;
  89                 if (str)
  90                         printk("%s ", str);
  91                 bits++;
  92         }
  93 }
  94
  95 static const struct bits isr_bits[] = {
  96         BIT(ISR_RWM,    "RX",           "TX"),
  97         BIT(ISR_ACKNAK, "NAK",          "ACK"),
  98         BIT(ISR_UB,     "Bsy",          "Rdy"),
  99         BIT(ISR_IBB,    "BusBsy",       "BusRdy"),
 100         BIT(ISR_SSD,    "SlaveStop",    NULL),
 101         BIT(ISR_ALD,    "ALD",          NULL),
 102         BIT(ISR_ITE,    "TxEmpty",      NULL),
 103         BIT(ISR_IRF,    "RxFull",       NULL),
 104         BIT(ISR_GCAD,   "GenCall",      NULL),
 105         BIT(ISR_SAD,    "SlaveAddr",    NULL),
 106         BIT(ISR_BED,    "BusErr",       NULL),
 107 };
 108
 109 static void decode_ISR(unsigned int val)
 110 {
 111         decode_bits(DBGLVL "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 112         printk("\n");
 113 }
 114
 115 static const struct bits icr_bits[] = {
 116         BIT(ICR_START,  "START",        NULL),
 117         BIT(ICR_STOP,   "STOP",         NULL),
 118         BIT(ICR_ACKNAK, "ACKNAK",       NULL),
 119         BIT(ICR_TB,     "TB",           NULL),
 120         BIT(ICR_MA,     "MA",           NULL),
 121         BIT(ICR_SCLE,   "SCLE",         "scle"),
 122         BIT(ICR_IUE,    "IUE",          "iue"),
 123         BIT(ICR_GCD,    "GCD",          NULL),
 124         BIT(ICR_ITEIE,  "ITEIE",        NULL),
 125         BIT(ICR_IRFIE,  "IRFIE",        NULL),
 126         BIT(ICR_BEIE,   "BEIE",         NULL),
 127         BIT(ICR_SSDIE,  "SSDIE",        NULL),
 128         BIT(ICR_ALDIE,  "ALDIE",        NULL),
 129         BIT(ICR_SADIE,  "SADIE",        NULL),
 130         BIT(ICR_UR,     "UR",           "ur"),
 131 };
 132
 133 static void decode_ICR(unsigned int val)
 134 {
 135         decode_bits(DBGLVL "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 136         printk("\n");
 137 }
 138
 139 static unsigned int i2c_debug = DEBUG;
 140
 141 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 142 {
 143         printk(DBGLVL "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR);
 144 }
 145
 146 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
 147 #else
 148 #define i2c_debug       0
 149
 150 #define show_state(i2c) do { } while (0)
 151 #define decode_ISR(val) do { } while (0)
 152 #define decode_ICR(val) do { } while (0)
 153 #endif
 154
 155 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(DBGLVL "" x); } } while(0)
 156
 157 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 158
 159 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 160 {
 161         unsigned int i;
 162         printk("i2c: error: %s\n", why);
 163         printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
 164                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 165         printk("i2c: ICR: %08x ISR: %08x\ni2c: log: ", ICR, ISR);
 166         for (i = 0; i < i2c->irqlogidx; i++)
 167                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
 168         printk("\n");
 169 }
 170
 171 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 172 {
 173         return !(ICR & ICR_SCLE);
 174 }
 175
 176 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 177 {
 178         unsigned long timeout = jiffies + HZ/4;
 179
 180         if (i2c_pxa_is_slavemode(i2c)) {
 181                 printk(DBGLVL "i2c_pxa_transfer: called in slave mode\n");
 182                 return;
 183         }
 184
 185         while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) {
 186                 unsigned long icr = ICR;
 187
 188                 icr &= ~ICR_START;
 189                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 190
 191                 ICR = icr;
 192
 193                 show_state(i2c);
 194
 195                 msleep(1);
 196         }
 197
 198         ICR &= ~(ICR_MA | ICR_START | ICR_STOP);
 199 }
 200
 201 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 202 {
 203         int timeout = DEF_TIMEOUT;
 204
 205         while (timeout-- && ISR & (ISR_IBB | ISR_UB)) {
 206                 if ((ISR & ISR_SAD) != 0)
 207                         timeout += 4;
 208
 209                 msleep(2);
 210                 show_state(i2c);
 211         }
 212
 213         if (timeout <= 0)
 214                 show_state(i2c);
 215
 216         return timeout <= 0 ? I2C_RETRY : 0;
 217 }
 218
 219 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 220 {
 221         unsigned long timeout = jiffies + HZ*4;
 222
 223         while (time_before(jiffies, timeout)) {
 224                 if (i2c_debug > 1)
 225                         printk(DBGLVL "i2c_pxa_wait_master: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 226                                (long)jiffies, ISR, ICR, IBMR);
 227
 228                 if (ISR & ISR_SAD) {
 229                         if (i2c_debug > 0)
 230                                 printk(DBGLVL "i2c_pxa_wait_master: Slave detected\n");
 231                         goto out;
 232                 }
 233
 234                 /* wait for unit and bus being not busy, and we also do a
 235                  * quick check of the i2c lines themselves to ensure they've
 236                  * gone high...
 237                  */
 238                 if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) {
 239                         if (i2c_debug > 0)
 240                                 printk(DBGLVL "i2c_pxa_wait_master: done\n");
 241                         return 1;
 242                 }
 243
 244                 msleep(1);
 245         }
 246
 247         if (i2c_debug > 0)
 248                 printk(DBGLVL "i2c_pxa_wait_master: did not free\n");
 249  out:
 250         return 0;
 251 }
 252
 253 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 254 {
 255         if (i2c_debug)
 256                 printk(DBGLVL "I2C: setting to bus master\n");
 257
 258         if ((ISR & (ISR_UB | ISR_IBB)) != 0) {
 259                 printk(DBGLVL "set_master: unit is busy\n");
 260                 if (!i2c_pxa_wait_master(i2c)) {
 261                         printk(DBGLVL "set_master: error: unit busy\n");
 262                         return I2C_RETRY;
 263                 }
 264         }
 265
 266         ICR |= ICR_SCLE;
 267         return 0;
 268 }
 269
 270 #ifdef CONFIG_I2C_PXA_SLAVE
 271 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 272 {
 273         unsigned long timeout = jiffies + HZ*1;
 274
 275         /* wait for stop */
 276
 277         show_state(i2c);
 278
 279         while (time_before(jiffies, timeout)) {
 280                 if (i2c_debug > 1)
 281                         printk(DBGLVL "i2c_pxa_wait_slave: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 282                                (long)jiffies, ISR, ICR, IBMR);
 283
 284                 if ((ISR & (ISR_UB|ISR_IBB|ISR_SAD)) == ISR_SAD ||
 285                     (ICR & ICR_SCLE) == 0) {
 286                         if (i2c_debug > 1)
 287                                 printk(DBGLVL "i2c_pxa_wait_slave: done\n");
 288                         return 1;
 289                 }
 290
 291                 msleep(1);
 292         }
 293
 294         if (i2c_debug > 0)
 295                 printk(DBGLVL "i2c_pxa_wait_slave: did not free\n");
 296         return 0;
 297 }
 298
 299 /*
 300  * clear the hold on the bus, and take of anything else
 301  * that has been configured
 302  */
 303 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 304 {
 305         show_state(i2c);
 306
 307         if (errcode < 0) {
 308                 udelay(100);   /* simple delay */
 309         } else {
 310                 /* we need to wait for the stop condition to end */
 311
 312                 /* if we where in stop, then clear... */
 313                 if (ICR & ICR_STOP) {
 314                         udelay(100);
 315                         ICR &= ~ICR_STOP;
 316                 }
 317
 318                 if (!i2c_pxa_wait_slave(i2c)) {
 319                         printk(KERN_ERR "i2c_pxa_set_slave: wait timedout\n");
 320                         return;
 321                 }
 322         }
 323
 324         ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA);
 325         ICR &= ~ICR_SCLE;
 326
 327         if (i2c_debug) {
 328                 printk(DBGLVL "ICR now %08x, ISR %08x\n", ICR, ISR);
 329                 decode_ICR(ICR);
 330         }
 331 }
 332 #else
 333 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 334 #endif
 335
 336 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 337 {
 338         pr_debug("Resetting I2C Controller Unit\n");
 339
 340         /* abort any transfer currently under way */
 341         i2c_pxa_abort(i2c);
 342
 343         /* reset according to 9.8 */
 344         ICR = ICR_UR;
 345         ISR = I2C_ISR_INIT;
 346         ICR &= ~ICR_UR;
 347
 348         ISAR = i2c->slave_addr;
 349
 350         /* set control register values */
 351         ICR = I2C_ICR_INIT;
 352
 353 #ifdef CONFIG_I2C_PXA_SLAVE
 354         printk(KERN_INFO "I2C: Enabling slave mode\n");
 355         ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE;
 356 #endif
 357
 358         i2c_pxa_set_slave(i2c, 0);
 359
 360         /* enable unit */
 361         ICR |= ICR_IUE;
 362         udelay(100);
 363 }
 364
 365
 366 #ifdef CONFIG_I2C_PXA_SLAVE
 367 /*
 368  * I2C EEPROM emulation.
 369  */
 370 static struct i2c_eeprom_emu eeprom = {
 371         .size = I2C_EEPROM_EMU_SIZE,
 372         .watch = LIST_HEAD_INIT(eeprom.watch),
 373 };
 374
 375 struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void)
 376 {
 377         return &eeprom;
 378 }
 379
 380 int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *emu, void *data,
 381                               unsigned int addr, unsigned int size,
 382                               struct i2c_eeprom_emu_watcher *watcher)
 383 {
 384         struct i2c_eeprom_emu_watch *watch;
 385         unsigned long flags;
 386
 387         if (addr + size > emu->size)
 388                 return -EINVAL;
 389
 390         watch = kmalloc(sizeof(struct i2c_eeprom_emu_watch), GFP_KERNEL);
 391         if (watch) {
 392                 watch->start = addr;
 393                 watch->end = addr + size - 1;
 394                 watch->ops = watcher;
 395                 watch->data = data;
 396
 397                 local_irq_save(flags);
 398                 list_add(&watch->node, &emu->watch);
 399                 local_irq_restore(flags);
 400         }
 401
 402         return watch ? 0 : -ENOMEM;
 403 }
 404
 405 void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *emu, void *data,
 406                                struct i2c_eeprom_emu_watcher *watcher)
 407 {
 408         struct i2c_eeprom_emu_watch *watch, *n;
 409         unsigned long flags;
 410
 411         list_for_each_entry_safe(watch, n, &emu->watch, node) {
 412                 if (watch->ops == watcher && watch->data == data) {
 413                         local_irq_save(flags);
 414                         list_del(&watch->node);
 415                         local_irq_restore(flags);
 416                         kfree(watch);
 417                 }
 418         }
 419 }
 420
 421 static void i2c_eeprom_emu_event(void *ptr, i2c_slave_event_t event)
 422 {
 423         struct i2c_eeprom_emu *emu = ptr;
 424
 425         eedbg(3, "i2c_eeprom_emu_event: %d\n", event);
 426
 427         switch (event) {
 428         case I2C_SLAVE_EVENT_START_WRITE:
 429                 emu->seen_start = 1;
 430                 eedbg(2, "i2c_eeprom: write initiated\n");
 431                 break;
 432
 433         case I2C_SLAVE_EVENT_START_READ:
 434                 emu->seen_start = 0;
 435                 eedbg(2, "i2c_eeprom: read initiated\n");
 436                 break;
 437
 438         case I2C_SLAVE_EVENT_STOP:
 439                 emu->seen_start = 0;
 440                 eedbg(2, "i2c_eeprom: received stop\n");
 441                 break;
 442
 443         default:
 444                 eedbg(0, "i2c_eeprom: unhandled event\n");
 445                 break;
 446         }
 447 }
 448
 449 static int i2c_eeprom_emu_read(void *ptr)
 450 {
 451         struct i2c_eeprom_emu *emu = ptr;
 452         int ret;
 453
 454         ret = emu->bytes[emu->ptr];
 455         emu->ptr = (emu->ptr + 1) % emu->size;
 456
 457         return ret;
 458 }
 459
 460 static void i2c_eeprom_emu_write(void *ptr, unsigned int val)
 461 {
 462         struct i2c_eeprom_emu *emu = ptr;
 463         struct i2c_eeprom_emu_watch *watch;
 464
 465         if (emu->seen_start != 0) {
 466                 eedbg(2, "i2c_eeprom_emu_write: setting ptr %02x\n", val);
 467                 emu->ptr = val;
 468                 emu->seen_start = 0;
 469                 return;
 470         }
 471
 472         emu->bytes[emu->ptr] = val;
 473
 474         eedbg(1, "i2c_eeprom_emu_write: ptr=0x%02x, val=0x%02x\n",
 475               emu->ptr, val);
 476
 477         list_for_each_entry(watch, &emu->watch, node) {
 478                 if (!watch->ops || !watch->ops->write)
 479                         continue;
 480                 if (watch->start <= emu->ptr && watch->end >= emu->ptr)
 481                         watch->ops->write(watch->data, emu->ptr, val);
 482         }
 483
 484         emu->ptr = (emu->ptr + 1) % emu->size;
 485 }
 486
 487 struct i2c_slave_client eeprom_client = {
 488         .data   = &eeprom,
 489         .event  = i2c_eeprom_emu_event,
 490         .read   = i2c_eeprom_emu_read,
 491         .write  = i2c_eeprom_emu_write
 492 };
 493
 494 /*
 495  * PXA I2C Slave mode
 496  */
 497
 498 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 499 {
 500         if (isr & ISR_BED) {
 501                 /* what should we do here? */
 502         } else {
 503                 int ret = i2c->slave->read(i2c->slave->data);
 504
 505                 IDBR = ret;
 506                 ICR |= ICR_TB;   /* allow next byte */
 507         }
 508 }
 509
 510 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 511 {
 512         unsigned int byte = IDBR;
 513
 514         if (i2c->slave != NULL)
 515                 i2c->slave->write(i2c->slave->data, byte);
 516
 517         ICR |= ICR_TB;
 518 }
 519
 520 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 521 {
 522         int timeout;
 523
 524         if (i2c_debug > 0)
 525                 printk(DBGLVL "I2C: SAD, mode is slave-%cx\n",
 526                        (isr & ISR_RWM) ? 'r' : 't');
 527
 528         if (i2c->slave != NULL)
 529                 i2c->slave->event(i2c->slave->data,
 530                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
 531
 532         /*
 533          * slave could interrupt in the middle of us generating a
 534          * start condition... if this happens, we'd better back off
 535          * and stop holding the poor thing up
 536          */
 537         ICR &= ~(ICR_START|ICR_STOP);
 538         ICR |= ICR_TB;
 539
 540         timeout = 0x10000;
 541
 542         while (1) {
 543                 if ((IBMR & 2) == 2)
 544                         break;
 545
 546                 timeout--;
 547
 548                 if (timeout <= 0) {
 549                         printk(KERN_ERR "timeout waiting for SCL high\n");
 550                         break;
 551                 }
 552         }
 553
 554         ICR &= ~ICR_SCLE;
 555 }
 556
 557 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 558 {
 559         if (i2c_debug > 2)
 560                 printk(DBGLVL "ISR: SSD (Slave Stop)\n");
 561
 562         if (i2c->slave != NULL)
 563                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
 564
 565         if (i2c_debug > 2)
 566                 printk(DBGLVL "ISR: SSD (Slave Stop) acked\n");
 567
 568         /*
 569          * If we have a master-mode message waiting,
 570          * kick it off now that the slave has completed.
 571          */
 572         if (i2c->msg)
 573                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 574 }
 575 #else
 576 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 577 {
 578         if (isr & ISR_BED) {
 579                 /* what should we do here? */
 580         } else {
 581                 IDBR = 0;
 582                 ICR |= ICR_TB;
 583         }
 584 }
 585
 586 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 587 {
 588         ICR |= ICR_TB | ICR_ACKNAK;
 589 }
 590
 591 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 592 {
 593         int timeout;
 594
 595         /*
 596          * slave could interrupt in the middle of us generating a
 597          * start condition... if this happens, we'd better back off
 598          * and stop holding the poor thing up
 599          */
 600         ICR &= ~(ICR_START|ICR_STOP);
 601         ICR |= ICR_TB | ICR_ACKNAK;
 602
 603         timeout = 0x10000;
 604
 605         while (1) {
 606                 if ((IBMR & 2) == 2)
 607                         break;
 608
 609                 timeout--;
 610
 611                 if (timeout <= 0) {
 612                         printk(KERN_ERR "timeout waiting for SCL high\n");
 613                         break;
 614                 }
 615         }
 616
 617         ICR &= ~ICR_SCLE;
 618 }
 619
 620 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 621 {
 622         if (i2c->msg)
 623                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 624 }
 625 #endif
 626
 627 /*
 628  * PXA I2C Master mode
 629  */
 630
 631 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
 632 {
 633         unsigned int addr = (msg->addr & 0x7f) << 1;
 634
 635         if (msg->flags & I2C_M_RD)
 636                 addr |= 1;
 637
 638         return addr;
 639 }
 640
 641 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 642 {
 643         u32 icr;
 644
 645         /*
 646          * Step 1: target slave address into IDBR
 647          */
 648         IDBR = i2c_pxa_addr_byte(i2c->msg);
 649
 650         /*
 651          * Step 2: initiate the write.
 652          */
 653         icr = ICR & ~(ICR_STOP | ICR_ALDIE);
 654         ICR = icr | ICR_START | ICR_TB;
 655 }
 656
 657 /*
 658  * We are protected by the adapter bus semaphore.
 659  */
 660 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
 661 {
 662         long timeout;
 663         int ret;
 664
 665         /*
 666          * Wait for the bus to become free.
 667          */
 668         ret = i2c_pxa_wait_bus_not_busy(i2c);
 669         if (ret) {
 670                 printk(KERN_INFO "i2c_pxa: timeout waiting for bus free\n");
 671                 goto out;
 672         }
 673
 674         /*
 675          * Set master mode.
 676          */
 677         ret = i2c_pxa_set_master(i2c);
 678         if (ret) {
 679                 printk(KERN_INFO "i2c_pxa_set_master: error %d\n", ret);
 680                 goto out;
 681         }
 682
 683         spin_lock_irq(&i2c->lock);
 684
 685         i2c->msg = msg;
 686         i2c->msg_num = num;
 687         i2c->msg_idx = 0;
 688         i2c->msg_ptr = 0;
 689         i2c->irqlogidx = 0;
 690
 691         i2c_pxa_start_message(i2c);
 692
 693         spin_unlock_irq(&i2c->lock);
 694
 695         /*
 696          * The rest of the processing occurs in the interrupt handler.
 697          */
 698         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 699
 700         /*
 701          * We place the return code in i2c->msg_idx.
 702          */
 703         ret = i2c->msg_idx;
 704
 705         if (timeout == 0)
 706                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 707
 708  out:
 709         return ret;
 710 }
 711
 712 /*
 713  * i2c_pxa_master_complete - complete the message and wake up.
 714  */
 715 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 716 {
 717         i2c->msg_ptr = 0;
 718         i2c->msg = NULL;
 719         i2c->msg_idx ++;
 720         i2c->msg_num = 0;
 721         if (ret)
 722                 i2c->msg_idx = ret;
 723         wake_up(&i2c->wait);
 724 }
 725
 726 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 727 {
 728         u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 729
 730  again:
 731         /*
 732          * If ISR_ALD is set, we lost arbitration.
 733          */
 734         if (isr & ISR_ALD) {
 735                 /*
 736                  * Do we need to do anything here?  The PXA docs
 737                  * are vague about what happens.
 738                  */
 739                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 740
 741                 /*
 742                  * We ignore this error.  We seem to see spurious ALDs
 743                  * for seemingly no reason.  If we handle them as I think
 744                  * they should, we end up causing an I2C error, which
 745                  * is painful for some systems.
 746                  */
 747                 return; /* ignore */
 748         }
 749
 750         if (isr & ISR_BED) {
 751                 int ret = BUS_ERROR;
 752
 753                 /*
 754                  * I2C bus error - either the device NAK'd us, or
 755                  * something more serious happened.  If we were NAK'd
 756                  * on the initial address phase, we can retry.
 757                  */
 758                 if (isr & ISR_ACKNAK) {
 759                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 760                                 ret = I2C_RETRY;
 761                         else
 762                                 ret = XFER_NAKED;
 763                 }
 764                 i2c_pxa_master_complete(i2c, ret);
 765         } else if (isr & ISR_RWM) {
 766                 /*
 767                  * Read mode.  We have just sent the address byte, and
 768                  * now we must initiate the transfer.
 769                  */
 770                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 771                     i2c->msg_idx == i2c->msg_num - 1)
 772                         icr |= ICR_STOP | ICR_ACKNAK;
 773
 774                 icr |= ICR_ALDIE | ICR_TB;
 775         } else if (i2c->msg_ptr < i2c->msg->len) {
 776                 /*
 777                  * Write mode.  Write the next data byte.
 778                  */
 779                 IDBR = i2c->msg->buf[i2c->msg_ptr++];
 780
 781                 icr |= ICR_ALDIE | ICR_TB;
 782
 783                 /*
 784                  * If this is the last byte of the last message, send
 785                  * a STOP.
 786                  */
 787                 if (i2c->msg_ptr == i2c->msg->len &&
 788                     i2c->msg_idx == i2c->msg_num - 1)
 789                         icr |= ICR_STOP;
 790         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 791                 /*
 792                  * Next segment of the message.
 793                  */
 794                 i2c->msg_ptr = 0;
 795                 i2c->msg_idx ++;
 796                 i2c->msg++;
 797
 798                 /*
 799                  * If we aren't doing a repeated start and address,
 800                  * go back and try to send the next byte.  Note that
 801                  * we do not support switching the R/W direction here.
 802                  */
 803                 if (i2c->msg->flags & I2C_M_NOSTART)
 804                         goto again;
 805
 806                 /*
 807                  * Write the next address.
 808                  */
 809                 IDBR = i2c_pxa_addr_byte(i2c->msg);
 810
 811                 /*
 812                  * And trigger a repeated start, and send the byte.
 813                  */
 814                 icr &= ~ICR_ALDIE;
 815                 icr |= ICR_START | ICR_TB;
 816         } else {
 817                 if (i2c->msg->len == 0) {
 818                         /*
 819                          * Device probes have a message length of zero
 820                          * and need the bus to be reset before it can
 821                          * be used again.
 822                          */
 823                         i2c_pxa_reset(i2c);
 824                 }
 825                 i2c_pxa_master_complete(i2c, 0);
 826         }
 827
 828         i2c->icrlog[i2c->irqlogidx-1] = icr;
 829
 830         ICR = icr;
 831         show_state(i2c);
 832 }
 833
 834 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 835 {
 836         u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 837
 838         /*
 839          * Read the byte.
 840          */
 841         i2c->msg->buf[i2c->msg_ptr++] = IDBR;
 842
 843         if (i2c->msg_ptr < i2c->msg->len) {
 844                 /*
 845                  * If this is the last byte of the last
 846                  * message, send a STOP.
 847                  */
 848                 if (i2c->msg_ptr == i2c->msg->len - 1)
 849                         icr |= ICR_STOP | ICR_ACKNAK;
 850
 851                 icr |= ICR_ALDIE | ICR_TB;
 852         } else {
 853                 i2c_pxa_master_complete(i2c, 0);
 854         }
 855
 856         i2c->icrlog[i2c->irqlogidx-1] = icr;
 857
 858         ICR = icr;
 859 }
 860
 861 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id, struct pt_regs *regs)
 862 {
 863         struct pxa_i2c *i2c = dev_id;
 864         u32 isr = ISR;
 865
 866         if (i2c_debug > 2 && 0) {
 867                 printk(DBGLVL "i2c_pxa_handler: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 868                        isr, ICR, IBMR);
 869                 decode_ISR(isr);
 870         }
 871
 872         if (i2c->irqlogidx < sizeof(i2c->isrlog)/sizeof(u32))
 873                 i2c->isrlog[i2c->irqlogidx++] = isr;
 874
 875         show_state(i2c);
 876
 877         /*
 878          * Always clear all pending IRQs.
 879          */
 880         ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED);
 881
 882         if (isr & ISR_SAD)
 883                 i2c_pxa_slave_start(i2c, isr);
 884         if (isr & ISR_SSD)
 885                 i2c_pxa_slave_stop(i2c);
 886
 887         if (i2c_pxa_is_slavemode(i2c)) {
 888                 if (isr & ISR_ITE)
 889                         i2c_pxa_slave_txempty(i2c, isr);
 890                 if (isr & ISR_IRF)
 891                         i2c_pxa_slave_rxfull(i2c, isr);
 892         } else if (i2c->msg) {
 893                 if (isr & ISR_ITE)
 894                         i2c_pxa_irq_txempty(i2c, isr);
 895                 if (isr & ISR_IRF)
 896                         i2c_pxa_irq_rxfull(i2c, isr);
 897         } else {
 898                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
 899         }
 900
 901         return IRQ_HANDLED;
 902 }
 903
 904
 905 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 906 {
 907         struct pxa_i2c *i2c = adap->algo_data;
 908         int ret, i;
 909
 910         for (i = adap->retries; i >= 0; i--) {
 911                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
 912                 if (ret != I2C_RETRY)
 913                         goto out;
 914
 915                 if (i2c_debug)
 916                         printk(KERN_INFO "Retrying transmission\n");
 917                 udelay(100);
 918         }
 919         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 920         ret = -EREMOTEIO;
 921  out:
 922         i2c_pxa_set_slave(i2c, ret);
 923         return ret;
 924 }
 925
 926 static struct i2c_algorithm i2c_pxa_algorithm = {
 927         .name           = "PXA-I2C-Algorithm",
 928         .id             = I2C_ALGO_PXA,
 929         .master_xfer    = i2c_pxa_xfer,
 930 };
 931
 932 static struct pxa_i2c i2c_pxa = {
 933         .lock   = SPIN_LOCK_UNLOCKED,
 934         .wait   = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),
 935         .adap   = {
 936                 .name           = "pxa2xx-i2c",
 937                 .id             = I2C_ALGO_PXA,
 938                 .algo           = &i2c_pxa_algorithm,
 939                 .retries        = 5,
 940         },
 941 };
 942
 943 static int i2c_pxa_probe(struct device *dev)
 944 {
 945         struct pxa_i2c *i2c = &i2c_pxa;
 946         struct i2c_pxa_platform_data *plat = dev->platform_data;
 947         int ret;
 948
 949 #ifdef CONFIG_PXA27x
 950         pxa_gpio_mode(GPIO117_I2CSCL_MD);
 951         pxa_gpio_mode(GPIO118_I2CSDA_MD);
 952         udelay(100);
 953 #endif
 954
 955         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
 956
 957 #ifdef CONFIG_I2C_PXA_SLAVE
 958         i2c->slave = &eeprom_client;
 959         if (plat) {
 960                 i2c->slave_addr = plat->slave_addr;
 961                 if (plat->slave)
 962                         i2c->slave = plat->slave;
 963         }
 964 #endif
 965
 966         pxa_set_cken(CKEN14_I2C, 1);
 967         ret = request_irq(IRQ_I2C, i2c_pxa_handler, SA_INTERRUPT,
 968                           "pxa2xx-i2c", i2c);
 969         if (ret)
 970                 goto out;
 971
 972         i2c_pxa_reset(i2c);
 973
 974         i2c->adap.algo_data = i2c;
 975         i2c->adap.dev.parent = dev;
 976
 977         ret = i2c_add_adapter(&i2c->adap);
 978         if (ret < 0) {
 979                 printk(KERN_INFO "I2C: Failed to add bus\n");
 980                 goto err_irq;
 981         }
 982
 983         dev_set_drvdata(dev, i2c);
 984
 985 #ifdef CONFIG_I2C_PXA_SLAVE
 986         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
 987                i2c->adap.dev.bus_id, i2c->slave_addr);
 988 #else
 989         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
 990                i2c->adap.dev.bus_id);
 991 #endif
 992         return 0;
 993
 994  err_irq:
 995         free_irq(IRQ_I2C, i2c);
 996  out:
 997         return ret;
 998 }
 999
1000 static int i2c_pxa_remove(struct device *dev)
1001 {
1002         struct pxa_i2c *i2c = dev_get_drvdata(dev);
1003
1004         dev_set_drvdata(dev, NULL);
1005
1006         i2c_del_adapter(&i2c->adap);
1007         free_irq(IRQ_I2C, i2c);
1008         pxa_set_cken(CKEN14_I2C, 0);
1009
1010         return 0;
1011 }
1012
1013 static struct device_driver i2c_pxa_driver = {
1014         .name           = "pxa2xx-i2c",
1015         .bus            = &platform_bus_type,
1016         .probe          = i2c_pxa_probe,
1017         .remove         = i2c_pxa_remove,
1018 };
1019
1020 static int __init i2c_adap_pxa_init(void)
1021 {
1022         return driver_register(&i2c_pxa_driver);
1023 }
1024
1025 static void i2c_adap_pxa_exit(void)
1026 {
1027         return driver_unregister(&i2c_pxa_driver);
1028 }
1029
1030 module_init(i2c_adap_pxa_init);
1031 module_exit(i2c_adap_pxa_exit);