SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40 #include <linux/slab.h>
  41 #include <linux/i2c-omap.h>
  42
  43 /* I2C controller revisions */
  44 #define OMAP_I2C_REV_2                  0x20
  45
  46 /* I2C controller revisions present on specific hardware */
  47 #define OMAP_I2C_REV_ON_2430            0x36
  48 #define OMAP_I2C_REV_ON_3430            0x3C
  49 #define OMAP_I2C_REV_ON_4430            0x40
  50
  51 /* timeout waiting for the controller to respond */
  52 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  53
  54 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
  55 enum {
  56         OMAP_I2C_REV_REG = 0,
  57         OMAP_I2C_IE_REG,
  58         OMAP_I2C_STAT_REG,
  59         OMAP_I2C_IV_REG,
  60         OMAP_I2C_WE_REG,
  61         OMAP_I2C_SYSS_REG,
  62         OMAP_I2C_BUF_REG,
  63         OMAP_I2C_CNT_REG,
  64         OMAP_I2C_DATA_REG,
  65         OMAP_I2C_SYSC_REG,
  66         OMAP_I2C_CON_REG,
  67         OMAP_I2C_OA_REG,
  68         OMAP_I2C_SA_REG,
  69         OMAP_I2C_PSC_REG,
  70         OMAP_I2C_SCLL_REG,
  71         OMAP_I2C_SCLH_REG,
  72         OMAP_I2C_SYSTEST_REG,
  73         OMAP_I2C_BUFSTAT_REG,
  74         OMAP_I2C_REVNB_LO,
  75         OMAP_I2C_REVNB_HI,
  76         OMAP_I2C_IRQSTATUS_RAW,
  77         OMAP_I2C_IRQENABLE_SET,
  78         OMAP_I2C_IRQENABLE_CLR,
  79 };
  80
  81 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  82 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  83 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  84 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  85 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  86 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  87 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  88 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  89
  90 /* I2C Status Register (OMAP_I2C_STAT): */
  91 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  92 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  93 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  94 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  95 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  96 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  97 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  98 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  99 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
 100 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
 101 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
 102 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
 103
 104 /* I2C WE wakeup enable register */
 105 #define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
 106 #define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
 107 #define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
 108 #define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
 109 #define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
 110 #define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
 111 #define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
 112 #define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
 113 #define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
 114 #define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
 115
 116 #define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
 117                                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
 118                                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
 119                                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
 120                                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
 121
 122 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
 123 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
 124 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
 125 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
 126 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
 127
 128 /* I2C Configuration Register (OMAP_I2C_CON): */
 129 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 130 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 131 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 132 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 133 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 134 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 135 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 136 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 137 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 138 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 139
 140 /* I2C SCL time value when Master */
 141 #define OMAP_I2C_SCLL_HSSCLL    8
 142 #define OMAP_I2C_SCLH_HSSCLH    8
 143
 144 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 145 #ifdef DEBUG
 146 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 147 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 148 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 149 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 150 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 151 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 152 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 153 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 154 #endif
 155
 156 /* OCP_SYSSTATUS bit definitions */
 157 #define SYSS_RESETDONE_MASK             (1 << 0)
 158
 159 /* OCP_SYSCONFIG bit definitions */
 160 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
 161 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
 162 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
 163 #define SYSC_SOFTRESET_MASK             (1 << 1)
 164 #define SYSC_AUTOIDLE_MASK              (1 << 0)
 165
 166 #define SYSC_IDLEMODE_SMART             0x2
 167 #define SYSC_CLOCKACTIVITY_FCLK         0x2
 168
 169 /* Errata definitions */
 170 #define I2C_OMAP_ERRATA_I207            (1 << 0)
 171
 172 struct omap_i2c_dev {
 173         struct device           *dev;
 174         void __iomem            *base;          /* virtual */
 175         int                     irq;
 176         int                     reg_shift;      /* bit shift for I2C register addresses */
 177         struct clk              *iclk;          /* Interface clock */
 178         struct clk              *fclk;          /* Functional clock */
 179         struct completion       cmd_complete;
 180         struct resource         *ioarea;
 181         u32                     latency;        /* maximum mpu wkup latency */
 182         void                    (*set_mpu_wkup_lat)(struct device *dev,
 183                                                     long latency);
 184         u32                     speed;          /* Speed of bus in Khz */
 185         u16                     cmd_err;
 186         u8                      *buf;
 187         u8                      *regs;
 188         size_t                  buf_len;
 189         struct i2c_adapter      adapter;
 190         u8                      fifo_size;      /* use as flag and value
 191                                                  * fifo_size==0 implies no fifo
 192                                                  * if set, should be trsh+1
 193                                                  */
 194         u8                      rev;
 195         unsigned                b_hw:1;         /* bad h/w fixes */
 196         unsigned                idle:1;
 197         u16                     iestate;        /* Saved interrupt register */
 198         u16                     pscstate;
 199         u16                     scllstate;
 200         u16                     sclhstate;
 201         u16                     bufstate;
 202         u16                     syscstate;
 203         u16                     westate;
 204         u16                     errata;
 205 };
 206
 207 const static u8 reg_map[] = {
 208         [OMAP_I2C_REV_REG] = 0x00,
 209         [OMAP_I2C_IE_REG] = 0x01,
 210         [OMAP_I2C_STAT_REG] = 0x02,
 211         [OMAP_I2C_IV_REG] = 0x03,
 212         [OMAP_I2C_WE_REG] = 0x03,
 213         [OMAP_I2C_SYSS_REG] = 0x04,
 214         [OMAP_I2C_BUF_REG] = 0x05,
 215         [OMAP_I2C_CNT_REG] = 0x06,
 216         [OMAP_I2C_DATA_REG] = 0x07,
 217         [OMAP_I2C_SYSC_REG] = 0x08,
 218         [OMAP_I2C_CON_REG] = 0x09,
 219         [OMAP_I2C_OA_REG] = 0x0a,
 220         [OMAP_I2C_SA_REG] = 0x0b,
 221         [OMAP_I2C_PSC_REG] = 0x0c,
 222         [OMAP_I2C_SCLL_REG] = 0x0d,
 223         [OMAP_I2C_SCLH_REG] = 0x0e,
 224         [OMAP_I2C_SYSTEST_REG] = 0x0f,
 225         [OMAP_I2C_BUFSTAT_REG] = 0x10,
 226 };
 227
 228 const static u8 omap4_reg_map[] = {
 229         [OMAP_I2C_REV_REG] = 0x04,
 230         [OMAP_I2C_IE_REG] = 0x2c,
 231         [OMAP_I2C_STAT_REG] = 0x28,
 232         [OMAP_I2C_IV_REG] = 0x34,
 233         [OMAP_I2C_WE_REG] = 0x34,
 234         [OMAP_I2C_SYSS_REG] = 0x90,
 235         [OMAP_I2C_BUF_REG] = 0x94,
 236         [OMAP_I2C_CNT_REG] = 0x98,
 237         [OMAP_I2C_DATA_REG] = 0x9c,
 238         [OMAP_I2C_SYSC_REG] = 0x20,
 239         [OMAP_I2C_CON_REG] = 0xa4,
 240         [OMAP_I2C_OA_REG] = 0xa8,
 241         [OMAP_I2C_SA_REG] = 0xac,
 242         [OMAP_I2C_PSC_REG] = 0xb0,
 243         [OMAP_I2C_SCLL_REG] = 0xb4,
 244         [OMAP_I2C_SCLH_REG] = 0xb8,
 245         [OMAP_I2C_SYSTEST_REG] = 0xbC,
 246         [OMAP_I2C_BUFSTAT_REG] = 0xc0,
 247         [OMAP_I2C_REVNB_LO] = 0x00,
 248         [OMAP_I2C_REVNB_HI] = 0x04,
 249         [OMAP_I2C_IRQSTATUS_RAW] = 0x24,
 250         [OMAP_I2C_IRQENABLE_SET] = 0x2c,
 251         [OMAP_I2C_IRQENABLE_CLR] = 0x30,
 252 };
 253
 254 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 255                                       int reg, u16 val)
 256 {
 257         __raw_writew(val, i2c_dev->base +
 258                         (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 259 }
 260
 261 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 262 {
 263         return __raw_readw(i2c_dev->base +
 264                                 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 265 }
 266
 267 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 268 {
 269         int ret;
 270
 271         dev->iclk = clk_get(dev->dev, "ick");
 272         if (IS_ERR(dev->iclk)) {
 273                 ret = PTR_ERR(dev->iclk);
 274                 dev->iclk = NULL;
 275                 return ret;
 276         }
 277
 278         dev->fclk = clk_get(dev->dev, "fck");
 279         if (IS_ERR(dev->fclk)) {
 280                 ret = PTR_ERR(dev->fclk);
 281                 if (dev->iclk != NULL) {
 282                         clk_put(dev->iclk);
 283                         dev->iclk = NULL;
 284                 }
 285                 dev->fclk = NULL;
 286                 return ret;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 293 {
 294         clk_put(dev->fclk);
 295         dev->fclk = NULL;
 296         clk_put(dev->iclk);
 297         dev->iclk = NULL;
 298 }
 299
 300 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 301 {
 302         WARN_ON(!dev->idle);
 303
 304         clk_enable(dev->iclk);
 305         clk_enable(dev->fclk);
 306         if (cpu_is_omap34xx()) {
 307                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 308                 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
 309                 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
 310                 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
 311                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
 312                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
 313                 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
 314                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 315         }
 316         dev->idle = 0;
 317
 318         /*
 319          * Don't write to this register if the IE state is 0 as it can
 320          * cause deadlock.
 321          */
 322         if (dev->iestate)
 323                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 324 }
 325
 326 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 327 {
 328         u16 iv;
 329
 330         WARN_ON(dev->idle);
 331
 332         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 333         if (dev->rev >= OMAP_I2C_REV_ON_4430)
 334                 omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
 335         else
 336                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 337
 338         if (dev->rev < OMAP_I2C_REV_2) {
 339                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
 340         } else {
 341                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 342
 343                 /* Flush posted write before the dev->idle store occurs */
 344                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 345         }
 346         dev->idle = 1;
 347         clk_disable(dev->fclk);
 348         clk_disable(dev->iclk);
 349 }
 350
 351 static int omap_i2c_init(struct omap_i2c_dev *dev)
 352 {
 353         u16 psc = 0, scll = 0, sclh = 0, buf = 0;
 354         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 355         unsigned long fclk_rate = 12000000;
 356         unsigned long timeout;
 357         unsigned long internal_clk = 0;
 358
 359         if (dev->rev >= OMAP_I2C_REV_2) {
 360                 /* Disable I2C controller before soft reset */
 361                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 362                         omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
 363                                 ~(OMAP_I2C_CON_EN));
 364
 365                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
 366                 /* For some reason we need to set the EN bit before the
 367                  * reset done bit gets set. */
 368                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 369                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 370                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 371                          SYSS_RESETDONE_MASK)) {
 372                         if (time_after(jiffies, timeout)) {
 373                                 dev_warn(dev->dev, "timeout waiting "
 374                                                 "for controller reset\n");
 375                                 return -ETIMEDOUT;
 376                         }
 377                         msleep(1);
 378                 }
 379
 380                 /* SYSC register is cleared by the reset; rewrite it */
 381                 if (dev->rev == OMAP_I2C_REV_ON_2430) {
 382
 383                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 384                                            SYSC_AUTOIDLE_MASK);
 385
 386                 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
 387                         dev->syscstate = SYSC_AUTOIDLE_MASK;
 388                         dev->syscstate |= SYSC_ENAWAKEUP_MASK;
 389                         dev->syscstate |= (SYSC_IDLEMODE_SMART <<
 390                               __ffs(SYSC_SIDLEMODE_MASK));
 391                         dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
 392                               __ffs(SYSC_CLOCKACTIVITY_MASK));
 393
 394                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 395                                                         dev->syscstate);
 396                         /*
 397                          * Enabling all wakup sources to stop I2C freezing on
 398                          * WFI instruction.
 399                          * REVISIT: Some wkup sources might not be needed.
 400                          */
 401                         dev->westate = OMAP_I2C_WE_ALL;
 402                         if (dev->rev < OMAP_I2C_REV_ON_4430)
 403                                 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
 404                                                                 dev->westate);
 405                 }
 406         }
 407         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 408
 409         if (cpu_class_is_omap1()) {
 410                 /*
 411                  * The I2C functional clock is the armxor_ck, so there's
 412                  * no need to get "armxor_ck" separately.  Now, if OMAP2420
 413                  * always returns 12MHz for the functional clock, we can
 414                  * do this bit unconditionally.
 415                  */
 416                 fclk_rate = clk_get_rate(dev->fclk);
 417
 418                 /* TRM for 5912 says the I2C clock must be prescaled to be
 419                  * between 7 - 12 MHz. The XOR input clock is typically
 420                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 421                  *
 422                  * XOR MHz      Divider         Prescaler
 423                  * 12           1               0
 424                  * 13           2               1
 425                  * 19.2         2               1
 426                  */
 427                 if (fclk_rate > 12000000)
 428                         psc = fclk_rate / 12000000;
 429         }
 430
 431         if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
 432
 433                 /*
 434                  * HSI2C controller internal clk rate should be 19.2 Mhz for
 435                  * HS and for all modes on 2430. On 34xx we can use lower rate
 436                  * to get longer filter period for better noise suppression.
 437                  * The filter is iclk (fclk for HS) period.
 438                  */
 439                 if (dev->speed > 400 || cpu_is_omap2430())
 440                         internal_clk = 19200;
 441                 else if (dev->speed > 100)
 442                         internal_clk = 9600;
 443                 else
 444                         internal_clk = 4000;
 445                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
 446
 447                 /* Compute prescaler divisor */
 448                 psc = fclk_rate / internal_clk;
 449                 psc = psc - 1;
 450
 451                 /* If configured for High Speed */
 452                 if (dev->speed > 400) {
 453                         unsigned long scl;
 454
 455                         /* For first phase of HS mode */
 456                         scl = internal_clk / 400;
 457                         fsscll = scl - (scl / 3) - 7;
 458                         fssclh = (scl / 3) - 5;
 459
 460                         /* For second phase of HS mode */
 461                         scl = fclk_rate / dev->speed;
 462                         hsscll = scl - (scl / 3) - 7;
 463                         hssclh = (scl / 3) - 5;
 464                 } else if (dev->speed > 100) {
 465                         unsigned long scl;
 466
 467                         /* Fast mode */
 468                         scl = internal_clk / dev->speed;
 469                         fsscll = scl - (scl / 3) - 7;
 470                         fssclh = (scl / 3) - 5;
 471                 } else {
 472                         /* Standard mode */
 473                         fsscll = internal_clk / (dev->speed * 2) - 7;
 474                         fssclh = internal_clk / (dev->speed * 2) - 5;
 475                 }
 476                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 477                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 478         } else {
 479                 /* Program desired operating rate */
 480                 fclk_rate /= (psc + 1) * 1000;
 481                 if (psc > 2)
 482                         psc = 2;
 483                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 484                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 485         }
 486
 487         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 488         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 489
 490         /* SCL low and high time values */
 491         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 492         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 493
 494         if (dev->fifo_size) {
 495                 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
 496                 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
 497                         (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
 498                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
 499         }
 500
 501         /* Take the I2C module out of reset: */
 502         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 503
 504         dev->errata = 0;
 505
 506         if (cpu_is_omap2430() || cpu_is_omap34xx())
 507                 dev->errata |= I2C_OMAP_ERRATA_I207;
 508
 509         /* Enable interrupts */
 510         dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 511                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 512                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 513                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
 514         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 515         if (cpu_is_omap34xx()) {
 516                 dev->pscstate = psc;
 517                 dev->scllstate = scll;
 518                 dev->sclhstate = sclh;
 519                 dev->bufstate = buf;
 520         }
 521         return 0;
 522 }
 523
 524 /*
 525  * Waiting on Bus Busy
 526  */
 527 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 528 {
 529         unsigned long timeout;
 530
 531         timeout = jiffies + OMAP_I2C_TIMEOUT;
 532         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 533                 if (time_after(jiffies, timeout)) {
 534                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 535                         return -ETIMEDOUT;
 536                 }
 537                 msleep(1);
 538         }
 539
 540         return 0;
 541 }
 542
 543 /*
 544  * Low level master read/write transaction.
 545  */
 546 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 547                              struct i2c_msg *msg, int stop)
 548 {
 549         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 550         int r;
 551         u16 w;
 552
 553         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 554                 msg->addr, msg->len, msg->flags, stop);
 555
 556         if (msg->len == 0)
 557                 return -EINVAL;
 558
 559         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 560
 561         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 562         dev->buf = msg->buf;
 563         dev->buf_len = msg->len;
 564
 565         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 566
 567         /* Clear the FIFO Buffers */
 568         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 569         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 570         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 571
 572         init_completion(&dev->cmd_complete);
 573         dev->cmd_err = 0;
 574
 575         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 576
 577         /* High speed configuration */
 578         if (dev->speed > 400)
 579                 w |= OMAP_I2C_CON_OPMODE_HS;
 580
 581         if (msg->flags & I2C_M_TEN)
 582                 w |= OMAP_I2C_CON_XA;
 583         if (!(msg->flags & I2C_M_RD))
 584                 w |= OMAP_I2C_CON_TRX;
 585
 586         if (!dev->b_hw && stop)
 587                 w |= OMAP_I2C_CON_STP;
 588
 589         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 590
 591         /*
 592          * Don't write stt and stp together on some hardware.
 593          */
 594         if (dev->b_hw && stop) {
 595                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 596                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 597                 while (con & OMAP_I2C_CON_STT) {
 598                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 599
 600                         /* Let the user know if i2c is in a bad state */
 601                         if (time_after(jiffies, delay)) {
 602                                 dev_err(dev->dev, "controller timed out "
 603                                 "waiting for start condition to finish\n");
 604                                 return -ETIMEDOUT;
 605                         }
 606                         cpu_relax();
 607                 }
 608
 609                 w |= OMAP_I2C_CON_STP;
 610                 w &= ~OMAP_I2C_CON_STT;
 611                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 612         }
 613
 614         /*
 615          * REVISIT: We should abort the transfer on signals, but the bus goes
 616          * into arbitration and we're currently unable to recover from it.
 617          */
 618         if (dev->set_mpu_wkup_lat != NULL)
 619                 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
 620         r = wait_for_completion_timeout(&dev->cmd_complete,
 621                                         OMAP_I2C_TIMEOUT);
 622         if (dev->set_mpu_wkup_lat != NULL)
 623                 dev->set_mpu_wkup_lat(dev->dev, -1);
 624         dev->buf_len = 0;
 625         if (r < 0)
 626                 return r;
 627         if (r == 0) {
 628                 dev_err(dev->dev, "controller timed out\n");
 629                 omap_i2c_init(dev);
 630                 return -ETIMEDOUT;
 631         }
 632
 633         if (likely(!dev->cmd_err))
 634                 return 0;
 635
 636         /* We have an error */
 637         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 638                             OMAP_I2C_STAT_XUDF)) {
 639                 omap_i2c_init(dev);
 640                 return -EIO;
 641         }
 642
 643         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 644                 if (msg->flags & I2C_M_IGNORE_NAK)
 645                         return 0;
 646                 if (stop) {
 647                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 648                         w |= OMAP_I2C_CON_STP;
 649                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 650                 }
 651                 return -EREMOTEIO;
 652         }
 653         return -EIO;
 654 }
 655
 656
 657 /*
 658  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 659  * to do the work during IRQ processing.
 660  */
 661 static int
 662 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 663 {
 664         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 665         int i;
 666         int r;
 667
 668         omap_i2c_unidle(dev);
 669
 670         r = omap_i2c_wait_for_bb(dev);
 671         if (r < 0)
 672                 goto out;
 673
 674         for (i = 0; i < num; i++) {
 675                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 676                 if (r != 0)
 677                         break;
 678         }
 679
 680         if (r == 0)
 681                 r = num;
 682 out:
 683         omap_i2c_idle(dev);
 684         return r;
 685 }
 686
 687 static u32
 688 omap_i2c_func(struct i2c_adapter *adap)
 689 {
 690         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 691 }
 692
 693 static inline void
 694 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 695 {
 696         dev->cmd_err |= err;
 697         complete(&dev->cmd_complete);
 698 }
 699
 700 static inline void
 701 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 702 {
 703         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 704 }
 705
 706 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
 707 {
 708         /*
 709          * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
 710          * Not applicable for OMAP4.
 711          * Under certain rare conditions, RDR could be set again
 712          * when the bus is busy, then ignore the interrupt and
 713          * clear the interrupt.
 714          */
 715         if (stat & OMAP_I2C_STAT_RDR) {
 716                 /* Step 1: If RDR is set, clear it */
 717                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 718
 719                 /* Step 2: */
 720                 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
 721                                                 & OMAP_I2C_STAT_BB)) {
 722
 723                         /* Step 3: */
 724                         if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
 725                                                 & OMAP_I2C_STAT_RDR) {
 726                                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 727                                 dev_dbg(dev->dev, "RDR when bus is busy.\n");
 728                         }
 729
 730                 }
 731         }
 732 }
 733
 734 /* rev1 devices are apparently only on some 15xx */
 735 #ifdef CONFIG_ARCH_OMAP15XX
 736
 737 static irqreturn_t
 738 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 739 {
 740         struct omap_i2c_dev *dev = dev_id;
 741         u16 iv, w;
 742
 743         if (dev->idle)
 744                 return IRQ_NONE;
 745
 746         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 747         switch (iv) {
 748         case 0x00:      /* None */
 749                 break;
 750         case 0x01:      /* Arbitration lost */
 751                 dev_err(dev->dev, "Arbitration lost\n");
 752                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 753                 break;
 754         case 0x02:      /* No acknowledgement */
 755                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 756                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 757                 break;
 758         case 0x03:      /* Register access ready */
 759                 omap_i2c_complete_cmd(dev, 0);
 760                 break;
 761         case 0x04:      /* Receive data ready */
 762                 if (dev->buf_len) {
 763                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 764                         *dev->buf++ = w;
 765                         dev->buf_len--;
 766                         if (dev->buf_len) {
 767                                 *dev->buf++ = w >> 8;
 768                                 dev->buf_len--;
 769                         }
 770                 } else
 771                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 772                 break;
 773         case 0x05:      /* Transmit data ready */
 774                 if (dev->buf_len) {
 775                         w = *dev->buf++;
 776                         dev->buf_len--;
 777                         if (dev->buf_len) {
 778                                 w |= *dev->buf++ << 8;
 779                                 dev->buf_len--;
 780                         }
 781                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 782                 } else
 783                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 784                 break;
 785         default:
 786                 return IRQ_NONE;
 787         }
 788
 789         return IRQ_HANDLED;
 790 }
 791 #else
 792 #define omap_i2c_rev1_isr               NULL
 793 #endif
 794
 795 /*
 796  * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
 797  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
 798  * them from the memory to the I2C interface.
 799  */
 800 static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
 801 {
 802         unsigned long timeout = 10000;
 803
 804         while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
 805                 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 806                         omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
 807                                                         OMAP_I2C_STAT_XDR));
 808                         *err |= OMAP_I2C_STAT_XUDF;
 809                         return -ETIMEDOUT;
 810                 }
 811
 812                 cpu_relax();
 813                 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 814         }
 815
 816         if (!timeout) {
 817                 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
 818                 return 0;
 819         }
 820
 821         return 0;
 822 }
 823
 824 static irqreturn_t
 825 omap_i2c_isr(int this_irq, void *dev_id)
 826 {
 827         struct omap_i2c_dev *dev = dev_id;
 828         u16 bits;
 829         u16 stat, w;
 830         int err, count = 0;
 831
 832         if (dev->idle)
 833                 return IRQ_NONE;
 834
 835         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 836         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 837                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 838                 if (count++ == 100) {
 839                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 840                         break;
 841                 }
 842
 843                 err = 0;
 844 complete:
 845                 /*
 846                  * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
 847                  * acked after the data operation is complete.
 848                  * Ref: TRM SWPU114Q Figure 18-31
 849                  */
 850                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
 851                                 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 852                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 853
 854                 if (stat & OMAP_I2C_STAT_NACK) {
 855                         err |= OMAP_I2C_STAT_NACK;
 856                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 857                                            OMAP_I2C_CON_STP);
 858                 }
 859                 if (stat & OMAP_I2C_STAT_AL) {
 860                         dev_err(dev->dev, "Arbitration lost\n");
 861                         err |= OMAP_I2C_STAT_AL;
 862                 }
 863                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 864                                         OMAP_I2C_STAT_AL)) {
 865                         omap_i2c_ack_stat(dev, stat &
 866                                 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 867                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 868                         omap_i2c_complete_cmd(dev, err);
 869                         return IRQ_HANDLED;
 870                 }
 871                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 872                         u8 num_bytes = 1;
 873
 874                         if (dev->errata & I2C_OMAP_ERRATA_I207)
 875                                 i2c_omap_errata_i207(dev, stat);
 876
 877                         if (dev->fifo_size) {
 878                                 if (stat & OMAP_I2C_STAT_RRDY)
 879                                         num_bytes = dev->fifo_size;
 880                                 else    /* read RXSTAT on RDR interrupt */
 881                                         num_bytes = (omap_i2c_read_reg(dev,
 882                                                         OMAP_I2C_BUFSTAT_REG)
 883                                                         >> 8) & 0x3F;
 884                         }
 885                         while (num_bytes) {
 886                                 num_bytes--;
 887                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 888                                 if (dev->buf_len) {
 889                                         *dev->buf++ = w;
 890                                         dev->buf_len--;
 891                                         /*
 892                                          * Data reg in 2430, omap3 and
 893                                          * omap4 is 8 bit wide
 894                                          */
 895                                         if (cpu_class_is_omap1() ||
 896                                                         cpu_is_omap2420()) {
 897                                                 if (dev->buf_len) {
 898                                                         *dev->buf++ = w >> 8;
 899                                                         dev->buf_len--;
 900                                                 }
 901                                         }
 902                                 } else {
 903                                         if (stat & OMAP_I2C_STAT_RRDY)
 904                                                 dev_err(dev->dev,
 905                                                         "RRDY IRQ while no data"
 906                                                                 " requested\n");
 907                                         if (stat & OMAP_I2C_STAT_RDR)
 908                                                 dev_err(dev->dev,
 909                                                         "RDR IRQ while no data"
 910                                                                 " requested\n");
 911                                         break;
 912                                 }
 913                         }
 914                         omap_i2c_ack_stat(dev,
 915                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 916                         continue;
 917                 }
 918                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 919                         u8 num_bytes = 1;
 920                         if (dev->fifo_size) {
 921                                 if (stat & OMAP_I2C_STAT_XRDY)
 922                                         num_bytes = dev->fifo_size;
 923                                 else    /* read TXSTAT on XDR interrupt */
 924                                         num_bytes = omap_i2c_read_reg(dev,
 925                                                         OMAP_I2C_BUFSTAT_REG)
 926                                                         & 0x3F;
 927                         }
 928                         while (num_bytes) {
 929                                 num_bytes--;
 930                                 w = 0;
 931                                 if (dev->buf_len) {
 932                                         w = *dev->buf++;
 933                                         dev->buf_len--;
 934                                         /*
 935                                          * Data reg in 2430, omap3 and
 936                                          * omap4 is 8 bit wide
 937                                          */
 938                                         if (cpu_class_is_omap1() ||
 939                                                         cpu_is_omap2420()) {
 940                                                 if (dev->buf_len) {
 941                                                         w |= *dev->buf++ << 8;
 942                                                         dev->buf_len--;
 943                                                 }
 944                                         }
 945                                 } else {
 946                                         if (stat & OMAP_I2C_STAT_XRDY)
 947                                                 dev_err(dev->dev,
 948                                                         "XRDY IRQ while no "
 949                                                         "data to send\n");
 950                                         if (stat & OMAP_I2C_STAT_XDR)
 951                                                 dev_err(dev->dev,
 952                                                         "XDR IRQ while no "
 953                                                         "data to send\n");
 954                                         break;
 955                                 }
 956
 957                                 if ((dev->rev <= OMAP_I2C_REV_ON_3430) &&
 958                                     errata_omap3_1p153(dev, &stat, &err))
 959                                         goto complete;
 960
 961                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 962                         }
 963                         omap_i2c_ack_stat(dev,
 964                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 965                         continue;
 966                 }
 967                 if (stat & OMAP_I2C_STAT_ROVR) {
 968                         dev_err(dev->dev, "Receive overrun\n");
 969                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 970                 }
 971                 if (stat & OMAP_I2C_STAT_XUDF) {
 972                         dev_err(dev->dev, "Transmit underflow\n");
 973                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 974                 }
 975         }
 976
 977         return count ? IRQ_HANDLED : IRQ_NONE;
 978 }
 979
 980 static const struct i2c_algorithm omap_i2c_algo = {
 981         .master_xfer    = omap_i2c_xfer,
 982         .functionality  = omap_i2c_func,
 983 };
 984
 985 static int __devinit
 986 omap_i2c_probe(struct platform_device *pdev)
 987 {
 988         struct omap_i2c_dev     *dev;
 989         struct i2c_adapter      *adap;
 990         struct resource         *mem, *irq, *ioarea;
 991         struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 992         irq_handler_t isr;
 993         int r;
 994         u32 speed = 0;
 995
 996         /* NOTE: driver uses the static register mapping */
 997         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 998         if (!mem) {
 999                 dev_err(&pdev->dev, "no mem resource?\n");
1000                 return -ENODEV;
1001         }
1002         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1003         if (!irq) {
1004                 dev_err(&pdev->dev, "no irq resource?\n");
1005                 return -ENODEV;
1006         }
1007
1008         ioarea = request_mem_region(mem->start, resource_size(mem),
1009                         pdev->name);
1010         if (!ioarea) {
1011                 dev_err(&pdev->dev, "I2C region already claimed\n");
1012                 return -EBUSY;
1013         }
1014
1015         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
1016         if (!dev) {
1017                 r = -ENOMEM;
1018                 goto err_release_region;
1019         }
1020
1021         if (pdata != NULL) {
1022                 speed = pdata->clkrate;
1023                 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1024         } else {
1025                 speed = 100;    /* Default speed */
1026                 dev->set_mpu_wkup_lat = NULL;
1027         }
1028
1029         dev->speed = speed;
1030         dev->idle = 1;
1031         dev->dev = &pdev->dev;
1032         dev->irq = irq->start;
1033         dev->base = ioremap(mem->start, resource_size(mem));
1034         if (!dev->base) {
1035                 r = -ENOMEM;
1036                 goto err_free_mem;
1037         }
1038
1039         platform_set_drvdata(pdev, dev);
1040
1041         if (cpu_is_omap7xx())
1042                 dev->reg_shift = 1;
1043         else if (cpu_is_omap44xx())
1044                 dev->reg_shift = 0;
1045         else
1046                 dev->reg_shift = 2;
1047
1048         if ((r = omap_i2c_get_clocks(dev)) != 0)
1049                 goto err_iounmap;
1050
1051         if (cpu_is_omap44xx())
1052                 dev->regs = (u8 *) omap4_reg_map;
1053         else
1054                 dev->regs = (u8 *) reg_map;
1055
1056         omap_i2c_unidle(dev);
1057
1058         dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1059
1060         if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
1061                 u16 s;
1062
1063                 /* Set up the fifo size - Get total size */
1064                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1065                 dev->fifo_size = 0x8 << s;
1066
1067                 /*
1068                  * Set up notification threshold as half the total available
1069                  * size. This is to ensure that we can handle the status on int
1070                  * call back latencies.
1071                  */
1072                 if (dev->rev >= OMAP_I2C_REV_ON_4430) {
1073                         dev->fifo_size = 0;
1074                         dev->b_hw = 0; /* Disable hardware fixes */
1075                 } else {
1076                         dev->fifo_size = (dev->fifo_size / 2);
1077                         dev->b_hw = 1; /* Enable hardware fixes */
1078                 }
1079                 /* calculate wakeup latency constraint for MPU */
1080                 if (dev->set_mpu_wkup_lat != NULL)
1081                         dev->latency = (1000000 * dev->fifo_size) /
1082                                        (1000 * speed / 8);
1083         }
1084
1085         /* reset ASAP, clearing any IRQs */
1086         omap_i2c_init(dev);
1087
1088         isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
1089         r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1090
1091         if (r) {
1092                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1093                 goto err_unuse_clocks;
1094         }
1095
1096         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
1097                  pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1098
1099         omap_i2c_idle(dev);
1100
1101         adap = &dev->adapter;
1102         i2c_set_adapdata(adap, dev);
1103         adap->owner = THIS_MODULE;
1104         adap->class = I2C_CLASS_HWMON;
1105         strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1106         adap->algo = &omap_i2c_algo;
1107         adap->dev.parent = &pdev->dev;
1108
1109         /* i2c device drivers may be active on return from add_adapter() */
1110         adap->nr = pdev->id;
1111         r = i2c_add_numbered_adapter(adap);
1112         if (r) {
1113                 dev_err(dev->dev, "failure adding adapter\n");
1114                 goto err_free_irq;
1115         }
1116
1117         return 0;
1118
1119 err_free_irq:
1120         free_irq(dev->irq, dev);
1121 err_unuse_clocks:
1122         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1123         omap_i2c_idle(dev);
1124         omap_i2c_put_clocks(dev);
1125 err_iounmap:
1126         iounmap(dev->base);
1127 err_free_mem:
1128         platform_set_drvdata(pdev, NULL);
1129         kfree(dev);
1130 err_release_region:
1131         release_mem_region(mem->start, resource_size(mem));
1132
1133         return r;
1134 }
1135
1136 static int
1137 omap_i2c_remove(struct platform_device *pdev)
1138 {
1139         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
1140         struct resource         *mem;
1141
1142         platform_set_drvdata(pdev, NULL);
1143
1144         free_irq(dev->irq, dev);
1145         i2c_del_adapter(&dev->adapter);
1146         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1147         omap_i2c_put_clocks(dev);
1148         iounmap(dev->base);
1149         kfree(dev);
1150         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1151         release_mem_region(mem->start, resource_size(mem));
1152         return 0;
1153 }
1154
1155 static struct platform_driver omap_i2c_driver = {
1156         .probe          = omap_i2c_probe,
1157         .remove         = omap_i2c_remove,
1158         .driver         = {
1159                 .name   = "i2c_omap",
1160                 .owner  = THIS_MODULE,
1161         },
1162 };
1163
1164 /* I2C may be needed to bring up other drivers */
1165 static int __init
1166 omap_i2c_init_driver(void)
1167 {
1168         return platform_driver_register(&omap_i2c_driver);
1169 }
1170 subsys_initcall(omap_i2c_init_driver);
1171
1172 static void __exit omap_i2c_exit_driver(void)
1173 {
1174         platform_driver_unregister(&omap_i2c_driver);
1175 }
1176 module_exit(omap_i2c_exit_driver);
1177
1178 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1179 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1180 MODULE_LICENSE("GPL");
1181 MODULE_ALIAS("platform:i2c_omap");