SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/i2c/busses/i2c-octeon.c

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
   4  *
   5  * Portions Copyright (C) 2010 Cavium Networks, Inc.
   6  *
   7  * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/sched.h>
  17 #include <linux/init.h>
  18
  19 #include <linux/io.h>
  20 #include <linux/i2c.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/delay.h>
  23 #include <linux/platform_device.h>
  24
  25 #include <asm/octeon/octeon.h>
  26
  27 #define DRV_NAME "i2c-octeon"
  28
  29 /* The previous out-of-tree version was implicitly version 1.0. */
  30 #define DRV_VERSION     "2.0"
  31
  32 /* register offsets */
  33 #define SW_TWSI  0x00
  34 #define TWSI_INT 0x10
  35
  36 /* Controller command patterns */
  37 #define SW_TWSI_V               0x8000000000000000ull
  38 #define SW_TWSI_EOP_TWSI_DATA   0x0C00000100000000ull
  39 #define SW_TWSI_EOP_TWSI_CTL    0x0C00000200000000ull
  40 #define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull
  41 #define SW_TWSI_EOP_TWSI_STAT   0x0C00000300000000ull
  42 #define SW_TWSI_EOP_TWSI_RST    0x0C00000700000000ull
  43 #define SW_TWSI_OP_TWSI_CLK     0x0800000000000000ull
  44 #define SW_TWSI_R               0x0100000000000000ull
  45
  46 /* Controller command and status bits */
  47 #define TWSI_CTL_CE   0x80
  48 #define TWSI_CTL_ENAB 0x40
  49 #define TWSI_CTL_STA  0x20
  50 #define TWSI_CTL_STP  0x10
  51 #define TWSI_CTL_IFLG 0x08
  52 #define TWSI_CTL_AAK  0x04
  53
  54 /* Some status values */
  55 #define STAT_START      0x08
  56 #define STAT_RSTART     0x10
  57 #define STAT_TXADDR_ACK 0x18
  58 #define STAT_TXDATA_ACK 0x28
  59 #define STAT_RXADDR_ACK 0x40
  60 #define STAT_RXDATA_ACK 0x50
  61 #define STAT_IDLE       0xF8
  62
  63 struct octeon_i2c {
  64         wait_queue_head_t queue;
  65         struct i2c_adapter adap;
  66         int irq;
  67         int twsi_freq;
  68         int sys_freq;
  69         resource_size_t twsi_phys;
  70         void __iomem *twsi_base;
  71         resource_size_t regsize;
  72         struct device *dev;
  73 };
  74
  75 /**
  76  * octeon_i2c_write_sw - write an I2C core register.
  77  * @i2c: The struct octeon_i2c.
  78  * @eop_reg: Register selector.
  79  * @data: Value to be written.
  80  *
  81  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
  82  */
  83 static void octeon_i2c_write_sw(struct octeon_i2c *i2c,
  84                                 u64 eop_reg,
  85                                 u8 data)
  86 {
  87         u64 tmp;
  88
  89         __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
  90         do {
  91                 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
  92         } while ((tmp & SW_TWSI_V) != 0);
  93 }
  94
  95 /**
  96  * octeon_i2c_read_sw - write an I2C core register.
  97  * @i2c: The struct octeon_i2c.
  98  * @eop_reg: Register selector.
  99  *
 100  * Returns the data.
 101  *
 102  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 103  */
 104 static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
 105 {
 106         u64 tmp;
 107
 108         __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
 109         do {
 110                 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
 111         } while ((tmp & SW_TWSI_V) != 0);
 112
 113         return tmp & 0xFF;
 114 }
 115
 116 /**
 117  * octeon_i2c_write_int - write the TWSI_INT register
 118  * @i2c: The struct octeon_i2c.
 119  * @data: Value to be written.
 120  */
 121 static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
 122 {
 123         u64 tmp;
 124
 125         __raw_writeq(data, i2c->twsi_base + TWSI_INT);
 126         tmp = __raw_readq(i2c->twsi_base + TWSI_INT);
 127 }
 128
 129 /**
 130  * octeon_i2c_int_enable - enable the TS interrupt.
 131  * @i2c: The struct octeon_i2c.
 132  *
 133  * The interrupt will be asserted when there is non-STAT_IDLE state in
 134  * the SW_TWSI_EOP_TWSI_STAT register.
 135  */
 136 static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
 137 {
 138         octeon_i2c_write_int(i2c, 0x40);
 139 }
 140
 141 /**
 142  * octeon_i2c_int_disable - disable the TS interrupt.
 143  * @i2c: The struct octeon_i2c.
 144  */
 145 static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
 146 {
 147         octeon_i2c_write_int(i2c, 0);
 148 }
 149
 150 /**
 151  * octeon_i2c_unblock - unblock the bus.
 152  * @i2c: The struct octeon_i2c.
 153  *
 154  * If there was a reset while a device was driving 0 to bus,
 155  * bus is blocked. We toggle it free manually by some clock
 156  * cycles and send a stop.
 157  */
 158 static void octeon_i2c_unblock(struct octeon_i2c *i2c)
 159 {
 160         int i;
 161
 162         dev_dbg(i2c->dev, "%s\n", __func__);
 163         for (i = 0; i < 9; i++) {
 164                 octeon_i2c_write_int(i2c, 0x0);
 165                 udelay(5);
 166                 octeon_i2c_write_int(i2c, 0x200);
 167                 udelay(5);
 168         }
 169         octeon_i2c_write_int(i2c, 0x300);
 170         udelay(5);
 171         octeon_i2c_write_int(i2c, 0x100);
 172         udelay(5);
 173         octeon_i2c_write_int(i2c, 0x0);
 174 }
 175
 176 /**
 177  * octeon_i2c_isr - the interrupt service routine.
 178  * @int: The irq, unused.
 179  * @dev_id: Our struct octeon_i2c.
 180  */
 181 static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
 182 {
 183         struct octeon_i2c *i2c = dev_id;
 184
 185         octeon_i2c_int_disable(i2c);
 186         wake_up_interruptible(&i2c->queue);
 187
 188         return IRQ_HANDLED;
 189 }
 190
 191
 192 static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
 193 {
 194         return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
 195 }
 196
 197 /**
 198  * octeon_i2c_wait - wait for the IFLG to be set.
 199  * @i2c: The struct octeon_i2c.
 200  *
 201  * Returns 0 on success, otherwise a negative errno.
 202  */
 203 static int octeon_i2c_wait(struct octeon_i2c *i2c)
 204 {
 205         int result;
 206
 207         octeon_i2c_int_enable(i2c);
 208
 209         result = wait_event_interruptible_timeout(i2c->queue,
 210                                                   octeon_i2c_test_iflg(i2c),
 211                                                   i2c->adap.timeout);
 212
 213         octeon_i2c_int_disable(i2c);
 214
 215         if (result < 0) {
 216                 dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__);
 217                 return result;
 218         } else if (result == 0) {
 219                 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
 220                 result = -ETIMEDOUT;
 221         }
 222
 223         return 0;
 224 }
 225
 226 /**
 227  * octeon_i2c_start - send START to the bus.
 228  * @i2c: The struct octeon_i2c.
 229  *
 230  * Returns 0 on success, otherwise a negative errno.
 231  */
 232 static int octeon_i2c_start(struct octeon_i2c *i2c)
 233 {
 234         u8 data;
 235         int result;
 236
 237         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 238                                 TWSI_CTL_ENAB | TWSI_CTL_STA);
 239
 240         result = octeon_i2c_wait(i2c);
 241         if (result) {
 242                 if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
 243                         /*
 244                          * Controller refused to send start flag May
 245                          * be a client is holding SDA low - let's try
 246                          * to free it.
 247                          */
 248                         octeon_i2c_unblock(i2c);
 249                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 250                                             TWSI_CTL_ENAB | TWSI_CTL_STA);
 251
 252                         result = octeon_i2c_wait(i2c);
 253                 }
 254                 if (result)
 255                         return result;
 256         }
 257
 258         data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 259         if ((data != STAT_START) && (data != STAT_RSTART)) {
 260                 dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
 261                 return -EIO;
 262         }
 263
 264         return 0;
 265 }
 266
 267 /**
 268  * octeon_i2c_stop - send STOP to the bus.
 269  * @i2c: The struct octeon_i2c.
 270  *
 271  * Returns 0 on success, otherwise a negative errno.
 272  */
 273 static int octeon_i2c_stop(struct octeon_i2c *i2c)
 274 {
 275         u8 data;
 276
 277         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 278                             TWSI_CTL_ENAB | TWSI_CTL_STP);
 279
 280         data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 281
 282         if (data != STAT_IDLE) {
 283                 dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data);
 284                 return -EIO;
 285         }
 286         return 0;
 287 }
 288
 289 /**
 290  * octeon_i2c_write - send data to the bus.
 291  * @i2c: The struct octeon_i2c.
 292  * @target: Target address.
 293  * @data: Pointer to the data to be sent.
 294  * @length: Length of the data.
 295  *
 296  * The address is sent over the bus, then the data.
 297  *
 298  * Returns 0 on success, otherwise a negative errno.
 299  */
 300 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
 301                             const u8 *data, int length)
 302 {
 303         int i, result;
 304         u8 tmp;
 305
 306         result = octeon_i2c_start(i2c);
 307         if (result)
 308                 return result;
 309
 310         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
 311         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 312
 313         result = octeon_i2c_wait(i2c);
 314         if (result)
 315                 return result;
 316
 317         for (i = 0; i < length; i++) {
 318                 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 319                 if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
 320                         dev_err(i2c->dev,
 321                                 "%s: bad status before write (0x%x)\n",
 322                                 __func__, tmp);
 323                         return -EIO;
 324                 }
 325
 326                 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
 327                 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 328
 329                 result = octeon_i2c_wait(i2c);
 330                 if (result)
 331                         return result;
 332         }
 333
 334         return 0;
 335 }
 336
 337 /**
 338  * octeon_i2c_read - receive data from the bus.
 339  * @i2c: The struct octeon_i2c.
 340  * @target: Target address.
 341  * @data: Pointer to the location to store the datae .
 342  * @length: Length of the data.
 343  *
 344  * The address is sent over the bus, then the data is read.
 345  *
 346  * Returns 0 on success, otherwise a negative errno.
 347  */
 348 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
 349                            u8 *data, int length)
 350 {
 351         int i, result;
 352         u8 tmp;
 353
 354         if (length < 1)
 355                 return -EINVAL;
 356
 357         result = octeon_i2c_start(i2c);
 358         if (result)
 359                 return result;
 360
 361         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target<<1) | 1);
 362         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 363
 364         result = octeon_i2c_wait(i2c);
 365         if (result)
 366                 return result;
 367
 368         for (i = 0; i < length; i++) {
 369                 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 370                 if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
 371                         dev_err(i2c->dev,
 372                                 "%s: bad status before read (0x%x)\n",
 373                                 __func__, tmp);
 374                         return -EIO;
 375                 }
 376
 377                 if (i+1 < length)
 378                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 379                                                 TWSI_CTL_ENAB | TWSI_CTL_AAK);
 380                 else
 381                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 382                                                 TWSI_CTL_ENAB);
 383
 384                 result = octeon_i2c_wait(i2c);
 385                 if (result)
 386                         return result;
 387
 388                 data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
 389         }
 390         return 0;
 391 }
 392
 393 /**
 394  * octeon_i2c_xfer - The driver's master_xfer function.
 395  * @adap: Pointer to the i2c_adapter structure.
 396  * @msgs: Pointer to the messages to be processed.
 397  * @num: Length of the MSGS array.
 398  *
 399  * Returns the number of messages processed, or a negative errno on
 400  * failure.
 401  */
 402 static int octeon_i2c_xfer(struct i2c_adapter *adap,
 403                            struct i2c_msg *msgs,
 404                            int num)
 405 {
 406         struct i2c_msg *pmsg;
 407         int i;
 408         int ret = 0;
 409         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 410
 411         for (i = 0; ret == 0 && i < num; i++) {
 412                 pmsg = &msgs[i];
 413                 dev_dbg(i2c->dev,
 414                         "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
 415                          pmsg->flags & I2C_M_RD ? "read" : "write",
 416                          pmsg->len, pmsg->addr, i + 1, num);
 417                 if (pmsg->flags & I2C_M_RD)
 418                         ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
 419                                                 pmsg->len);
 420                 else
 421                         ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
 422                                                 pmsg->len);
 423         }
 424         octeon_i2c_stop(i2c);
 425
 426         return (ret != 0) ? ret : num;
 427 }
 428
 429 static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
 430 {
 431         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 432 }
 433
 434 static const struct i2c_algorithm octeon_i2c_algo = {
 435         .master_xfer = octeon_i2c_xfer,
 436         .functionality = octeon_i2c_functionality,
 437 };
 438
 439 static struct i2c_adapter octeon_i2c_ops = {
 440         .owner = THIS_MODULE,
 441         .name = "OCTEON adapter",
 442         .algo = &octeon_i2c_algo,
 443         .timeout = 2,
 444 };
 445
 446 /**
 447  * octeon_i2c_setclock - Calculate and set clock divisors.
 448  */
 449 static int __init octeon_i2c_setclock(struct octeon_i2c *i2c)
 450 {
 451         int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
 452         int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
 453
 454         for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
 455                 /*
 456                  * An mdiv value of less than 2 seems to not work well
 457                  * with ds1337 RTCs, so we constrain it to larger
 458                  * values.
 459                  */
 460                 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
 461                         /*
 462                          * For given ndiv and mdiv values check the
 463                          * two closest thp values.
 464                          */
 465                         tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
 466                         tclk *= (1 << ndiv_idx);
 467                         thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
 468                         for (inc = 0; inc <= 1; inc++) {
 469                                 thp_idx = thp_base + inc;
 470                                 if (thp_idx < 5 || thp_idx > 0xff)
 471                                         continue;
 472
 473                                 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
 474                                 foscl = foscl / (1 << ndiv_idx);
 475                                 foscl = foscl / (mdiv_idx + 1) / 10;
 476                                 diff = abs(foscl - i2c->twsi_freq);
 477                                 if (diff < delta_hz) {
 478                                         delta_hz = diff;
 479                                         thp = thp_idx;
 480                                         mdiv = mdiv_idx;
 481                                         ndiv = ndiv_idx;
 482                                 }
 483                         }
 484                 }
 485         }
 486         octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
 487         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
 488
 489         return 0;
 490 }
 491
 492 static int __init octeon_i2c_initlowlevel(struct octeon_i2c *i2c)
 493 {
 494         u8 status;
 495         int tries;
 496
 497         /* disable high level controller, enable bus access */
 498         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 499
 500         /* reset controller */
 501         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
 502
 503         for (tries = 10; tries; tries--) {
 504                 udelay(1);
 505                 status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 506                 if (status == STAT_IDLE)
 507                         return 0;
 508         }
 509         dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
 510         return -EIO;
 511 }
 512
 513 static int __devinit octeon_i2c_probe(struct platform_device *pdev)
 514 {
 515         int irq, result = 0;
 516         struct octeon_i2c *i2c;
 517         struct octeon_i2c_data *i2c_data;
 518         struct resource *res_mem;
 519
 520         /* All adaptors have an irq.  */
 521         irq = platform_get_irq(pdev, 0);
 522         if (irq < 0)
 523                 return irq;
 524
 525         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
 526         if (!i2c) {
 527                 dev_err(&pdev->dev, "kzalloc failed\n");
 528                 result = -ENOMEM;
 529                 goto out;
 530         }
 531         i2c->dev = &pdev->dev;
 532         i2c_data = pdev->dev.platform_data;
 533
 534         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 535
 536         if (res_mem == NULL) {
 537                 dev_err(i2c->dev, "found no memory resource\n");
 538                 result = -ENXIO;
 539                 goto fail_region;
 540         }
 541
 542         if (i2c_data == NULL) {
 543                 dev_err(i2c->dev, "no I2C frequency data\n");
 544                 result = -ENXIO;
 545                 goto fail_region;
 546         }
 547
 548         i2c->twsi_phys = res_mem->start;
 549         i2c->regsize = resource_size(res_mem);
 550         i2c->twsi_freq = i2c_data->i2c_freq;
 551         i2c->sys_freq = i2c_data->sys_freq;
 552
 553         if (!request_mem_region(i2c->twsi_phys, i2c->regsize, res_mem->name)) {
 554                 dev_err(i2c->dev, "request_mem_region failed\n");
 555                 goto fail_region;
 556         }
 557         i2c->twsi_base = ioremap(i2c->twsi_phys, i2c->regsize);
 558
 559         init_waitqueue_head(&i2c->queue);
 560
 561         i2c->irq = irq;
 562
 563         result = request_irq(i2c->irq, octeon_i2c_isr, 0, DRV_NAME, i2c);
 564         if (result < 0) {
 565                 dev_err(i2c->dev, "failed to attach interrupt\n");
 566                 goto fail_irq;
 567         }
 568
 569         result = octeon_i2c_initlowlevel(i2c);
 570         if (result) {
 571                 dev_err(i2c->dev, "init low level failed\n");
 572                 goto  fail_add;
 573         }
 574
 575         result = octeon_i2c_setclock(i2c);
 576         if (result) {
 577                 dev_err(i2c->dev, "clock init failed\n");
 578                 goto  fail_add;
 579         }
 580
 581         i2c->adap = octeon_i2c_ops;
 582         i2c->adap.dev.parent = &pdev->dev;
 583         i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0;
 584         i2c_set_adapdata(&i2c->adap, i2c);
 585         platform_set_drvdata(pdev, i2c);
 586
 587         result = i2c_add_numbered_adapter(&i2c->adap);
 588         if (result < 0) {
 589                 dev_err(i2c->dev, "failed to add adapter\n");
 590                 goto fail_add;
 591         }
 592
 593         dev_info(i2c->dev, "version %s\n", DRV_VERSION);
 594
 595         return result;
 596
 597 fail_add:
 598         platform_set_drvdata(pdev, NULL);
 599         free_irq(i2c->irq, i2c);
 600 fail_irq:
 601         iounmap(i2c->twsi_base);
 602         release_mem_region(i2c->twsi_phys, i2c->regsize);
 603 fail_region:
 604         kfree(i2c);
 605 out:
 606         return result;
 607 };
 608
 609 static int __devexit octeon_i2c_remove(struct platform_device *pdev)
 610 {
 611         struct octeon_i2c *i2c = platform_get_drvdata(pdev);
 612
 613         i2c_del_adapter(&i2c->adap);
 614         platform_set_drvdata(pdev, NULL);
 615         free_irq(i2c->irq, i2c);
 616         iounmap(i2c->twsi_base);
 617         release_mem_region(i2c->twsi_phys, i2c->regsize);
 618         kfree(i2c);
 619         return 0;
 620 };
 621
 622 static struct platform_driver octeon_i2c_driver = {
 623         .probe          = octeon_i2c_probe,
 624         .remove         = __devexit_p(octeon_i2c_remove),
 625         .driver         = {
 626                 .owner  = THIS_MODULE,
 627                 .name   = DRV_NAME,
 628         },
 629 };
 630
 631 static int __init octeon_i2c_init(void)
 632 {
 633         int rv;
 634
 635         rv = platform_driver_register(&octeon_i2c_driver);
 636         return rv;
 637 }
 638
 639 static void __exit octeon_i2c_exit(void)
 640 {
 641         platform_driver_unregister(&octeon_i2c_driver);
 642 }
 643
 644 MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
 645 MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
 646 MODULE_LICENSE("GPL");
 647 MODULE_VERSION(DRV_VERSION);
 648 MODULE_ALIAS("platform:" DRV_NAME);
 649
 650 module_init(octeon_i2c_init);
 651 module_exit(octeon_i2c_exit);