SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/i2c/busses/i2c-bfin-twi.c

   1 /*
   2  * Blackfin On-Chip Two Wire Interface Driver
   3  *
   4  * Copyright 2005-2007 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/i2c.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/timer.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <asm/blackfin.h>
  25 #include <asm/portmux.h>
  26 #include <asm/irq.h>
  27
  28 /* SMBus mode*/
  29 #define TWI_I2C_MODE_STANDARD           1
  30 #define TWI_I2C_MODE_STANDARDSUB        2
  31 #define TWI_I2C_MODE_COMBINED           3
  32 #define TWI_I2C_MODE_REPEAT             4
  33
  34 struct bfin_twi_iface {
  35         int                     irq;
  36         spinlock_t              lock;
  37         char                    read_write;
  38         u8                      command;
  39         u8                      *transPtr;
  40         int                     readNum;
  41         int                     writeNum;
  42         int                     cur_mode;
  43         int                     manual_stop;
  44         int                     result;
  45         struct i2c_adapter      adap;
  46         struct completion       complete;
  47         struct i2c_msg          *pmsg;
  48         int                     msg_num;
  49         int                     cur_msg;
  50         u16                     saved_clkdiv;
  51         u16                     saved_control;
  52         void __iomem            *regs_base;
  53 };
  54
  55
  56 #define DEFINE_TWI_REG(reg, off) \
  57 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
  58         { return bfin_read16(iface->regs_base + (off)); } \
  59 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
  60         { bfin_write16(iface->regs_base + (off), v); }
  61
  62 DEFINE_TWI_REG(CLKDIV, 0x00)
  63 DEFINE_TWI_REG(CONTROL, 0x04)
  64 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
  65 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
  66 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
  67 DEFINE_TWI_REG(MASTER_CTL, 0x14)
  68 DEFINE_TWI_REG(MASTER_STAT, 0x18)
  69 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
  70 DEFINE_TWI_REG(INT_STAT, 0x20)
  71 DEFINE_TWI_REG(INT_MASK, 0x24)
  72 DEFINE_TWI_REG(FIFO_CTL, 0x28)
  73 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
  74 DEFINE_TWI_REG(XMT_DATA8, 0x80)
  75 DEFINE_TWI_REG(XMT_DATA16, 0x84)
  76 DEFINE_TWI_REG(RCV_DATA8, 0x88)
  77 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
  78
  79 static const u16 pin_req[2][3] = {
  80         {P_TWI0_SCL, P_TWI0_SDA, 0},
  81         {P_TWI1_SCL, P_TWI1_SDA, 0},
  82 };
  83
  84 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
  85 {
  86         unsigned short twi_int_status = read_INT_STAT(iface);
  87         unsigned short mast_stat = read_MASTER_STAT(iface);
  88
  89         if (twi_int_status & XMTSERV) {
  90                 /* Transmit next data */
  91                 if (iface->writeNum > 0) {
  92                         write_XMT_DATA8(iface, *(iface->transPtr++));
  93                         iface->writeNum--;
  94                 }
  95                 /* start receive immediately after complete sending in
  96                  * combine mode.
  97                  */
  98                 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
  99                         write_MASTER_CTL(iface,
 100                                 read_MASTER_CTL(iface) | MDIR | RSTART);
 101                 else if (iface->manual_stop)
 102                         write_MASTER_CTL(iface,
 103                                 read_MASTER_CTL(iface) | STOP);
 104                 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 105                          iface->cur_msg + 1 < iface->msg_num) {
 106                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 107                                 write_MASTER_CTL(iface,
 108                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 109                         else
 110                                 write_MASTER_CTL(iface,
 111                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 112                 }
 113                 SSYNC();
 114                 /* Clear status */
 115                 write_INT_STAT(iface, XMTSERV);
 116                 SSYNC();
 117         }
 118         if (twi_int_status & RCVSERV) {
 119                 if (iface->readNum > 0) {
 120                         /* Receive next data */
 121                         *(iface->transPtr) = read_RCV_DATA8(iface);
 122                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 123                                 /* Change combine mode into sub mode after
 124                                  * read first data.
 125                                  */
 126                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 127                                 /* Get read number from first byte in block
 128                                  * combine mode.
 129                                  */
 130                                 if (iface->readNum == 1 && iface->manual_stop)
 131                                         iface->readNum = *iface->transPtr + 1;
 132                         }
 133                         iface->transPtr++;
 134                         iface->readNum--;
 135                 } else if (iface->manual_stop) {
 136                         write_MASTER_CTL(iface,
 137                                 read_MASTER_CTL(iface) | STOP);
 138                         SSYNC();
 139                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 140                            iface->cur_msg + 1 < iface->msg_num) {
 141                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 142                                 write_MASTER_CTL(iface,
 143                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 144                         else
 145                                 write_MASTER_CTL(iface,
 146                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 147                         SSYNC();
 148                 }
 149                 /* Clear interrupt source */
 150                 write_INT_STAT(iface, RCVSERV);
 151                 SSYNC();
 152         }
 153         if (twi_int_status & MERR) {
 154                 write_INT_STAT(iface, MERR);
 155                 write_INT_MASK(iface, 0);
 156                 write_MASTER_STAT(iface, 0x3e);
 157                 write_MASTER_CTL(iface, 0);
 158                 SSYNC();
 159                 iface->result = -EIO;
 160                 /* if both err and complete int stats are set, return proper
 161                  * results.
 162                  */
 163                 if (twi_int_status & MCOMP) {
 164                         write_INT_STAT(iface, MCOMP);
 165                         write_INT_MASK(iface, 0);
 166                         write_MASTER_CTL(iface, 0);
 167                         SSYNC();
 168                         /* If it is a quick transfer, only address without data,
 169                          * not an err, return 1.
 170                          * If address is acknowledged return 1.
 171                          */
 172                         if ((iface->writeNum == 0 && (mast_stat & BUFRDERR))
 173                                 || !(mast_stat & ANAK))
 174                                 iface->result = 1;
 175                 }
 176                 complete(&iface->complete);
 177                 return;
 178         }
 179         if (twi_int_status & MCOMP) {
 180                 write_INT_STAT(iface, MCOMP);
 181                 SSYNC();
 182                 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 183                         if (iface->readNum == 0) {
 184                                 /* set the read number to 1 and ask for manual
 185                                  * stop in block combine mode
 186                                  */
 187                                 iface->readNum = 1;
 188                                 iface->manual_stop = 1;
 189                                 write_MASTER_CTL(iface,
 190                                         read_MASTER_CTL(iface) | (0xff << 6));
 191                         } else {
 192                                 /* set the readd number in other
 193                                  * combine mode.
 194                                  */
 195                                 write_MASTER_CTL(iface,
 196                                         (read_MASTER_CTL(iface) &
 197                                         (~(0xff << 6))) |
 198                                         (iface->readNum << 6));
 199                         }
 200                         /* remove restart bit and enable master receive */
 201                         write_MASTER_CTL(iface,
 202                                 read_MASTER_CTL(iface) & ~RSTART);
 203                         SSYNC();
 204                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 205                                 iface->cur_msg+1 < iface->msg_num) {
 206                         iface->cur_msg++;
 207                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
 208                         iface->writeNum = iface->readNum =
 209                                 iface->pmsg[iface->cur_msg].len;
 210                         /* Set Transmit device address */
 211                         write_MASTER_ADDR(iface,
 212                                 iface->pmsg[iface->cur_msg].addr);
 213                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
 214                                 iface->read_write = I2C_SMBUS_READ;
 215                         else {
 216                                 iface->read_write = I2C_SMBUS_WRITE;
 217                                 /* Transmit first data */
 218                                 if (iface->writeNum > 0) {
 219                                         write_XMT_DATA8(iface,
 220                                                 *(iface->transPtr++));
 221                                         iface->writeNum--;
 222                                         SSYNC();
 223                                 }
 224                         }
 225
 226                         if (iface->pmsg[iface->cur_msg].len <= 255)
 227                                         write_MASTER_CTL(iface,
 228                                         (read_MASTER_CTL(iface) &
 229                                         (~(0xff << 6))) |
 230                                 (iface->pmsg[iface->cur_msg].len << 6));
 231                         else {
 232                                 write_MASTER_CTL(iface,
 233                                         (read_MASTER_CTL(iface) |
 234                                         (0xff << 6)));
 235                                 iface->manual_stop = 1;
 236                         }
 237                         /* remove restart bit and enable master receive */
 238                         write_MASTER_CTL(iface,
 239                                 read_MASTER_CTL(iface) & ~RSTART);
 240                         SSYNC();
 241                 } else {
 242                         iface->result = 1;
 243                         write_INT_MASK(iface, 0);
 244                         write_MASTER_CTL(iface, 0);
 245                         SSYNC();
 246                 }
 247         }
 248         complete(&iface->complete);
 249 }
 250
 251 /* Interrupt handler */
 252 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 253 {
 254         struct bfin_twi_iface *iface = dev_id;
 255         unsigned long flags;
 256
 257         spin_lock_irqsave(&iface->lock, flags);
 258         bfin_twi_handle_interrupt(iface);
 259         spin_unlock_irqrestore(&iface->lock, flags);
 260         return IRQ_HANDLED;
 261 }
 262
 263 /*
 264  * One i2c master transfer
 265  */
 266 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 267                                 struct i2c_msg *msgs, int num)
 268 {
 269         struct bfin_twi_iface *iface = adap->algo_data;
 270         struct i2c_msg *pmsg;
 271         int rc = 0;
 272
 273         if (!(read_CONTROL(iface) & TWI_ENA))
 274                 return -ENXIO;
 275
 276         while (read_MASTER_STAT(iface) & BUSBUSY)
 277                 yield();
 278
 279         iface->pmsg = msgs;
 280         iface->msg_num = num;
 281         iface->cur_msg = 0;
 282
 283         pmsg = &msgs[0];
 284         if (pmsg->flags & I2C_M_TEN) {
 285                 dev_err(&adap->dev, "10 bits addr not supported!\n");
 286                 return -EINVAL;
 287         }
 288
 289         iface->cur_mode = TWI_I2C_MODE_REPEAT;
 290         iface->manual_stop = 0;
 291         iface->transPtr = pmsg->buf;
 292         iface->writeNum = iface->readNum = pmsg->len;
 293         iface->result = 0;
 294         init_completion(&(iface->complete));
 295         /* Set Transmit device address */
 296         write_MASTER_ADDR(iface, pmsg->addr);
 297
 298         /* FIFO Initiation. Data in FIFO should be
 299          *  discarded before start a new operation.
 300          */
 301         write_FIFO_CTL(iface, 0x3);
 302         SSYNC();
 303         write_FIFO_CTL(iface, 0);
 304         SSYNC();
 305
 306         if (pmsg->flags & I2C_M_RD)
 307                 iface->read_write = I2C_SMBUS_READ;
 308         else {
 309                 iface->read_write = I2C_SMBUS_WRITE;
 310                 /* Transmit first data */
 311                 if (iface->writeNum > 0) {
 312                         write_XMT_DATA8(iface, *(iface->transPtr++));
 313                         iface->writeNum--;
 314                         SSYNC();
 315                 }
 316         }
 317
 318         /* clear int stat */
 319         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 320
 321         /* Interrupt mask . Enable XMT, RCV interrupt */
 322         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 323         SSYNC();
 324
 325         if (pmsg->len <= 255)
 326                 write_MASTER_CTL(iface, pmsg->len << 6);
 327         else {
 328                 write_MASTER_CTL(iface, 0xff << 6);
 329                 iface->manual_stop = 1;
 330         }
 331
 332         /* Master enable */
 333         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 334                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 335                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 336         SSYNC();
 337
 338         while (!iface->result) {
 339                 if (!wait_for_completion_timeout(&iface->complete,
 340                         adap->timeout)) {
 341                         iface->result = -1;
 342                         dev_err(&adap->dev, "master transfer timeout\n");
 343                 }
 344         }
 345
 346         if (iface->result == 1)
 347                 rc = iface->cur_msg + 1;
 348         else
 349                 rc = iface->result;
 350
 351         return rc;
 352 }
 353
 354 /*
 355  * Generic i2c master transfer entrypoint
 356  */
 357 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
 358                                 struct i2c_msg *msgs, int num)
 359 {
 360         int i, ret = 0;
 361
 362         for (i = 0; i < adap->retries; i++) {
 363                 ret = bfin_twi_do_master_xfer(adap, msgs, num);
 364                 if (ret > 0)
 365                         break;
 366         }
 367
 368         return ret;
 369 }
 370
 371 /*
 372  * One I2C SMBus transfer
 373  */
 374 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 375                         unsigned short flags, char read_write,
 376                         u8 command, int size, union i2c_smbus_data *data)
 377 {
 378         struct bfin_twi_iface *iface = adap->algo_data;
 379         int rc = 0;
 380
 381         if (!(read_CONTROL(iface) & TWI_ENA))
 382                 return -ENXIO;
 383
 384         while (read_MASTER_STAT(iface) & BUSBUSY)
 385                 yield();
 386
 387         iface->writeNum = 0;
 388         iface->readNum = 0;
 389
 390         /* Prepare datas & select mode */
 391         switch (size) {
 392         case I2C_SMBUS_QUICK:
 393                 iface->transPtr = NULL;
 394                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 395                 break;
 396         case I2C_SMBUS_BYTE:
 397                 if (data == NULL)
 398                         iface->transPtr = NULL;
 399                 else {
 400                         if (read_write == I2C_SMBUS_READ)
 401                                 iface->readNum = 1;
 402                         else
 403                                 iface->writeNum = 1;
 404                         iface->transPtr = &data->byte;
 405                 }
 406                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 407                 break;
 408         case I2C_SMBUS_BYTE_DATA:
 409                 if (read_write == I2C_SMBUS_READ) {
 410                         iface->readNum = 1;
 411                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 412                 } else {
 413                         iface->writeNum = 1;
 414                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 415                 }
 416                 iface->transPtr = &data->byte;
 417                 break;
 418         case I2C_SMBUS_WORD_DATA:
 419                 if (read_write == I2C_SMBUS_READ) {
 420                         iface->readNum = 2;
 421                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 422                 } else {
 423                         iface->writeNum = 2;
 424                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 425                 }
 426                 iface->transPtr = (u8 *)&data->word;
 427                 break;
 428         case I2C_SMBUS_PROC_CALL:
 429                 iface->writeNum = 2;
 430                 iface->readNum = 2;
 431                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
 432                 iface->transPtr = (u8 *)&data->word;
 433                 break;
 434         case I2C_SMBUS_BLOCK_DATA:
 435                 if (read_write == I2C_SMBUS_READ) {
 436                         iface->readNum = 0;
 437                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 438                 } else {
 439                         iface->writeNum = data->block[0] + 1;
 440                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 441                 }
 442                 iface->transPtr = data->block;
 443                 break;
 444         case I2C_SMBUS_I2C_BLOCK_DATA:
 445                 if (read_write == I2C_SMBUS_READ) {
 446                         iface->readNum = data->block[0];
 447                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 448                 } else {
 449                         iface->writeNum = data->block[0];
 450                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 451                 }
 452                 iface->transPtr = (u8 *)&data->block[1];
 453                 break;
 454         default:
 455                 return -1;
 456         }
 457
 458         iface->result = 0;
 459         iface->manual_stop = 0;
 460         iface->read_write = read_write;
 461         iface->command = command;
 462         init_completion(&(iface->complete));
 463
 464         /* FIFO Initiation. Data in FIFO should be discarded before
 465          * start a new operation.
 466          */
 467         write_FIFO_CTL(iface, 0x3);
 468         SSYNC();
 469         write_FIFO_CTL(iface, 0);
 470
 471         /* clear int stat */
 472         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 473
 474         /* Set Transmit device address */
 475         write_MASTER_ADDR(iface, addr);
 476         SSYNC();
 477
 478         switch (iface->cur_mode) {
 479         case TWI_I2C_MODE_STANDARDSUB:
 480                 write_XMT_DATA8(iface, iface->command);
 481                 write_INT_MASK(iface, MCOMP | MERR |
 482                         ((iface->read_write == I2C_SMBUS_READ) ?
 483                         RCVSERV : XMTSERV));
 484                 SSYNC();
 485
 486                 if (iface->writeNum + 1 <= 255)
 487                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 488                 else {
 489                         write_MASTER_CTL(iface, 0xff << 6);
 490                         iface->manual_stop = 1;
 491                 }
 492                 /* Master enable */
 493                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 494                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 495                 break;
 496         case TWI_I2C_MODE_COMBINED:
 497                 write_XMT_DATA8(iface, iface->command);
 498                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 499                 SSYNC();
 500
 501                 if (iface->writeNum > 0)
 502                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 503                 else
 504                         write_MASTER_CTL(iface, 0x1 << 6);
 505                 /* Master enable */
 506                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 507                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 508                 break;
 509         default:
 510                 write_MASTER_CTL(iface, 0);
 511                 if (size != I2C_SMBUS_QUICK) {
 512                         /* Don't access xmit data register when this is a
 513                          * read operation.
 514                          */
 515                         if (iface->read_write != I2C_SMBUS_READ) {
 516                                 if (iface->writeNum > 0) {
 517                                         write_XMT_DATA8(iface,
 518                                                 *(iface->transPtr++));
 519                                         if (iface->writeNum <= 255)
 520                                                 write_MASTER_CTL(iface,
 521                                                         iface->writeNum << 6);
 522                                         else {
 523                                                 write_MASTER_CTL(iface,
 524                                                         0xff << 6);
 525                                                 iface->manual_stop = 1;
 526                                         }
 527                                         iface->writeNum--;
 528                                 } else {
 529                                         write_XMT_DATA8(iface, iface->command);
 530                                         write_MASTER_CTL(iface, 1 << 6);
 531                                 }
 532                         } else {
 533                                 if (iface->readNum > 0 && iface->readNum <= 255)
 534                                         write_MASTER_CTL(iface,
 535                                                 iface->readNum << 6);
 536                                 else if (iface->readNum > 255) {
 537                                         write_MASTER_CTL(iface, 0xff << 6);
 538                                         iface->manual_stop = 1;
 539                                 } else
 540                                         break;
 541                         }
 542                 }
 543                 write_INT_MASK(iface, MCOMP | MERR |
 544                         ((iface->read_write == I2C_SMBUS_READ) ?
 545                         RCVSERV : XMTSERV));
 546                 SSYNC();
 547
 548                 /* Master enable */
 549                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 550                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 551                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 552                 break;
 553         }
 554         SSYNC();
 555
 556         while (!iface->result) {
 557                 if (!wait_for_completion_timeout(&iface->complete,
 558                         adap->timeout)) {
 559                         iface->result = -1;
 560                         dev_err(&adap->dev, "smbus transfer timeout\n");
 561                 }
 562         }
 563
 564         rc = (iface->result >= 0) ? 0 : -1;
 565
 566         return rc;
 567 }
 568
 569 /*
 570  * Generic I2C SMBus transfer entrypoint
 571  */
 572 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 573                         unsigned short flags, char read_write,
 574                         u8 command, int size, union i2c_smbus_data *data)
 575 {
 576         int i, ret = 0;
 577
 578         for (i = 0; i < adap->retries; i++) {
 579                 ret = bfin_twi_do_smbus_xfer(adap, addr, flags,
 580                         read_write, command, size, data);
 581                 if (ret == 0)
 582                         break;
 583         }
 584
 585         return ret;
 586 }
 587
 588 /*
 589  * Return what the adapter supports
 590  */
 591 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 592 {
 593         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 594                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 595                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
 596                I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
 597 }
 598
 599 static struct i2c_algorithm bfin_twi_algorithm = {
 600         .master_xfer   = bfin_twi_master_xfer,
 601         .smbus_xfer    = bfin_twi_smbus_xfer,
 602         .functionality = bfin_twi_functionality,
 603 };
 604
 605 static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
 606 {
 607         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 608
 609         iface->saved_clkdiv = read_CLKDIV(iface);
 610         iface->saved_control = read_CONTROL(iface);
 611
 612         free_irq(iface->irq, iface);
 613
 614         /* Disable TWI */
 615         write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
 616
 617         return 0;
 618 }
 619
 620 static int i2c_bfin_twi_resume(struct platform_device *pdev)
 621 {
 622         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 623
 624         int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 625                 IRQF_DISABLED, pdev->name, iface);
 626         if (rc) {
 627                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 628                 return -ENODEV;
 629         }
 630
 631         /* Resume TWI interface clock as specified */
 632         write_CLKDIV(iface, iface->saved_clkdiv);
 633
 634         /* Resume TWI */
 635         write_CONTROL(iface, iface->saved_control);
 636
 637         return 0;
 638 }
 639
 640 static int i2c_bfin_twi_probe(struct platform_device *pdev)
 641 {
 642         struct bfin_twi_iface *iface;
 643         struct i2c_adapter *p_adap;
 644         struct resource *res;
 645         int rc;
 646         unsigned int clkhilow;
 647
 648         iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
 649         if (!iface) {
 650                 dev_err(&pdev->dev, "Cannot allocate memory\n");
 651                 rc = -ENOMEM;
 652                 goto out_error_nomem;
 653         }
 654
 655         spin_lock_init(&(iface->lock));
 656
 657         /* Find and map our resources */
 658         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 659         if (res == NULL) {
 660                 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
 661                 rc = -ENOENT;
 662                 goto out_error_get_res;
 663         }
 664
 665         iface->regs_base = ioremap(res->start, resource_size(res));
 666         if (iface->regs_base == NULL) {
 667                 dev_err(&pdev->dev, "Cannot map IO\n");
 668                 rc = -ENXIO;
 669                 goto out_error_ioremap;
 670         }
 671
 672         iface->irq = platform_get_irq(pdev, 0);
 673         if (iface->irq < 0) {
 674                 dev_err(&pdev->dev, "No IRQ specified\n");
 675                 rc = -ENOENT;
 676                 goto out_error_no_irq;
 677         }
 678
 679         p_adap = &iface->adap;
 680         p_adap->nr = pdev->id;
 681         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
 682         p_adap->algo = &bfin_twi_algorithm;
 683         p_adap->algo_data = iface;
 684         p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 685         p_adap->dev.parent = &pdev->dev;
 686         p_adap->timeout = 5 * HZ;
 687         p_adap->retries = 3;
 688
 689         rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
 690         if (rc) {
 691                 dev_err(&pdev->dev, "Can't setup pin mux!\n");
 692                 goto out_error_pin_mux;
 693         }
 694
 695         rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 696                 IRQF_DISABLED, pdev->name, iface);
 697         if (rc) {
 698                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 699                 rc = -ENODEV;
 700                 goto out_error_req_irq;
 701         }
 702
 703         /* Set TWI internal clock as 10MHz */
 704         write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
 705
 706         /*
 707          * We will not end up with a CLKDIV=0 because no one will specify
 708          * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
 709          */
 710         clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
 711
 712         /* Set Twi interface clock as specified */
 713         write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
 714
 715         /* Enable TWI */
 716         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 717         SSYNC();
 718
 719         rc = i2c_add_numbered_adapter(p_adap);
 720         if (rc < 0) {
 721                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
 722                 goto out_error_add_adapter;
 723         }
 724
 725         platform_set_drvdata(pdev, iface);
 726
 727         dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
 728                 "regs_base@%p\n", iface->regs_base);
 729
 730         return 0;
 731
 732 out_error_add_adapter:
 733         free_irq(iface->irq, iface);
 734 out_error_req_irq:
 735 out_error_no_irq:
 736         peripheral_free_list(pin_req[pdev->id]);
 737 out_error_pin_mux:
 738         iounmap(iface->regs_base);
 739 out_error_ioremap:
 740 out_error_get_res:
 741         kfree(iface);
 742 out_error_nomem:
 743         return rc;
 744 }
 745
 746 static int i2c_bfin_twi_remove(struct platform_device *pdev)
 747 {
 748         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 749
 750         platform_set_drvdata(pdev, NULL);
 751
 752         i2c_del_adapter(&(iface->adap));
 753         free_irq(iface->irq, iface);
 754         peripheral_free_list(pin_req[pdev->id]);
 755         iounmap(iface->regs_base);
 756         kfree(iface);
 757
 758         return 0;
 759 }
 760
 761 static struct platform_driver i2c_bfin_twi_driver = {
 762         .probe          = i2c_bfin_twi_probe,
 763         .remove         = i2c_bfin_twi_remove,
 764         .suspend        = i2c_bfin_twi_suspend,
 765         .resume         = i2c_bfin_twi_resume,
 766         .driver         = {
 767                 .name   = "i2c-bfin-twi",
 768                 .owner  = THIS_MODULE,
 769         },
 770 };
 771
 772 static int __init i2c_bfin_twi_init(void)
 773 {
 774         return platform_driver_register(&i2c_bfin_twi_driver);
 775 }
 776
 777 static void __exit i2c_bfin_twi_exit(void)
 778 {
 779         platform_driver_unregister(&i2c_bfin_twi_driver);
 780 }
 781
 782 module_init(i2c_bfin_twi_init);
 783 module_exit(i2c_bfin_twi_exit);
 784
 785 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
 786 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
 787 MODULE_LICENSE("GPL");
 788 MODULE_ALIAS("platform:i2c-bfin-twi");