SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include "drmP.h"
  31 #include "radeon.h"
  32 #include "radeon_drm.h"
  33 #include "rv770d.h"
  34 #include "atom.h"
  35 #include "avivod.h"
  36
  37 #define R700_PFP_UCODE_SIZE 848
  38 #define R700_PM4_UCODE_SIZE 1360
  39
  40 static void rv770_gpu_init(struct radeon_device *rdev);
  41 void rv770_fini(struct radeon_device *rdev);
  42
  43
  44 /*
  45  * GART
  46  */
  47 int rv770_pcie_gart_enable(struct radeon_device *rdev)
  48 {
  49         u32 tmp;
  50         int r, i;
  51
  52         if (rdev->gart.table.vram.robj == NULL) {
  53                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  54                 return -EINVAL;
  55         }
  56         r = radeon_gart_table_vram_pin(rdev);
  57         if (r)
  58                 return r;
  59         radeon_gart_restore(rdev);
  60         /* Setup L2 cache */
  61         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  62                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  63                                 EFFECTIVE_L2_QUEUE_SIZE(7));
  64         WREG32(VM_L2_CNTL2, 0);
  65         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  66         /* Setup TLB control */
  67         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  68                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  69                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  70                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  71         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  72         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  73         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  74         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  75         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  76         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  77         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  78         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  79         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
  80         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  81         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  82                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
  83         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  84                         (u32)(rdev->dummy_page.addr >> 12));
  85         for (i = 1; i < 7; i++)
  86                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  87
  88         r600_pcie_gart_tlb_flush(rdev);
  89         rdev->gart.ready = true;
  90         return 0;
  91 }
  92
  93 void rv770_pcie_gart_disable(struct radeon_device *rdev)
  94 {
  95         u32 tmp;
  96         int i, r;
  97
  98         /* Disable all tables */
  99         for (i = 0; i < 7; i++)
 100                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 101
 102         /* Setup L2 cache */
 103         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 104                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 105         WREG32(VM_L2_CNTL2, 0);
 106         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 107         /* Setup TLB control */
 108         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 109         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 110         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 111         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 112         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 113         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 114         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 115         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 116         if (rdev->gart.table.vram.robj) {
 117                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 118                 if (likely(r == 0)) {
 119                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 120                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 121                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 122                 }
 123         }
 124 }
 125
 126 void rv770_pcie_gart_fini(struct radeon_device *rdev)
 127 {
 128         rv770_pcie_gart_disable(rdev);
 129         radeon_gart_table_vram_free(rdev);
 130         radeon_gart_fini(rdev);
 131 }
 132
 133
 134 void rv770_agp_enable(struct radeon_device *rdev)
 135 {
 136         u32 tmp;
 137         int i;
 138
 139         /* Setup L2 cache */
 140         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 141                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 142                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 143         WREG32(VM_L2_CNTL2, 0);
 144         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 145         /* Setup TLB control */
 146         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 147                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 148                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 149                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 150         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 151         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 152         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 153         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 154         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 155         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 156         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 157         for (i = 0; i < 7; i++)
 158                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 159 }
 160
 161 static void rv770_mc_program(struct radeon_device *rdev)
 162 {
 163         struct rv515_mc_save save;
 164         u32 tmp;
 165         int i, j;
 166
 167         /* Initialize HDP */
 168         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 169                 WREG32((0x2c14 + j), 0x00000000);
 170                 WREG32((0x2c18 + j), 0x00000000);
 171                 WREG32((0x2c1c + j), 0x00000000);
 172                 WREG32((0x2c20 + j), 0x00000000);
 173                 WREG32((0x2c24 + j), 0x00000000);
 174         }
 175         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 176
 177         rv515_mc_stop(rdev, &save);
 178         if (r600_mc_wait_for_idle(rdev)) {
 179                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 180         }
 181         /* Lockout access through VGA aperture*/
 182         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 183         /* Update configuration */
 184         if (rdev->flags & RADEON_IS_AGP) {
 185                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 186                         /* VRAM before AGP */
 187                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 188                                 rdev->mc.vram_start >> 12);
 189                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 190                                 rdev->mc.gtt_end >> 12);
 191                 } else {
 192                         /* VRAM after AGP */
 193                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 194                                 rdev->mc.gtt_start >> 12);
 195                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 196                                 rdev->mc.vram_end >> 12);
 197                 }
 198         } else {
 199                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 200                         rdev->mc.vram_start >> 12);
 201                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 202                         rdev->mc.vram_end >> 12);
 203         }
 204         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 205         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 206         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 207         WREG32(MC_VM_FB_LOCATION, tmp);
 208         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 209         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 210         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
 211         if (rdev->flags & RADEON_IS_AGP) {
 212                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
 213                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 214                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 215         } else {
 216                 WREG32(MC_VM_AGP_BASE, 0);
 217                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 218                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 219         }
 220         if (r600_mc_wait_for_idle(rdev)) {
 221                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 222         }
 223         rv515_mc_resume(rdev, &save);
 224         /* we need to own VRAM, so turn off the VGA renderer here
 225          * to stop it overwriting our objects */
 226         rv515_vga_render_disable(rdev);
 227 }
 228
 229
 230 /*
 231  * CP.
 232  */
 233 void r700_cp_stop(struct radeon_device *rdev)
 234 {
 235         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 236 }
 237
 238
 239 static int rv770_cp_load_microcode(struct radeon_device *rdev)
 240 {
 241         const __be32 *fw_data;
 242         int i;
 243
 244         if (!rdev->me_fw || !rdev->pfp_fw)
 245                 return -EINVAL;
 246
 247         r700_cp_stop(rdev);
 248         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
 249
 250         /* Reset cp */
 251         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
 252         RREG32(GRBM_SOFT_RESET);
 253         mdelay(15);
 254         WREG32(GRBM_SOFT_RESET, 0);
 255
 256         fw_data = (const __be32 *)rdev->pfp_fw->data;
 257         WREG32(CP_PFP_UCODE_ADDR, 0);
 258         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 259                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 260         WREG32(CP_PFP_UCODE_ADDR, 0);
 261
 262         fw_data = (const __be32 *)rdev->me_fw->data;
 263         WREG32(CP_ME_RAM_WADDR, 0);
 264         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 265                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 266
 267         WREG32(CP_PFP_UCODE_ADDR, 0);
 268         WREG32(CP_ME_RAM_WADDR, 0);
 269         WREG32(CP_ME_RAM_RADDR, 0);
 270         return 0;
 271 }
 272
 273
 274 /*
 275  * Core functions
 276  */
 277 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 278                                              u32 num_tile_pipes,
 279                                              u32 num_backends,
 280                                              u32 backend_disable_mask)
 281 {
 282         u32 backend_map = 0;
 283         u32 enabled_backends_mask;
 284         u32 enabled_backends_count;
 285         u32 cur_pipe;
 286         u32 swizzle_pipe[R7XX_MAX_PIPES];
 287         u32 cur_backend;
 288         u32 i;
 289         bool force_no_swizzle;
 290
 291         if (num_tile_pipes > R7XX_MAX_PIPES)
 292                 num_tile_pipes = R7XX_MAX_PIPES;
 293         if (num_tile_pipes < 1)
 294                 num_tile_pipes = 1;
 295         if (num_backends > R7XX_MAX_BACKENDS)
 296                 num_backends = R7XX_MAX_BACKENDS;
 297         if (num_backends < 1)
 298                 num_backends = 1;
 299
 300         enabled_backends_mask = 0;
 301         enabled_backends_count = 0;
 302         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
 303                 if (((backend_disable_mask >> i) & 1) == 0) {
 304                         enabled_backends_mask |= (1 << i);
 305                         ++enabled_backends_count;
 306                 }
 307                 if (enabled_backends_count == num_backends)
 308                         break;
 309         }
 310
 311         if (enabled_backends_count == 0) {
 312                 enabled_backends_mask = 1;
 313                 enabled_backends_count = 1;
 314         }
 315
 316         if (enabled_backends_count != num_backends)
 317                 num_backends = enabled_backends_count;
 318
 319         switch (rdev->family) {
 320         case CHIP_RV770:
 321         case CHIP_RV730:
 322                 force_no_swizzle = false;
 323                 break;
 324         case CHIP_RV710:
 325         case CHIP_RV740:
 326         default:
 327                 force_no_swizzle = true;
 328                 break;
 329         }
 330
 331         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
 332         switch (num_tile_pipes) {
 333         case 1:
 334                 swizzle_pipe[0] = 0;
 335                 break;
 336         case 2:
 337                 swizzle_pipe[0] = 0;
 338                 swizzle_pipe[1] = 1;
 339                 break;
 340         case 3:
 341                 if (force_no_swizzle) {
 342                         swizzle_pipe[0] = 0;
 343                         swizzle_pipe[1] = 1;
 344                         swizzle_pipe[2] = 2;
 345                 } else {
 346                         swizzle_pipe[0] = 0;
 347                         swizzle_pipe[1] = 2;
 348                         swizzle_pipe[2] = 1;
 349                 }
 350                 break;
 351         case 4:
 352                 if (force_no_swizzle) {
 353                         swizzle_pipe[0] = 0;
 354                         swizzle_pipe[1] = 1;
 355                         swizzle_pipe[2] = 2;
 356                         swizzle_pipe[3] = 3;
 357                 } else {
 358                         swizzle_pipe[0] = 0;
 359                         swizzle_pipe[1] = 2;
 360                         swizzle_pipe[2] = 3;
 361                         swizzle_pipe[3] = 1;
 362                 }
 363                 break;
 364         case 5:
 365                 if (force_no_swizzle) {
 366                         swizzle_pipe[0] = 0;
 367                         swizzle_pipe[1] = 1;
 368                         swizzle_pipe[2] = 2;
 369                         swizzle_pipe[3] = 3;
 370                         swizzle_pipe[4] = 4;
 371                 } else {
 372                         swizzle_pipe[0] = 0;
 373                         swizzle_pipe[1] = 2;
 374                         swizzle_pipe[2] = 4;
 375                         swizzle_pipe[3] = 1;
 376                         swizzle_pipe[4] = 3;
 377                 }
 378                 break;
 379         case 6:
 380                 if (force_no_swizzle) {
 381                         swizzle_pipe[0] = 0;
 382                         swizzle_pipe[1] = 1;
 383                         swizzle_pipe[2] = 2;
 384                         swizzle_pipe[3] = 3;
 385                         swizzle_pipe[4] = 4;
 386                         swizzle_pipe[5] = 5;
 387                 } else {
 388                         swizzle_pipe[0] = 0;
 389                         swizzle_pipe[1] = 2;
 390                         swizzle_pipe[2] = 4;
 391                         swizzle_pipe[3] = 5;
 392                         swizzle_pipe[4] = 3;
 393                         swizzle_pipe[5] = 1;
 394                 }
 395                 break;
 396         case 7:
 397                 if (force_no_swizzle) {
 398                         swizzle_pipe[0] = 0;
 399                         swizzle_pipe[1] = 1;
 400                         swizzle_pipe[2] = 2;
 401                         swizzle_pipe[3] = 3;
 402                         swizzle_pipe[4] = 4;
 403                         swizzle_pipe[5] = 5;
 404                         swizzle_pipe[6] = 6;
 405                 } else {
 406                         swizzle_pipe[0] = 0;
 407                         swizzle_pipe[1] = 2;
 408                         swizzle_pipe[2] = 4;
 409                         swizzle_pipe[3] = 6;
 410                         swizzle_pipe[4] = 3;
 411                         swizzle_pipe[5] = 1;
 412                         swizzle_pipe[6] = 5;
 413                 }
 414                 break;
 415         case 8:
 416                 if (force_no_swizzle) {
 417                         swizzle_pipe[0] = 0;
 418                         swizzle_pipe[1] = 1;
 419                         swizzle_pipe[2] = 2;
 420                         swizzle_pipe[3] = 3;
 421                         swizzle_pipe[4] = 4;
 422                         swizzle_pipe[5] = 5;
 423                         swizzle_pipe[6] = 6;
 424                         swizzle_pipe[7] = 7;
 425                 } else {
 426                         swizzle_pipe[0] = 0;
 427                         swizzle_pipe[1] = 2;
 428                         swizzle_pipe[2] = 4;
 429                         swizzle_pipe[3] = 6;
 430                         swizzle_pipe[4] = 3;
 431                         swizzle_pipe[5] = 1;
 432                         swizzle_pipe[6] = 7;
 433                         swizzle_pipe[7] = 5;
 434                 }
 435                 break;
 436         }
 437
 438         cur_backend = 0;
 439         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 440                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 441                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 442
 443                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 444
 445                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 446         }
 447
 448         return backend_map;
 449 }
 450
 451 static void rv770_gpu_init(struct radeon_device *rdev)
 452 {
 453         int i, j, num_qd_pipes;
 454         u32 ta_aux_cntl;
 455         u32 sx_debug_1;
 456         u32 smx_dc_ctl0;
 457         u32 db_debug3;
 458         u32 num_gs_verts_per_thread;
 459         u32 vgt_gs_per_es;
 460         u32 gs_prim_buffer_depth = 0;
 461         u32 sq_ms_fifo_sizes;
 462         u32 sq_config;
 463         u32 sq_thread_resource_mgmt;
 464         u32 hdp_host_path_cntl;
 465         u32 sq_dyn_gpr_size_simd_ab_0;
 466         u32 backend_map;
 467         u32 gb_tiling_config = 0;
 468         u32 cc_rb_backend_disable = 0;
 469         u32 cc_gc_shader_pipe_config = 0;
 470         u32 mc_arb_ramcfg;
 471         u32 db_debug4;
 472
 473         /* setup chip specs */
 474         switch (rdev->family) {
 475         case CHIP_RV770:
 476                 rdev->config.rv770.max_pipes = 4;
 477                 rdev->config.rv770.max_tile_pipes = 8;
 478                 rdev->config.rv770.max_simds = 10;
 479                 rdev->config.rv770.max_backends = 4;
 480                 rdev->config.rv770.max_gprs = 256;
 481                 rdev->config.rv770.max_threads = 248;
 482                 rdev->config.rv770.max_stack_entries = 512;
 483                 rdev->config.rv770.max_hw_contexts = 8;
 484                 rdev->config.rv770.max_gs_threads = 16 * 2;
 485                 rdev->config.rv770.sx_max_export_size = 128;
 486                 rdev->config.rv770.sx_max_export_pos_size = 16;
 487                 rdev->config.rv770.sx_max_export_smx_size = 112;
 488                 rdev->config.rv770.sq_num_cf_insts = 2;
 489
 490                 rdev->config.rv770.sx_num_of_sets = 7;
 491                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
 492                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 493                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 494                 break;
 495         case CHIP_RV730:
 496                 rdev->config.rv770.max_pipes = 2;
 497                 rdev->config.rv770.max_tile_pipes = 4;
 498                 rdev->config.rv770.max_simds = 8;
 499                 rdev->config.rv770.max_backends = 2;
 500                 rdev->config.rv770.max_gprs = 128;
 501                 rdev->config.rv770.max_threads = 248;
 502                 rdev->config.rv770.max_stack_entries = 256;
 503                 rdev->config.rv770.max_hw_contexts = 8;
 504                 rdev->config.rv770.max_gs_threads = 16 * 2;
 505                 rdev->config.rv770.sx_max_export_size = 256;
 506                 rdev->config.rv770.sx_max_export_pos_size = 32;
 507                 rdev->config.rv770.sx_max_export_smx_size = 224;
 508                 rdev->config.rv770.sq_num_cf_insts = 2;
 509
 510                 rdev->config.rv770.sx_num_of_sets = 7;
 511                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
 512                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 513                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 514                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 515                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 516                         rdev->config.rv770.sx_max_export_smx_size += 16;
 517                 }
 518                 break;
 519         case CHIP_RV710:
 520                 rdev->config.rv770.max_pipes = 2;
 521                 rdev->config.rv770.max_tile_pipes = 2;
 522                 rdev->config.rv770.max_simds = 2;
 523                 rdev->config.rv770.max_backends = 1;
 524                 rdev->config.rv770.max_gprs = 256;
 525                 rdev->config.rv770.max_threads = 192;
 526                 rdev->config.rv770.max_stack_entries = 256;
 527                 rdev->config.rv770.max_hw_contexts = 4;
 528                 rdev->config.rv770.max_gs_threads = 8 * 2;
 529                 rdev->config.rv770.sx_max_export_size = 128;
 530                 rdev->config.rv770.sx_max_export_pos_size = 16;
 531                 rdev->config.rv770.sx_max_export_smx_size = 112;
 532                 rdev->config.rv770.sq_num_cf_insts = 1;
 533
 534                 rdev->config.rv770.sx_num_of_sets = 7;
 535                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
 536                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 537                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 538                 break;
 539         case CHIP_RV740:
 540                 rdev->config.rv770.max_pipes = 4;
 541                 rdev->config.rv770.max_tile_pipes = 4;
 542                 rdev->config.rv770.max_simds = 8;
 543                 rdev->config.rv770.max_backends = 4;
 544                 rdev->config.rv770.max_gprs = 256;
 545                 rdev->config.rv770.max_threads = 248;
 546                 rdev->config.rv770.max_stack_entries = 512;
 547                 rdev->config.rv770.max_hw_contexts = 8;
 548                 rdev->config.rv770.max_gs_threads = 16 * 2;
 549                 rdev->config.rv770.sx_max_export_size = 256;
 550                 rdev->config.rv770.sx_max_export_pos_size = 32;
 551                 rdev->config.rv770.sx_max_export_smx_size = 224;
 552                 rdev->config.rv770.sq_num_cf_insts = 2;
 553
 554                 rdev->config.rv770.sx_num_of_sets = 7;
 555                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
 556                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 557                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 558
 559                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 560                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 561                         rdev->config.rv770.sx_max_export_smx_size += 16;
 562                 }
 563                 break;
 564         default:
 565                 break;
 566         }
 567
 568         /* Initialize HDP */
 569         j = 0;
 570         for (i = 0; i < 32; i++) {
 571                 WREG32((0x2c14 + j), 0x00000000);
 572                 WREG32((0x2c18 + j), 0x00000000);
 573                 WREG32((0x2c1c + j), 0x00000000);
 574                 WREG32((0x2c20 + j), 0x00000000);
 575                 WREG32((0x2c24 + j), 0x00000000);
 576                 j += 0x18;
 577         }
 578
 579         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 580
 581         /* setup tiling, simd, pipe config */
 582         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 583
 584         switch (rdev->config.rv770.max_tile_pipes) {
 585         case 1:
 586         default:
 587                 gb_tiling_config |= PIPE_TILING(0);
 588                 break;
 589         case 2:
 590                 gb_tiling_config |= PIPE_TILING(1);
 591                 break;
 592         case 4:
 593                 gb_tiling_config |= PIPE_TILING(2);
 594                 break;
 595         case 8:
 596                 gb_tiling_config |= PIPE_TILING(3);
 597                 break;
 598         }
 599         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
 600
 601         if (rdev->family == CHIP_RV770)
 602                 gb_tiling_config |= BANK_TILING(1);
 603         else
 604                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 605         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
 606
 607         gb_tiling_config |= GROUP_SIZE(0);
 608         rdev->config.rv770.tiling_group_size = 256;
 609
 610         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
 611                 gb_tiling_config |= ROW_TILING(3);
 612                 gb_tiling_config |= SAMPLE_SPLIT(3);
 613         } else {
 614                 gb_tiling_config |=
 615                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 616                 gb_tiling_config |=
 617                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 618         }
 619
 620         gb_tiling_config |= BANK_SWAPS(1);
 621
 622         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
 623         cc_rb_backend_disable |=
 624                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 625
 626         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
 627         cc_gc_shader_pipe_config |=
 628                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
 629         cc_gc_shader_pipe_config |=
 630                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 631
 632         if (rdev->family == CHIP_RV740)
 633                 backend_map = 0x28;
 634         else
 635                 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
 636                                                                 rdev->config.rv770.max_tile_pipes,
 637                                                                 (R7XX_MAX_BACKENDS -
 638                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
 639                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
 640                                                                 (cc_rb_backend_disable >> 16));
 641         gb_tiling_config |= BACKEND_MAP(backend_map);
 642
 643
 644         WREG32(GB_TILING_CONFIG, gb_tiling_config);
 645         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 646         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 647
 648         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 649         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 650         WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
 651
 652         WREG32(CGTS_SYS_TCC_DISABLE, 0);
 653         WREG32(CGTS_TCC_DISABLE, 0);
 654
 655         num_qd_pipes =
 656                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
 657         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
 658         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 659
 660         /* set HW defaults for 3D engine */
 661         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
 662                                      ROQ_IB2_START(0x2b)));
 663
 664         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 665
 666         ta_aux_cntl = RREG32(TA_CNTL_AUX);
 667         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
 668
 669         sx_debug_1 = RREG32(SX_DEBUG_1);
 670         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 671         WREG32(SX_DEBUG_1, sx_debug_1);
 672
 673         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 674         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
 675         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
 676         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 677
 678         if (rdev->family != CHIP_RV740)
 679                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
 680                                        GS_FLUSH_CTL(4) |
 681                                        ACK_FLUSH_CTL(3) |
 682                                        SYNC_FLUSH_CTL));
 683
 684         db_debug3 = RREG32(DB_DEBUG3);
 685         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
 686         switch (rdev->family) {
 687         case CHIP_RV770:
 688         case CHIP_RV740:
 689                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
 690                 break;
 691         case CHIP_RV710:
 692         case CHIP_RV730:
 693         default:
 694                 db_debug3 |= DB_CLK_OFF_DELAY(2);
 695                 break;
 696         }
 697         WREG32(DB_DEBUG3, db_debug3);
 698
 699         if (rdev->family != CHIP_RV770) {
 700                 db_debug4 = RREG32(DB_DEBUG4);
 701                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
 702                 WREG32(DB_DEBUG4, db_debug4);
 703         }
 704
 705         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
 706                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
 707                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 708
 709         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
 710                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
 711                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 712
 713         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 714
 715         WREG32(VGT_NUM_INSTANCES, 1);
 716
 717         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 718
 719         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 720
 721         WREG32(CP_PERFMON_CNTL, 0);
 722
 723         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
 724                             DONE_FIFO_HIWATER(0xe0) |
 725                             ALU_UPDATE_FIFO_HIWATER(0x8));
 726         switch (rdev->family) {
 727         case CHIP_RV770:
 728         case CHIP_RV730:
 729         case CHIP_RV710:
 730                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
 731                 break;
 732         case CHIP_RV740:
 733         default:
 734                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
 735                 break;
 736         }
 737         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 738
 739         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 740          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 741          */
 742         sq_config = RREG32(SQ_CONFIG);
 743         sq_config &= ~(PS_PRIO(3) |
 744                        VS_PRIO(3) |
 745                        GS_PRIO(3) |
 746                        ES_PRIO(3));
 747         sq_config |= (DX9_CONSTS |
 748                       VC_ENABLE |
 749                       EXPORT_SRC_C |
 750                       PS_PRIO(0) |
 751                       VS_PRIO(1) |
 752                       GS_PRIO(2) |
 753                       ES_PRIO(3));
 754         if (rdev->family == CHIP_RV710)
 755                 /* no vertex cache */
 756                 sq_config &= ~VC_ENABLE;
 757
 758         WREG32(SQ_CONFIG, sq_config);
 759
 760         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 761                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 762                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 763
 764         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
 765                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 766
 767         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 768                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
 769                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
 770         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
 771                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
 772         else
 773                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
 774         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 775
 776         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 777                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 778
 779         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 780                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 781
 782         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 783                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
 784                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 785                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 786
 787         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
 788         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
 789         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
 790         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
 791         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
 792         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
 793         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
 794         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 795
 796         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 797                                           FORCE_EOV_MAX_REZ_CNT(255)));
 798
 799         if (rdev->family == CHIP_RV710)
 800                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
 801                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 802         else
 803                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
 804                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 805
 806         switch (rdev->family) {
 807         case CHIP_RV770:
 808         case CHIP_RV730:
 809         case CHIP_RV740:
 810                 gs_prim_buffer_depth = 384;
 811                 break;
 812         case CHIP_RV710:
 813                 gs_prim_buffer_depth = 128;
 814                 break;
 815         default:
 816                 break;
 817         }
 818
 819         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
 820         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
 821         /* Max value for this is 256 */
 822         if (vgt_gs_per_es > 256)
 823                 vgt_gs_per_es = 256;
 824
 825         WREG32(VGT_ES_PER_GS, 128);
 826         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
 827         WREG32(VGT_GS_PER_VS, 2);
 828
 829         /* more default values. 2D/3D driver should adjust as needed */
 830         WREG32(VGT_GS_VERTEX_REUSE, 16);
 831         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 832         WREG32(VGT_STRMOUT_EN, 0);
 833         WREG32(SX_MISC, 0);
 834         WREG32(PA_SC_MODE_CNTL, 0);
 835         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
 836         WREG32(PA_SC_AA_CONFIG, 0);
 837         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
 838         WREG32(PA_SC_LINE_STIPPLE, 0);
 839         WREG32(SPI_INPUT_Z, 0);
 840         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 841         WREG32(CB_COLOR7_FRAG, 0);
 842
 843         /* clear render buffer base addresses */
 844         WREG32(CB_COLOR0_BASE, 0);
 845         WREG32(CB_COLOR1_BASE, 0);
 846         WREG32(CB_COLOR2_BASE, 0);
 847         WREG32(CB_COLOR3_BASE, 0);
 848         WREG32(CB_COLOR4_BASE, 0);
 849         WREG32(CB_COLOR5_BASE, 0);
 850         WREG32(CB_COLOR6_BASE, 0);
 851         WREG32(CB_COLOR7_BASE, 0);
 852
 853         WREG32(TCP_CNTL, 0);
 854
 855         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 856         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 857
 858         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 859
 860         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
 861                                           NUM_CLIP_SEQ(3)));
 862
 863 }
 864
 865 int rv770_mc_init(struct radeon_device *rdev)
 866 {
 867         fixed20_12 a;
 868         u32 tmp;
 869         int chansize, numchan;
 870
 871         /* Get VRAM informations */
 872         rdev->mc.vram_is_ddr = true;
 873         tmp = RREG32(MC_ARB_RAMCFG);
 874         if (tmp & CHANSIZE_OVERRIDE) {
 875                 chansize = 16;
 876         } else if (tmp & CHANSIZE_MASK) {
 877                 chansize = 64;
 878         } else {
 879                 chansize = 32;
 880         }
 881         tmp = RREG32(MC_SHARED_CHMAP);
 882         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 883         case 0:
 884         default:
 885                 numchan = 1;
 886                 break;
 887         case 1:
 888                 numchan = 2;
 889                 break;
 890         case 2:
 891                 numchan = 4;
 892                 break;
 893         case 3:
 894                 numchan = 8;
 895                 break;
 896         }
 897         rdev->mc.vram_width = numchan * chansize;
 898         /* Could aper size report 0 ? */
 899         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 900         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 901         /* Setup GPU memory space */
 902         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 903         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 904         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 905         /* FIXME remove this once we support unmappable VRAM */
 906         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
 907                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 908                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 909         }
 910         r600_vram_gtt_location(rdev, &rdev->mc);
 911         /* FIXME: we should enforce default clock in case GPU is not in
 912          * default setup
 913          */
 914         a.full = rfixed_const(100);
 915         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 916         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 917         return 0;
 918 }
 919
 920 int rv770_gpu_reset(struct radeon_device *rdev)
 921 {
 922         /* FIXME: implement any rv770 specific bits */
 923         return r600_gpu_reset(rdev);
 924 }
 925
 926 static int rv770_startup(struct radeon_device *rdev)
 927 {
 928         int r;
 929
 930         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
 931                 r = r600_init_microcode(rdev);
 932                 if (r) {
 933                         DRM_ERROR("Failed to load firmware!\n");
 934                         return r;
 935                 }
 936         }
 937
 938         rv770_mc_program(rdev);
 939         if (rdev->flags & RADEON_IS_AGP) {
 940                 rv770_agp_enable(rdev);
 941         } else {
 942                 r = rv770_pcie_gart_enable(rdev);
 943                 if (r)
 944                         return r;
 945         }
 946         rv770_gpu_init(rdev);
 947         r = r600_blit_init(rdev);
 948         if (r) {
 949                 r600_blit_fini(rdev);
 950                 rdev->asic->copy = NULL;
 951                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
 952         }
 953         /* pin copy shader into vram */
 954         if (rdev->r600_blit.shader_obj) {
 955                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 956                 if (unlikely(r != 0))
 957                         return r;
 958                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 959                                 &rdev->r600_blit.shader_gpu_addr);
 960                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 961                 if (r) {
 962                         DRM_ERROR("failed to pin blit object %d\n", r);
 963                         return r;
 964                 }
 965         }
 966         /* Enable IRQ */
 967         r = r600_irq_init(rdev);
 968         if (r) {
 969                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
 970                 radeon_irq_kms_fini(rdev);
 971                 return r;
 972         }
 973         r600_irq_set(rdev);
 974
 975         r = radeon_ring_init(rdev, rdev->cp.ring_size);
 976         if (r)
 977                 return r;
 978         r = rv770_cp_load_microcode(rdev);
 979         if (r)
 980                 return r;
 981         r = r600_cp_resume(rdev);
 982         if (r)
 983                 return r;
 984         /* write back buffer are not vital so don't worry about failure */
 985         r600_wb_enable(rdev);
 986         return 0;
 987 }
 988
 989 int rv770_resume(struct radeon_device *rdev)
 990 {
 991         int r;
 992
 993         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
 994          * posting will perform necessary task to bring back GPU into good
 995          * shape.
 996          */
 997         /* post card */
 998         atom_asic_init(rdev->mode_info.atom_context);
 999         /* Initialize clocks */
1000         r = radeon_clocks_init(rdev);
1001         if (r) {
1002                 return r;
1003         }
1004
1005         r = rv770_startup(rdev);
1006         if (r) {
1007                 DRM_ERROR("r600 startup failed on resume\n");
1008                 return r;
1009         }
1010
1011         r = r600_ib_test(rdev);
1012         if (r) {
1013                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1014                 return r;
1015         }
1016
1017         r = r600_audio_init(rdev);
1018         if (r) {
1019                 dev_err(rdev->dev, "radeon: audio init failed\n");
1020                 return r;
1021         }
1022
1023         return r;
1024
1025 }
1026
1027 int rv770_suspend(struct radeon_device *rdev)
1028 {
1029         int r;
1030
1031         r600_audio_fini(rdev);
1032         /* FIXME: we should wait for ring to be empty */
1033         r700_cp_stop(rdev);
1034         rdev->cp.ready = false;
1035         r600_irq_suspend(rdev);
1036         r600_wb_disable(rdev);
1037         rv770_pcie_gart_disable(rdev);
1038         /* unpin shaders bo */
1039         if (rdev->r600_blit.shader_obj) {
1040                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1041                 if (likely(r == 0)) {
1042                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1043                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1044                 }
1045         }
1046         return 0;
1047 }
1048
1049 /* Plan is to move initialization in that function and use
1050  * helper function so that radeon_device_init pretty much
1051  * do nothing more than calling asic specific function. This
1052  * should also allow to remove a bunch of callback function
1053  * like vram_info.
1054  */
1055 int rv770_init(struct radeon_device *rdev)
1056 {
1057         int r;
1058
1059         r = radeon_dummy_page_init(rdev);
1060         if (r)
1061                 return r;
1062         /* This don't do much */
1063         r = radeon_gem_init(rdev);
1064         if (r)
1065                 return r;
1066         /* Read BIOS */
1067         if (!radeon_get_bios(rdev)) {
1068                 if (ASIC_IS_AVIVO(rdev))
1069                         return -EINVAL;
1070         }
1071         /* Must be an ATOMBIOS */
1072         if (!rdev->is_atom_bios) {
1073                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1074                 return -EINVAL;
1075         }
1076         r = radeon_atombios_init(rdev);
1077         if (r)
1078                 return r;
1079         /* Post card if necessary */
1080         if (!r600_card_posted(rdev)) {
1081                 if (!rdev->bios) {
1082                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1083                         return -EINVAL;
1084                 }
1085                 DRM_INFO("GPU not posted. posting now...\n");
1086                 atom_asic_init(rdev->mode_info.atom_context);
1087         }
1088         /* Initialize scratch registers */
1089         r600_scratch_init(rdev);
1090         /* Initialize surface registers */
1091         radeon_surface_init(rdev);
1092         /* Initialize clocks */
1093         radeon_get_clock_info(rdev->ddev);
1094         r = radeon_clocks_init(rdev);
1095         if (r)
1096                 return r;
1097         /* Initialize power management */
1098         radeon_pm_init(rdev);
1099         /* Fence driver */
1100         r = radeon_fence_driver_init(rdev);
1101         if (r)
1102                 return r;
1103         /* initialize AGP */
1104         if (rdev->flags & RADEON_IS_AGP) {
1105                 r = radeon_agp_init(rdev);
1106                 if (r)
1107                         radeon_agp_disable(rdev);
1108         }
1109         r = rv770_mc_init(rdev);
1110         if (r)
1111                 return r;
1112         /* Memory manager */
1113         r = radeon_bo_init(rdev);
1114         if (r)
1115                 return r;
1116
1117         r = radeon_irq_kms_init(rdev);
1118         if (r)
1119                 return r;
1120
1121         rdev->cp.ring_obj = NULL;
1122         r600_ring_init(rdev, 1024 * 1024);
1123
1124         rdev->ih.ring_obj = NULL;
1125         r600_ih_ring_init(rdev, 64 * 1024);
1126
1127         r = r600_pcie_gart_init(rdev);
1128         if (r)
1129                 return r;
1130
1131         rdev->accel_working = true;
1132         r = rv770_startup(rdev);
1133         if (r) {
1134                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1135                 r600_cp_fini(rdev);
1136                 r600_wb_fini(rdev);
1137                 r600_irq_fini(rdev);
1138                 radeon_irq_kms_fini(rdev);
1139                 rv770_pcie_gart_fini(rdev);
1140                 rdev->accel_working = false;
1141         }
1142         if (rdev->accel_working) {
1143                 r = radeon_ib_pool_init(rdev);
1144                 if (r) {
1145                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1146                         rdev->accel_working = false;
1147                 } else {
1148                         r = r600_ib_test(rdev);
1149                         if (r) {
1150                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1151                                 rdev->accel_working = false;
1152                         }
1153                 }
1154         }
1155
1156         r = r600_audio_init(rdev);
1157         if (r) {
1158                 dev_err(rdev->dev, "radeon: audio init failed\n");
1159                 return r;
1160         }
1161
1162         return 0;
1163 }
1164
1165 void rv770_fini(struct radeon_device *rdev)
1166 {
1167         r600_blit_fini(rdev);
1168         r600_cp_fini(rdev);
1169         r600_wb_fini(rdev);
1170         r600_irq_fini(rdev);
1171         radeon_irq_kms_fini(rdev);
1172         rv770_pcie_gart_fini(rdev);
1173         radeon_gem_fini(rdev);
1174         radeon_fence_driver_fini(rdev);
1175         radeon_clocks_fini(rdev);
1176         radeon_agp_fini(rdev);
1177         radeon_bo_fini(rdev);
1178         radeon_atombios_fini(rdev);
1179         kfree(rdev->bios);
1180         rdev->bios = NULL;
1181         radeon_dummy_page_fini(rdev);
1182 }