SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include "drmP.h"
  31 #include "radeon.h"
  32 #include "rv770d.h"
  33 #include "avivod.h"
  34 #include "atom.h"
  35
  36 #define R700_PFP_UCODE_SIZE 848
  37 #define R700_PM4_UCODE_SIZE 1360
  38
  39 static void rv770_gpu_init(struct radeon_device *rdev);
  40 void rv770_fini(struct radeon_device *rdev);
  41
  42
  43 /*
  44  * GART
  45  */
  46 int rv770_pcie_gart_enable(struct radeon_device *rdev)
  47 {
  48         u32 tmp;
  49         int r, i;
  50
  51         /* Initialize common gart structure */
  52         r = radeon_gart_init(rdev);
  53         if (r) {
  54                 return r;
  55         }
  56         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
  57         r = radeon_gart_table_vram_alloc(rdev);
  58         if (r) {
  59                 return r;
  60         }
  61         for (i = 0; i < rdev->gart.num_gpu_pages; i++)
  62                 r600_gart_clear_page(rdev, i);
  63         /* Setup L2 cache */
  64         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  65                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  66                                 EFFECTIVE_L2_QUEUE_SIZE(7));
  67         WREG32(VM_L2_CNTL2, 0);
  68         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  69         /* Setup TLB control */
  70         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  71                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  72                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  73                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  74         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  75         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  76         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  77         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  78         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  79         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  80         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  81         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  82         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
  83         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  84         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  85                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
  86         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  87                         (u32)(rdev->dummy_page.addr >> 12));
  88         for (i = 1; i < 7; i++)
  89                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  90
  91         r600_pcie_gart_tlb_flush(rdev);
  92         rdev->gart.ready = true;
  93         return 0;
  94 }
  95
  96 void rv770_pcie_gart_disable(struct radeon_device *rdev)
  97 {
  98         u32 tmp;
  99         int i;
 100
 101         /* Clear ptes*/
 102         for (i = 0; i < rdev->gart.num_gpu_pages; i++)
 103                 r600_gart_clear_page(rdev, i);
 104         r600_pcie_gart_tlb_flush(rdev);
 105         /* Disable all tables */
 106         for (i = 0; i < 7; i++)
 107                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 108
 109         /* Setup L2 cache */
 110         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 111                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 112         WREG32(VM_L2_CNTL2, 0);
 113         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 114         /* Setup TLB control */
 115         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 116         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 117         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 118         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 119         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 120         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 121         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 122         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 123 }
 124
 125
 126 /*
 127  * MC
 128  */
 129 static void rv770_mc_resume(struct radeon_device *rdev)
 130 {
 131         u32 d1vga_control, d2vga_control;
 132         u32 vga_render_control, vga_hdp_control;
 133         u32 d1crtc_control, d2crtc_control;
 134         u32 new_d1grph_primary, new_d1grph_secondary;
 135         u32 new_d2grph_primary, new_d2grph_secondary;
 136         u64 old_vram_start;
 137         u32 tmp;
 138         int i, j;
 139
 140         /* Initialize HDP */
 141         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 142                 WREG32((0x2c14 + j), 0x00000000);
 143                 WREG32((0x2c18 + j), 0x00000000);
 144                 WREG32((0x2c1c + j), 0x00000000);
 145                 WREG32((0x2c20 + j), 0x00000000);
 146                 WREG32((0x2c24 + j), 0x00000000);
 147         }
 148         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 149
 150         d1vga_control = RREG32(D1VGA_CONTROL);
 151         d2vga_control = RREG32(D2VGA_CONTROL);
 152         vga_render_control = RREG32(VGA_RENDER_CONTROL);
 153         vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 154         d1crtc_control = RREG32(D1CRTC_CONTROL);
 155         d2crtc_control = RREG32(D2CRTC_CONTROL);
 156         old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
 157         new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
 158         new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
 159         new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
 160         new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
 161         new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
 162         new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
 163         new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
 164         new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
 165
 166         /* Stop all video */
 167         WREG32(D1VGA_CONTROL, 0);
 168         WREG32(D2VGA_CONTROL, 0);
 169         WREG32(VGA_RENDER_CONTROL, 0);
 170         WREG32(D1CRTC_UPDATE_LOCK, 1);
 171         WREG32(D2CRTC_UPDATE_LOCK, 1);
 172         WREG32(D1CRTC_CONTROL, 0);
 173         WREG32(D2CRTC_CONTROL, 0);
 174         WREG32(D1CRTC_UPDATE_LOCK, 0);
 175         WREG32(D2CRTC_UPDATE_LOCK, 0);
 176
 177         mdelay(1);
 178         if (r600_mc_wait_for_idle(rdev)) {
 179                 printk(KERN_WARNING "[drm] MC not idle !\n");
 180         }
 181
 182         /* Lockout access through VGA aperture*/
 183         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 184
 185         /* Update configuration */
 186         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 187         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
 188         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 189         tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
 190         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 191         WREG32(MC_VM_FB_LOCATION, tmp);
 192         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 193         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 194         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
 195         if (rdev->flags & RADEON_IS_AGP) {
 196                 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
 197                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 198                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 199         } else {
 200                 WREG32(MC_VM_AGP_BASE, 0);
 201                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 202                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 203         }
 204         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
 205         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
 206         WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
 207         WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
 208         WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
 209
 210         /* Unlock host access */
 211         WREG32(VGA_HDP_CONTROL, vga_hdp_control);
 212
 213         mdelay(1);
 214         if (r600_mc_wait_for_idle(rdev)) {
 215                 printk(KERN_WARNING "[drm] MC not idle !\n");
 216         }
 217
 218         /* Restore video state */
 219         WREG32(D1CRTC_UPDATE_LOCK, 1);
 220         WREG32(D2CRTC_UPDATE_LOCK, 1);
 221         WREG32(D1CRTC_CONTROL, d1crtc_control);
 222         WREG32(D2CRTC_CONTROL, d2crtc_control);
 223         WREG32(D1CRTC_UPDATE_LOCK, 0);
 224         WREG32(D2CRTC_UPDATE_LOCK, 0);
 225         WREG32(D1VGA_CONTROL, d1vga_control);
 226         WREG32(D2VGA_CONTROL, d2vga_control);
 227         WREG32(VGA_RENDER_CONTROL, vga_render_control);
 228 }
 229
 230
 231 /*
 232  * CP.
 233  */
 234 void r700_cp_stop(struct radeon_device *rdev)
 235 {
 236         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 237 }
 238
 239
 240 static int rv770_cp_load_microcode(struct radeon_device *rdev)
 241 {
 242         const __be32 *fw_data;
 243         int i;
 244
 245         if (!rdev->me_fw || !rdev->pfp_fw)
 246                 return -EINVAL;
 247
 248         r700_cp_stop(rdev);
 249         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
 250
 251         /* Reset cp */
 252         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
 253         RREG32(GRBM_SOFT_RESET);
 254         mdelay(15);
 255         WREG32(GRBM_SOFT_RESET, 0);
 256
 257         fw_data = (const __be32 *)rdev->pfp_fw->data;
 258         WREG32(CP_PFP_UCODE_ADDR, 0);
 259         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 260                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 261         WREG32(CP_PFP_UCODE_ADDR, 0);
 262
 263         fw_data = (const __be32 *)rdev->me_fw->data;
 264         WREG32(CP_ME_RAM_WADDR, 0);
 265         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 266                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 267
 268         WREG32(CP_PFP_UCODE_ADDR, 0);
 269         WREG32(CP_ME_RAM_WADDR, 0);
 270         WREG32(CP_ME_RAM_RADDR, 0);
 271         return 0;
 272 }
 273
 274
 275 /*
 276  * Core functions
 277  */
 278 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 279                                                 u32 num_backends,
 280                                                 u32 backend_disable_mask)
 281 {
 282         u32 backend_map = 0;
 283         u32 enabled_backends_mask;
 284         u32 enabled_backends_count;
 285         u32 cur_pipe;
 286         u32 swizzle_pipe[R7XX_MAX_PIPES];
 287         u32 cur_backend;
 288         u32 i;
 289
 290         if (num_tile_pipes > R7XX_MAX_PIPES)
 291                 num_tile_pipes = R7XX_MAX_PIPES;
 292         if (num_tile_pipes < 1)
 293                 num_tile_pipes = 1;
 294         if (num_backends > R7XX_MAX_BACKENDS)
 295                 num_backends = R7XX_MAX_BACKENDS;
 296         if (num_backends < 1)
 297                 num_backends = 1;
 298
 299         enabled_backends_mask = 0;
 300         enabled_backends_count = 0;
 301         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
 302                 if (((backend_disable_mask >> i) & 1) == 0) {
 303                         enabled_backends_mask |= (1 << i);
 304                         ++enabled_backends_count;
 305                 }
 306                 if (enabled_backends_count == num_backends)
 307                         break;
 308         }
 309
 310         if (enabled_backends_count == 0) {
 311                 enabled_backends_mask = 1;
 312                 enabled_backends_count = 1;
 313         }
 314
 315         if (enabled_backends_count != num_backends)
 316                 num_backends = enabled_backends_count;
 317
 318         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
 319         switch (num_tile_pipes) {
 320         case 1:
 321                 swizzle_pipe[0] = 0;
 322                 break;
 323         case 2:
 324                 swizzle_pipe[0] = 0;
 325                 swizzle_pipe[1] = 1;
 326                 break;
 327         case 3:
 328                 swizzle_pipe[0] = 0;
 329                 swizzle_pipe[1] = 2;
 330                 swizzle_pipe[2] = 1;
 331                 break;
 332         case 4:
 333                 swizzle_pipe[0] = 0;
 334                 swizzle_pipe[1] = 2;
 335                 swizzle_pipe[2] = 3;
 336                 swizzle_pipe[3] = 1;
 337                 break;
 338         case 5:
 339                 swizzle_pipe[0] = 0;
 340                 swizzle_pipe[1] = 2;
 341                 swizzle_pipe[2] = 4;
 342                 swizzle_pipe[3] = 1;
 343                 swizzle_pipe[4] = 3;
 344                 break;
 345         case 6:
 346                 swizzle_pipe[0] = 0;
 347                 swizzle_pipe[1] = 2;
 348                 swizzle_pipe[2] = 4;
 349                 swizzle_pipe[3] = 5;
 350                 swizzle_pipe[4] = 3;
 351                 swizzle_pipe[5] = 1;
 352                 break;
 353         case 7:
 354                 swizzle_pipe[0] = 0;
 355                 swizzle_pipe[1] = 2;
 356                 swizzle_pipe[2] = 4;
 357                 swizzle_pipe[3] = 6;
 358                 swizzle_pipe[4] = 3;
 359                 swizzle_pipe[5] = 1;
 360                 swizzle_pipe[6] = 5;
 361                 break;
 362         case 8:
 363                 swizzle_pipe[0] = 0;
 364                 swizzle_pipe[1] = 2;
 365                 swizzle_pipe[2] = 4;
 366                 swizzle_pipe[3] = 6;
 367                 swizzle_pipe[4] = 3;
 368                 swizzle_pipe[5] = 1;
 369                 swizzle_pipe[6] = 7;
 370                 swizzle_pipe[7] = 5;
 371                 break;
 372         }
 373
 374         cur_backend = 0;
 375         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 376                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 377                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 378
 379                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 380
 381                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 382         }
 383
 384         return backend_map;
 385 }
 386
 387 static void rv770_gpu_init(struct radeon_device *rdev)
 388 {
 389         int i, j, num_qd_pipes;
 390         u32 sx_debug_1;
 391         u32 smx_dc_ctl0;
 392         u32 num_gs_verts_per_thread;
 393         u32 vgt_gs_per_es;
 394         u32 gs_prim_buffer_depth = 0;
 395         u32 sq_ms_fifo_sizes;
 396         u32 sq_config;
 397         u32 sq_thread_resource_mgmt;
 398         u32 hdp_host_path_cntl;
 399         u32 sq_dyn_gpr_size_simd_ab_0;
 400         u32 backend_map;
 401         u32 gb_tiling_config = 0;
 402         u32 cc_rb_backend_disable = 0;
 403         u32 cc_gc_shader_pipe_config = 0;
 404         u32 mc_arb_ramcfg;
 405         u32 db_debug4;
 406
 407         /* setup chip specs */
 408         switch (rdev->family) {
 409         case CHIP_RV770:
 410                 rdev->config.rv770.max_pipes = 4;
 411                 rdev->config.rv770.max_tile_pipes = 8;
 412                 rdev->config.rv770.max_simds = 10;
 413                 rdev->config.rv770.max_backends = 4;
 414                 rdev->config.rv770.max_gprs = 256;
 415                 rdev->config.rv770.max_threads = 248;
 416                 rdev->config.rv770.max_stack_entries = 512;
 417                 rdev->config.rv770.max_hw_contexts = 8;
 418                 rdev->config.rv770.max_gs_threads = 16 * 2;
 419                 rdev->config.rv770.sx_max_export_size = 128;
 420                 rdev->config.rv770.sx_max_export_pos_size = 16;
 421                 rdev->config.rv770.sx_max_export_smx_size = 112;
 422                 rdev->config.rv770.sq_num_cf_insts = 2;
 423
 424                 rdev->config.rv770.sx_num_of_sets = 7;
 425                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
 426                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 427                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 428                 break;
 429         case CHIP_RV730:
 430                 rdev->config.rv770.max_pipes = 2;
 431                 rdev->config.rv770.max_tile_pipes = 4;
 432                 rdev->config.rv770.max_simds = 8;
 433                 rdev->config.rv770.max_backends = 2;
 434                 rdev->config.rv770.max_gprs = 128;
 435                 rdev->config.rv770.max_threads = 248;
 436                 rdev->config.rv770.max_stack_entries = 256;
 437                 rdev->config.rv770.max_hw_contexts = 8;
 438                 rdev->config.rv770.max_gs_threads = 16 * 2;
 439                 rdev->config.rv770.sx_max_export_size = 256;
 440                 rdev->config.rv770.sx_max_export_pos_size = 32;
 441                 rdev->config.rv770.sx_max_export_smx_size = 224;
 442                 rdev->config.rv770.sq_num_cf_insts = 2;
 443
 444                 rdev->config.rv770.sx_num_of_sets = 7;
 445                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
 446                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 447                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 448                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 449                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 450                         rdev->config.rv770.sx_max_export_smx_size += 16;
 451                 }
 452                 break;
 453         case CHIP_RV710:
 454                 rdev->config.rv770.max_pipes = 2;
 455                 rdev->config.rv770.max_tile_pipes = 2;
 456                 rdev->config.rv770.max_simds = 2;
 457                 rdev->config.rv770.max_backends = 1;
 458                 rdev->config.rv770.max_gprs = 256;
 459                 rdev->config.rv770.max_threads = 192;
 460                 rdev->config.rv770.max_stack_entries = 256;
 461                 rdev->config.rv770.max_hw_contexts = 4;
 462                 rdev->config.rv770.max_gs_threads = 8 * 2;
 463                 rdev->config.rv770.sx_max_export_size = 128;
 464                 rdev->config.rv770.sx_max_export_pos_size = 16;
 465                 rdev->config.rv770.sx_max_export_smx_size = 112;
 466                 rdev->config.rv770.sq_num_cf_insts = 1;
 467
 468                 rdev->config.rv770.sx_num_of_sets = 7;
 469                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
 470                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 471                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 472                 break;
 473         case CHIP_RV740:
 474                 rdev->config.rv770.max_pipes = 4;
 475                 rdev->config.rv770.max_tile_pipes = 4;
 476                 rdev->config.rv770.max_simds = 8;
 477                 rdev->config.rv770.max_backends = 4;
 478                 rdev->config.rv770.max_gprs = 256;
 479                 rdev->config.rv770.max_threads = 248;
 480                 rdev->config.rv770.max_stack_entries = 512;
 481                 rdev->config.rv770.max_hw_contexts = 8;
 482                 rdev->config.rv770.max_gs_threads = 16 * 2;
 483                 rdev->config.rv770.sx_max_export_size = 256;
 484                 rdev->config.rv770.sx_max_export_pos_size = 32;
 485                 rdev->config.rv770.sx_max_export_smx_size = 224;
 486                 rdev->config.rv770.sq_num_cf_insts = 2;
 487
 488                 rdev->config.rv770.sx_num_of_sets = 7;
 489                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
 490                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 491                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 492
 493                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 494                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 495                         rdev->config.rv770.sx_max_export_smx_size += 16;
 496                 }
 497                 break;
 498         default:
 499                 break;
 500         }
 501
 502         /* Initialize HDP */
 503         j = 0;
 504         for (i = 0; i < 32; i++) {
 505                 WREG32((0x2c14 + j), 0x00000000);
 506                 WREG32((0x2c18 + j), 0x00000000);
 507                 WREG32((0x2c1c + j), 0x00000000);
 508                 WREG32((0x2c20 + j), 0x00000000);
 509                 WREG32((0x2c24 + j), 0x00000000);
 510                 j += 0x18;
 511         }
 512
 513         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 514
 515         /* setup tiling, simd, pipe config */
 516         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 517
 518         switch (rdev->config.rv770.max_tile_pipes) {
 519         case 1:
 520                 gb_tiling_config |= PIPE_TILING(0);
 521                 break;
 522         case 2:
 523                 gb_tiling_config |= PIPE_TILING(1);
 524                 break;
 525         case 4:
 526                 gb_tiling_config |= PIPE_TILING(2);
 527                 break;
 528         case 8:
 529                 gb_tiling_config |= PIPE_TILING(3);
 530                 break;
 531         default:
 532                 break;
 533         }
 534
 535         if (rdev->family == CHIP_RV770)
 536                 gb_tiling_config |= BANK_TILING(1);
 537         else
 538                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
 539
 540         gb_tiling_config |= GROUP_SIZE(0);
 541
 542         if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
 543                 gb_tiling_config |= ROW_TILING(3);
 544                 gb_tiling_config |= SAMPLE_SPLIT(3);
 545         } else {
 546                 gb_tiling_config |=
 547                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 548                 gb_tiling_config |=
 549                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 550         }
 551
 552         gb_tiling_config |= BANK_SWAPS(1);
 553
 554         backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
 555                                                         rdev->config.rv770.max_backends,
 556                                                         (0xff << rdev->config.rv770.max_backends) & 0xff);
 557         gb_tiling_config |= BACKEND_MAP(backend_map);
 558
 559         cc_gc_shader_pipe_config =
 560                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
 561         cc_gc_shader_pipe_config |=
 562                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 563
 564         cc_rb_backend_disable =
 565                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 566
 567         WREG32(GB_TILING_CONFIG, gb_tiling_config);
 568         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 569         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 570
 571         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 572         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 573         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 574
 575         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 576         WREG32(CGTS_SYS_TCC_DISABLE, 0);
 577         WREG32(CGTS_TCC_DISABLE, 0);
 578         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
 579         WREG32(CGTS_USER_TCC_DISABLE, 0);
 580
 581         num_qd_pipes =
 582                 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
 583         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
 584         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 585
 586         /* set HW defaults for 3D engine */
 587         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
 588                                                 ROQ_IB2_START(0x2b)));
 589
 590         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 591
 592         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
 593                                         SYNC_GRADIENT |
 594                                         SYNC_WALKER |
 595                                         SYNC_ALIGNER));
 596
 597         sx_debug_1 = RREG32(SX_DEBUG_1);
 598         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 599         WREG32(SX_DEBUG_1, sx_debug_1);
 600
 601         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 602         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
 603         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
 604         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 605
 606         WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
 607                                           GS_FLUSH_CTL(4) |
 608                                           ACK_FLUSH_CTL(3) |
 609                                           SYNC_FLUSH_CTL));
 610
 611         if (rdev->family == CHIP_RV770)
 612                 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
 613         else {
 614                 db_debug4 = RREG32(DB_DEBUG4);
 615                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
 616                 WREG32(DB_DEBUG4, db_debug4);
 617         }
 618
 619         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
 620                                                    POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
 621                                                    SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 622
 623         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
 624                                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
 625                                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 626
 627         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 628
 629         WREG32(VGT_NUM_INSTANCES, 1);
 630
 631         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 632
 633         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 634
 635         WREG32(CP_PERFMON_CNTL, 0);
 636
 637         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
 638                             DONE_FIFO_HIWATER(0xe0) |
 639                             ALU_UPDATE_FIFO_HIWATER(0x8));
 640         switch (rdev->family) {
 641         case CHIP_RV770:
 642                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
 643                 break;
 644         case CHIP_RV730:
 645         case CHIP_RV710:
 646         case CHIP_RV740:
 647         default:
 648                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
 649                 break;
 650         }
 651         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 652
 653         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 654          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 655          */
 656         sq_config = RREG32(SQ_CONFIG);
 657         sq_config &= ~(PS_PRIO(3) |
 658                        VS_PRIO(3) |
 659                        GS_PRIO(3) |
 660                        ES_PRIO(3));
 661         sq_config |= (DX9_CONSTS |
 662                       VC_ENABLE |
 663                       EXPORT_SRC_C |
 664                       PS_PRIO(0) |
 665                       VS_PRIO(1) |
 666                       GS_PRIO(2) |
 667                       ES_PRIO(3));
 668         if (rdev->family == CHIP_RV710)
 669                 /* no vertex cache */
 670                 sq_config &= ~VC_ENABLE;
 671
 672         WREG32(SQ_CONFIG, sq_config);
 673
 674         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 675                                                     NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 676                                                     NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 677
 678         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
 679                                                     NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 680
 681         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 682                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
 683                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
 684         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
 685                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
 686         else
 687                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
 688         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 689
 690         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 691                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 692
 693         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 694                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 695
 696         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 697                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
 698                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 699                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 700
 701         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
 702         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
 703         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
 704         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
 705         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
 706         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
 707         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
 708         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 709
 710         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 711                                                      FORCE_EOV_MAX_REZ_CNT(255)));
 712
 713         if (rdev->family == CHIP_RV710)
 714                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
 715                                                            AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 716         else
 717                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
 718                                                            AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 719
 720         switch (rdev->family) {
 721         case CHIP_RV770:
 722         case CHIP_RV730:
 723         case CHIP_RV740:
 724                 gs_prim_buffer_depth = 384;
 725                 break;
 726         case CHIP_RV710:
 727                 gs_prim_buffer_depth = 128;
 728                 break;
 729         default:
 730                 break;
 731         }
 732
 733         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
 734         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
 735         /* Max value for this is 256 */
 736         if (vgt_gs_per_es > 256)
 737                 vgt_gs_per_es = 256;
 738
 739         WREG32(VGT_ES_PER_GS, 128);
 740         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
 741         WREG32(VGT_GS_PER_VS, 2);
 742
 743         /* more default values. 2D/3D driver should adjust as needed */
 744         WREG32(VGT_GS_VERTEX_REUSE, 16);
 745         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 746         WREG32(VGT_STRMOUT_EN, 0);
 747         WREG32(SX_MISC, 0);
 748         WREG32(PA_SC_MODE_CNTL, 0);
 749         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
 750         WREG32(PA_SC_AA_CONFIG, 0);
 751         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
 752         WREG32(PA_SC_LINE_STIPPLE, 0);
 753         WREG32(SPI_INPUT_Z, 0);
 754         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 755         WREG32(CB_COLOR7_FRAG, 0);
 756
 757         /* clear render buffer base addresses */
 758         WREG32(CB_COLOR0_BASE, 0);
 759         WREG32(CB_COLOR1_BASE, 0);
 760         WREG32(CB_COLOR2_BASE, 0);
 761         WREG32(CB_COLOR3_BASE, 0);
 762         WREG32(CB_COLOR4_BASE, 0);
 763         WREG32(CB_COLOR5_BASE, 0);
 764         WREG32(CB_COLOR6_BASE, 0);
 765         WREG32(CB_COLOR7_BASE, 0);
 766
 767         WREG32(TCP_CNTL, 0);
 768
 769         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 770         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 771
 772         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 773
 774         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
 775                                           NUM_CLIP_SEQ(3)));
 776
 777 }
 778
 779 int rv770_mc_init(struct radeon_device *rdev)
 780 {
 781         fixed20_12 a;
 782         u32 tmp;
 783         int r;
 784
 785         /* Get VRAM informations */
 786         /* FIXME: Don't know how to determine vram width, need to check
 787          * vram_width usage
 788          */
 789         rdev->mc.vram_width = 128;
 790         rdev->mc.vram_is_ddr = true;
 791         /* Could aper size report 0 ? */
 792         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 793         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 794         /* Setup GPU memory space */
 795         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 796         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 797         if (rdev->flags & RADEON_IS_AGP) {
 798                 r = radeon_agp_init(rdev);
 799                 if (r)
 800                         return r;
 801                 /* gtt_size is setup by radeon_agp_init */
 802                 rdev->mc.gtt_location = rdev->mc.agp_base;
 803                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
 804                 /* Try to put vram before or after AGP because we
 805                  * we want SYSTEM_APERTURE to cover both VRAM and
 806                  * AGP so that GPU can catch out of VRAM/AGP access
 807                  */
 808                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
 809                         /* Enought place before */
 810                         rdev->mc.vram_location = rdev->mc.gtt_location -
 811                                                         rdev->mc.mc_vram_size;
 812                 } else if (tmp > rdev->mc.mc_vram_size) {
 813                         /* Enought place after */
 814                         rdev->mc.vram_location = rdev->mc.gtt_location +
 815                                                         rdev->mc.gtt_size;
 816                 } else {
 817                         /* Try to setup VRAM then AGP might not
 818                          * not work on some card
 819                          */
 820                         rdev->mc.vram_location = 0x00000000UL;
 821                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 822                 }
 823         } else {
 824                 rdev->mc.vram_location = 0x00000000UL;
 825                 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 826                 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 827         }
 828         rdev->mc.vram_start = rdev->mc.vram_location;
 829         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 830         rdev->mc.gtt_start = rdev->mc.gtt_location;
 831         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
 832         /* FIXME: we should enforce default clock in case GPU is not in
 833          * default setup
 834          */
 835         a.full = rfixed_const(100);
 836         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 837         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 838         return 0;
 839 }
 840 int rv770_gpu_reset(struct radeon_device *rdev)
 841 {
 842         /* FIXME: implement */
 843         return 0;
 844 }
 845
 846 int rv770_resume(struct radeon_device *rdev)
 847 {
 848         int r;
 849
 850         rv770_mc_resume(rdev);
 851         r = rv770_pcie_gart_enable(rdev);
 852         if (r)
 853                 return r;
 854         rv770_gpu_init(rdev);
 855         r = radeon_ring_init(rdev, rdev->cp.ring_size);
 856         if (r)
 857                 return r;
 858         r = rv770_cp_load_microcode(rdev);
 859         if (r)
 860                 return r;
 861         r = r600_cp_resume(rdev);
 862         if (r)
 863                 return r;
 864         r = r600_wb_init(rdev);
 865         if (r)
 866                 return r;
 867         return 0;
 868 }
 869
 870 int rv770_suspend(struct radeon_device *rdev)
 871 {
 872         /* FIXME: we should wait for ring to be empty */
 873         r700_cp_stop(rdev);
 874         return 0;
 875 }
 876
 877 /* Plan is to move initialization in that function and use
 878  * helper function so that radeon_device_init pretty much
 879  * do nothing more than calling asic specific function. This
 880  * should also allow to remove a bunch of callback function
 881  * like vram_info.
 882  */
 883 int rv770_init(struct radeon_device *rdev)
 884 {
 885         int r;
 886
 887         rdev->new_init_path = true;
 888         r = radeon_dummy_page_init(rdev);
 889         if (r)
 890                 return r;
 891         /* This don't do much */
 892         r = radeon_gem_init(rdev);
 893         if (r)
 894                 return r;
 895         /* Read BIOS */
 896         if (!radeon_get_bios(rdev)) {
 897                 if (ASIC_IS_AVIVO(rdev))
 898                         return -EINVAL;
 899         }
 900         /* Must be an ATOMBIOS */
 901         if (!rdev->is_atom_bios)
 902                 return -EINVAL;
 903         r = radeon_atombios_init(rdev);
 904         if (r)
 905                 return r;
 906         /* Post card if necessary */
 907         if (!r600_card_posted(rdev) && rdev->bios) {
 908                 DRM_INFO("GPU not posted. posting now...\n");
 909                 atom_asic_init(rdev->mode_info.atom_context);
 910         }
 911         /* Initialize scratch registers */
 912         r600_scratch_init(rdev);
 913         /* Initialize surface registers */
 914         radeon_surface_init(rdev);
 915         r = radeon_clocks_init(rdev);
 916         if (r)
 917                 return r;
 918         /* Fence driver */
 919         r = radeon_fence_driver_init(rdev);
 920         if (r)
 921                 return r;
 922         r = rv770_mc_init(rdev);
 923         if (r) {
 924                 if (rdev->flags & RADEON_IS_AGP) {
 925                         /* Retry with disabling AGP */
 926                         rv770_fini(rdev);
 927                         rdev->flags &= ~RADEON_IS_AGP;
 928                         return rv770_init(rdev);
 929                 }
 930                 return r;
 931         }
 932         /* Memory manager */
 933         r = radeon_object_init(rdev);
 934         if (r)
 935                 return r;
 936         rdev->cp.ring_obj = NULL;
 937         r600_ring_init(rdev, 1024 * 1024);
 938
 939         if (!rdev->me_fw || !rdev->pfp_fw) {
 940                 r = r600_cp_init_microcode(rdev);
 941                 if (r) {
 942                         DRM_ERROR("Failed to load firmware!\n");
 943                         return r;
 944                 }
 945         }
 946
 947         r = rv770_resume(rdev);
 948         if (r) {
 949                 if (rdev->flags & RADEON_IS_AGP) {
 950                         /* Retry with disabling AGP */
 951                         rv770_fini(rdev);
 952                         rdev->flags &= ~RADEON_IS_AGP;
 953                         return rv770_init(rdev);
 954                 }
 955                 return r;
 956         }
 957         r = r600_blit_init(rdev);
 958         if (r) {
 959                 DRM_ERROR("radeon: failled blitter (%d).\n", r);
 960                 return r;
 961         }
 962         r = radeon_ib_pool_init(rdev);
 963         if (r) {
 964                 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
 965                 return r;
 966         }
 967         r = radeon_ib_test(rdev);
 968         if (r) {
 969                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
 970                         return r;
 971         }
 972         return 0;
 973 }
 974
 975 void rv770_fini(struct radeon_device *rdev)
 976 {
 977         r600_blit_fini(rdev);
 978         radeon_ring_fini(rdev);
 979         rv770_pcie_gart_disable(rdev);
 980         radeon_gart_table_vram_free(rdev);
 981         radeon_gart_fini(rdev);
 982         radeon_gem_fini(rdev);
 983         radeon_fence_driver_fini(rdev);
 984         radeon_clocks_fini(rdev);
 985 #if __OS_HAS_AGP
 986         if (rdev->flags & RADEON_IS_AGP)
 987                 radeon_agp_fini(rdev);
 988 #endif
 989         radeon_object_fini(rdev);
 990         if (rdev->is_atom_bios) {
 991                 radeon_atombios_fini(rdev);
 992         } else {
 993                 radeon_combios_fini(rdev);
 994         }
 995         kfree(rdev->bios);
 996         rdev->bios = NULL;
 997         radeon_dummy_page_fini(rdev);
 998 }