SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/rv515.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "rv515r.h"
  31 #include "radeon.h"
  32 #include "radeon_share.h"
  33
  34 #include "rv515_reg_safe.h"
  35 /* rv515 depends on : */
  36 void r100_hdp_reset(struct radeon_device *rdev);
  37 int r100_cp_reset(struct radeon_device *rdev);
  38 int r100_rb2d_reset(struct radeon_device *rdev);
  39 int r100_gui_wait_for_idle(struct radeon_device *rdev);
  40 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  41 int rv370_pcie_gart_enable(struct radeon_device *rdev);
  42 void rv370_pcie_gart_disable(struct radeon_device *rdev);
  43 void r420_pipes_init(struct radeon_device *rdev);
  44 void rs600_mc_disable_clients(struct radeon_device *rdev);
  45 void rs600_disable_vga(struct radeon_device *rdev);
  46
  47 /* This files gather functions specifics to:
  48  * rv515
  49  *
  50  * Some of these functions might be used by newer ASICs.
  51  */
  52 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  53 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  54 void rv515_gpu_init(struct radeon_device *rdev);
  55 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  56
  57
  58 /*
  59  * MC
  60  */
  61 int rv515_mc_init(struct radeon_device *rdev)
  62 {
  63         uint32_t tmp;
  64         int r;
  65
  66         if (r100_debugfs_rbbm_init(rdev)) {
  67                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  68         }
  69         if (rv515_debugfs_pipes_info_init(rdev)) {
  70                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  71         }
  72         if (rv515_debugfs_ga_info_init(rdev)) {
  73                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  74         }
  75
  76         rv515_gpu_init(rdev);
  77         rv370_pcie_gart_disable(rdev);
  78
  79         /* Setup GPU memory space */
  80         rdev->mc.vram_location = 0xFFFFFFFFUL;
  81         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  82         if (rdev->flags & RADEON_IS_AGP) {
  83                 r = radeon_agp_init(rdev);
  84                 if (r) {
  85                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  86                         rdev->flags &= ~RADEON_IS_AGP;
  87                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  88                 } else {
  89                         rdev->mc.gtt_location = rdev->mc.agp_base;
  90                 }
  91         }
  92         r = radeon_mc_setup(rdev);
  93         if (r) {
  94                 return r;
  95         }
  96
  97         /* Program GPU memory space */
  98         rs600_mc_disable_clients(rdev);
  99         if (rv515_mc_wait_for_idle(rdev)) {
 100                 printk(KERN_WARNING "Failed to wait MC idle while "
 101                        "programming pipes. Bad things might happen.\n");
 102         }
 103         /* Write VRAM size in case we are limiting it */
 104         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 105         tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
 106         WREG32(0x134, tmp);
 107         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 108         tmp = REG_SET(MC_FB_TOP, tmp >> 16);
 109         tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
 110         WREG32_MC(MC_FB_LOCATION, tmp);
 111         WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
 112         WREG32(0x310, rdev->mc.vram_location);
 113         if (rdev->flags & RADEON_IS_AGP) {
 114                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 115                 tmp = REG_SET(MC_AGP_TOP, tmp >> 16);
 116                 tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16);
 117                 WREG32_MC(MC_AGP_LOCATION, tmp);
 118                 WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base);
 119                 WREG32_MC(MC_AGP_BASE_2, 0);
 120         } else {
 121                 WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF);
 122                 WREG32_MC(MC_AGP_BASE, 0);
 123                 WREG32_MC(MC_AGP_BASE_2, 0);
 124         }
 125         return 0;
 126 }
 127
 128 void rv515_mc_fini(struct radeon_device *rdev)
 129 {
 130         rv370_pcie_gart_disable(rdev);
 131         radeon_gart_table_vram_free(rdev);
 132         radeon_gart_fini(rdev);
 133 }
 134
 135
 136 /*
 137  * Global GPU functions
 138  */
 139 void rv515_ring_start(struct radeon_device *rdev)
 140 {
 141         int r;
 142
 143         r = radeon_ring_lock(rdev, 64);
 144         if (r) {
 145                 return;
 146         }
 147         radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
 148         radeon_ring_write(rdev,
 149                           ISYNC_ANY2D_IDLE3D |
 150                           ISYNC_ANY3D_IDLE2D |
 151                           ISYNC_WAIT_IDLEGUI |
 152                           ISYNC_CPSCRATCH_IDLEGUI);
 153         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
 154         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
 155         radeon_ring_write(rdev, PACKET0(0x170C, 0));
 156         radeon_ring_write(rdev, 1 << 31);
 157         radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
 158         radeon_ring_write(rdev, 0);
 159         radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
 160         radeon_ring_write(rdev, 0);
 161         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
 162         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
 163         radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
 164         radeon_ring_write(rdev, 0);
 165         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
 166         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
 167         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
 168         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
 169         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
 170         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
 171         radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
 172         radeon_ring_write(rdev, 0);
 173         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
 174         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
 175         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
 176         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
 177         radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
 178         radeon_ring_write(rdev,
 179                           ((6 << MS_X0_SHIFT) |
 180                            (6 << MS_Y0_SHIFT) |
 181                            (6 << MS_X1_SHIFT) |
 182                            (6 << MS_Y1_SHIFT) |
 183                            (6 << MS_X2_SHIFT) |
 184                            (6 << MS_Y2_SHIFT) |
 185                            (6 << MSBD0_Y_SHIFT) |
 186                            (6 << MSBD0_X_SHIFT)));
 187         radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
 188         radeon_ring_write(rdev,
 189                           ((6 << MS_X3_SHIFT) |
 190                            (6 << MS_Y3_SHIFT) |
 191                            (6 << MS_X4_SHIFT) |
 192                            (6 << MS_Y4_SHIFT) |
 193                            (6 << MS_X5_SHIFT) |
 194                            (6 << MS_Y5_SHIFT) |
 195                            (6 << MSBD1_SHIFT)));
 196         radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
 197         radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
 198         radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
 199         radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
 200         radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
 201         radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
 202         radeon_ring_write(rdev, PACKET0(0x20C8, 0));
 203         radeon_ring_write(rdev, 0);
 204         radeon_ring_unlock_commit(rdev);
 205 }
 206
 207 void rv515_errata(struct radeon_device *rdev)
 208 {
 209         rdev->pll_errata = 0;
 210 }
 211
 212 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
 213 {
 214         unsigned i;
 215         uint32_t tmp;
 216
 217         for (i = 0; i < rdev->usec_timeout; i++) {
 218                 /* read MC_STATUS */
 219                 tmp = RREG32_MC(MC_STATUS);
 220                 if (tmp & MC_STATUS_IDLE) {
 221                         return 0;
 222                 }
 223                 DRM_UDELAY(1);
 224         }
 225         return -1;
 226 }
 227
 228 void rv515_gpu_init(struct radeon_device *rdev)
 229 {
 230         unsigned pipe_select_current, gb_pipe_select, tmp;
 231
 232         r100_hdp_reset(rdev);
 233         r100_rb2d_reset(rdev);
 234
 235         if (r100_gui_wait_for_idle(rdev)) {
 236                 printk(KERN_WARNING "Failed to wait GUI idle while "
 237                        "reseting GPU. Bad things might happen.\n");
 238         }
 239
 240         rs600_disable_vga(rdev);
 241
 242         r420_pipes_init(rdev);
 243         gb_pipe_select = RREG32(0x402C);
 244         tmp = RREG32(0x170C);
 245         pipe_select_current = (tmp >> 2) & 3;
 246         tmp = (1 << pipe_select_current) |
 247               (((gb_pipe_select >> 8) & 0xF) << 4);
 248         WREG32_PLL(0x000D, tmp);
 249         if (r100_gui_wait_for_idle(rdev)) {
 250                 printk(KERN_WARNING "Failed to wait GUI idle while "
 251                        "reseting GPU. Bad things might happen.\n");
 252         }
 253         if (rv515_mc_wait_for_idle(rdev)) {
 254                 printk(KERN_WARNING "Failed to wait MC idle while "
 255                        "programming pipes. Bad things might happen.\n");
 256         }
 257 }
 258
 259 int rv515_ga_reset(struct radeon_device *rdev)
 260 {
 261         uint32_t tmp;
 262         bool reinit_cp;
 263         int i;
 264
 265         reinit_cp = rdev->cp.ready;
 266         rdev->cp.ready = false;
 267         for (i = 0; i < rdev->usec_timeout; i++) {
 268                 WREG32(CP_CSQ_MODE, 0);
 269                 WREG32(CP_CSQ_CNTL, 0);
 270                 WREG32(RBBM_SOFT_RESET, 0x32005);
 271                 (void)RREG32(RBBM_SOFT_RESET);
 272                 udelay(200);
 273                 WREG32(RBBM_SOFT_RESET, 0);
 274                 /* Wait to prevent race in RBBM_STATUS */
 275                 mdelay(1);
 276                 tmp = RREG32(RBBM_STATUS);
 277                 if (tmp & ((1 << 20) | (1 << 26))) {
 278                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
 279                         /* GA still busy soft reset it */
 280                         WREG32(0x429C, 0x200);
 281                         WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
 282                         WREG32(0x43E0, 0);
 283                         WREG32(0x43E4, 0);
 284                         WREG32(0x24AC, 0);
 285                 }
 286                 /* Wait to prevent race in RBBM_STATUS */
 287                 mdelay(1);
 288                 tmp = RREG32(RBBM_STATUS);
 289                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 290                         break;
 291                 }
 292         }
 293         for (i = 0; i < rdev->usec_timeout; i++) {
 294                 tmp = RREG32(RBBM_STATUS);
 295                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 296                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
 297                                  tmp);
 298                         DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
 299                         DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
 300                         DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
 301                         if (reinit_cp) {
 302                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 303                         }
 304                         return 0;
 305                 }
 306                 DRM_UDELAY(1);
 307         }
 308         tmp = RREG32(RBBM_STATUS);
 309         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
 310         return -1;
 311 }
 312
 313 int rv515_gpu_reset(struct radeon_device *rdev)
 314 {
 315         uint32_t status;
 316
 317         /* reset order likely matter */
 318         status = RREG32(RBBM_STATUS);
 319         /* reset HDP */
 320         r100_hdp_reset(rdev);
 321         /* reset rb2d */
 322         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
 323                 r100_rb2d_reset(rdev);
 324         }
 325         /* reset GA */
 326         if (status & ((1 << 20) | (1 << 26))) {
 327                 rv515_ga_reset(rdev);
 328         }
 329         /* reset CP */
 330         status = RREG32(RBBM_STATUS);
 331         if (status & (1 << 16)) {
 332                 r100_cp_reset(rdev);
 333         }
 334         /* Check if GPU is idle */
 335         status = RREG32(RBBM_STATUS);
 336         if (status & (1 << 31)) {
 337                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
 338                 return -1;
 339         }
 340         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
 341         return 0;
 342 }
 343
 344
 345 /*
 346  * VRAM info
 347  */
 348 static void rv515_vram_get_type(struct radeon_device *rdev)
 349 {
 350         uint32_t tmp;
 351
 352         rdev->mc.vram_width = 128;
 353         rdev->mc.vram_is_ddr = true;
 354         tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
 355         switch (tmp) {
 356         case 0:
 357                 rdev->mc.vram_width = 64;
 358                 break;
 359         case 1:
 360                 rdev->mc.vram_width = 128;
 361                 break;
 362         default:
 363                 rdev->mc.vram_width = 128;
 364                 break;
 365         }
 366 }
 367
 368 void rv515_vram_info(struct radeon_device *rdev)
 369 {
 370         fixed20_12 a;
 371
 372         rv515_vram_get_type(rdev);
 373
 374         r100_vram_init_sizes(rdev);
 375         /* FIXME: we should enforce default clock in case GPU is not in
 376          * default setup
 377          */
 378         a.full = rfixed_const(100);
 379         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 380         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 381 }
 382
 383
 384 /*
 385  * Indirect registers accessor
 386  */
 387 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 388 {
 389         uint32_t r;
 390
 391         WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
 392         r = RREG32(MC_IND_DATA);
 393         WREG32(MC_IND_INDEX, 0);
 394         return r;
 395 }
 396
 397 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 398 {
 399         WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
 400         WREG32(MC_IND_DATA, (v));
 401         WREG32(MC_IND_INDEX, 0);
 402 }
 403
 404 /*
 405  * Debugfs info
 406  */
 407 #if defined(CONFIG_DEBUG_FS)
 408 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
 409 {
 410         struct drm_info_node *node = (struct drm_info_node *) m->private;
 411         struct drm_device *dev = node->minor->dev;
 412         struct radeon_device *rdev = dev->dev_private;
 413         uint32_t tmp;
 414
 415         tmp = RREG32(GB_PIPE_SELECT);
 416         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 417         tmp = RREG32(SU_REG_DEST);
 418         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
 419         tmp = RREG32(GB_TILE_CONFIG);
 420         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 421         tmp = RREG32(DST_PIPE_CONFIG);
 422         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 423         return 0;
 424 }
 425
 426 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 427 {
 428         struct drm_info_node *node = (struct drm_info_node *) m->private;
 429         struct drm_device *dev = node->minor->dev;
 430         struct radeon_device *rdev = dev->dev_private;
 431         uint32_t tmp;
 432
 433         tmp = RREG32(0x2140);
 434         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
 435         radeon_gpu_reset(rdev);
 436         tmp = RREG32(0x425C);
 437         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
 438         return 0;
 439 }
 440
 441 static struct drm_info_list rv515_pipes_info_list[] = {
 442         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
 443 };
 444
 445 static struct drm_info_list rv515_ga_info_list[] = {
 446         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
 447 };
 448 #endif
 449
 450 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
 451 {
 452 #if defined(CONFIG_DEBUG_FS)
 453         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
 454 #else
 455         return 0;
 456 #endif
 457 }
 458
 459 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
 460 {
 461 #if defined(CONFIG_DEBUG_FS)
 462         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
 463 #else
 464         return 0;
 465 #endif
 466 }
 467
 468 /*
 469  * Asic initialization
 470  */
 471 int rv515_init(struct radeon_device *rdev)
 472 {
 473         rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
 474         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
 475         return 0;
 476 }
 477
 478 void atom_rv515_force_tv_scaler(struct radeon_device *rdev)
 479 {
 480
 481         WREG32(0x659C, 0x0);
 482         WREG32(0x6594, 0x705);
 483         WREG32(0x65A4, 0x10001);
 484         WREG32(0x65D8, 0x0);
 485         WREG32(0x65B0, 0x0);
 486         WREG32(0x65C0, 0x0);
 487         WREG32(0x65D4, 0x0);
 488         WREG32(0x6578, 0x0);
 489         WREG32(0x657C, 0x841880A8);
 490         WREG32(0x6578, 0x1);
 491         WREG32(0x657C, 0x84208680);
 492         WREG32(0x6578, 0x2);
 493         WREG32(0x657C, 0xBFF880B0);
 494         WREG32(0x6578, 0x100);
 495         WREG32(0x657C, 0x83D88088);
 496         WREG32(0x6578, 0x101);
 497         WREG32(0x657C, 0x84608680);
 498         WREG32(0x6578, 0x102);
 499         WREG32(0x657C, 0xBFF080D0);
 500         WREG32(0x6578, 0x200);
 501         WREG32(0x657C, 0x83988068);
 502         WREG32(0x6578, 0x201);
 503         WREG32(0x657C, 0x84A08680);
 504         WREG32(0x6578, 0x202);
 505         WREG32(0x657C, 0xBFF080F8);
 506         WREG32(0x6578, 0x300);
 507         WREG32(0x657C, 0x83588058);
 508         WREG32(0x6578, 0x301);
 509         WREG32(0x657C, 0x84E08660);
 510         WREG32(0x6578, 0x302);
 511         WREG32(0x657C, 0xBFF88120);
 512         WREG32(0x6578, 0x400);
 513         WREG32(0x657C, 0x83188040);
 514         WREG32(0x6578, 0x401);
 515         WREG32(0x657C, 0x85008660);
 516         WREG32(0x6578, 0x402);
 517         WREG32(0x657C, 0xBFF88150);
 518         WREG32(0x6578, 0x500);
 519         WREG32(0x657C, 0x82D88030);
 520         WREG32(0x6578, 0x501);
 521         WREG32(0x657C, 0x85408640);
 522         WREG32(0x6578, 0x502);
 523         WREG32(0x657C, 0xBFF88180);
 524         WREG32(0x6578, 0x600);
 525         WREG32(0x657C, 0x82A08018);
 526         WREG32(0x6578, 0x601);
 527         WREG32(0x657C, 0x85808620);
 528         WREG32(0x6578, 0x602);
 529         WREG32(0x657C, 0xBFF081B8);
 530         WREG32(0x6578, 0x700);
 531         WREG32(0x657C, 0x82608010);
 532         WREG32(0x6578, 0x701);
 533         WREG32(0x657C, 0x85A08600);
 534         WREG32(0x6578, 0x702);
 535         WREG32(0x657C, 0x800081F0);
 536         WREG32(0x6578, 0x800);
 537         WREG32(0x657C, 0x8228BFF8);
 538         WREG32(0x6578, 0x801);
 539         WREG32(0x657C, 0x85E085E0);
 540         WREG32(0x6578, 0x802);
 541         WREG32(0x657C, 0xBFF88228);
 542         WREG32(0x6578, 0x10000);
 543         WREG32(0x657C, 0x82A8BF00);
 544         WREG32(0x6578, 0x10001);
 545         WREG32(0x657C, 0x82A08CC0);
 546         WREG32(0x6578, 0x10002);
 547         WREG32(0x657C, 0x8008BEF8);
 548         WREG32(0x6578, 0x10100);
 549         WREG32(0x657C, 0x81F0BF28);
 550         WREG32(0x6578, 0x10101);
 551         WREG32(0x657C, 0x83608CA0);
 552         WREG32(0x6578, 0x10102);
 553         WREG32(0x657C, 0x8018BED0);
 554         WREG32(0x6578, 0x10200);
 555         WREG32(0x657C, 0x8148BF38);
 556         WREG32(0x6578, 0x10201);
 557         WREG32(0x657C, 0x84408C80);
 558         WREG32(0x6578, 0x10202);
 559         WREG32(0x657C, 0x8008BEB8);
 560         WREG32(0x6578, 0x10300);
 561         WREG32(0x657C, 0x80B0BF78);
 562         WREG32(0x6578, 0x10301);
 563         WREG32(0x657C, 0x85008C20);
 564         WREG32(0x6578, 0x10302);
 565         WREG32(0x657C, 0x8020BEA0);
 566         WREG32(0x6578, 0x10400);
 567         WREG32(0x657C, 0x8028BF90);
 568         WREG32(0x6578, 0x10401);
 569         WREG32(0x657C, 0x85E08BC0);
 570         WREG32(0x6578, 0x10402);
 571         WREG32(0x657C, 0x8018BE90);
 572         WREG32(0x6578, 0x10500);
 573         WREG32(0x657C, 0xBFB8BFB0);
 574         WREG32(0x6578, 0x10501);
 575         WREG32(0x657C, 0x86C08B40);
 576         WREG32(0x6578, 0x10502);
 577         WREG32(0x657C, 0x8010BE90);
 578         WREG32(0x6578, 0x10600);
 579         WREG32(0x657C, 0xBF58BFC8);
 580         WREG32(0x6578, 0x10601);
 581         WREG32(0x657C, 0x87A08AA0);
 582         WREG32(0x6578, 0x10602);
 583         WREG32(0x657C, 0x8010BE98);
 584         WREG32(0x6578, 0x10700);
 585         WREG32(0x657C, 0xBF10BFF0);
 586         WREG32(0x6578, 0x10701);
 587         WREG32(0x657C, 0x886089E0);
 588         WREG32(0x6578, 0x10702);
 589         WREG32(0x657C, 0x8018BEB0);
 590         WREG32(0x6578, 0x10800);
 591         WREG32(0x657C, 0xBED8BFE8);
 592         WREG32(0x6578, 0x10801);
 593         WREG32(0x657C, 0x89408940);
 594         WREG32(0x6578, 0x10802);
 595         WREG32(0x657C, 0xBFE8BED8);
 596         WREG32(0x6578, 0x20000);
 597         WREG32(0x657C, 0x80008000);
 598         WREG32(0x6578, 0x20001);
 599         WREG32(0x657C, 0x90008000);
 600         WREG32(0x6578, 0x20002);
 601         WREG32(0x657C, 0x80008000);
 602         WREG32(0x6578, 0x20003);
 603         WREG32(0x657C, 0x80008000);
 604         WREG32(0x6578, 0x20100);
 605         WREG32(0x657C, 0x80108000);
 606         WREG32(0x6578, 0x20101);
 607         WREG32(0x657C, 0x8FE0BF70);
 608         WREG32(0x6578, 0x20102);
 609         WREG32(0x657C, 0xBFE880C0);
 610         WREG32(0x6578, 0x20103);
 611         WREG32(0x657C, 0x80008000);
 612         WREG32(0x6578, 0x20200);
 613         WREG32(0x657C, 0x8018BFF8);
 614         WREG32(0x6578, 0x20201);
 615         WREG32(0x657C, 0x8F80BF08);
 616         WREG32(0x6578, 0x20202);
 617         WREG32(0x657C, 0xBFD081A0);
 618         WREG32(0x6578, 0x20203);
 619         WREG32(0x657C, 0xBFF88000);
 620         WREG32(0x6578, 0x20300);
 621         WREG32(0x657C, 0x80188000);
 622         WREG32(0x6578, 0x20301);
 623         WREG32(0x657C, 0x8EE0BEC0);
 624         WREG32(0x6578, 0x20302);
 625         WREG32(0x657C, 0xBFB082A0);
 626         WREG32(0x6578, 0x20303);
 627         WREG32(0x657C, 0x80008000);
 628         WREG32(0x6578, 0x20400);
 629         WREG32(0x657C, 0x80188000);
 630         WREG32(0x6578, 0x20401);
 631         WREG32(0x657C, 0x8E00BEA0);
 632         WREG32(0x6578, 0x20402);
 633         WREG32(0x657C, 0xBF8883C0);
 634         WREG32(0x6578, 0x20403);
 635         WREG32(0x657C, 0x80008000);
 636         WREG32(0x6578, 0x20500);
 637         WREG32(0x657C, 0x80188000);
 638         WREG32(0x6578, 0x20501);
 639         WREG32(0x657C, 0x8D00BE90);
 640         WREG32(0x6578, 0x20502);
 641         WREG32(0x657C, 0xBF588500);
 642         WREG32(0x6578, 0x20503);
 643         WREG32(0x657C, 0x80008008);
 644         WREG32(0x6578, 0x20600);
 645         WREG32(0x657C, 0x80188000);
 646         WREG32(0x6578, 0x20601);
 647         WREG32(0x657C, 0x8BC0BE98);
 648         WREG32(0x6578, 0x20602);
 649         WREG32(0x657C, 0xBF308660);
 650         WREG32(0x6578, 0x20603);
 651         WREG32(0x657C, 0x80008008);
 652         WREG32(0x6578, 0x20700);
 653         WREG32(0x657C, 0x80108000);
 654         WREG32(0x6578, 0x20701);
 655         WREG32(0x657C, 0x8A80BEB0);
 656         WREG32(0x6578, 0x20702);
 657         WREG32(0x657C, 0xBF0087C0);
 658         WREG32(0x6578, 0x20703);
 659         WREG32(0x657C, 0x80008008);
 660         WREG32(0x6578, 0x20800);
 661         WREG32(0x657C, 0x80108000);
 662         WREG32(0x6578, 0x20801);
 663         WREG32(0x657C, 0x8920BED0);
 664         WREG32(0x6578, 0x20802);
 665         WREG32(0x657C, 0xBED08920);
 666         WREG32(0x6578, 0x20803);
 667         WREG32(0x657C, 0x80008010);
 668         WREG32(0x6578, 0x30000);
 669         WREG32(0x657C, 0x90008000);
 670         WREG32(0x6578, 0x30001);
 671         WREG32(0x657C, 0x80008000);
 672         WREG32(0x6578, 0x30100);
 673         WREG32(0x657C, 0x8FE0BF90);
 674         WREG32(0x6578, 0x30101);
 675         WREG32(0x657C, 0xBFF880A0);
 676         WREG32(0x6578, 0x30200);
 677         WREG32(0x657C, 0x8F60BF40);
 678         WREG32(0x6578, 0x30201);
 679         WREG32(0x657C, 0xBFE88180);
 680         WREG32(0x6578, 0x30300);
 681         WREG32(0x657C, 0x8EC0BF00);
 682         WREG32(0x6578, 0x30301);
 683         WREG32(0x657C, 0xBFC88280);
 684         WREG32(0x6578, 0x30400);
 685         WREG32(0x657C, 0x8DE0BEE0);
 686         WREG32(0x6578, 0x30401);
 687         WREG32(0x657C, 0xBFA083A0);
 688         WREG32(0x6578, 0x30500);
 689         WREG32(0x657C, 0x8CE0BED0);
 690         WREG32(0x6578, 0x30501);
 691         WREG32(0x657C, 0xBF7884E0);
 692         WREG32(0x6578, 0x30600);
 693         WREG32(0x657C, 0x8BA0BED8);
 694         WREG32(0x6578, 0x30601);
 695         WREG32(0x657C, 0xBF508640);
 696         WREG32(0x6578, 0x30700);
 697         WREG32(0x657C, 0x8A60BEE8);
 698         WREG32(0x6578, 0x30701);
 699         WREG32(0x657C, 0xBF2087A0);
 700         WREG32(0x6578, 0x30800);
 701         WREG32(0x657C, 0x8900BF00);
 702         WREG32(0x6578, 0x30801);
 703         WREG32(0x657C, 0xBF008900);
 704 }
 705
 706 struct rv515_watermark {
 707         u32        lb_request_fifo_depth;
 708         fixed20_12 num_line_pair;
 709         fixed20_12 estimated_width;
 710         fixed20_12 worst_case_latency;
 711         fixed20_12 consumption_rate;
 712         fixed20_12 active_time;
 713         fixed20_12 dbpp;
 714         fixed20_12 priority_mark_max;
 715         fixed20_12 priority_mark;
 716         fixed20_12 sclk;
 717 };
 718
 719 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 720                                   struct radeon_crtc *crtc,
 721                                   struct rv515_watermark *wm)
 722 {
 723         struct drm_display_mode *mode = &crtc->base.mode;
 724         fixed20_12 a, b, c;
 725         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 726         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 727
 728         if (!crtc->base.enabled) {
 729                 /* FIXME: wouldn't it better to set priority mark to maximum */
 730                 wm->lb_request_fifo_depth = 4;
 731                 return;
 732         }
 733
 734         if (crtc->vsc.full > rfixed_const(2))
 735                 wm->num_line_pair.full = rfixed_const(2);
 736         else
 737                 wm->num_line_pair.full = rfixed_const(1);
 738
 739         b.full = rfixed_const(mode->crtc_hdisplay);
 740         c.full = rfixed_const(256);
 741         a.full = rfixed_mul(wm->num_line_pair, b);
 742         request_fifo_depth.full = rfixed_div(a, c);
 743         if (a.full < rfixed_const(4)) {
 744                 wm->lb_request_fifo_depth = 4;
 745         } else {
 746                 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
 747         }
 748
 749         /* Determine consumption rate
 750          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 751          *  vtaps = number of vertical taps,
 752          *  vsc = vertical scaling ratio, defined as source/destination
 753          *  hsc = horizontal scaling ration, defined as source/destination
 754          */
 755         a.full = rfixed_const(mode->clock);
 756         b.full = rfixed_const(1000);
 757         a.full = rfixed_div(a, b);
 758         pclk.full = rfixed_div(b, a);
 759         if (crtc->rmx_type != RMX_OFF) {
 760                 b.full = rfixed_const(2);
 761                 if (crtc->vsc.full > b.full)
 762                         b.full = crtc->vsc.full;
 763                 b.full = rfixed_mul(b, crtc->hsc);
 764                 c.full = rfixed_const(2);
 765                 b.full = rfixed_div(b, c);
 766                 consumption_time.full = rfixed_div(pclk, b);
 767         } else {
 768                 consumption_time.full = pclk.full;
 769         }
 770         a.full = rfixed_const(1);
 771         wm->consumption_rate.full = rfixed_div(a, consumption_time);
 772
 773
 774         /* Determine line time
 775          *  LineTime = total time for one line of displayhtotal
 776          *  LineTime = total number of horizontal pixels
 777          *  pclk = pixel clock period(ns)
 778          */
 779         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 780         line_time.full = rfixed_mul(a, pclk);
 781
 782         /* Determine active time
 783          *  ActiveTime = time of active region of display within one line,
 784          *  hactive = total number of horizontal active pixels
 785          *  htotal = total number of horizontal pixels
 786          */
 787         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 788         b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 789         wm->active_time.full = rfixed_mul(line_time, b);
 790         wm->active_time.full = rfixed_div(wm->active_time, a);
 791
 792         /* Determine chunk time
 793          * ChunkTime = the time it takes the DCP to send one chunk of data
 794          * to the LB which consists of pipeline delay and inter chunk gap
 795          * sclk = system clock(Mhz)
 796          */
 797         a.full = rfixed_const(600 * 1000);
 798         chunk_time.full = rfixed_div(a, rdev->pm.sclk);
 799         read_delay_latency.full = rfixed_const(1000);
 800
 801         /* Determine the worst case latency
 802          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 803          * WorstCaseLatency = worst case time from urgent to when the MC starts
 804          *                    to return data
 805          * READ_DELAY_IDLE_MAX = constant of 1us
 806          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 807          *             which consists of pipeline delay and inter chunk gap
 808          */
 809         if (rfixed_trunc(wm->num_line_pair) > 1) {
 810                 a.full = rfixed_const(3);
 811                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 812                 wm->worst_case_latency.full += read_delay_latency.full;
 813         } else {
 814                 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
 815         }
 816
 817         /* Determine the tolerable latency
 818          * TolerableLatency = Any given request has only 1 line time
 819          *                    for the data to be returned
 820          * LBRequestFifoDepth = Number of chunk requests the LB can
 821          *                      put into the request FIFO for a display
 822          *  LineTime = total time for one line of display
 823          *  ChunkTime = the time it takes the DCP to send one chunk
 824          *              of data to the LB which consists of
 825          *  pipeline delay and inter chunk gap
 826          */
 827         if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
 828                 tolerable_latency.full = line_time.full;
 829         } else {
 830                 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
 831                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 832                 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
 833                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 834         }
 835         /* We assume worst case 32bits (4 bytes) */
 836         wm->dbpp.full = rfixed_const(2 * 16);
 837
 838         /* Determine the maximum priority mark
 839          *  width = viewport width in pixels
 840          */
 841         a.full = rfixed_const(16);
 842         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 843         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
 844
 845         /* Determine estimated width */
 846         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 847         estimated_width.full = rfixed_div(estimated_width, consumption_time);
 848         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 849                 wm->priority_mark.full = rfixed_const(10);
 850         } else {
 851                 a.full = rfixed_const(16);
 852                 wm->priority_mark.full = rfixed_div(estimated_width, a);
 853                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 854         }
 855 }
 856
 857 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
 858 {
 859         struct drm_display_mode *mode0 = NULL;
 860         struct drm_display_mode *mode1 = NULL;
 861         struct rv515_watermark wm0;
 862         struct rv515_watermark wm1;
 863         u32 tmp;
 864         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 865         fixed20_12 a, b;
 866
 867         if (rdev->mode_info.crtcs[0]->base.enabled)
 868                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 869         if (rdev->mode_info.crtcs[1]->base.enabled)
 870                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 871         rs690_line_buffer_adjust(rdev, mode0, mode1);
 872
 873         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 874         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 875
 876         tmp = wm0.lb_request_fifo_depth;
 877         tmp |= wm1.lb_request_fifo_depth << 16;
 878         WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
 879
 880         if (mode0 && mode1) {
 881                 if (rfixed_trunc(wm0.dbpp) > 64)
 882                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
 883                 else
 884                         a.full = wm0.num_line_pair.full;
 885                 if (rfixed_trunc(wm1.dbpp) > 64)
 886                         b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
 887                 else
 888                         b.full = wm1.num_line_pair.full;
 889                 a.full += b.full;
 890                 fill_rate.full = rfixed_div(wm0.sclk, a);
 891                 if (wm0.consumption_rate.full > fill_rate.full) {
 892                         b.full = wm0.consumption_rate.full - fill_rate.full;
 893                         b.full = rfixed_mul(b, wm0.active_time);
 894                         a.full = rfixed_const(16);
 895                         b.full = rfixed_div(b, a);
 896                         a.full = rfixed_mul(wm0.worst_case_latency,
 897                                                 wm0.consumption_rate);
 898                         priority_mark02.full = a.full + b.full;
 899                 } else {
 900                         a.full = rfixed_mul(wm0.worst_case_latency,
 901                                                 wm0.consumption_rate);
 902                         b.full = rfixed_const(16 * 1000);
 903                         priority_mark02.full = rfixed_div(a, b);
 904                 }
 905                 if (wm1.consumption_rate.full > fill_rate.full) {
 906                         b.full = wm1.consumption_rate.full - fill_rate.full;
 907                         b.full = rfixed_mul(b, wm1.active_time);
 908                         a.full = rfixed_const(16);
 909                         b.full = rfixed_div(b, a);
 910                         a.full = rfixed_mul(wm1.worst_case_latency,
 911                                                 wm1.consumption_rate);
 912                         priority_mark12.full = a.full + b.full;
 913                 } else {
 914                         a.full = rfixed_mul(wm1.worst_case_latency,
 915                                                 wm1.consumption_rate);
 916                         b.full = rfixed_const(16 * 1000);
 917                         priority_mark12.full = rfixed_div(a, b);
 918                 }
 919                 if (wm0.priority_mark.full > priority_mark02.full)
 920                         priority_mark02.full = wm0.priority_mark.full;
 921                 if (rfixed_trunc(priority_mark02) < 0)
 922                         priority_mark02.full = 0;
 923                 if (wm0.priority_mark_max.full > priority_mark02.full)
 924                         priority_mark02.full = wm0.priority_mark_max.full;
 925                 if (wm1.priority_mark.full > priority_mark12.full)
 926                         priority_mark12.full = wm1.priority_mark.full;
 927                 if (rfixed_trunc(priority_mark12) < 0)
 928                         priority_mark12.full = 0;
 929                 if (wm1.priority_mark_max.full > priority_mark12.full)
 930                         priority_mark12.full = wm1.priority_mark_max.full;
 931                 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
 932                 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
 933                 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
 934                 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
 935         } else if (mode0) {
 936                 if (rfixed_trunc(wm0.dbpp) > 64)
 937                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
 938                 else
 939                         a.full = wm0.num_line_pair.full;
 940                 fill_rate.full = rfixed_div(wm0.sclk, a);
 941                 if (wm0.consumption_rate.full > fill_rate.full) {
 942                         b.full = wm0.consumption_rate.full - fill_rate.full;
 943                         b.full = rfixed_mul(b, wm0.active_time);
 944                         a.full = rfixed_const(16);
 945                         b.full = rfixed_div(b, a);
 946                         a.full = rfixed_mul(wm0.worst_case_latency,
 947                                                 wm0.consumption_rate);
 948                         priority_mark02.full = a.full + b.full;
 949                 } else {
 950                         a.full = rfixed_mul(wm0.worst_case_latency,
 951                                                 wm0.consumption_rate);
 952                         b.full = rfixed_const(16);
 953                         priority_mark02.full = rfixed_div(a, b);
 954                 }
 955                 if (wm0.priority_mark.full > priority_mark02.full)
 956                         priority_mark02.full = wm0.priority_mark.full;
 957                 if (rfixed_trunc(priority_mark02) < 0)
 958                         priority_mark02.full = 0;
 959                 if (wm0.priority_mark_max.full > priority_mark02.full)
 960                         priority_mark02.full = wm0.priority_mark_max.full;
 961                 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
 962                 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
 963                 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
 964                 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
 965         } else {
 966                 if (rfixed_trunc(wm1.dbpp) > 64)
 967                         a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
 968                 else
 969                         a.full = wm1.num_line_pair.full;
 970                 fill_rate.full = rfixed_div(wm1.sclk, a);
 971                 if (wm1.consumption_rate.full > fill_rate.full) {
 972                         b.full = wm1.consumption_rate.full - fill_rate.full;
 973                         b.full = rfixed_mul(b, wm1.active_time);
 974                         a.full = rfixed_const(16);
 975                         b.full = rfixed_div(b, a);
 976                         a.full = rfixed_mul(wm1.worst_case_latency,
 977                                                 wm1.consumption_rate);
 978                         priority_mark12.full = a.full + b.full;
 979                 } else {
 980                         a.full = rfixed_mul(wm1.worst_case_latency,
 981                                                 wm1.consumption_rate);
 982                         b.full = rfixed_const(16 * 1000);
 983                         priority_mark12.full = rfixed_div(a, b);
 984                 }
 985                 if (wm1.priority_mark.full > priority_mark12.full)
 986                         priority_mark12.full = wm1.priority_mark.full;
 987                 if (rfixed_trunc(priority_mark12) < 0)
 988                         priority_mark12.full = 0;
 989                 if (wm1.priority_mark_max.full > priority_mark12.full)
 990                         priority_mark12.full = wm1.priority_mark_max.full;
 991                 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
 992                 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
 993                 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
 994                 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
 995         }
 996 }
 997
 998 void rv515_bandwidth_update(struct radeon_device *rdev)
 999 {
1000         uint32_t tmp;
1001         struct drm_display_mode *mode0 = NULL;
1002         struct drm_display_mode *mode1 = NULL;
1003
1004         if (rdev->mode_info.crtcs[0]->base.enabled)
1005                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1006         if (rdev->mode_info.crtcs[1]->base.enabled)
1007                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1008         /*
1009          * Set display0/1 priority up in the memory controller for
1010          * modes if the user specifies HIGH for displaypriority
1011          * option.
1012          */
1013         if (rdev->disp_priority == 2) {
1014                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1015                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1016                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1017                 if (mode1)
1018                         tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1019                 if (mode0)
1020                         tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1021                 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1022         }
1023         rv515_bandwidth_avivo_update(rdev);
1024 }