SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/rv515.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "rv515d.h"
  31 #include "radeon.h"
  32 #include "atom.h"
  33 #include "rv515_reg_safe.h"
  34
  35 /* This files gather functions specifics to: rv515 */
  36 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  37 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  38 void rv515_gpu_init(struct radeon_device *rdev);
  39 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  40
  41 void rv515_debugfs(struct radeon_device *rdev)
  42 {
  43         if (r100_debugfs_rbbm_init(rdev)) {
  44                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  45         }
  46         if (rv515_debugfs_pipes_info_init(rdev)) {
  47                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  48         }
  49         if (rv515_debugfs_ga_info_init(rdev)) {
  50                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  51         }
  52 }
  53
  54 void rv515_ring_start(struct radeon_device *rdev)
  55 {
  56         int r;
  57
  58         r = radeon_ring_lock(rdev, 64);
  59         if (r) {
  60                 return;
  61         }
  62         radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
  63         radeon_ring_write(rdev,
  64                           ISYNC_ANY2D_IDLE3D |
  65                           ISYNC_ANY3D_IDLE2D |
  66                           ISYNC_WAIT_IDLEGUI |
  67                           ISYNC_CPSCRATCH_IDLEGUI);
  68         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
  69         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  70         radeon_ring_write(rdev, PACKET0(0x170C, 0));
  71         radeon_ring_write(rdev, 1 << 31);
  72         radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
  73         radeon_ring_write(rdev, 0);
  74         radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
  75         radeon_ring_write(rdev, 0);
  76         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
  77         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
  78         radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
  79         radeon_ring_write(rdev, 0);
  80         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  81         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
  82         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  83         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
  84         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
  85         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  86         radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
  87         radeon_ring_write(rdev, 0);
  88         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  89         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
  90         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  91         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
  92         radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
  93         radeon_ring_write(rdev,
  94                           ((6 << MS_X0_SHIFT) |
  95                            (6 << MS_Y0_SHIFT) |
  96                            (6 << MS_X1_SHIFT) |
  97                            (6 << MS_Y1_SHIFT) |
  98                            (6 << MS_X2_SHIFT) |
  99                            (6 << MS_Y2_SHIFT) |
 100                            (6 << MSBD0_Y_SHIFT) |
 101                            (6 << MSBD0_X_SHIFT)));
 102         radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
 103         radeon_ring_write(rdev,
 104                           ((6 << MS_X3_SHIFT) |
 105                            (6 << MS_Y3_SHIFT) |
 106                            (6 << MS_X4_SHIFT) |
 107                            (6 << MS_Y4_SHIFT) |
 108                            (6 << MS_X5_SHIFT) |
 109                            (6 << MS_Y5_SHIFT) |
 110                            (6 << MSBD1_SHIFT)));
 111         radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
 112         radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
 113         radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
 114         radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
 115         radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
 116         radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
 117         radeon_ring_write(rdev, PACKET0(0x20C8, 0));
 118         radeon_ring_write(rdev, 0);
 119         radeon_ring_unlock_commit(rdev);
 120 }
 121
 122 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
 123 {
 124         unsigned i;
 125         uint32_t tmp;
 126
 127         for (i = 0; i < rdev->usec_timeout; i++) {
 128                 /* read MC_STATUS */
 129                 tmp = RREG32_MC(MC_STATUS);
 130                 if (tmp & MC_STATUS_IDLE) {
 131                         return 0;
 132                 }
 133                 DRM_UDELAY(1);
 134         }
 135         return -1;
 136 }
 137
 138 void rv515_vga_render_disable(struct radeon_device *rdev)
 139 {
 140         WREG32(R_000300_VGA_RENDER_CONTROL,
 141                 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
 142 }
 143
 144 void rv515_gpu_init(struct radeon_device *rdev)
 145 {
 146         unsigned pipe_select_current, gb_pipe_select, tmp;
 147
 148         r100_hdp_reset(rdev);
 149         r100_rb2d_reset(rdev);
 150
 151         if (r100_gui_wait_for_idle(rdev)) {
 152                 printk(KERN_WARNING "Failed to wait GUI idle while "
 153                        "reseting GPU. Bad things might happen.\n");
 154         }
 155
 156         rv515_vga_render_disable(rdev);
 157
 158         r420_pipes_init(rdev);
 159         gb_pipe_select = RREG32(0x402C);
 160         tmp = RREG32(0x170C);
 161         pipe_select_current = (tmp >> 2) & 3;
 162         tmp = (1 << pipe_select_current) |
 163               (((gb_pipe_select >> 8) & 0xF) << 4);
 164         WREG32_PLL(0x000D, tmp);
 165         if (r100_gui_wait_for_idle(rdev)) {
 166                 printk(KERN_WARNING "Failed to wait GUI idle while "
 167                        "reseting GPU. Bad things might happen.\n");
 168         }
 169         if (rv515_mc_wait_for_idle(rdev)) {
 170                 printk(KERN_WARNING "Failed to wait MC idle while "
 171                        "programming pipes. Bad things might happen.\n");
 172         }
 173 }
 174
 175 int rv515_ga_reset(struct radeon_device *rdev)
 176 {
 177         uint32_t tmp;
 178         bool reinit_cp;
 179         int i;
 180
 181         reinit_cp = rdev->cp.ready;
 182         rdev->cp.ready = false;
 183         for (i = 0; i < rdev->usec_timeout; i++) {
 184                 WREG32(CP_CSQ_MODE, 0);
 185                 WREG32(CP_CSQ_CNTL, 0);
 186                 WREG32(RBBM_SOFT_RESET, 0x32005);
 187                 (void)RREG32(RBBM_SOFT_RESET);
 188                 udelay(200);
 189                 WREG32(RBBM_SOFT_RESET, 0);
 190                 /* Wait to prevent race in RBBM_STATUS */
 191                 mdelay(1);
 192                 tmp = RREG32(RBBM_STATUS);
 193                 if (tmp & ((1 << 20) | (1 << 26))) {
 194                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
 195                         /* GA still busy soft reset it */
 196                         WREG32(0x429C, 0x200);
 197                         WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
 198                         WREG32(0x43E0, 0);
 199                         WREG32(0x43E4, 0);
 200                         WREG32(0x24AC, 0);
 201                 }
 202                 /* Wait to prevent race in RBBM_STATUS */
 203                 mdelay(1);
 204                 tmp = RREG32(RBBM_STATUS);
 205                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 206                         break;
 207                 }
 208         }
 209         for (i = 0; i < rdev->usec_timeout; i++) {
 210                 tmp = RREG32(RBBM_STATUS);
 211                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 212                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
 213                                  tmp);
 214                         DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
 215                         DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
 216                         DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
 217                         if (reinit_cp) {
 218                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 219                         }
 220                         return 0;
 221                 }
 222                 DRM_UDELAY(1);
 223         }
 224         tmp = RREG32(RBBM_STATUS);
 225         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
 226         return -1;
 227 }
 228
 229 int rv515_gpu_reset(struct radeon_device *rdev)
 230 {
 231         uint32_t status;
 232
 233         /* reset order likely matter */
 234         status = RREG32(RBBM_STATUS);
 235         /* reset HDP */
 236         r100_hdp_reset(rdev);
 237         /* reset rb2d */
 238         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
 239                 r100_rb2d_reset(rdev);
 240         }
 241         /* reset GA */
 242         if (status & ((1 << 20) | (1 << 26))) {
 243                 rv515_ga_reset(rdev);
 244         }
 245         /* reset CP */
 246         status = RREG32(RBBM_STATUS);
 247         if (status & (1 << 16)) {
 248                 r100_cp_reset(rdev);
 249         }
 250         /* Check if GPU is idle */
 251         status = RREG32(RBBM_STATUS);
 252         if (status & (1 << 31)) {
 253                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
 254                 return -1;
 255         }
 256         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
 257         return 0;
 258 }
 259
 260 static void rv515_vram_get_type(struct radeon_device *rdev)
 261 {
 262         uint32_t tmp;
 263
 264         rdev->mc.vram_width = 128;
 265         rdev->mc.vram_is_ddr = true;
 266         tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
 267         switch (tmp) {
 268         case 0:
 269                 rdev->mc.vram_width = 64;
 270                 break;
 271         case 1:
 272                 rdev->mc.vram_width = 128;
 273                 break;
 274         default:
 275                 rdev->mc.vram_width = 128;
 276                 break;
 277         }
 278 }
 279
 280 void rv515_mc_init(struct radeon_device *rdev)
 281 {
 282         fixed20_12 a;
 283
 284         rv515_vram_get_type(rdev);
 285         r100_vram_init_sizes(rdev);
 286         radeon_vram_location(rdev, &rdev->mc, 0);
 287         if (!(rdev->flags & RADEON_IS_AGP))
 288                 radeon_gtt_location(rdev, &rdev->mc);
 289         /* FIXME: we should enforce default clock in case GPU is not in
 290          * default setup
 291          */
 292         a.full = rfixed_const(100);
 293         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 294         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 295 }
 296
 297 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 298 {
 299         uint32_t r;
 300
 301         WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
 302         r = RREG32(MC_IND_DATA);
 303         WREG32(MC_IND_INDEX, 0);
 304         return r;
 305 }
 306
 307 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 308 {
 309         WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
 310         WREG32(MC_IND_DATA, (v));
 311         WREG32(MC_IND_INDEX, 0);
 312 }
 313
 314 #if defined(CONFIG_DEBUG_FS)
 315 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
 316 {
 317         struct drm_info_node *node = (struct drm_info_node *) m->private;
 318         struct drm_device *dev = node->minor->dev;
 319         struct radeon_device *rdev = dev->dev_private;
 320         uint32_t tmp;
 321
 322         tmp = RREG32(GB_PIPE_SELECT);
 323         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 324         tmp = RREG32(SU_REG_DEST);
 325         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
 326         tmp = RREG32(GB_TILE_CONFIG);
 327         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 328         tmp = RREG32(DST_PIPE_CONFIG);
 329         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 330         return 0;
 331 }
 332
 333 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 334 {
 335         struct drm_info_node *node = (struct drm_info_node *) m->private;
 336         struct drm_device *dev = node->minor->dev;
 337         struct radeon_device *rdev = dev->dev_private;
 338         uint32_t tmp;
 339
 340         tmp = RREG32(0x2140);
 341         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
 342         radeon_gpu_reset(rdev);
 343         tmp = RREG32(0x425C);
 344         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
 345         return 0;
 346 }
 347
 348 static struct drm_info_list rv515_pipes_info_list[] = {
 349         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
 350 };
 351
 352 static struct drm_info_list rv515_ga_info_list[] = {
 353         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
 354 };
 355 #endif
 356
 357 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
 358 {
 359 #if defined(CONFIG_DEBUG_FS)
 360         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
 361 #else
 362         return 0;
 363 #endif
 364 }
 365
 366 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
 367 {
 368 #if defined(CONFIG_DEBUG_FS)
 369         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
 370 #else
 371         return 0;
 372 #endif
 373 }
 374
 375 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
 376 {
 377         save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
 378         save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
 379         save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
 380         save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
 381         save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
 382         save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
 383
 384         /* Stop all video */
 385         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 386         WREG32(R_000300_VGA_RENDER_CONTROL, 0);
 387         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
 388         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
 389         WREG32(R_006080_D1CRTC_CONTROL, 0);
 390         WREG32(R_006880_D2CRTC_CONTROL, 0);
 391         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
 392         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 393         WREG32(R_000330_D1VGA_CONTROL, 0);
 394         WREG32(R_000338_D2VGA_CONTROL, 0);
 395 }
 396
 397 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
 398 {
 399         WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 400         WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 401         WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 402         WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 403         WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
 404         /* Unlock host access */
 405         WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
 406         mdelay(1);
 407         /* Restore video state */
 408         WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
 409         WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
 410         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
 411         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
 412         WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
 413         WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
 414         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
 415         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 416         WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
 417 }
 418
 419 void rv515_mc_program(struct radeon_device *rdev)
 420 {
 421         struct rv515_mc_save save;
 422
 423         /* Stops all mc clients */
 424         rv515_mc_stop(rdev, &save);
 425
 426         /* Wait for mc idle */
 427         if (rv515_mc_wait_for_idle(rdev))
 428                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 429         /* Write VRAM size in case we are limiting it */
 430         WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 431         /* Program MC, should be a 32bits limited address space */
 432         WREG32_MC(R_000001_MC_FB_LOCATION,
 433                         S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
 434                         S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
 435         WREG32(R_000134_HDP_FB_LOCATION,
 436                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 437         if (rdev->flags & RADEON_IS_AGP) {
 438                 WREG32_MC(R_000002_MC_AGP_LOCATION,
 439                         S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
 440                         S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
 441                 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
 442                 WREG32_MC(R_000004_MC_AGP_BASE_2,
 443                         S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
 444         } else {
 445                 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
 446                 WREG32_MC(R_000003_MC_AGP_BASE, 0);
 447                 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
 448         }
 449
 450         rv515_mc_resume(rdev, &save);
 451 }
 452
 453 void rv515_clock_startup(struct radeon_device *rdev)
 454 {
 455         if (radeon_dynclks != -1 && radeon_dynclks)
 456                 radeon_atom_set_clock_gating(rdev, 1);
 457         /* We need to force on some of the block */
 458         WREG32_PLL(R_00000F_CP_DYN_CNTL,
 459                 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
 460         WREG32_PLL(R_000011_E2_DYN_CNTL,
 461                 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
 462         WREG32_PLL(R_000013_IDCT_DYN_CNTL,
 463                 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
 464 }
 465
 466 static int rv515_startup(struct radeon_device *rdev)
 467 {
 468         int r;
 469
 470         rv515_mc_program(rdev);
 471         /* Resume clock */
 472         rv515_clock_startup(rdev);
 473         /* Initialize GPU configuration (# pipes, ...) */
 474         rv515_gpu_init(rdev);
 475         /* Initialize GART (initialize after TTM so we can allocate
 476          * memory through TTM but finalize after TTM) */
 477         if (rdev->flags & RADEON_IS_PCIE) {
 478                 r = rv370_pcie_gart_enable(rdev);
 479                 if (r)
 480                         return r;
 481         }
 482         /* Enable IRQ */
 483         rs600_irq_set(rdev);
 484         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 485         /* 1M ring buffer */
 486         r = r100_cp_init(rdev, 1024 * 1024);
 487         if (r) {
 488                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 489                 return r;
 490         }
 491         r = r100_wb_init(rdev);
 492         if (r)
 493                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 494         r = r100_ib_init(rdev);
 495         if (r) {
 496                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 497                 return r;
 498         }
 499         return 0;
 500 }
 501
 502 int rv515_resume(struct radeon_device *rdev)
 503 {
 504         /* Make sur GART are not working */
 505         if (rdev->flags & RADEON_IS_PCIE)
 506                 rv370_pcie_gart_disable(rdev);
 507         /* Resume clock before doing reset */
 508         rv515_clock_startup(rdev);
 509         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 510         if (radeon_gpu_reset(rdev)) {
 511                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 512                         RREG32(R_000E40_RBBM_STATUS),
 513                         RREG32(R_0007C0_CP_STAT));
 514         }
 515         /* post */
 516         atom_asic_init(rdev->mode_info.atom_context);
 517         /* Resume clock after posting */
 518         rv515_clock_startup(rdev);
 519         /* Initialize surface registers */
 520         radeon_surface_init(rdev);
 521         return rv515_startup(rdev);
 522 }
 523
 524 int rv515_suspend(struct radeon_device *rdev)
 525 {
 526         r100_cp_disable(rdev);
 527         r100_wb_disable(rdev);
 528         rs600_irq_disable(rdev);
 529         if (rdev->flags & RADEON_IS_PCIE)
 530                 rv370_pcie_gart_disable(rdev);
 531         return 0;
 532 }
 533
 534 void rv515_set_safe_registers(struct radeon_device *rdev)
 535 {
 536         rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
 537         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
 538 }
 539
 540 void rv515_fini(struct radeon_device *rdev)
 541 {
 542         r100_cp_fini(rdev);
 543         r100_wb_fini(rdev);
 544         r100_ib_fini(rdev);
 545         radeon_gem_fini(rdev);
 546         rv370_pcie_gart_fini(rdev);
 547         radeon_agp_fini(rdev);
 548         radeon_irq_kms_fini(rdev);
 549         radeon_fence_driver_fini(rdev);
 550         radeon_bo_fini(rdev);
 551         radeon_atombios_fini(rdev);
 552         kfree(rdev->bios);
 553         rdev->bios = NULL;
 554 }
 555
 556 int rv515_init(struct radeon_device *rdev)
 557 {
 558         int r;
 559
 560         /* Initialize scratch registers */
 561         radeon_scratch_init(rdev);
 562         /* Initialize surface registers */
 563         radeon_surface_init(rdev);
 564         /* TODO: disable VGA need to use VGA request */
 565         /* BIOS*/
 566         if (!radeon_get_bios(rdev)) {
 567                 if (ASIC_IS_AVIVO(rdev))
 568                         return -EINVAL;
 569         }
 570         if (rdev->is_atom_bios) {
 571                 r = radeon_atombios_init(rdev);
 572                 if (r)
 573                         return r;
 574         } else {
 575                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 576                 return -EINVAL;
 577         }
 578         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 579         if (radeon_gpu_reset(rdev)) {
 580                 dev_warn(rdev->dev,
 581                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 582                         RREG32(R_000E40_RBBM_STATUS),
 583                         RREG32(R_0007C0_CP_STAT));
 584         }
 585         /* check if cards are posted or not */
 586         if (radeon_boot_test_post_card(rdev) == false)
 587                 return -EINVAL;
 588         /* Initialize clocks */
 589         radeon_get_clock_info(rdev->ddev);
 590         /* Initialize power management */
 591         radeon_pm_init(rdev);
 592         /* initialize AGP */
 593         if (rdev->flags & RADEON_IS_AGP) {
 594                 r = radeon_agp_init(rdev);
 595                 if (r) {
 596                         radeon_agp_disable(rdev);
 597                 }
 598         }
 599         /* initialize memory controller */
 600         rv515_mc_init(rdev);
 601         rv515_debugfs(rdev);
 602         /* Fence driver */
 603         r = radeon_fence_driver_init(rdev);
 604         if (r)
 605                 return r;
 606         r = radeon_irq_kms_init(rdev);
 607         if (r)
 608                 return r;
 609         /* Memory manager */
 610         r = radeon_bo_init(rdev);
 611         if (r)
 612                 return r;
 613         r = rv370_pcie_gart_init(rdev);
 614         if (r)
 615                 return r;
 616         rv515_set_safe_registers(rdev);
 617         rdev->accel_working = true;
 618         r = rv515_startup(rdev);
 619         if (r) {
 620                 /* Somethings want wront with the accel init stop accel */
 621                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 622                 r100_cp_fini(rdev);
 623                 r100_wb_fini(rdev);
 624                 r100_ib_fini(rdev);
 625                 radeon_irq_kms_fini(rdev);
 626                 rv370_pcie_gart_fini(rdev);
 627                 radeon_agp_fini(rdev);
 628                 rdev->accel_working = false;
 629         }
 630         return 0;
 631 }
 632
 633 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
 634 {
 635         int index_reg = 0x6578 + crtc->crtc_offset;
 636         int data_reg = 0x657c + crtc->crtc_offset;
 637
 638         WREG32(0x659C + crtc->crtc_offset, 0x0);
 639         WREG32(0x6594 + crtc->crtc_offset, 0x705);
 640         WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
 641         WREG32(0x65D8 + crtc->crtc_offset, 0x0);
 642         WREG32(0x65B0 + crtc->crtc_offset, 0x0);
 643         WREG32(0x65C0 + crtc->crtc_offset, 0x0);
 644         WREG32(0x65D4 + crtc->crtc_offset, 0x0);
 645         WREG32(index_reg, 0x0);
 646         WREG32(data_reg, 0x841880A8);
 647         WREG32(index_reg, 0x1);
 648         WREG32(data_reg, 0x84208680);
 649         WREG32(index_reg, 0x2);
 650         WREG32(data_reg, 0xBFF880B0);
 651         WREG32(index_reg, 0x100);
 652         WREG32(data_reg, 0x83D88088);
 653         WREG32(index_reg, 0x101);
 654         WREG32(data_reg, 0x84608680);
 655         WREG32(index_reg, 0x102);
 656         WREG32(data_reg, 0xBFF080D0);
 657         WREG32(index_reg, 0x200);
 658         WREG32(data_reg, 0x83988068);
 659         WREG32(index_reg, 0x201);
 660         WREG32(data_reg, 0x84A08680);
 661         WREG32(index_reg, 0x202);
 662         WREG32(data_reg, 0xBFF080F8);
 663         WREG32(index_reg, 0x300);
 664         WREG32(data_reg, 0x83588058);
 665         WREG32(index_reg, 0x301);
 666         WREG32(data_reg, 0x84E08660);
 667         WREG32(index_reg, 0x302);
 668         WREG32(data_reg, 0xBFF88120);
 669         WREG32(index_reg, 0x400);
 670         WREG32(data_reg, 0x83188040);
 671         WREG32(index_reg, 0x401);
 672         WREG32(data_reg, 0x85008660);
 673         WREG32(index_reg, 0x402);
 674         WREG32(data_reg, 0xBFF88150);
 675         WREG32(index_reg, 0x500);
 676         WREG32(data_reg, 0x82D88030);
 677         WREG32(index_reg, 0x501);
 678         WREG32(data_reg, 0x85408640);
 679         WREG32(index_reg, 0x502);
 680         WREG32(data_reg, 0xBFF88180);
 681         WREG32(index_reg, 0x600);
 682         WREG32(data_reg, 0x82A08018);
 683         WREG32(index_reg, 0x601);
 684         WREG32(data_reg, 0x85808620);
 685         WREG32(index_reg, 0x602);
 686         WREG32(data_reg, 0xBFF081B8);
 687         WREG32(index_reg, 0x700);
 688         WREG32(data_reg, 0x82608010);
 689         WREG32(index_reg, 0x701);
 690         WREG32(data_reg, 0x85A08600);
 691         WREG32(index_reg, 0x702);
 692         WREG32(data_reg, 0x800081F0);
 693         WREG32(index_reg, 0x800);
 694         WREG32(data_reg, 0x8228BFF8);
 695         WREG32(index_reg, 0x801);
 696         WREG32(data_reg, 0x85E085E0);
 697         WREG32(index_reg, 0x802);
 698         WREG32(data_reg, 0xBFF88228);
 699         WREG32(index_reg, 0x10000);
 700         WREG32(data_reg, 0x82A8BF00);
 701         WREG32(index_reg, 0x10001);
 702         WREG32(data_reg, 0x82A08CC0);
 703         WREG32(index_reg, 0x10002);
 704         WREG32(data_reg, 0x8008BEF8);
 705         WREG32(index_reg, 0x10100);
 706         WREG32(data_reg, 0x81F0BF28);
 707         WREG32(index_reg, 0x10101);
 708         WREG32(data_reg, 0x83608CA0);
 709         WREG32(index_reg, 0x10102);
 710         WREG32(data_reg, 0x8018BED0);
 711         WREG32(index_reg, 0x10200);
 712         WREG32(data_reg, 0x8148BF38);
 713         WREG32(index_reg, 0x10201);
 714         WREG32(data_reg, 0x84408C80);
 715         WREG32(index_reg, 0x10202);
 716         WREG32(data_reg, 0x8008BEB8);
 717         WREG32(index_reg, 0x10300);
 718         WREG32(data_reg, 0x80B0BF78);
 719         WREG32(index_reg, 0x10301);
 720         WREG32(data_reg, 0x85008C20);
 721         WREG32(index_reg, 0x10302);
 722         WREG32(data_reg, 0x8020BEA0);
 723         WREG32(index_reg, 0x10400);
 724         WREG32(data_reg, 0x8028BF90);
 725         WREG32(index_reg, 0x10401);
 726         WREG32(data_reg, 0x85E08BC0);
 727         WREG32(index_reg, 0x10402);
 728         WREG32(data_reg, 0x8018BE90);
 729         WREG32(index_reg, 0x10500);
 730         WREG32(data_reg, 0xBFB8BFB0);
 731         WREG32(index_reg, 0x10501);
 732         WREG32(data_reg, 0x86C08B40);
 733         WREG32(index_reg, 0x10502);
 734         WREG32(data_reg, 0x8010BE90);
 735         WREG32(index_reg, 0x10600);
 736         WREG32(data_reg, 0xBF58BFC8);
 737         WREG32(index_reg, 0x10601);
 738         WREG32(data_reg, 0x87A08AA0);
 739         WREG32(index_reg, 0x10602);
 740         WREG32(data_reg, 0x8010BE98);
 741         WREG32(index_reg, 0x10700);
 742         WREG32(data_reg, 0xBF10BFF0);
 743         WREG32(index_reg, 0x10701);
 744         WREG32(data_reg, 0x886089E0);
 745         WREG32(index_reg, 0x10702);
 746         WREG32(data_reg, 0x8018BEB0);
 747         WREG32(index_reg, 0x10800);
 748         WREG32(data_reg, 0xBED8BFE8);
 749         WREG32(index_reg, 0x10801);
 750         WREG32(data_reg, 0x89408940);
 751         WREG32(index_reg, 0x10802);
 752         WREG32(data_reg, 0xBFE8BED8);
 753         WREG32(index_reg, 0x20000);
 754         WREG32(data_reg, 0x80008000);
 755         WREG32(index_reg, 0x20001);
 756         WREG32(data_reg, 0x90008000);
 757         WREG32(index_reg, 0x20002);
 758         WREG32(data_reg, 0x80008000);
 759         WREG32(index_reg, 0x20003);
 760         WREG32(data_reg, 0x80008000);
 761         WREG32(index_reg, 0x20100);
 762         WREG32(data_reg, 0x80108000);
 763         WREG32(index_reg, 0x20101);
 764         WREG32(data_reg, 0x8FE0BF70);
 765         WREG32(index_reg, 0x20102);
 766         WREG32(data_reg, 0xBFE880C0);
 767         WREG32(index_reg, 0x20103);
 768         WREG32(data_reg, 0x80008000);
 769         WREG32(index_reg, 0x20200);
 770         WREG32(data_reg, 0x8018BFF8);
 771         WREG32(index_reg, 0x20201);
 772         WREG32(data_reg, 0x8F80BF08);
 773         WREG32(index_reg, 0x20202);
 774         WREG32(data_reg, 0xBFD081A0);
 775         WREG32(index_reg, 0x20203);
 776         WREG32(data_reg, 0xBFF88000);
 777         WREG32(index_reg, 0x20300);
 778         WREG32(data_reg, 0x80188000);
 779         WREG32(index_reg, 0x20301);
 780         WREG32(data_reg, 0x8EE0BEC0);
 781         WREG32(index_reg, 0x20302);
 782         WREG32(data_reg, 0xBFB082A0);
 783         WREG32(index_reg, 0x20303);
 784         WREG32(data_reg, 0x80008000);
 785         WREG32(index_reg, 0x20400);
 786         WREG32(data_reg, 0x80188000);
 787         WREG32(index_reg, 0x20401);
 788         WREG32(data_reg, 0x8E00BEA0);
 789         WREG32(index_reg, 0x20402);
 790         WREG32(data_reg, 0xBF8883C0);
 791         WREG32(index_reg, 0x20403);
 792         WREG32(data_reg, 0x80008000);
 793         WREG32(index_reg, 0x20500);
 794         WREG32(data_reg, 0x80188000);
 795         WREG32(index_reg, 0x20501);
 796         WREG32(data_reg, 0x8D00BE90);
 797         WREG32(index_reg, 0x20502);
 798         WREG32(data_reg, 0xBF588500);
 799         WREG32(index_reg, 0x20503);
 800         WREG32(data_reg, 0x80008008);
 801         WREG32(index_reg, 0x20600);
 802         WREG32(data_reg, 0x80188000);
 803         WREG32(index_reg, 0x20601);
 804         WREG32(data_reg, 0x8BC0BE98);
 805         WREG32(index_reg, 0x20602);
 806         WREG32(data_reg, 0xBF308660);
 807         WREG32(index_reg, 0x20603);
 808         WREG32(data_reg, 0x80008008);
 809         WREG32(index_reg, 0x20700);
 810         WREG32(data_reg, 0x80108000);
 811         WREG32(index_reg, 0x20701);
 812         WREG32(data_reg, 0x8A80BEB0);
 813         WREG32(index_reg, 0x20702);
 814         WREG32(data_reg, 0xBF0087C0);
 815         WREG32(index_reg, 0x20703);
 816         WREG32(data_reg, 0x80008008);
 817         WREG32(index_reg, 0x20800);
 818         WREG32(data_reg, 0x80108000);
 819         WREG32(index_reg, 0x20801);
 820         WREG32(data_reg, 0x8920BED0);
 821         WREG32(index_reg, 0x20802);
 822         WREG32(data_reg, 0xBED08920);
 823         WREG32(index_reg, 0x20803);
 824         WREG32(data_reg, 0x80008010);
 825         WREG32(index_reg, 0x30000);
 826         WREG32(data_reg, 0x90008000);
 827         WREG32(index_reg, 0x30001);
 828         WREG32(data_reg, 0x80008000);
 829         WREG32(index_reg, 0x30100);
 830         WREG32(data_reg, 0x8FE0BF90);
 831         WREG32(index_reg, 0x30101);
 832         WREG32(data_reg, 0xBFF880A0);
 833         WREG32(index_reg, 0x30200);
 834         WREG32(data_reg, 0x8F60BF40);
 835         WREG32(index_reg, 0x30201);
 836         WREG32(data_reg, 0xBFE88180);
 837         WREG32(index_reg, 0x30300);
 838         WREG32(data_reg, 0x8EC0BF00);
 839         WREG32(index_reg, 0x30301);
 840         WREG32(data_reg, 0xBFC88280);
 841         WREG32(index_reg, 0x30400);
 842         WREG32(data_reg, 0x8DE0BEE0);
 843         WREG32(index_reg, 0x30401);
 844         WREG32(data_reg, 0xBFA083A0);
 845         WREG32(index_reg, 0x30500);
 846         WREG32(data_reg, 0x8CE0BED0);
 847         WREG32(index_reg, 0x30501);
 848         WREG32(data_reg, 0xBF7884E0);
 849         WREG32(index_reg, 0x30600);
 850         WREG32(data_reg, 0x8BA0BED8);
 851         WREG32(index_reg, 0x30601);
 852         WREG32(data_reg, 0xBF508640);
 853         WREG32(index_reg, 0x30700);
 854         WREG32(data_reg, 0x8A60BEE8);
 855         WREG32(index_reg, 0x30701);
 856         WREG32(data_reg, 0xBF2087A0);
 857         WREG32(index_reg, 0x30800);
 858         WREG32(data_reg, 0x8900BF00);
 859         WREG32(index_reg, 0x30801);
 860         WREG32(data_reg, 0xBF008900);
 861 }
 862
 863 struct rv515_watermark {
 864         u32        lb_request_fifo_depth;
 865         fixed20_12 num_line_pair;
 866         fixed20_12 estimated_width;
 867         fixed20_12 worst_case_latency;
 868         fixed20_12 consumption_rate;
 869         fixed20_12 active_time;
 870         fixed20_12 dbpp;
 871         fixed20_12 priority_mark_max;
 872         fixed20_12 priority_mark;
 873         fixed20_12 sclk;
 874 };
 875
 876 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 877                                   struct radeon_crtc *crtc,
 878                                   struct rv515_watermark *wm)
 879 {
 880         struct drm_display_mode *mode = &crtc->base.mode;
 881         fixed20_12 a, b, c;
 882         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 883         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 884
 885         if (!crtc->base.enabled) {
 886                 /* FIXME: wouldn't it better to set priority mark to maximum */
 887                 wm->lb_request_fifo_depth = 4;
 888                 return;
 889         }
 890
 891         if (crtc->vsc.full > rfixed_const(2))
 892                 wm->num_line_pair.full = rfixed_const(2);
 893         else
 894                 wm->num_line_pair.full = rfixed_const(1);
 895
 896         b.full = rfixed_const(mode->crtc_hdisplay);
 897         c.full = rfixed_const(256);
 898         a.full = rfixed_div(b, c);
 899         request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
 900         request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
 901         if (a.full < rfixed_const(4)) {
 902                 wm->lb_request_fifo_depth = 4;
 903         } else {
 904                 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
 905         }
 906
 907         /* Determine consumption rate
 908          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 909          *  vtaps = number of vertical taps,
 910          *  vsc = vertical scaling ratio, defined as source/destination
 911          *  hsc = horizontal scaling ration, defined as source/destination
 912          */
 913         a.full = rfixed_const(mode->clock);
 914         b.full = rfixed_const(1000);
 915         a.full = rfixed_div(a, b);
 916         pclk.full = rfixed_div(b, a);
 917         if (crtc->rmx_type != RMX_OFF) {
 918                 b.full = rfixed_const(2);
 919                 if (crtc->vsc.full > b.full)
 920                         b.full = crtc->vsc.full;
 921                 b.full = rfixed_mul(b, crtc->hsc);
 922                 c.full = rfixed_const(2);
 923                 b.full = rfixed_div(b, c);
 924                 consumption_time.full = rfixed_div(pclk, b);
 925         } else {
 926                 consumption_time.full = pclk.full;
 927         }
 928         a.full = rfixed_const(1);
 929         wm->consumption_rate.full = rfixed_div(a, consumption_time);
 930
 931
 932         /* Determine line time
 933          *  LineTime = total time for one line of displayhtotal
 934          *  LineTime = total number of horizontal pixels
 935          *  pclk = pixel clock period(ns)
 936          */
 937         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 938         line_time.full = rfixed_mul(a, pclk);
 939
 940         /* Determine active time
 941          *  ActiveTime = time of active region of display within one line,
 942          *  hactive = total number of horizontal active pixels
 943          *  htotal = total number of horizontal pixels
 944          */
 945         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 946         b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 947         wm->active_time.full = rfixed_mul(line_time, b);
 948         wm->active_time.full = rfixed_div(wm->active_time, a);
 949
 950         /* Determine chunk time
 951          * ChunkTime = the time it takes the DCP to send one chunk of data
 952          * to the LB which consists of pipeline delay and inter chunk gap
 953          * sclk = system clock(Mhz)
 954          */
 955         a.full = rfixed_const(600 * 1000);
 956         chunk_time.full = rfixed_div(a, rdev->pm.sclk);
 957         read_delay_latency.full = rfixed_const(1000);
 958
 959         /* Determine the worst case latency
 960          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 961          * WorstCaseLatency = worst case time from urgent to when the MC starts
 962          *                    to return data
 963          * READ_DELAY_IDLE_MAX = constant of 1us
 964          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 965          *             which consists of pipeline delay and inter chunk gap
 966          */
 967         if (rfixed_trunc(wm->num_line_pair) > 1) {
 968                 a.full = rfixed_const(3);
 969                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 970                 wm->worst_case_latency.full += read_delay_latency.full;
 971         } else {
 972                 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
 973         }
 974
 975         /* Determine the tolerable latency
 976          * TolerableLatency = Any given request has only 1 line time
 977          *                    for the data to be returned
 978          * LBRequestFifoDepth = Number of chunk requests the LB can
 979          *                      put into the request FIFO for a display
 980          *  LineTime = total time for one line of display
 981          *  ChunkTime = the time it takes the DCP to send one chunk
 982          *              of data to the LB which consists of
 983          *  pipeline delay and inter chunk gap
 984          */
 985         if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
 986                 tolerable_latency.full = line_time.full;
 987         } else {
 988                 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
 989                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 990                 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
 991                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 992         }
 993         /* We assume worst case 32bits (4 bytes) */
 994         wm->dbpp.full = rfixed_const(2 * 16);
 995
 996         /* Determine the maximum priority mark
 997          *  width = viewport width in pixels
 998          */
 999         a.full = rfixed_const(16);
1000         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
1001         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
1002         wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
1003
1004         /* Determine estimated width */
1005         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1006         estimated_width.full = rfixed_div(estimated_width, consumption_time);
1007         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1008                 wm->priority_mark.full = wm->priority_mark_max.full;
1009         } else {
1010                 a.full = rfixed_const(16);
1011                 wm->priority_mark.full = rfixed_div(estimated_width, a);
1012                 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
1013                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1014         }
1015 }
1016
1017 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1018 {
1019         struct drm_display_mode *mode0 = NULL;
1020         struct drm_display_mode *mode1 = NULL;
1021         struct rv515_watermark wm0;
1022         struct rv515_watermark wm1;
1023         u32 tmp;
1024         fixed20_12 priority_mark02, priority_mark12, fill_rate;
1025         fixed20_12 a, b;
1026
1027         if (rdev->mode_info.crtcs[0]->base.enabled)
1028                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1029         if (rdev->mode_info.crtcs[1]->base.enabled)
1030                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1031         rs690_line_buffer_adjust(rdev, mode0, mode1);
1032
1033         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
1034         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
1035
1036         tmp = wm0.lb_request_fifo_depth;
1037         tmp |= wm1.lb_request_fifo_depth << 16;
1038         WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1039
1040         if (mode0 && mode1) {
1041                 if (rfixed_trunc(wm0.dbpp) > 64)
1042                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1043                 else
1044                         a.full = wm0.num_line_pair.full;
1045                 if (rfixed_trunc(wm1.dbpp) > 64)
1046                         b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1047                 else
1048                         b.full = wm1.num_line_pair.full;
1049                 a.full += b.full;
1050                 fill_rate.full = rfixed_div(wm0.sclk, a);
1051                 if (wm0.consumption_rate.full > fill_rate.full) {
1052                         b.full = wm0.consumption_rate.full - fill_rate.full;
1053                         b.full = rfixed_mul(b, wm0.active_time);
1054                         a.full = rfixed_const(16);
1055                         b.full = rfixed_div(b, a);
1056                         a.full = rfixed_mul(wm0.worst_case_latency,
1057                                                 wm0.consumption_rate);
1058                         priority_mark02.full = a.full + b.full;
1059                 } else {
1060                         a.full = rfixed_mul(wm0.worst_case_latency,
1061                                                 wm0.consumption_rate);
1062                         b.full = rfixed_const(16 * 1000);
1063                         priority_mark02.full = rfixed_div(a, b);
1064                 }
1065                 if (wm1.consumption_rate.full > fill_rate.full) {
1066                         b.full = wm1.consumption_rate.full - fill_rate.full;
1067                         b.full = rfixed_mul(b, wm1.active_time);
1068                         a.full = rfixed_const(16);
1069                         b.full = rfixed_div(b, a);
1070                         a.full = rfixed_mul(wm1.worst_case_latency,
1071                                                 wm1.consumption_rate);
1072                         priority_mark12.full = a.full + b.full;
1073                 } else {
1074                         a.full = rfixed_mul(wm1.worst_case_latency,
1075                                                 wm1.consumption_rate);
1076                         b.full = rfixed_const(16 * 1000);
1077                         priority_mark12.full = rfixed_div(a, b);
1078                 }
1079                 if (wm0.priority_mark.full > priority_mark02.full)
1080                         priority_mark02.full = wm0.priority_mark.full;
1081                 if (rfixed_trunc(priority_mark02) < 0)
1082                         priority_mark02.full = 0;
1083                 if (wm0.priority_mark_max.full > priority_mark02.full)
1084                         priority_mark02.full = wm0.priority_mark_max.full;
1085                 if (wm1.priority_mark.full > priority_mark12.full)
1086                         priority_mark12.full = wm1.priority_mark.full;
1087                 if (rfixed_trunc(priority_mark12) < 0)
1088                         priority_mark12.full = 0;
1089                 if (wm1.priority_mark_max.full > priority_mark12.full)
1090                         priority_mark12.full = wm1.priority_mark_max.full;
1091                 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1092                 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1093                 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1094                 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1095         } else if (mode0) {
1096                 if (rfixed_trunc(wm0.dbpp) > 64)
1097                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1098                 else
1099                         a.full = wm0.num_line_pair.full;
1100                 fill_rate.full = rfixed_div(wm0.sclk, a);
1101                 if (wm0.consumption_rate.full > fill_rate.full) {
1102                         b.full = wm0.consumption_rate.full - fill_rate.full;
1103                         b.full = rfixed_mul(b, wm0.active_time);
1104                         a.full = rfixed_const(16);
1105                         b.full = rfixed_div(b, a);
1106                         a.full = rfixed_mul(wm0.worst_case_latency,
1107                                                 wm0.consumption_rate);
1108                         priority_mark02.full = a.full + b.full;
1109                 } else {
1110                         a.full = rfixed_mul(wm0.worst_case_latency,
1111                                                 wm0.consumption_rate);
1112                         b.full = rfixed_const(16);
1113                         priority_mark02.full = rfixed_div(a, b);
1114                 }
1115                 if (wm0.priority_mark.full > priority_mark02.full)
1116                         priority_mark02.full = wm0.priority_mark.full;
1117                 if (rfixed_trunc(priority_mark02) < 0)
1118                         priority_mark02.full = 0;
1119                 if (wm0.priority_mark_max.full > priority_mark02.full)
1120                         priority_mark02.full = wm0.priority_mark_max.full;
1121                 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1122                 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1123                 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1124                 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1125         } else {
1126                 if (rfixed_trunc(wm1.dbpp) > 64)
1127                         a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1128                 else
1129                         a.full = wm1.num_line_pair.full;
1130                 fill_rate.full = rfixed_div(wm1.sclk, a);
1131                 if (wm1.consumption_rate.full > fill_rate.full) {
1132                         b.full = wm1.consumption_rate.full - fill_rate.full;
1133                         b.full = rfixed_mul(b, wm1.active_time);
1134                         a.full = rfixed_const(16);
1135                         b.full = rfixed_div(b, a);
1136                         a.full = rfixed_mul(wm1.worst_case_latency,
1137                                                 wm1.consumption_rate);
1138                         priority_mark12.full = a.full + b.full;
1139                 } else {
1140                         a.full = rfixed_mul(wm1.worst_case_latency,
1141                                                 wm1.consumption_rate);
1142                         b.full = rfixed_const(16 * 1000);
1143                         priority_mark12.full = rfixed_div(a, b);
1144                 }
1145                 if (wm1.priority_mark.full > priority_mark12.full)
1146                         priority_mark12.full = wm1.priority_mark.full;
1147                 if (rfixed_trunc(priority_mark12) < 0)
1148                         priority_mark12.full = 0;
1149                 if (wm1.priority_mark_max.full > priority_mark12.full)
1150                         priority_mark12.full = wm1.priority_mark_max.full;
1151                 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1152                 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1153                 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1154                 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1155         }
1156 }
1157
1158 void rv515_bandwidth_update(struct radeon_device *rdev)
1159 {
1160         uint32_t tmp;
1161         struct drm_display_mode *mode0 = NULL;
1162         struct drm_display_mode *mode1 = NULL;
1163
1164         if (rdev->mode_info.crtcs[0]->base.enabled)
1165                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1166         if (rdev->mode_info.crtcs[1]->base.enabled)
1167                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1168         /*
1169          * Set display0/1 priority up in the memory controller for
1170          * modes if the user specifies HIGH for displaypriority
1171          * option.
1172          */
1173         if (rdev->disp_priority == 2) {
1174                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1175                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1176                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1177                 if (mode1)
1178                         tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1179                 if (mode0)
1180                         tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1181                 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1182         }
1183         rv515_bandwidth_avivo_update(rdev);
1184 }