SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/rv515.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "rv515d.h"
  31 #include "radeon.h"
  32
  33 #include "rv515_reg_safe.h"
  34 /* rv515 depends on : */
  35 void r100_hdp_reset(struct radeon_device *rdev);
  36 int r100_cp_reset(struct radeon_device *rdev);
  37 int r100_rb2d_reset(struct radeon_device *rdev);
  38 int r100_gui_wait_for_idle(struct radeon_device *rdev);
  39 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  40 int rv370_pcie_gart_enable(struct radeon_device *rdev);
  41 void rv370_pcie_gart_disable(struct radeon_device *rdev);
  42 void r420_pipes_init(struct radeon_device *rdev);
  43 void rs600_mc_disable_clients(struct radeon_device *rdev);
  44 void rs600_disable_vga(struct radeon_device *rdev);
  45
  46 /* This files gather functions specifics to:
  47  * rv515
  48  *
  49  * Some of these functions might be used by newer ASICs.
  50  */
  51 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  52 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  53 void rv515_gpu_init(struct radeon_device *rdev);
  54 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  55
  56
  57 /*
  58  * MC
  59  */
  60 int rv515_mc_init(struct radeon_device *rdev)
  61 {
  62         uint32_t tmp;
  63         int r;
  64
  65         if (r100_debugfs_rbbm_init(rdev)) {
  66                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  67         }
  68         if (rv515_debugfs_pipes_info_init(rdev)) {
  69                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  70         }
  71         if (rv515_debugfs_ga_info_init(rdev)) {
  72                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  73         }
  74
  75         rv515_gpu_init(rdev);
  76         rv370_pcie_gart_disable(rdev);
  77
  78         /* Setup GPU memory space */
  79         rdev->mc.vram_location = 0xFFFFFFFFUL;
  80         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  81         if (rdev->flags & RADEON_IS_AGP) {
  82                 r = radeon_agp_init(rdev);
  83                 if (r) {
  84                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  85                         rdev->flags &= ~RADEON_IS_AGP;
  86                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  87                 } else {
  88                         rdev->mc.gtt_location = rdev->mc.agp_base;
  89                 }
  90         }
  91         r = radeon_mc_setup(rdev);
  92         if (r) {
  93                 return r;
  94         }
  95
  96         /* Program GPU memory space */
  97         rs600_mc_disable_clients(rdev);
  98         if (rv515_mc_wait_for_idle(rdev)) {
  99                 printk(KERN_WARNING "Failed to wait MC idle while "
 100                        "programming pipes. Bad things might happen.\n");
 101         }
 102         /* Write VRAM size in case we are limiting it */
 103         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 104         tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
 105         WREG32(0x134, tmp);
 106         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 107         tmp = REG_SET(MC_FB_TOP, tmp >> 16);
 108         tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
 109         WREG32_MC(MC_FB_LOCATION, tmp);
 110         WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
 111         WREG32(0x310, rdev->mc.vram_location);
 112         if (rdev->flags & RADEON_IS_AGP) {
 113                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 114                 tmp = REG_SET(MC_AGP_TOP, tmp >> 16);
 115                 tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16);
 116                 WREG32_MC(MC_AGP_LOCATION, tmp);
 117                 WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base);
 118                 WREG32_MC(MC_AGP_BASE_2, 0);
 119         } else {
 120                 WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF);
 121                 WREG32_MC(MC_AGP_BASE, 0);
 122                 WREG32_MC(MC_AGP_BASE_2, 0);
 123         }
 124         return 0;
 125 }
 126
 127 void rv515_mc_fini(struct radeon_device *rdev)
 128 {
 129         rv370_pcie_gart_disable(rdev);
 130         radeon_gart_table_vram_free(rdev);
 131         radeon_gart_fini(rdev);
 132 }
 133
 134
 135 /*
 136  * Global GPU functions
 137  */
 138 void rv515_ring_start(struct radeon_device *rdev)
 139 {
 140         int r;
 141
 142         r = radeon_ring_lock(rdev, 64);
 143         if (r) {
 144                 return;
 145         }
 146         radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
 147         radeon_ring_write(rdev,
 148                           ISYNC_ANY2D_IDLE3D |
 149                           ISYNC_ANY3D_IDLE2D |
 150                           ISYNC_WAIT_IDLEGUI |
 151                           ISYNC_CPSCRATCH_IDLEGUI);
 152         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
 153         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
 154         radeon_ring_write(rdev, PACKET0(0x170C, 0));
 155         radeon_ring_write(rdev, 1 << 31);
 156         radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
 157         radeon_ring_write(rdev, 0);
 158         radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
 159         radeon_ring_write(rdev, 0);
 160         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
 161         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
 162         radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
 163         radeon_ring_write(rdev, 0);
 164         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
 165         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
 166         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
 167         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
 168         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
 169         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
 170         radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
 171         radeon_ring_write(rdev, 0);
 172         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
 173         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
 174         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
 175         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
 176         radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
 177         radeon_ring_write(rdev,
 178                           ((6 << MS_X0_SHIFT) |
 179                            (6 << MS_Y0_SHIFT) |
 180                            (6 << MS_X1_SHIFT) |
 181                            (6 << MS_Y1_SHIFT) |
 182                            (6 << MS_X2_SHIFT) |
 183                            (6 << MS_Y2_SHIFT) |
 184                            (6 << MSBD0_Y_SHIFT) |
 185                            (6 << MSBD0_X_SHIFT)));
 186         radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
 187         radeon_ring_write(rdev,
 188                           ((6 << MS_X3_SHIFT) |
 189                            (6 << MS_Y3_SHIFT) |
 190                            (6 << MS_X4_SHIFT) |
 191                            (6 << MS_Y4_SHIFT) |
 192                            (6 << MS_X5_SHIFT) |
 193                            (6 << MS_Y5_SHIFT) |
 194                            (6 << MSBD1_SHIFT)));
 195         radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
 196         radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
 197         radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
 198         radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
 199         radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
 200         radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
 201         radeon_ring_write(rdev, PACKET0(0x20C8, 0));
 202         radeon_ring_write(rdev, 0);
 203         radeon_ring_unlock_commit(rdev);
 204 }
 205
 206 void rv515_errata(struct radeon_device *rdev)
 207 {
 208         rdev->pll_errata = 0;
 209 }
 210
 211 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
 212 {
 213         unsigned i;
 214         uint32_t tmp;
 215
 216         for (i = 0; i < rdev->usec_timeout; i++) {
 217                 /* read MC_STATUS */
 218                 tmp = RREG32_MC(MC_STATUS);
 219                 if (tmp & MC_STATUS_IDLE) {
 220                         return 0;
 221                 }
 222                 DRM_UDELAY(1);
 223         }
 224         return -1;
 225 }
 226
 227 void rv515_gpu_init(struct radeon_device *rdev)
 228 {
 229         unsigned pipe_select_current, gb_pipe_select, tmp;
 230
 231         r100_hdp_reset(rdev);
 232         r100_rb2d_reset(rdev);
 233
 234         if (r100_gui_wait_for_idle(rdev)) {
 235                 printk(KERN_WARNING "Failed to wait GUI idle while "
 236                        "reseting GPU. Bad things might happen.\n");
 237         }
 238
 239         rs600_disable_vga(rdev);
 240
 241         r420_pipes_init(rdev);
 242         gb_pipe_select = RREG32(0x402C);
 243         tmp = RREG32(0x170C);
 244         pipe_select_current = (tmp >> 2) & 3;
 245         tmp = (1 << pipe_select_current) |
 246               (((gb_pipe_select >> 8) & 0xF) << 4);
 247         WREG32_PLL(0x000D, tmp);
 248         if (r100_gui_wait_for_idle(rdev)) {
 249                 printk(KERN_WARNING "Failed to wait GUI idle while "
 250                        "reseting GPU. Bad things might happen.\n");
 251         }
 252         if (rv515_mc_wait_for_idle(rdev)) {
 253                 printk(KERN_WARNING "Failed to wait MC idle while "
 254                        "programming pipes. Bad things might happen.\n");
 255         }
 256 }
 257
 258 int rv515_ga_reset(struct radeon_device *rdev)
 259 {
 260         uint32_t tmp;
 261         bool reinit_cp;
 262         int i;
 263
 264         reinit_cp = rdev->cp.ready;
 265         rdev->cp.ready = false;
 266         for (i = 0; i < rdev->usec_timeout; i++) {
 267                 WREG32(CP_CSQ_MODE, 0);
 268                 WREG32(CP_CSQ_CNTL, 0);
 269                 WREG32(RBBM_SOFT_RESET, 0x32005);
 270                 (void)RREG32(RBBM_SOFT_RESET);
 271                 udelay(200);
 272                 WREG32(RBBM_SOFT_RESET, 0);
 273                 /* Wait to prevent race in RBBM_STATUS */
 274                 mdelay(1);
 275                 tmp = RREG32(RBBM_STATUS);
 276                 if (tmp & ((1 << 20) | (1 << 26))) {
 277                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
 278                         /* GA still busy soft reset it */
 279                         WREG32(0x429C, 0x200);
 280                         WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
 281                         WREG32(0x43E0, 0);
 282                         WREG32(0x43E4, 0);
 283                         WREG32(0x24AC, 0);
 284                 }
 285                 /* Wait to prevent race in RBBM_STATUS */
 286                 mdelay(1);
 287                 tmp = RREG32(RBBM_STATUS);
 288                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 289                         break;
 290                 }
 291         }
 292         for (i = 0; i < rdev->usec_timeout; i++) {
 293                 tmp = RREG32(RBBM_STATUS);
 294                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 295                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
 296                                  tmp);
 297                         DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
 298                         DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
 299                         DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
 300                         if (reinit_cp) {
 301                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 302                         }
 303                         return 0;
 304                 }
 305                 DRM_UDELAY(1);
 306         }
 307         tmp = RREG32(RBBM_STATUS);
 308         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
 309         return -1;
 310 }
 311
 312 int rv515_gpu_reset(struct radeon_device *rdev)
 313 {
 314         uint32_t status;
 315
 316         /* reset order likely matter */
 317         status = RREG32(RBBM_STATUS);
 318         /* reset HDP */
 319         r100_hdp_reset(rdev);
 320         /* reset rb2d */
 321         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
 322                 r100_rb2d_reset(rdev);
 323         }
 324         /* reset GA */
 325         if (status & ((1 << 20) | (1 << 26))) {
 326                 rv515_ga_reset(rdev);
 327         }
 328         /* reset CP */
 329         status = RREG32(RBBM_STATUS);
 330         if (status & (1 << 16)) {
 331                 r100_cp_reset(rdev);
 332         }
 333         /* Check if GPU is idle */
 334         status = RREG32(RBBM_STATUS);
 335         if (status & (1 << 31)) {
 336                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
 337                 return -1;
 338         }
 339         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
 340         return 0;
 341 }
 342
 343
 344 /*
 345  * VRAM info
 346  */
 347 static void rv515_vram_get_type(struct radeon_device *rdev)
 348 {
 349         uint32_t tmp;
 350
 351         rdev->mc.vram_width = 128;
 352         rdev->mc.vram_is_ddr = true;
 353         tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
 354         switch (tmp) {
 355         case 0:
 356                 rdev->mc.vram_width = 64;
 357                 break;
 358         case 1:
 359                 rdev->mc.vram_width = 128;
 360                 break;
 361         default:
 362                 rdev->mc.vram_width = 128;
 363                 break;
 364         }
 365 }
 366
 367 void rv515_vram_info(struct radeon_device *rdev)
 368 {
 369         fixed20_12 a;
 370
 371         rv515_vram_get_type(rdev);
 372
 373         r100_vram_init_sizes(rdev);
 374         /* FIXME: we should enforce default clock in case GPU is not in
 375          * default setup
 376          */
 377         a.full = rfixed_const(100);
 378         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 379         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 380 }
 381
 382
 383 /*
 384  * Indirect registers accessor
 385  */
 386 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 387 {
 388         uint32_t r;
 389
 390         WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
 391         r = RREG32(MC_IND_DATA);
 392         WREG32(MC_IND_INDEX, 0);
 393         return r;
 394 }
 395
 396 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 397 {
 398         WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
 399         WREG32(MC_IND_DATA, (v));
 400         WREG32(MC_IND_INDEX, 0);
 401 }
 402
 403 /*
 404  * Debugfs info
 405  */
 406 #if defined(CONFIG_DEBUG_FS)
 407 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
 408 {
 409         struct drm_info_node *node = (struct drm_info_node *) m->private;
 410         struct drm_device *dev = node->minor->dev;
 411         struct radeon_device *rdev = dev->dev_private;
 412         uint32_t tmp;
 413
 414         tmp = RREG32(GB_PIPE_SELECT);
 415         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 416         tmp = RREG32(SU_REG_DEST);
 417         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
 418         tmp = RREG32(GB_TILE_CONFIG);
 419         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 420         tmp = RREG32(DST_PIPE_CONFIG);
 421         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 422         return 0;
 423 }
 424
 425 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 426 {
 427         struct drm_info_node *node = (struct drm_info_node *) m->private;
 428         struct drm_device *dev = node->minor->dev;
 429         struct radeon_device *rdev = dev->dev_private;
 430         uint32_t tmp;
 431
 432         tmp = RREG32(0x2140);
 433         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
 434         radeon_gpu_reset(rdev);
 435         tmp = RREG32(0x425C);
 436         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
 437         return 0;
 438 }
 439
 440 static struct drm_info_list rv515_pipes_info_list[] = {
 441         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
 442 };
 443
 444 static struct drm_info_list rv515_ga_info_list[] = {
 445         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
 446 };
 447 #endif
 448
 449 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
 450 {
 451 #if defined(CONFIG_DEBUG_FS)
 452         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
 453 #else
 454         return 0;
 455 #endif
 456 }
 457
 458 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
 459 {
 460 #if defined(CONFIG_DEBUG_FS)
 461         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
 462 #else
 463         return 0;
 464 #endif
 465 }
 466
 467 /*
 468  * Asic initialization
 469  */
 470 int rv515_init(struct radeon_device *rdev)
 471 {
 472         rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
 473         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
 474         return 0;
 475 }
 476
 477 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
 478 {
 479         int index_reg = 0x6578 + crtc->crtc_offset;
 480         int data_reg = 0x657c + crtc->crtc_offset;
 481
 482         WREG32(0x659C + crtc->crtc_offset, 0x0);
 483         WREG32(0x6594 + crtc->crtc_offset, 0x705);
 484         WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
 485         WREG32(0x65D8 + crtc->crtc_offset, 0x0);
 486         WREG32(0x65B0 + crtc->crtc_offset, 0x0);
 487         WREG32(0x65C0 + crtc->crtc_offset, 0x0);
 488         WREG32(0x65D4 + crtc->crtc_offset, 0x0);
 489         WREG32(index_reg, 0x0);
 490         WREG32(data_reg, 0x841880A8);
 491         WREG32(index_reg, 0x1);
 492         WREG32(data_reg, 0x84208680);
 493         WREG32(index_reg, 0x2);
 494         WREG32(data_reg, 0xBFF880B0);
 495         WREG32(index_reg, 0x100);
 496         WREG32(data_reg, 0x83D88088);
 497         WREG32(index_reg, 0x101);
 498         WREG32(data_reg, 0x84608680);
 499         WREG32(index_reg, 0x102);
 500         WREG32(data_reg, 0xBFF080D0);
 501         WREG32(index_reg, 0x200);
 502         WREG32(data_reg, 0x83988068);
 503         WREG32(index_reg, 0x201);
 504         WREG32(data_reg, 0x84A08680);
 505         WREG32(index_reg, 0x202);
 506         WREG32(data_reg, 0xBFF080F8);
 507         WREG32(index_reg, 0x300);
 508         WREG32(data_reg, 0x83588058);
 509         WREG32(index_reg, 0x301);
 510         WREG32(data_reg, 0x84E08660);
 511         WREG32(index_reg, 0x302);
 512         WREG32(data_reg, 0xBFF88120);
 513         WREG32(index_reg, 0x400);
 514         WREG32(data_reg, 0x83188040);
 515         WREG32(index_reg, 0x401);
 516         WREG32(data_reg, 0x85008660);
 517         WREG32(index_reg, 0x402);
 518         WREG32(data_reg, 0xBFF88150);
 519         WREG32(index_reg, 0x500);
 520         WREG32(data_reg, 0x82D88030);
 521         WREG32(index_reg, 0x501);
 522         WREG32(data_reg, 0x85408640);
 523         WREG32(index_reg, 0x502);
 524         WREG32(data_reg, 0xBFF88180);
 525         WREG32(index_reg, 0x600);
 526         WREG32(data_reg, 0x82A08018);
 527         WREG32(index_reg, 0x601);
 528         WREG32(data_reg, 0x85808620);
 529         WREG32(index_reg, 0x602);
 530         WREG32(data_reg, 0xBFF081B8);
 531         WREG32(index_reg, 0x700);
 532         WREG32(data_reg, 0x82608010);
 533         WREG32(index_reg, 0x701);
 534         WREG32(data_reg, 0x85A08600);
 535         WREG32(index_reg, 0x702);
 536         WREG32(data_reg, 0x800081F0);
 537         WREG32(index_reg, 0x800);
 538         WREG32(data_reg, 0x8228BFF8);
 539         WREG32(index_reg, 0x801);
 540         WREG32(data_reg, 0x85E085E0);
 541         WREG32(index_reg, 0x802);
 542         WREG32(data_reg, 0xBFF88228);
 543         WREG32(index_reg, 0x10000);
 544         WREG32(data_reg, 0x82A8BF00);
 545         WREG32(index_reg, 0x10001);
 546         WREG32(data_reg, 0x82A08CC0);
 547         WREG32(index_reg, 0x10002);
 548         WREG32(data_reg, 0x8008BEF8);
 549         WREG32(index_reg, 0x10100);
 550         WREG32(data_reg, 0x81F0BF28);
 551         WREG32(index_reg, 0x10101);
 552         WREG32(data_reg, 0x83608CA0);
 553         WREG32(index_reg, 0x10102);
 554         WREG32(data_reg, 0x8018BED0);
 555         WREG32(index_reg, 0x10200);
 556         WREG32(data_reg, 0x8148BF38);
 557         WREG32(index_reg, 0x10201);
 558         WREG32(data_reg, 0x84408C80);
 559         WREG32(index_reg, 0x10202);
 560         WREG32(data_reg, 0x8008BEB8);
 561         WREG32(index_reg, 0x10300);
 562         WREG32(data_reg, 0x80B0BF78);
 563         WREG32(index_reg, 0x10301);
 564         WREG32(data_reg, 0x85008C20);
 565         WREG32(index_reg, 0x10302);
 566         WREG32(data_reg, 0x8020BEA0);
 567         WREG32(index_reg, 0x10400);
 568         WREG32(data_reg, 0x8028BF90);
 569         WREG32(index_reg, 0x10401);
 570         WREG32(data_reg, 0x85E08BC0);
 571         WREG32(index_reg, 0x10402);
 572         WREG32(data_reg, 0x8018BE90);
 573         WREG32(index_reg, 0x10500);
 574         WREG32(data_reg, 0xBFB8BFB0);
 575         WREG32(index_reg, 0x10501);
 576         WREG32(data_reg, 0x86C08B40);
 577         WREG32(index_reg, 0x10502);
 578         WREG32(data_reg, 0x8010BE90);
 579         WREG32(index_reg, 0x10600);
 580         WREG32(data_reg, 0xBF58BFC8);
 581         WREG32(index_reg, 0x10601);
 582         WREG32(data_reg, 0x87A08AA0);
 583         WREG32(index_reg, 0x10602);
 584         WREG32(data_reg, 0x8010BE98);
 585         WREG32(index_reg, 0x10700);
 586         WREG32(data_reg, 0xBF10BFF0);
 587         WREG32(index_reg, 0x10701);
 588         WREG32(data_reg, 0x886089E0);
 589         WREG32(index_reg, 0x10702);
 590         WREG32(data_reg, 0x8018BEB0);
 591         WREG32(index_reg, 0x10800);
 592         WREG32(data_reg, 0xBED8BFE8);
 593         WREG32(index_reg, 0x10801);
 594         WREG32(data_reg, 0x89408940);
 595         WREG32(index_reg, 0x10802);
 596         WREG32(data_reg, 0xBFE8BED8);
 597         WREG32(index_reg, 0x20000);
 598         WREG32(data_reg, 0x80008000);
 599         WREG32(index_reg, 0x20001);
 600         WREG32(data_reg, 0x90008000);
 601         WREG32(index_reg, 0x20002);
 602         WREG32(data_reg, 0x80008000);
 603         WREG32(index_reg, 0x20003);
 604         WREG32(data_reg, 0x80008000);
 605         WREG32(index_reg, 0x20100);
 606         WREG32(data_reg, 0x80108000);
 607         WREG32(index_reg, 0x20101);
 608         WREG32(data_reg, 0x8FE0BF70);
 609         WREG32(index_reg, 0x20102);
 610         WREG32(data_reg, 0xBFE880C0);
 611         WREG32(index_reg, 0x20103);
 612         WREG32(data_reg, 0x80008000);
 613         WREG32(index_reg, 0x20200);
 614         WREG32(data_reg, 0x8018BFF8);
 615         WREG32(index_reg, 0x20201);
 616         WREG32(data_reg, 0x8F80BF08);
 617         WREG32(index_reg, 0x20202);
 618         WREG32(data_reg, 0xBFD081A0);
 619         WREG32(index_reg, 0x20203);
 620         WREG32(data_reg, 0xBFF88000);
 621         WREG32(index_reg, 0x20300);
 622         WREG32(data_reg, 0x80188000);
 623         WREG32(index_reg, 0x20301);
 624         WREG32(data_reg, 0x8EE0BEC0);
 625         WREG32(index_reg, 0x20302);
 626         WREG32(data_reg, 0xBFB082A0);
 627         WREG32(index_reg, 0x20303);
 628         WREG32(data_reg, 0x80008000);
 629         WREG32(index_reg, 0x20400);
 630         WREG32(data_reg, 0x80188000);
 631         WREG32(index_reg, 0x20401);
 632         WREG32(data_reg, 0x8E00BEA0);
 633         WREG32(index_reg, 0x20402);
 634         WREG32(data_reg, 0xBF8883C0);
 635         WREG32(index_reg, 0x20403);
 636         WREG32(data_reg, 0x80008000);
 637         WREG32(index_reg, 0x20500);
 638         WREG32(data_reg, 0x80188000);
 639         WREG32(index_reg, 0x20501);
 640         WREG32(data_reg, 0x8D00BE90);
 641         WREG32(index_reg, 0x20502);
 642         WREG32(data_reg, 0xBF588500);
 643         WREG32(index_reg, 0x20503);
 644         WREG32(data_reg, 0x80008008);
 645         WREG32(index_reg, 0x20600);
 646         WREG32(data_reg, 0x80188000);
 647         WREG32(index_reg, 0x20601);
 648         WREG32(data_reg, 0x8BC0BE98);
 649         WREG32(index_reg, 0x20602);
 650         WREG32(data_reg, 0xBF308660);
 651         WREG32(index_reg, 0x20603);
 652         WREG32(data_reg, 0x80008008);
 653         WREG32(index_reg, 0x20700);
 654         WREG32(data_reg, 0x80108000);
 655         WREG32(index_reg, 0x20701);
 656         WREG32(data_reg, 0x8A80BEB0);
 657         WREG32(index_reg, 0x20702);
 658         WREG32(data_reg, 0xBF0087C0);
 659         WREG32(index_reg, 0x20703);
 660         WREG32(data_reg, 0x80008008);
 661         WREG32(index_reg, 0x20800);
 662         WREG32(data_reg, 0x80108000);
 663         WREG32(index_reg, 0x20801);
 664         WREG32(data_reg, 0x8920BED0);
 665         WREG32(index_reg, 0x20802);
 666         WREG32(data_reg, 0xBED08920);
 667         WREG32(index_reg, 0x20803);
 668         WREG32(data_reg, 0x80008010);
 669         WREG32(index_reg, 0x30000);
 670         WREG32(data_reg, 0x90008000);
 671         WREG32(index_reg, 0x30001);
 672         WREG32(data_reg, 0x80008000);
 673         WREG32(index_reg, 0x30100);
 674         WREG32(data_reg, 0x8FE0BF90);
 675         WREG32(index_reg, 0x30101);
 676         WREG32(data_reg, 0xBFF880A0);
 677         WREG32(index_reg, 0x30200);
 678         WREG32(data_reg, 0x8F60BF40);
 679         WREG32(index_reg, 0x30201);
 680         WREG32(data_reg, 0xBFE88180);
 681         WREG32(index_reg, 0x30300);
 682         WREG32(data_reg, 0x8EC0BF00);
 683         WREG32(index_reg, 0x30301);
 684         WREG32(data_reg, 0xBFC88280);
 685         WREG32(index_reg, 0x30400);
 686         WREG32(data_reg, 0x8DE0BEE0);
 687         WREG32(index_reg, 0x30401);
 688         WREG32(data_reg, 0xBFA083A0);
 689         WREG32(index_reg, 0x30500);
 690         WREG32(data_reg, 0x8CE0BED0);
 691         WREG32(index_reg, 0x30501);
 692         WREG32(data_reg, 0xBF7884E0);
 693         WREG32(index_reg, 0x30600);
 694         WREG32(data_reg, 0x8BA0BED8);
 695         WREG32(index_reg, 0x30601);
 696         WREG32(data_reg, 0xBF508640);
 697         WREG32(index_reg, 0x30700);
 698         WREG32(data_reg, 0x8A60BEE8);
 699         WREG32(index_reg, 0x30701);
 700         WREG32(data_reg, 0xBF2087A0);
 701         WREG32(index_reg, 0x30800);
 702         WREG32(data_reg, 0x8900BF00);
 703         WREG32(index_reg, 0x30801);
 704         WREG32(data_reg, 0xBF008900);
 705 }
 706
 707 struct rv515_watermark {
 708         u32        lb_request_fifo_depth;
 709         fixed20_12 num_line_pair;
 710         fixed20_12 estimated_width;
 711         fixed20_12 worst_case_latency;
 712         fixed20_12 consumption_rate;
 713         fixed20_12 active_time;
 714         fixed20_12 dbpp;
 715         fixed20_12 priority_mark_max;
 716         fixed20_12 priority_mark;
 717         fixed20_12 sclk;
 718 };
 719
 720 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 721                                   struct radeon_crtc *crtc,
 722                                   struct rv515_watermark *wm)
 723 {
 724         struct drm_display_mode *mode = &crtc->base.mode;
 725         fixed20_12 a, b, c;
 726         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 727         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 728
 729         if (!crtc->base.enabled) {
 730                 /* FIXME: wouldn't it better to set priority mark to maximum */
 731                 wm->lb_request_fifo_depth = 4;
 732                 return;
 733         }
 734
 735         if (crtc->vsc.full > rfixed_const(2))
 736                 wm->num_line_pair.full = rfixed_const(2);
 737         else
 738                 wm->num_line_pair.full = rfixed_const(1);
 739
 740         b.full = rfixed_const(mode->crtc_hdisplay);
 741         c.full = rfixed_const(256);
 742         a.full = rfixed_mul(wm->num_line_pair, b);
 743         request_fifo_depth.full = rfixed_div(a, c);
 744         if (a.full < rfixed_const(4)) {
 745                 wm->lb_request_fifo_depth = 4;
 746         } else {
 747                 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
 748         }
 749
 750         /* Determine consumption rate
 751          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 752          *  vtaps = number of vertical taps,
 753          *  vsc = vertical scaling ratio, defined as source/destination
 754          *  hsc = horizontal scaling ration, defined as source/destination
 755          */
 756         a.full = rfixed_const(mode->clock);
 757         b.full = rfixed_const(1000);
 758         a.full = rfixed_div(a, b);
 759         pclk.full = rfixed_div(b, a);
 760         if (crtc->rmx_type != RMX_OFF) {
 761                 b.full = rfixed_const(2);
 762                 if (crtc->vsc.full > b.full)
 763                         b.full = crtc->vsc.full;
 764                 b.full = rfixed_mul(b, crtc->hsc);
 765                 c.full = rfixed_const(2);
 766                 b.full = rfixed_div(b, c);
 767                 consumption_time.full = rfixed_div(pclk, b);
 768         } else {
 769                 consumption_time.full = pclk.full;
 770         }
 771         a.full = rfixed_const(1);
 772         wm->consumption_rate.full = rfixed_div(a, consumption_time);
 773
 774
 775         /* Determine line time
 776          *  LineTime = total time for one line of displayhtotal
 777          *  LineTime = total number of horizontal pixels
 778          *  pclk = pixel clock period(ns)
 779          */
 780         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 781         line_time.full = rfixed_mul(a, pclk);
 782
 783         /* Determine active time
 784          *  ActiveTime = time of active region of display within one line,
 785          *  hactive = total number of horizontal active pixels
 786          *  htotal = total number of horizontal pixels
 787          */
 788         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 789         b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 790         wm->active_time.full = rfixed_mul(line_time, b);
 791         wm->active_time.full = rfixed_div(wm->active_time, a);
 792
 793         /* Determine chunk time
 794          * ChunkTime = the time it takes the DCP to send one chunk of data
 795          * to the LB which consists of pipeline delay and inter chunk gap
 796          * sclk = system clock(Mhz)
 797          */
 798         a.full = rfixed_const(600 * 1000);
 799         chunk_time.full = rfixed_div(a, rdev->pm.sclk);
 800         read_delay_latency.full = rfixed_const(1000);
 801
 802         /* Determine the worst case latency
 803          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 804          * WorstCaseLatency = worst case time from urgent to when the MC starts
 805          *                    to return data
 806          * READ_DELAY_IDLE_MAX = constant of 1us
 807          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 808          *             which consists of pipeline delay and inter chunk gap
 809          */
 810         if (rfixed_trunc(wm->num_line_pair) > 1) {
 811                 a.full = rfixed_const(3);
 812                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 813                 wm->worst_case_latency.full += read_delay_latency.full;
 814         } else {
 815                 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
 816         }
 817
 818         /* Determine the tolerable latency
 819          * TolerableLatency = Any given request has only 1 line time
 820          *                    for the data to be returned
 821          * LBRequestFifoDepth = Number of chunk requests the LB can
 822          *                      put into the request FIFO for a display
 823          *  LineTime = total time for one line of display
 824          *  ChunkTime = the time it takes the DCP to send one chunk
 825          *              of data to the LB which consists of
 826          *  pipeline delay and inter chunk gap
 827          */
 828         if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
 829                 tolerable_latency.full = line_time.full;
 830         } else {
 831                 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
 832                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 833                 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
 834                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 835         }
 836         /* We assume worst case 32bits (4 bytes) */
 837         wm->dbpp.full = rfixed_const(2 * 16);
 838
 839         /* Determine the maximum priority mark
 840          *  width = viewport width in pixels
 841          */
 842         a.full = rfixed_const(16);
 843         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 844         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
 845
 846         /* Determine estimated width */
 847         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 848         estimated_width.full = rfixed_div(estimated_width, consumption_time);
 849         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 850                 wm->priority_mark.full = rfixed_const(10);
 851         } else {
 852                 a.full = rfixed_const(16);
 853                 wm->priority_mark.full = rfixed_div(estimated_width, a);
 854                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 855         }
 856 }
 857
 858 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
 859 {
 860         struct drm_display_mode *mode0 = NULL;
 861         struct drm_display_mode *mode1 = NULL;
 862         struct rv515_watermark wm0;
 863         struct rv515_watermark wm1;
 864         u32 tmp;
 865         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 866         fixed20_12 a, b;
 867
 868         if (rdev->mode_info.crtcs[0]->base.enabled)
 869                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 870         if (rdev->mode_info.crtcs[1]->base.enabled)
 871                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 872         rs690_line_buffer_adjust(rdev, mode0, mode1);
 873
 874         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 875         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 876
 877         tmp = wm0.lb_request_fifo_depth;
 878         tmp |= wm1.lb_request_fifo_depth << 16;
 879         WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
 880
 881         if (mode0 && mode1) {
 882                 if (rfixed_trunc(wm0.dbpp) > 64)
 883                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
 884                 else
 885                         a.full = wm0.num_line_pair.full;
 886                 if (rfixed_trunc(wm1.dbpp) > 64)
 887                         b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
 888                 else
 889                         b.full = wm1.num_line_pair.full;
 890                 a.full += b.full;
 891                 fill_rate.full = rfixed_div(wm0.sclk, a);
 892                 if (wm0.consumption_rate.full > fill_rate.full) {
 893                         b.full = wm0.consumption_rate.full - fill_rate.full;
 894                         b.full = rfixed_mul(b, wm0.active_time);
 895                         a.full = rfixed_const(16);
 896                         b.full = rfixed_div(b, a);
 897                         a.full = rfixed_mul(wm0.worst_case_latency,
 898                                                 wm0.consumption_rate);
 899                         priority_mark02.full = a.full + b.full;
 900                 } else {
 901                         a.full = rfixed_mul(wm0.worst_case_latency,
 902                                                 wm0.consumption_rate);
 903                         b.full = rfixed_const(16 * 1000);
 904                         priority_mark02.full = rfixed_div(a, b);
 905                 }
 906                 if (wm1.consumption_rate.full > fill_rate.full) {
 907                         b.full = wm1.consumption_rate.full - fill_rate.full;
 908                         b.full = rfixed_mul(b, wm1.active_time);
 909                         a.full = rfixed_const(16);
 910                         b.full = rfixed_div(b, a);
 911                         a.full = rfixed_mul(wm1.worst_case_latency,
 912                                                 wm1.consumption_rate);
 913                         priority_mark12.full = a.full + b.full;
 914                 } else {
 915                         a.full = rfixed_mul(wm1.worst_case_latency,
 916                                                 wm1.consumption_rate);
 917                         b.full = rfixed_const(16 * 1000);
 918                         priority_mark12.full = rfixed_div(a, b);
 919                 }
 920                 if (wm0.priority_mark.full > priority_mark02.full)
 921                         priority_mark02.full = wm0.priority_mark.full;
 922                 if (rfixed_trunc(priority_mark02) < 0)
 923                         priority_mark02.full = 0;
 924                 if (wm0.priority_mark_max.full > priority_mark02.full)
 925                         priority_mark02.full = wm0.priority_mark_max.full;
 926                 if (wm1.priority_mark.full > priority_mark12.full)
 927                         priority_mark12.full = wm1.priority_mark.full;
 928                 if (rfixed_trunc(priority_mark12) < 0)
 929                         priority_mark12.full = 0;
 930                 if (wm1.priority_mark_max.full > priority_mark12.full)
 931                         priority_mark12.full = wm1.priority_mark_max.full;
 932                 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
 933                 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
 934                 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
 935                 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
 936         } else if (mode0) {
 937                 if (rfixed_trunc(wm0.dbpp) > 64)
 938                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
 939                 else
 940                         a.full = wm0.num_line_pair.full;
 941                 fill_rate.full = rfixed_div(wm0.sclk, a);
 942                 if (wm0.consumption_rate.full > fill_rate.full) {
 943                         b.full = wm0.consumption_rate.full - fill_rate.full;
 944                         b.full = rfixed_mul(b, wm0.active_time);
 945                         a.full = rfixed_const(16);
 946                         b.full = rfixed_div(b, a);
 947                         a.full = rfixed_mul(wm0.worst_case_latency,
 948                                                 wm0.consumption_rate);
 949                         priority_mark02.full = a.full + b.full;
 950                 } else {
 951                         a.full = rfixed_mul(wm0.worst_case_latency,
 952                                                 wm0.consumption_rate);
 953                         b.full = rfixed_const(16);
 954                         priority_mark02.full = rfixed_div(a, b);
 955                 }
 956                 if (wm0.priority_mark.full > priority_mark02.full)
 957                         priority_mark02.full = wm0.priority_mark.full;
 958                 if (rfixed_trunc(priority_mark02) < 0)
 959                         priority_mark02.full = 0;
 960                 if (wm0.priority_mark_max.full > priority_mark02.full)
 961                         priority_mark02.full = wm0.priority_mark_max.full;
 962                 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
 963                 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
 964                 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
 965                 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
 966         } else {
 967                 if (rfixed_trunc(wm1.dbpp) > 64)
 968                         a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
 969                 else
 970                         a.full = wm1.num_line_pair.full;
 971                 fill_rate.full = rfixed_div(wm1.sclk, a);
 972                 if (wm1.consumption_rate.full > fill_rate.full) {
 973                         b.full = wm1.consumption_rate.full - fill_rate.full;
 974                         b.full = rfixed_mul(b, wm1.active_time);
 975                         a.full = rfixed_const(16);
 976                         b.full = rfixed_div(b, a);
 977                         a.full = rfixed_mul(wm1.worst_case_latency,
 978                                                 wm1.consumption_rate);
 979                         priority_mark12.full = a.full + b.full;
 980                 } else {
 981                         a.full = rfixed_mul(wm1.worst_case_latency,
 982                                                 wm1.consumption_rate);
 983                         b.full = rfixed_const(16 * 1000);
 984                         priority_mark12.full = rfixed_div(a, b);
 985                 }
 986                 if (wm1.priority_mark.full > priority_mark12.full)
 987                         priority_mark12.full = wm1.priority_mark.full;
 988                 if (rfixed_trunc(priority_mark12) < 0)
 989                         priority_mark12.full = 0;
 990                 if (wm1.priority_mark_max.full > priority_mark12.full)
 991                         priority_mark12.full = wm1.priority_mark_max.full;
 992                 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
 993                 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
 994                 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
 995                 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
 996         }
 997 }
 998
 999 void rv515_bandwidth_update(struct radeon_device *rdev)
1000 {
1001         uint32_t tmp;
1002         struct drm_display_mode *mode0 = NULL;
1003         struct drm_display_mode *mode1 = NULL;
1004
1005         if (rdev->mode_info.crtcs[0]->base.enabled)
1006                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1007         if (rdev->mode_info.crtcs[1]->base.enabled)
1008                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1009         /*
1010          * Set display0/1 priority up in the memory controller for
1011          * modes if the user specifies HIGH for displaypriority
1012          * option.
1013          */
1014         if (rdev->disp_priority == 2) {
1015                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1016                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1017                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1018                 if (mode1)
1019                         tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1020                 if (mode0)
1021                         tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1022                 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1023         }
1024         rv515_bandwidth_avivo_update(rdev);
1025 }