SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/rs690.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "atom.h"
  32 #include "rs690d.h"
  33
  34 static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
  35 {
  36         unsigned i;
  37         uint32_t tmp;
  38
  39         for (i = 0; i < rdev->usec_timeout; i++) {
  40                 /* read MC_STATUS */
  41                 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
  42                 if (G_000090_MC_SYSTEM_IDLE(tmp))
  43                         return 0;
  44                 udelay(1);
  45         }
  46         return -1;
  47 }
  48
  49 static void rs690_gpu_init(struct radeon_device *rdev)
  50 {
  51         /* FIXME: HDP same place on rs690 ? */
  52         r100_hdp_reset(rdev);
  53         /* FIXME: is this correct ? */
  54         r420_pipes_init(rdev);
  55         if (rs690_mc_wait_for_idle(rdev)) {
  56                 printk(KERN_WARNING "Failed to wait MC idle while "
  57                        "programming pipes. Bad things might happen.\n");
  58         }
  59 }
  60
  61 union igp_info {
  62         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
  63         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
  64 };
  65
  66 void rs690_pm_info(struct radeon_device *rdev)
  67 {
  68         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  69         union igp_info *info;
  70         uint16_t data_offset;
  71         uint8_t frev, crev;
  72         fixed20_12 tmp;
  73
  74         if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
  75                                    &frev, &crev, &data_offset)) {
  76                 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
  77
  78                 /* Get various system informations from bios */
  79                 switch (crev) {
  80                 case 1:
  81                         tmp.full = rfixed_const(100);
  82                         rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info.ulBootUpMemoryClock);
  83                         rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  84                         rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
  85                         rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->info.usFSBClock));
  86                         rdev->pm.igp_ht_link_width.full = rfixed_const(info->info.ucHTLinkWidth);
  87                         break;
  88                 case 2:
  89                         tmp.full = rfixed_const(100);
  90                         rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info_v2.ulBootUpSidePortClock);
  91                         rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  92                         rdev->pm.igp_system_mclk.full = rfixed_const(info->info_v2.ulBootUpUMAClock);
  93                         rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
  94                         rdev->pm.igp_ht_link_clk.full = rfixed_const(info->info_v2.ulHTLinkFreq);
  95                         rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
  96                         rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
  97                         break;
  98                 default:
  99                         tmp.full = rfixed_const(100);
 100                         /* We assume the slower possible clock ie worst case */
 101                         /* DDR 333Mhz */
 102                         rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
 103                         /* FIXME: system clock ? */
 104                         rdev->pm.igp_system_mclk.full = rfixed_const(100);
 105                         rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
 106                         rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
 107                         rdev->pm.igp_ht_link_width.full = rfixed_const(8);
 108                         DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 109                         break;
 110                 }
 111         } else {
 112                 tmp.full = rfixed_const(100);
 113                 /* We assume the slower possible clock ie worst case */
 114                 /* DDR 333Mhz */
 115                 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
 116                 /* FIXME: system clock ? */
 117                 rdev->pm.igp_system_mclk.full = rfixed_const(100);
 118                 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
 119                 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
 120                 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
 121                 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 122         }
 123         /* Compute various bandwidth */
 124         /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
 125         tmp.full = rfixed_const(4);
 126         rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
 127         /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
 128          *              = ht_clk * ht_width / 5
 129          */
 130         tmp.full = rfixed_const(5);
 131         rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
 132                                                 rdev->pm.igp_ht_link_width);
 133         rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
 134         if (tmp.full < rdev->pm.max_bandwidth.full) {
 135                 /* HT link is a limiting factor */
 136                 rdev->pm.max_bandwidth.full = tmp.full;
 137         }
 138         /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
 139          *                    = (sideport_clk * 14) / 10
 140          */
 141         tmp.full = rfixed_const(14);
 142         rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
 143         tmp.full = rfixed_const(10);
 144         rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
 145 }
 146
 147 void rs690_mc_init(struct radeon_device *rdev)
 148 {
 149         u64 base;
 150
 151         rs400_gart_adjust_size(rdev);
 152         rdev->mc.vram_is_ddr = true;
 153         rdev->mc.vram_width = 128;
 154         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 155         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 156         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 157         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 158         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 159         base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
 160         base = G_000100_MC_FB_START(base) << 16;
 161         rs690_pm_info(rdev);
 162         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 163         radeon_vram_location(rdev, &rdev->mc, base);
 164         radeon_gtt_location(rdev, &rdev->mc);
 165         radeon_update_bandwidth_info(rdev);
 166 }
 167
 168 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 169                               struct drm_display_mode *mode1,
 170                               struct drm_display_mode *mode2)
 171 {
 172         u32 tmp;
 173
 174         /*
 175          * Line Buffer Setup
 176          * There is a single line buffer shared by both display controllers.
 177          * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 178          * the display controllers.  The paritioning can either be done
 179          * manually or via one of four preset allocations specified in bits 1:0:
 180          *  0 - line buffer is divided in half and shared between crtc
 181          *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
 182          *  2 - D1 gets the whole buffer
 183          *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
 184          * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
 185          * allocation mode. In manual allocation mode, D1 always starts at 0,
 186          * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
 187          */
 188         tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
 189         tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
 190         /* auto */
 191         if (mode1 && mode2) {
 192                 if (mode1->hdisplay > mode2->hdisplay) {
 193                         if (mode1->hdisplay > 2560)
 194                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
 195                         else
 196                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 197                 } else if (mode2->hdisplay > mode1->hdisplay) {
 198                         if (mode2->hdisplay > 2560)
 199                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 200                         else
 201                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 202                 } else
 203                         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 204         } else if (mode1) {
 205                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
 206         } else if (mode2) {
 207                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 208         }
 209         WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
 210 }
 211
 212 struct rs690_watermark {
 213         u32        lb_request_fifo_depth;
 214         fixed20_12 num_line_pair;
 215         fixed20_12 estimated_width;
 216         fixed20_12 worst_case_latency;
 217         fixed20_12 consumption_rate;
 218         fixed20_12 active_time;
 219         fixed20_12 dbpp;
 220         fixed20_12 priority_mark_max;
 221         fixed20_12 priority_mark;
 222         fixed20_12 sclk;
 223 };
 224
 225 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 226                                   struct radeon_crtc *crtc,
 227                                   struct rs690_watermark *wm)
 228 {
 229         struct drm_display_mode *mode = &crtc->base.mode;
 230         fixed20_12 a, b, c;
 231         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 232         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 233         /* FIXME: detect IGP with sideport memory, i don't think there is any
 234          * such product available
 235          */
 236         bool sideport = false;
 237
 238         if (!crtc->base.enabled) {
 239                 /* FIXME: wouldn't it better to set priority mark to maximum */
 240                 wm->lb_request_fifo_depth = 4;
 241                 return;
 242         }
 243
 244         if (crtc->vsc.full > rfixed_const(2))
 245                 wm->num_line_pair.full = rfixed_const(2);
 246         else
 247                 wm->num_line_pair.full = rfixed_const(1);
 248
 249         b.full = rfixed_const(mode->crtc_hdisplay);
 250         c.full = rfixed_const(256);
 251         a.full = rfixed_div(b, c);
 252         request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
 253         request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
 254         if (a.full < rfixed_const(4)) {
 255                 wm->lb_request_fifo_depth = 4;
 256         } else {
 257                 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
 258         }
 259
 260         /* Determine consumption rate
 261          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 262          *  vtaps = number of vertical taps,
 263          *  vsc = vertical scaling ratio, defined as source/destination
 264          *  hsc = horizontal scaling ration, defined as source/destination
 265          */
 266         a.full = rfixed_const(mode->clock);
 267         b.full = rfixed_const(1000);
 268         a.full = rfixed_div(a, b);
 269         pclk.full = rfixed_div(b, a);
 270         if (crtc->rmx_type != RMX_OFF) {
 271                 b.full = rfixed_const(2);
 272                 if (crtc->vsc.full > b.full)
 273                         b.full = crtc->vsc.full;
 274                 b.full = rfixed_mul(b, crtc->hsc);
 275                 c.full = rfixed_const(2);
 276                 b.full = rfixed_div(b, c);
 277                 consumption_time.full = rfixed_div(pclk, b);
 278         } else {
 279                 consumption_time.full = pclk.full;
 280         }
 281         a.full = rfixed_const(1);
 282         wm->consumption_rate.full = rfixed_div(a, consumption_time);
 283
 284
 285         /* Determine line time
 286          *  LineTime = total time for one line of displayhtotal
 287          *  LineTime = total number of horizontal pixels
 288          *  pclk = pixel clock period(ns)
 289          */
 290         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 291         line_time.full = rfixed_mul(a, pclk);
 292
 293         /* Determine active time
 294          *  ActiveTime = time of active region of display within one line,
 295          *  hactive = total number of horizontal active pixels
 296          *  htotal = total number of horizontal pixels
 297          */
 298         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 299         b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 300         wm->active_time.full = rfixed_mul(line_time, b);
 301         wm->active_time.full = rfixed_div(wm->active_time, a);
 302
 303         /* Maximun bandwidth is the minimun bandwidth of all component */
 304         rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
 305         if (sideport) {
 306                 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
 307                         rdev->pm.sideport_bandwidth.full)
 308                         rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
 309                 read_delay_latency.full = rfixed_const(370 * 800 * 1000);
 310                 read_delay_latency.full = rfixed_div(read_delay_latency,
 311                         rdev->pm.igp_sideport_mclk);
 312         } else {
 313                 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
 314                         rdev->pm.k8_bandwidth.full)
 315                         rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
 316                 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
 317                         rdev->pm.ht_bandwidth.full)
 318                         rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
 319                 read_delay_latency.full = rfixed_const(5000);
 320         }
 321
 322         /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
 323         a.full = rfixed_const(16);
 324         rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
 325         a.full = rfixed_const(1000);
 326         rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
 327         /* Determine chunk time
 328          * ChunkTime = the time it takes the DCP to send one chunk of data
 329          * to the LB which consists of pipeline delay and inter chunk gap
 330          * sclk = system clock(ns)
 331          */
 332         a.full = rfixed_const(256 * 13);
 333         chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
 334         a.full = rfixed_const(10);
 335         chunk_time.full = rfixed_div(chunk_time, a);
 336
 337         /* Determine the worst case latency
 338          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 339          * WorstCaseLatency = worst case time from urgent to when the MC starts
 340          *                    to return data
 341          * READ_DELAY_IDLE_MAX = constant of 1us
 342          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 343          *             which consists of pipeline delay and inter chunk gap
 344          */
 345         if (rfixed_trunc(wm->num_line_pair) > 1) {
 346                 a.full = rfixed_const(3);
 347                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 348                 wm->worst_case_latency.full += read_delay_latency.full;
 349         } else {
 350                 a.full = rfixed_const(2);
 351                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 352                 wm->worst_case_latency.full += read_delay_latency.full;
 353         }
 354
 355         /* Determine the tolerable latency
 356          * TolerableLatency = Any given request has only 1 line time
 357          *                    for the data to be returned
 358          * LBRequestFifoDepth = Number of chunk requests the LB can
 359          *                      put into the request FIFO for a display
 360          *  LineTime = total time for one line of display
 361          *  ChunkTime = the time it takes the DCP to send one chunk
 362          *              of data to the LB which consists of
 363          *  pipeline delay and inter chunk gap
 364          */
 365         if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
 366                 tolerable_latency.full = line_time.full;
 367         } else {
 368                 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
 369                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 370                 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
 371                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 372         }
 373         /* We assume worst case 32bits (4 bytes) */
 374         wm->dbpp.full = rfixed_const(4 * 8);
 375
 376         /* Determine the maximum priority mark
 377          *  width = viewport width in pixels
 378          */
 379         a.full = rfixed_const(16);
 380         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 381         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
 382         wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
 383
 384         /* Determine estimated width */
 385         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 386         estimated_width.full = rfixed_div(estimated_width, consumption_time);
 387         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 388                 wm->priority_mark.full = rfixed_const(10);
 389         } else {
 390                 a.full = rfixed_const(16);
 391                 wm->priority_mark.full = rfixed_div(estimated_width, a);
 392                 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
 393                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 394         }
 395 }
 396
 397 void rs690_bandwidth_update(struct radeon_device *rdev)
 398 {
 399         struct drm_display_mode *mode0 = NULL;
 400         struct drm_display_mode *mode1 = NULL;
 401         struct rs690_watermark wm0;
 402         struct rs690_watermark wm1;
 403         u32 tmp;
 404         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 405         fixed20_12 a, b;
 406
 407         if (rdev->mode_info.crtcs[0]->base.enabled)
 408                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 409         if (rdev->mode_info.crtcs[1]->base.enabled)
 410                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 411         /*
 412          * Set display0/1 priority up in the memory controller for
 413          * modes if the user specifies HIGH for displaypriority
 414          * option.
 415          */
 416         if (rdev->disp_priority == 2) {
 417                 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
 418                 tmp &= C_000104_MC_DISP0R_INIT_LAT;
 419                 tmp &= C_000104_MC_DISP1R_INIT_LAT;
 420                 if (mode0)
 421                         tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
 422                 if (mode1)
 423                         tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
 424                 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
 425         }
 426         rs690_line_buffer_adjust(rdev, mode0, mode1);
 427
 428         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
 429                 WREG32(R_006C9C_DCP_CONTROL, 0);
 430         if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 431                 WREG32(R_006C9C_DCP_CONTROL, 2);
 432
 433         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 434         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 435
 436         tmp = (wm0.lb_request_fifo_depth - 1);
 437         tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
 438         WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
 439
 440         if (mode0 && mode1) {
 441                 if (rfixed_trunc(wm0.dbpp) > 64)
 442                         a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
 443                 else
 444                         a.full = wm0.num_line_pair.full;
 445                 if (rfixed_trunc(wm1.dbpp) > 64)
 446                         b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
 447                 else
 448                         b.full = wm1.num_line_pair.full;
 449                 a.full += b.full;
 450                 fill_rate.full = rfixed_div(wm0.sclk, a);
 451                 if (wm0.consumption_rate.full > fill_rate.full) {
 452                         b.full = wm0.consumption_rate.full - fill_rate.full;
 453                         b.full = rfixed_mul(b, wm0.active_time);
 454                         a.full = rfixed_mul(wm0.worst_case_latency,
 455                                                 wm0.consumption_rate);
 456                         a.full = a.full + b.full;
 457                         b.full = rfixed_const(16 * 1000);
 458                         priority_mark02.full = rfixed_div(a, b);
 459                 } else {
 460                         a.full = rfixed_mul(wm0.worst_case_latency,
 461                                                 wm0.consumption_rate);
 462                         b.full = rfixed_const(16 * 1000);
 463                         priority_mark02.full = rfixed_div(a, b);
 464                 }
 465                 if (wm1.consumption_rate.full > fill_rate.full) {
 466                         b.full = wm1.consumption_rate.full - fill_rate.full;
 467                         b.full = rfixed_mul(b, wm1.active_time);
 468                         a.full = rfixed_mul(wm1.worst_case_latency,
 469                                                 wm1.consumption_rate);
 470                         a.full = a.full + b.full;
 471                         b.full = rfixed_const(16 * 1000);
 472                         priority_mark12.full = rfixed_div(a, b);
 473                 } else {
 474                         a.full = rfixed_mul(wm1.worst_case_latency,
 475                                                 wm1.consumption_rate);
 476                         b.full = rfixed_const(16 * 1000);
 477                         priority_mark12.full = rfixed_div(a, b);
 478                 }
 479                 if (wm0.priority_mark.full > priority_mark02.full)
 480                         priority_mark02.full = wm0.priority_mark.full;
 481                 if (rfixed_trunc(priority_mark02) < 0)
 482                         priority_mark02.full = 0;
 483                 if (wm0.priority_mark_max.full > priority_mark02.full)
 484                         priority_mark02.full = wm0.priority_mark_max.full;
 485                 if (wm1.priority_mark.full > priority_mark12.full)
 486                         priority_mark12.full = wm1.priority_mark.full;
 487                 if (rfixed_trunc(priority_mark12) < 0)
 488                         priority_mark12.full = 0;
 489                 if (wm1.priority_mark_max.full > priority_mark12.full)
 490                         priority_mark12.full = wm1.priority_mark_max.full;
 491                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
 492                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
 493                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
 494                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
 495         } else if (mode0) {
 496                 if (rfixed_trunc(wm0.dbpp) > 64)
 497                         a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
 498                 else
 499                         a.full = wm0.num_line_pair.full;
 500                 fill_rate.full = rfixed_div(wm0.sclk, a);
 501                 if (wm0.consumption_rate.full > fill_rate.full) {
 502                         b.full = wm0.consumption_rate.full - fill_rate.full;
 503                         b.full = rfixed_mul(b, wm0.active_time);
 504                         a.full = rfixed_mul(wm0.worst_case_latency,
 505                                                 wm0.consumption_rate);
 506                         a.full = a.full + b.full;
 507                         b.full = rfixed_const(16 * 1000);
 508                         priority_mark02.full = rfixed_div(a, b);
 509                 } else {
 510                         a.full = rfixed_mul(wm0.worst_case_latency,
 511                                                 wm0.consumption_rate);
 512                         b.full = rfixed_const(16 * 1000);
 513                         priority_mark02.full = rfixed_div(a, b);
 514                 }
 515                 if (wm0.priority_mark.full > priority_mark02.full)
 516                         priority_mark02.full = wm0.priority_mark.full;
 517                 if (rfixed_trunc(priority_mark02) < 0)
 518                         priority_mark02.full = 0;
 519                 if (wm0.priority_mark_max.full > priority_mark02.full)
 520                         priority_mark02.full = wm0.priority_mark_max.full;
 521                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
 522                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
 523                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
 524                         S_006D48_D2MODE_PRIORITY_A_OFF(1));
 525                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
 526                         S_006D4C_D2MODE_PRIORITY_B_OFF(1));
 527         } else {
 528                 if (rfixed_trunc(wm1.dbpp) > 64)
 529                         a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
 530                 else
 531                         a.full = wm1.num_line_pair.full;
 532                 fill_rate.full = rfixed_div(wm1.sclk, a);
 533                 if (wm1.consumption_rate.full > fill_rate.full) {
 534                         b.full = wm1.consumption_rate.full - fill_rate.full;
 535                         b.full = rfixed_mul(b, wm1.active_time);
 536                         a.full = rfixed_mul(wm1.worst_case_latency,
 537                                                 wm1.consumption_rate);
 538                         a.full = a.full + b.full;
 539                         b.full = rfixed_const(16 * 1000);
 540                         priority_mark12.full = rfixed_div(a, b);
 541                 } else {
 542                         a.full = rfixed_mul(wm1.worst_case_latency,
 543                                                 wm1.consumption_rate);
 544                         b.full = rfixed_const(16 * 1000);
 545                         priority_mark12.full = rfixed_div(a, b);
 546                 }
 547                 if (wm1.priority_mark.full > priority_mark12.full)
 548                         priority_mark12.full = wm1.priority_mark.full;
 549                 if (rfixed_trunc(priority_mark12) < 0)
 550                         priority_mark12.full = 0;
 551                 if (wm1.priority_mark_max.full > priority_mark12.full)
 552                         priority_mark12.full = wm1.priority_mark_max.full;
 553                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
 554                         S_006548_D1MODE_PRIORITY_A_OFF(1));
 555                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
 556                         S_00654C_D1MODE_PRIORITY_B_OFF(1));
 557                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
 558                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
 559         }
 560 }
 561
 562 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 563 {
 564         uint32_t r;
 565
 566         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
 567         r = RREG32(R_00007C_MC_DATA);
 568         WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
 569         return r;
 570 }
 571
 572 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 573 {
 574         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
 575                 S_000078_MC_IND_WR_EN(1));
 576         WREG32(R_00007C_MC_DATA, v);
 577         WREG32(R_000078_MC_INDEX, 0x7F);
 578 }
 579
 580 void rs690_mc_program(struct radeon_device *rdev)
 581 {
 582         struct rv515_mc_save save;
 583
 584         /* Stops all mc clients */
 585         rv515_mc_stop(rdev, &save);
 586
 587         /* Wait for mc idle */
 588         if (rs690_mc_wait_for_idle(rdev))
 589                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 590         /* Program MC, should be a 32bits limited address space */
 591         WREG32_MC(R_000100_MCCFG_FB_LOCATION,
 592                         S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
 593                         S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
 594         WREG32(R_000134_HDP_FB_LOCATION,
 595                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 596
 597         rv515_mc_resume(rdev, &save);
 598 }
 599
 600 static int rs690_startup(struct radeon_device *rdev)
 601 {
 602         int r;
 603
 604         rs690_mc_program(rdev);
 605         /* Resume clock */
 606         rv515_clock_startup(rdev);
 607         /* Initialize GPU configuration (# pipes, ...) */
 608         rs690_gpu_init(rdev);
 609         /* Initialize GART (initialize after TTM so we can allocate
 610          * memory through TTM but finalize after TTM) */
 611         r = rs400_gart_enable(rdev);
 612         if (r)
 613                 return r;
 614         /* Enable IRQ */
 615         rs600_irq_set(rdev);
 616         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 617         /* 1M ring buffer */
 618         r = r100_cp_init(rdev, 1024 * 1024);
 619         if (r) {
 620                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 621                 return r;
 622         }
 623         r = r100_wb_init(rdev);
 624         if (r)
 625                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 626         r = r100_ib_init(rdev);
 627         if (r) {
 628                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 629                 return r;
 630         }
 631         return 0;
 632 }
 633
 634 int rs690_resume(struct radeon_device *rdev)
 635 {
 636         /* Make sur GART are not working */
 637         rs400_gart_disable(rdev);
 638         /* Resume clock before doing reset */
 639         rv515_clock_startup(rdev);
 640         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 641         if (radeon_gpu_reset(rdev)) {
 642                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 643                         RREG32(R_000E40_RBBM_STATUS),
 644                         RREG32(R_0007C0_CP_STAT));
 645         }
 646         /* post */
 647         atom_asic_init(rdev->mode_info.atom_context);
 648         /* Resume clock after posting */
 649         rv515_clock_startup(rdev);
 650         /* Initialize surface registers */
 651         radeon_surface_init(rdev);
 652         return rs690_startup(rdev);
 653 }
 654
 655 int rs690_suspend(struct radeon_device *rdev)
 656 {
 657         r100_cp_disable(rdev);
 658         r100_wb_disable(rdev);
 659         rs600_irq_disable(rdev);
 660         rs400_gart_disable(rdev);
 661         return 0;
 662 }
 663
 664 void rs690_fini(struct radeon_device *rdev)
 665 {
 666         radeon_pm_fini(rdev);
 667         r100_cp_fini(rdev);
 668         r100_wb_fini(rdev);
 669         r100_ib_fini(rdev);
 670         radeon_gem_fini(rdev);
 671         rs400_gart_fini(rdev);
 672         radeon_irq_kms_fini(rdev);
 673         radeon_fence_driver_fini(rdev);
 674         radeon_bo_fini(rdev);
 675         radeon_atombios_fini(rdev);
 676         kfree(rdev->bios);
 677         rdev->bios = NULL;
 678 }
 679
 680 int rs690_init(struct radeon_device *rdev)
 681 {
 682         int r;
 683
 684         /* Disable VGA */
 685         rv515_vga_render_disable(rdev);
 686         /* Initialize scratch registers */
 687         radeon_scratch_init(rdev);
 688         /* Initialize surface registers */
 689         radeon_surface_init(rdev);
 690         /* TODO: disable VGA need to use VGA request */
 691         /* BIOS*/
 692         if (!radeon_get_bios(rdev)) {
 693                 if (ASIC_IS_AVIVO(rdev))
 694                         return -EINVAL;
 695         }
 696         if (rdev->is_atom_bios) {
 697                 r = radeon_atombios_init(rdev);
 698                 if (r)
 699                         return r;
 700         } else {
 701                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 702                 return -EINVAL;
 703         }
 704         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 705         if (radeon_gpu_reset(rdev)) {
 706                 dev_warn(rdev->dev,
 707                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 708                         RREG32(R_000E40_RBBM_STATUS),
 709                         RREG32(R_0007C0_CP_STAT));
 710         }
 711         /* check if cards are posted or not */
 712         if (radeon_boot_test_post_card(rdev) == false)
 713                 return -EINVAL;
 714
 715         /* Initialize clocks */
 716         radeon_get_clock_info(rdev->ddev);
 717         /* Initialize power management */
 718         radeon_pm_init(rdev);
 719         /* initialize memory controller */
 720         rs690_mc_init(rdev);
 721         rv515_debugfs(rdev);
 722         /* Fence driver */
 723         r = radeon_fence_driver_init(rdev);
 724         if (r)
 725                 return r;
 726         r = radeon_irq_kms_init(rdev);
 727         if (r)
 728                 return r;
 729         /* Memory manager */
 730         r = radeon_bo_init(rdev);
 731         if (r)
 732                 return r;
 733         r = rs400_gart_init(rdev);
 734         if (r)
 735                 return r;
 736         rs600_set_safe_registers(rdev);
 737         rdev->accel_working = true;
 738         r = rs690_startup(rdev);
 739         if (r) {
 740                 /* Somethings want wront with the accel init stop accel */
 741                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 742                 r100_cp_fini(rdev);
 743                 r100_wb_fini(rdev);
 744                 r100_ib_fini(rdev);
 745                 rs400_gart_fini(rdev);
 746                 radeon_irq_kms_fini(rdev);
 747                 rdev->accel_working = false;
 748         }
 749         return 0;
 750 }