SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/rs600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 /* RS600 / Radeon X1250/X1270 integrated GPU
  29  *
  30  * This file gather function specific to RS600 which is the IGP of
  31  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33  * the avivo one, bios is an atombios, 3D block are the one of the
  34  * R4XX family. The GART is different from the RS400 one and is very
  35  * close to the one of the R600 family (R600 likely being an evolution
  36  * of the RS600 GART block).
  37  */
  38 #include "drmP.h"
  39 #include "radeon.h"
  40 #include "atom.h"
  41 #include "rs600d.h"
  42
  43 #include "rs600_reg_safe.h"
  44
  45 void rs600_gpu_init(struct radeon_device *rdev);
  46 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  47
  48 int rs600_mc_init(struct radeon_device *rdev)
  49 {
  50         /* read back the MC value from the hw */
  51         uint32_t mc_fb_loc;
  52         int r;
  53
  54         mc_fb_loc = RREG32_MC(R_000004_MC_FB_LOCATION);
  55         rdev->mc.vram_location = G_000004_MC_FB_START(mc_fb_loc) << 16;
  56         rdev->mc.gtt_location = 0xffffffffUL;
  57         r = radeon_mc_setup(rdev);
  58         if (r)
  59                 return r;
  60         return 0;
  61 }
  62 /*
  63  * GART.
  64  */
  65 void rs600_gart_tlb_flush(struct radeon_device *rdev)
  66 {
  67         uint32_t tmp;
  68
  69         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  70         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  71         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  72
  73         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  74         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
  75         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  76
  77         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  78         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  79         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  80         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  81 }
  82
  83 int rs600_gart_init(struct radeon_device *rdev)
  84 {
  85         int r;
  86
  87         if (rdev->gart.table.vram.robj) {
  88                 WARN(1, "RS600 GART already initialized.\n");
  89                 return 0;
  90         }
  91         /* Initialize common gart structure */
  92         r = radeon_gart_init(rdev);
  93         if (r) {
  94                 return r;
  95         }
  96         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
  97         return radeon_gart_table_vram_alloc(rdev);
  98 }
  99
 100 int rs600_gart_enable(struct radeon_device *rdev)
 101 {
 102         u32 tmp;
 103         int r, i;
 104
 105         if (rdev->gart.table.vram.robj == NULL) {
 106                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 107                 return -EINVAL;
 108         }
 109         r = radeon_gart_table_vram_pin(rdev);
 110         if (r)
 111                 return r;
 112         /* Enable bus master */
 113         tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
 114         WREG32(R_00004C_BUS_CNTL, tmp);
 115         /* FIXME: setup default page */
 116         WREG32_MC(R_000100_MC_PT0_CNTL,
 117                   (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
 118                    S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 119
 120         for (i = 0; i < 19; i++) {
 121                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
 122                           S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
 123                           S_00016C_SYSTEM_ACCESS_MODE_MASK(
 124                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
 125                           S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
 126                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
 127                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
 128                           S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
 129                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
 130         }
 131         /* enable first context */
 132         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
 133                   S_000102_ENABLE_PAGE_TABLE(1) |
 134                   S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 135
 136         /* disable all other contexts */
 137         for (i = 1; i < 8; i++)
 138                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 139
 140         /* setup the page table */
 141         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 142                   rdev->gart.table_addr);
 143         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
 144         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
 145         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 146
 147         /* System context maps to VRAM space */
 148         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
 149         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 150
 151         /* enable page tables */
 152         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 153         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
 154         tmp = RREG32_MC(R_000009_MC_CNTL1);
 155         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
 156         rs600_gart_tlb_flush(rdev);
 157         rdev->gart.ready = true;
 158         return 0;
 159 }
 160
 161 void rs600_gart_disable(struct radeon_device *rdev)
 162 {
 163         u32 tmp;
 164         int r;
 165
 166         /* FIXME: disable out of gart access */
 167         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
 168         tmp = RREG32_MC(R_000009_MC_CNTL1);
 169         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
 170         if (rdev->gart.table.vram.robj) {
 171                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 172                 if (r == 0) {
 173                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 174                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 175                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 176                 }
 177         }
 178 }
 179
 180 void rs600_gart_fini(struct radeon_device *rdev)
 181 {
 182         rs600_gart_disable(rdev);
 183         radeon_gart_table_vram_free(rdev);
 184         radeon_gart_fini(rdev);
 185 }
 186
 187 #define R600_PTE_VALID     (1 << 0)
 188 #define R600_PTE_SYSTEM    (1 << 1)
 189 #define R600_PTE_SNOOPED   (1 << 2)
 190 #define R600_PTE_READABLE  (1 << 5)
 191 #define R600_PTE_WRITEABLE (1 << 6)
 192
 193 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 194 {
 195         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 196
 197         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 198                 return -EINVAL;
 199         }
 200         addr = addr & 0xFFFFFFFFFFFFF000ULL;
 201         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 202         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 203         writeq(addr, ((void __iomem *)ptr) + (i * 8));
 204         return 0;
 205 }
 206
 207 int rs600_irq_set(struct radeon_device *rdev)
 208 {
 209         uint32_t tmp = 0;
 210         uint32_t mode_int = 0;
 211
 212         if (rdev->irq.sw_int) {
 213                 tmp |= S_000040_SW_INT_EN(1);
 214         }
 215         if (rdev->irq.crtc_vblank_int[0]) {
 216                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
 217         }
 218         if (rdev->irq.crtc_vblank_int[1]) {
 219                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
 220         }
 221         WREG32(R_000040_GEN_INT_CNTL, tmp);
 222         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
 223         return 0;
 224 }
 225
 226 static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
 227 {
 228         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
 229         uint32_t irq_mask = ~C_000044_SW_INT;
 230
 231         if (G_000044_DISPLAY_INT_STAT(irqs)) {
 232                 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
 233                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
 234                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
 235                                 S_006534_D1MODE_VBLANK_ACK(1));
 236                 }
 237                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
 238                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
 239                                 S_006D34_D2MODE_VBLANK_ACK(1));
 240                 }
 241         } else {
 242                 *r500_disp_int = 0;
 243         }
 244
 245         if (irqs) {
 246                 WREG32(R_000044_GEN_INT_STATUS, irqs);
 247         }
 248         return irqs & irq_mask;
 249 }
 250
 251 void rs600_irq_disable(struct radeon_device *rdev)
 252 {
 253         u32 tmp;
 254
 255         WREG32(R_000040_GEN_INT_CNTL, 0);
 256         WREG32(R_006540_DxMODE_INT_MASK, 0);
 257         /* Wait and acknowledge irq */
 258         mdelay(1);
 259         rs600_irq_ack(rdev, &tmp);
 260 }
 261
 262 int rs600_irq_process(struct radeon_device *rdev)
 263 {
 264         uint32_t status, msi_rearm;
 265         uint32_t r500_disp_int;
 266
 267         status = rs600_irq_ack(rdev, &r500_disp_int);
 268         if (!status && !r500_disp_int) {
 269                 return IRQ_NONE;
 270         }
 271         while (status || r500_disp_int) {
 272                 /* SW interrupt */
 273                 if (G_000040_SW_INT_EN(status))
 274                         radeon_fence_process(rdev);
 275                 /* Vertical blank interrupts */
 276                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
 277                         drm_handle_vblank(rdev->ddev, 0);
 278                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int))
 279                         drm_handle_vblank(rdev->ddev, 1);
 280                 status = rs600_irq_ack(rdev, &r500_disp_int);
 281         }
 282         if (rdev->msi_enabled) {
 283                 switch (rdev->family) {
 284                 case CHIP_RS600:
 285                 case CHIP_RS690:
 286                 case CHIP_RS740:
 287                         msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
 288                         WREG32(RADEON_BUS_CNTL, msi_rearm);
 289                         WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
 290                         break;
 291                 default:
 292                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 293                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 294                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 295                         break;
 296                 }
 297         }
 298         return IRQ_HANDLED;
 299 }
 300
 301 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
 302 {
 303         if (crtc == 0)
 304                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
 305         else
 306                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
 307 }
 308
 309 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
 310 {
 311         unsigned i;
 312
 313         for (i = 0; i < rdev->usec_timeout; i++) {
 314                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
 315                         return 0;
 316                 udelay(1);
 317         }
 318         return -1;
 319 }
 320
 321 void rs600_gpu_init(struct radeon_device *rdev)
 322 {
 323         r100_hdp_reset(rdev);
 324         r420_pipes_init(rdev);
 325         /* Wait for mc idle */
 326         if (rs600_mc_wait_for_idle(rdev))
 327                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 328 }
 329
 330 void rs600_vram_info(struct radeon_device *rdev)
 331 {
 332         rdev->mc.vram_is_ddr = true;
 333         rdev->mc.vram_width = 128;
 334
 335         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 336         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 337
 338         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 339         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 340
 341         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
 342                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 343
 344         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
 345                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 346 }
 347
 348 void rs600_bandwidth_update(struct radeon_device *rdev)
 349 {
 350         /* FIXME: implement, should this be like rs690 ? */
 351 }
 352
 353 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 354 {
 355         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 356                 S_000070_MC_IND_CITF_ARB0(1));
 357         return RREG32(R_000074_MC_IND_DATA);
 358 }
 359
 360 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 361 {
 362         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 363                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
 364         WREG32(R_000074_MC_IND_DATA, v);
 365 }
 366
 367 void rs600_debugfs(struct radeon_device *rdev)
 368 {
 369         if (r100_debugfs_rbbm_init(rdev))
 370                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 371 }
 372
 373 void rs600_set_safe_registers(struct radeon_device *rdev)
 374 {
 375         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
 376         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
 377 }
 378
 379 static void rs600_mc_program(struct radeon_device *rdev)
 380 {
 381         struct rv515_mc_save save;
 382
 383         /* Stops all mc clients */
 384         rv515_mc_stop(rdev, &save);
 385
 386         /* Wait for mc idle */
 387         if (rs600_mc_wait_for_idle(rdev))
 388                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 389
 390         /* FIXME: What does AGP means for such chipset ? */
 391         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
 392         WREG32_MC(R_000006_AGP_BASE, 0);
 393         WREG32_MC(R_000007_AGP_BASE_2, 0);
 394         /* Program MC */
 395         WREG32_MC(R_000004_MC_FB_LOCATION,
 396                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
 397                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
 398         WREG32(R_000134_HDP_FB_LOCATION,
 399                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 400
 401         rv515_mc_resume(rdev, &save);
 402 }
 403
 404 static int rs600_startup(struct radeon_device *rdev)
 405 {
 406         int r;
 407
 408         rs600_mc_program(rdev);
 409         /* Resume clock */
 410         rv515_clock_startup(rdev);
 411         /* Initialize GPU configuration (# pipes, ...) */
 412         rs600_gpu_init(rdev);
 413         /* Initialize GART (initialize after TTM so we can allocate
 414          * memory through TTM but finalize after TTM) */
 415         r = rs600_gart_enable(rdev);
 416         if (r)
 417                 return r;
 418         /* Enable IRQ */
 419         rs600_irq_set(rdev);
 420         /* 1M ring buffer */
 421         r = r100_cp_init(rdev, 1024 * 1024);
 422         if (r) {
 423                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 424                 return r;
 425         }
 426         r = r100_wb_init(rdev);
 427         if (r)
 428                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 429         r = r100_ib_init(rdev);
 430         if (r) {
 431                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 432                 return r;
 433         }
 434         return 0;
 435 }
 436
 437 int rs600_resume(struct radeon_device *rdev)
 438 {
 439         /* Make sur GART are not working */
 440         rs600_gart_disable(rdev);
 441         /* Resume clock before doing reset */
 442         rv515_clock_startup(rdev);
 443         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 444         if (radeon_gpu_reset(rdev)) {
 445                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 446                         RREG32(R_000E40_RBBM_STATUS),
 447                         RREG32(R_0007C0_CP_STAT));
 448         }
 449         /* post */
 450         atom_asic_init(rdev->mode_info.atom_context);
 451         /* Resume clock after posting */
 452         rv515_clock_startup(rdev);
 453         return rs600_startup(rdev);
 454 }
 455
 456 int rs600_suspend(struct radeon_device *rdev)
 457 {
 458         r100_cp_disable(rdev);
 459         r100_wb_disable(rdev);
 460         rs600_irq_disable(rdev);
 461         rs600_gart_disable(rdev);
 462         return 0;
 463 }
 464
 465 void rs600_fini(struct radeon_device *rdev)
 466 {
 467         rs600_suspend(rdev);
 468         r100_cp_fini(rdev);
 469         r100_wb_fini(rdev);
 470         r100_ib_fini(rdev);
 471         radeon_gem_fini(rdev);
 472         rs600_gart_fini(rdev);
 473         radeon_irq_kms_fini(rdev);
 474         radeon_fence_driver_fini(rdev);
 475         radeon_bo_fini(rdev);
 476         radeon_atombios_fini(rdev);
 477         kfree(rdev->bios);
 478         rdev->bios = NULL;
 479 }
 480
 481 int rs600_init(struct radeon_device *rdev)
 482 {
 483         int r;
 484
 485         /* Disable VGA */
 486         rv515_vga_render_disable(rdev);
 487         /* Initialize scratch registers */
 488         radeon_scratch_init(rdev);
 489         /* Initialize surface registers */
 490         radeon_surface_init(rdev);
 491         /* BIOS */
 492         if (!radeon_get_bios(rdev)) {
 493                 if (ASIC_IS_AVIVO(rdev))
 494                         return -EINVAL;
 495         }
 496         if (rdev->is_atom_bios) {
 497                 r = radeon_atombios_init(rdev);
 498                 if (r)
 499                         return r;
 500         } else {
 501                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
 502                 return -EINVAL;
 503         }
 504         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 505         if (radeon_gpu_reset(rdev)) {
 506                 dev_warn(rdev->dev,
 507                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 508                         RREG32(R_000E40_RBBM_STATUS),
 509                         RREG32(R_0007C0_CP_STAT));
 510         }
 511         /* check if cards are posted or not */
 512         if (radeon_boot_test_post_card(rdev) == false)
 513                 return -EINVAL;
 514
 515         /* Initialize clocks */
 516         radeon_get_clock_info(rdev->ddev);
 517         /* Initialize power management */
 518         radeon_pm_init(rdev);
 519         /* Get vram informations */
 520         rs600_vram_info(rdev);
 521         /* Initialize memory controller (also test AGP) */
 522         r = rs600_mc_init(rdev);
 523         if (r)
 524                 return r;
 525         rs600_debugfs(rdev);
 526         /* Fence driver */
 527         r = radeon_fence_driver_init(rdev);
 528         if (r)
 529                 return r;
 530         r = radeon_irq_kms_init(rdev);
 531         if (r)
 532                 return r;
 533         /* Memory manager */
 534         r = radeon_bo_init(rdev);
 535         if (r)
 536                 return r;
 537         r = rs600_gart_init(rdev);
 538         if (r)
 539                 return r;
 540         rs600_set_safe_registers(rdev);
 541         rdev->accel_working = true;
 542         r = rs600_startup(rdev);
 543         if (r) {
 544                 /* Somethings want wront with the accel init stop accel */
 545                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 546                 rs600_suspend(rdev);
 547                 r100_cp_fini(rdev);
 548                 r100_wb_fini(rdev);
 549                 r100_ib_fini(rdev);
 550                 rs600_gart_fini(rdev);
 551                 radeon_irq_kms_fini(rdev);
 552                 rdev->accel_working = false;
 553         }
 554         return 0;
 555 }