2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
33 /* This files gather functions specifics to : rs400,rs480 */
34 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
36 void rs400_gart_adjust_size(struct radeon_device *rdev)
39 switch (rdev->mc.gtt_size/(1024*1024)) {
49 DRM_ERROR("Unable to use IGP GART size %uM\n",
50 (unsigned)(rdev->mc.gtt_size >> 20));
51 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
52 DRM_ERROR("Forcing to 32M GART size\n");
53 rdev->mc.gtt_size = 32 * 1024 * 1024;
56 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
57 /* FIXME: RS400 & RS480 seems to have issue with GART size
58 * if 4G of system memory (needs more testing) */
59 rdev->mc.gtt_size = 32 * 1024 * 1024;
60 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
64 void rs400_gart_tlb_flush(struct radeon_device *rdev)
67 unsigned int timeout = rdev->usec_timeout;
69 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
71 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
72 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
76 } while (timeout > 0);
77 WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
80 int rs400_gart_init(struct radeon_device *rdev)
84 if (rdev->gart.table.ram.ptr) {
85 WARN(1, "RS400 GART already initialized.\n");
89 switch(rdev->mc.gtt_size / (1024 * 1024)) {
101 /* Initialize common gart structure */
102 r = radeon_gart_init(rdev);
105 if (rs400_debugfs_pcie_gart_info_init(rdev))
106 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
108 return radeon_gart_table_ram_alloc(rdev);
111 int rs400_gart_enable(struct radeon_device *rdev)
116 radeon_gart_restore(rdev);
117 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
118 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
119 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
120 /* Check gart size */
121 switch(rdev->mc.gtt_size / (1024 * 1024)) {
123 size_reg = RS480_VA_SIZE_32MB;
126 size_reg = RS480_VA_SIZE_64MB;
129 size_reg = RS480_VA_SIZE_128MB;
132 size_reg = RS480_VA_SIZE_256MB;
135 size_reg = RS480_VA_SIZE_512MB;
138 size_reg = RS480_VA_SIZE_1GB;
141 size_reg = RS480_VA_SIZE_2GB;
146 /* It should be fine to program it to max value */
147 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
148 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
149 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
151 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
152 WREG32(RS480_AGP_BASE_2, 0);
154 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
155 tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16);
156 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16);
157 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
158 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
159 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
160 WREG32(RADEON_BUS_CNTL, tmp);
162 WREG32(RADEON_MC_AGP_LOCATION, tmp);
163 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
164 WREG32(RADEON_BUS_CNTL, tmp);
166 /* Table should be in 32bits address space so ignore bits above. */
167 tmp = (u32)rdev->gart.table_addr & 0xfffff000;
168 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
170 WREG32_MC(RS480_GART_BASE, tmp);
171 /* TODO: more tweaking here */
172 WREG32_MC(RS480_GART_FEATURE_ID,
174 RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
175 /* Disable snooping */
176 WREG32_MC(RS480_AGP_MODE_CNTL,
177 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
178 /* Disable AGP mode */
179 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
180 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
181 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
182 WREG32_MC(RS480_MC_MISC_CNTL,
183 (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
185 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
188 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
189 rs400_gart_tlb_flush(rdev);
190 rdev->gart.ready = true;
194 void rs400_gart_disable(struct radeon_device *rdev)
198 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
199 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
200 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
201 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
204 void rs400_gart_fini(struct radeon_device *rdev)
206 rs400_gart_disable(rdev);
207 radeon_gart_table_ram_free(rdev);
208 radeon_gart_fini(rdev);
211 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
215 if (i < 0 || i > rdev->gart.num_gpu_pages) {
219 entry = (lower_32_bits(addr) & PAGE_MASK) |
220 ((upper_32_bits(addr) & 0xff) << 4) |
222 entry = cpu_to_le32(entry);
223 rdev->gart.table.ram.ptr[i] = entry;
227 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
232 for (i = 0; i < rdev->usec_timeout; i++) {
234 tmp = RREG32(0x0150);
235 if (tmp & (1 << 2)) {
243 void rs400_gpu_init(struct radeon_device *rdev)
245 /* FIXME: HDP same place on rs400 ? */
246 r100_hdp_reset(rdev);
247 /* FIXME: is this correct ? */
248 r420_pipes_init(rdev);
249 if (rs400_mc_wait_for_idle(rdev)) {
250 printk(KERN_WARNING "rs400: Failed to wait MC idle while "
251 "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
255 void rs400_vram_info(struct radeon_device *rdev)
257 rs400_gart_adjust_size(rdev);
258 /* DDR for all card after R300 & IGP */
259 rdev->mc.vram_is_ddr = true;
260 rdev->mc.vram_width = 128;
262 r100_vram_init_sizes(rdev);
265 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
269 WREG32(RS480_NB_MC_INDEX, reg & 0xff);
270 r = RREG32(RS480_NB_MC_DATA);
271 WREG32(RS480_NB_MC_INDEX, 0xff);
275 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
277 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
278 WREG32(RS480_NB_MC_DATA, (v));
279 WREG32(RS480_NB_MC_INDEX, 0xff);
282 #if defined(CONFIG_DEBUG_FS)
283 static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
285 struct drm_info_node *node = (struct drm_info_node *) m->private;
286 struct drm_device *dev = node->minor->dev;
287 struct radeon_device *rdev = dev->dev_private;
290 tmp = RREG32(RADEON_HOST_PATH_CNTL);
291 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
292 tmp = RREG32(RADEON_BUS_CNTL);
293 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
294 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
295 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
296 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
297 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
298 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
299 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
300 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
301 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
302 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
303 tmp = RREG32_MC(0x100);
304 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
306 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
308 tmp = RREG32(RADEON_AGP_BASE);
309 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
310 tmp = RREG32(RS480_AGP_BASE_2);
311 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
312 tmp = RREG32(RADEON_MC_AGP_LOCATION);
313 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
315 tmp = RREG32_MC(RS480_GART_BASE);
316 seq_printf(m, "GART_BASE 0x%08x\n", tmp);
317 tmp = RREG32_MC(RS480_GART_FEATURE_ID);
318 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
319 tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
320 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
321 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
322 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
323 tmp = RREG32_MC(0x5F);
324 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
325 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
326 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
327 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
328 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
329 tmp = RREG32_MC(0x3B);
330 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
331 tmp = RREG32_MC(0x3C);
332 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
333 tmp = RREG32_MC(0x30);
334 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
335 tmp = RREG32_MC(0x31);
336 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
337 tmp = RREG32_MC(0x32);
338 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
339 tmp = RREG32_MC(0x33);
340 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
341 tmp = RREG32_MC(0x34);
342 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
343 tmp = RREG32_MC(0x35);
344 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
345 tmp = RREG32_MC(0x36);
346 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
347 tmp = RREG32_MC(0x37);
348 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
352 static struct drm_info_list rs400_gart_info_list[] = {
353 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
357 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
359 #if defined(CONFIG_DEBUG_FS)
360 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
366 static int rs400_mc_init(struct radeon_device *rdev)
371 /* Setup GPU memory space */
372 tmp = RREG32(R_00015C_NB_TOM);
373 rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
374 rdev->mc.gtt_location = 0xFFFFFFFFUL;
375 r = radeon_mc_setup(rdev);
376 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
382 void rs400_mc_program(struct radeon_device *rdev)
384 struct r100_mc_save save;
386 /* Stops all mc clients */
387 r100_mc_stop(rdev, &save);
389 /* Wait for mc idle */
390 if (rs400_mc_wait_for_idle(rdev))
391 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
392 WREG32(R_000148_MC_FB_LOCATION,
393 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
394 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
396 r100_mc_resume(rdev, &save);
399 static int rs400_startup(struct radeon_device *rdev)
403 rs400_mc_program(rdev);
405 r300_clock_startup(rdev);
406 /* Initialize GPU configuration (# pipes, ...) */
407 rs400_gpu_init(rdev);
408 r100_enable_bm(rdev);
409 /* Initialize GART (initialize after TTM so we can allocate
410 * memory through TTM but finalize after TTM) */
411 r = rs400_gart_enable(rdev);
416 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
418 r = r100_cp_init(rdev, 1024 * 1024);
420 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
423 r = r100_wb_init(rdev);
425 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
426 r = r100_ib_init(rdev);
428 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
434 int rs400_resume(struct radeon_device *rdev)
436 /* Make sur GART are not working */
437 rs400_gart_disable(rdev);
438 /* Resume clock before doing reset */
439 r300_clock_startup(rdev);
440 /* setup MC before calling post tables */
441 rs400_mc_program(rdev);
442 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
443 if (radeon_gpu_reset(rdev)) {
444 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
445 RREG32(R_000E40_RBBM_STATUS),
446 RREG32(R_0007C0_CP_STAT));
449 radeon_combios_asic_init(rdev->ddev);
450 /* Resume clock after posting */
451 r300_clock_startup(rdev);
452 /* Initialize surface registers */
453 radeon_surface_init(rdev);
454 return rs400_startup(rdev);
457 int rs400_suspend(struct radeon_device *rdev)
459 r100_cp_disable(rdev);
460 r100_wb_disable(rdev);
461 r100_irq_disable(rdev);
462 rs400_gart_disable(rdev);
466 void rs400_fini(struct radeon_device *rdev)
471 radeon_gem_fini(rdev);
472 rs400_gart_fini(rdev);
473 radeon_irq_kms_fini(rdev);
474 radeon_fence_driver_fini(rdev);
475 radeon_bo_fini(rdev);
476 radeon_atombios_fini(rdev);
481 int rs400_init(struct radeon_device *rdev)
486 r100_vga_render_disable(rdev);
487 /* Initialize scratch registers */
488 radeon_scratch_init(rdev);
489 /* Initialize surface registers */
490 radeon_surface_init(rdev);
491 /* TODO: disable VGA need to use VGA request */
493 if (!radeon_get_bios(rdev)) {
494 if (ASIC_IS_AVIVO(rdev))
497 if (rdev->is_atom_bios) {
498 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
501 r = radeon_combios_init(rdev);
505 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
506 if (radeon_gpu_reset(rdev)) {
508 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
509 RREG32(R_000E40_RBBM_STATUS),
510 RREG32(R_0007C0_CP_STAT));
512 /* check if cards are posted or not */
513 if (radeon_boot_test_post_card(rdev) == false)
516 /* Initialize clocks */
517 radeon_get_clock_info(rdev->ddev);
518 /* Initialize power management */
519 radeon_pm_init(rdev);
520 /* Get vram informations */
521 rs400_vram_info(rdev);
522 /* Initialize memory controller (also test AGP) */
523 r = rs400_mc_init(rdev);
527 r = radeon_fence_driver_init(rdev);
530 r = radeon_irq_kms_init(rdev);
534 r = radeon_bo_init(rdev);
537 r = rs400_gart_init(rdev);
540 r300_set_reg_safe(rdev);
541 rdev->accel_working = true;
542 r = rs400_startup(rdev);
544 /* Somethings want wront with the accel init stop accel */
545 dev_err(rdev->dev, "Disabling GPU acceleration\n");
549 rs400_gart_fini(rdev);
550 radeon_irq_kms_fini(rdev);
551 rdev->accel_working = false;