2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #include <linux/acpi.h>
29 #include <linux/power_supply.h>
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
34 #define RADEON_WAIT_IDLE_TIMEOUT 200
36 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
37 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
38 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
39 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
40 static void radeon_pm_update_profile(struct radeon_device *rdev);
41 static void radeon_pm_set_clocks(struct radeon_device *rdev);
43 #define ACPI_AC_CLASS "ac_adapter"
46 static int radeon_acpi_event(struct notifier_block *nb,
50 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
51 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
53 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
54 if (power_supply_is_system_supplied() > 0)
55 DRM_DEBUG("pm: AC\n");
57 DRM_DEBUG("pm: DC\n");
59 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
60 if (rdev->pm.profile == PM_PROFILE_AUTO) {
61 mutex_lock(&rdev->pm.mutex);
62 radeon_pm_update_profile(rdev);
63 radeon_pm_set_clocks(rdev);
64 mutex_unlock(&rdev->pm.mutex);
73 static void radeon_pm_update_profile(struct radeon_device *rdev)
75 switch (rdev->pm.profile) {
76 case PM_PROFILE_DEFAULT:
77 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
80 if (power_supply_is_system_supplied() > 0) {
81 if (rdev->pm.active_crtc_count > 1)
82 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
84 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
86 if (rdev->pm.active_crtc_count > 1)
87 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
89 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
93 if (rdev->pm.active_crtc_count > 1)
94 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
96 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
99 if (rdev->pm.active_crtc_count > 1)
100 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
102 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
104 case PM_PROFILE_HIGH:
105 if (rdev->pm.active_crtc_count > 1)
106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
112 if (rdev->pm.active_crtc_count == 0) {
113 rdev->pm.requested_power_state_index =
114 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
115 rdev->pm.requested_clock_mode_index =
116 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
118 rdev->pm.requested_power_state_index =
119 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
120 rdev->pm.requested_clock_mode_index =
121 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
125 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
127 struct radeon_bo *bo, *n;
129 if (list_empty(&rdev->gem.objects))
132 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
133 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
134 ttm_bo_unmap_virtual(&bo->tbo);
138 static void radeon_sync_with_vblank(struct radeon_device *rdev)
140 if (rdev->pm.active_crtcs) {
141 rdev->pm.vblank_sync = false;
143 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
144 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
148 static void radeon_set_power_state(struct radeon_device *rdev)
151 bool misc_after = false;
153 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
154 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
157 if (radeon_gui_idle(rdev)) {
158 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
159 clock_info[rdev->pm.requested_clock_mode_index].sclk;
160 if (sclk > rdev->clock.default_sclk)
161 sclk = rdev->clock.default_sclk;
163 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
164 clock_info[rdev->pm.requested_clock_mode_index].mclk;
165 if (mclk > rdev->clock.default_mclk)
166 mclk = rdev->clock.default_mclk;
168 /* upvolt before raising clocks, downvolt after lowering clocks */
169 if (sclk < rdev->pm.current_sclk)
172 radeon_sync_with_vblank(rdev);
174 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
175 if (!radeon_pm_in_vbl(rdev))
179 radeon_pm_prepare(rdev);
182 /* voltage, pcie lanes, etc.*/
183 radeon_pm_misc(rdev);
185 /* set engine clock */
186 if (sclk != rdev->pm.current_sclk) {
187 radeon_pm_debug_check_in_vbl(rdev, false);
188 radeon_set_engine_clock(rdev, sclk);
189 radeon_pm_debug_check_in_vbl(rdev, true);
190 rdev->pm.current_sclk = sclk;
191 DRM_DEBUG("Setting: e: %d\n", sclk);
194 /* set memory clock */
195 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
196 radeon_pm_debug_check_in_vbl(rdev, false);
197 radeon_set_memory_clock(rdev, mclk);
198 radeon_pm_debug_check_in_vbl(rdev, true);
199 rdev->pm.current_mclk = mclk;
200 DRM_DEBUG("Setting: m: %d\n", mclk);
204 /* voltage, pcie lanes, etc.*/
205 radeon_pm_misc(rdev);
207 radeon_pm_finish(rdev);
209 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
210 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
212 DRM_DEBUG("pm: GUI not idle!!!\n");
215 static void radeon_pm_set_clocks(struct radeon_device *rdev)
219 mutex_lock(&rdev->ddev->struct_mutex);
220 mutex_lock(&rdev->vram_mutex);
221 mutex_lock(&rdev->cp.mutex);
223 /* gui idle int has issues on older chips it seems */
224 if (rdev->family >= CHIP_R600) {
225 if (rdev->irq.installed) {
226 /* wait for GPU idle */
227 rdev->pm.gui_idle = false;
228 rdev->irq.gui_idle = true;
229 radeon_irq_set(rdev);
230 wait_event_interruptible_timeout(
231 rdev->irq.idle_queue, rdev->pm.gui_idle,
232 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
233 rdev->irq.gui_idle = false;
234 radeon_irq_set(rdev);
237 if (rdev->cp.ready) {
238 struct radeon_fence *fence;
239 radeon_ring_alloc(rdev, 64);
240 radeon_fence_create(rdev, &fence);
241 radeon_fence_emit(rdev, fence);
242 radeon_ring_commit(rdev);
243 radeon_fence_wait(fence, false);
244 radeon_fence_unref(&fence);
247 radeon_unmap_vram_bos(rdev);
249 if (rdev->irq.installed) {
250 for (i = 0; i < rdev->num_crtc; i++) {
251 if (rdev->pm.active_crtcs & (1 << i)) {
252 rdev->pm.req_vblank |= (1 << i);
253 drm_vblank_get(rdev->ddev, i);
258 radeon_set_power_state(rdev);
260 if (rdev->irq.installed) {
261 for (i = 0; i < rdev->num_crtc; i++) {
262 if (rdev->pm.req_vblank & (1 << i)) {
263 rdev->pm.req_vblank &= ~(1 << i);
264 drm_vblank_put(rdev->ddev, i);
269 /* update display watermarks based on new power state */
270 radeon_update_bandwidth_info(rdev);
271 if (rdev->pm.active_crtc_count)
272 radeon_bandwidth_update(rdev);
274 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
276 mutex_unlock(&rdev->cp.mutex);
277 mutex_unlock(&rdev->vram_mutex);
278 mutex_unlock(&rdev->ddev->struct_mutex);
281 static ssize_t radeon_get_pm_profile(struct device *dev,
282 struct device_attribute *attr,
285 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
286 struct radeon_device *rdev = ddev->dev_private;
287 int cp = rdev->pm.profile;
289 return snprintf(buf, PAGE_SIZE, "%s\n",
290 (cp == PM_PROFILE_AUTO) ? "auto" :
291 (cp == PM_PROFILE_LOW) ? "low" :
292 (cp == PM_PROFILE_HIGH) ? "high" : "default");
295 static ssize_t radeon_set_pm_profile(struct device *dev,
296 struct device_attribute *attr,
300 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
301 struct radeon_device *rdev = ddev->dev_private;
303 mutex_lock(&rdev->pm.mutex);
304 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
305 if (strncmp("default", buf, strlen("default")) == 0)
306 rdev->pm.profile = PM_PROFILE_DEFAULT;
307 else if (strncmp("auto", buf, strlen("auto")) == 0)
308 rdev->pm.profile = PM_PROFILE_AUTO;
309 else if (strncmp("low", buf, strlen("low")) == 0)
310 rdev->pm.profile = PM_PROFILE_LOW;
311 else if (strncmp("mid", buf, strlen("mid")) == 0)
312 rdev->pm.profile = PM_PROFILE_MID;
313 else if (strncmp("high", buf, strlen("high")) == 0)
314 rdev->pm.profile = PM_PROFILE_HIGH;
316 DRM_ERROR("invalid power profile!\n");
319 radeon_pm_update_profile(rdev);
320 radeon_pm_set_clocks(rdev);
323 mutex_unlock(&rdev->pm.mutex);
328 static ssize_t radeon_get_pm_method(struct device *dev,
329 struct device_attribute *attr,
332 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
333 struct radeon_device *rdev = ddev->dev_private;
334 int pm = rdev->pm.pm_method;
336 return snprintf(buf, PAGE_SIZE, "%s\n",
337 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
340 static ssize_t radeon_set_pm_method(struct device *dev,
341 struct device_attribute *attr,
345 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
346 struct radeon_device *rdev = ddev->dev_private;
349 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
350 mutex_lock(&rdev->pm.mutex);
351 rdev->pm.pm_method = PM_METHOD_DYNPM;
352 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
353 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
354 mutex_unlock(&rdev->pm.mutex);
355 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
356 mutex_lock(&rdev->pm.mutex);
357 rdev->pm.pm_method = PM_METHOD_PROFILE;
359 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
360 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
361 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
362 mutex_unlock(&rdev->pm.mutex);
364 DRM_ERROR("invalid power method!\n");
367 radeon_pm_compute_clocks(rdev);
372 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
373 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
375 void radeon_pm_suspend(struct radeon_device *rdev)
377 mutex_lock(&rdev->pm.mutex);
378 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
379 mutex_unlock(&rdev->pm.mutex);
382 void radeon_pm_resume(struct radeon_device *rdev)
384 /* asic init will reset the default power state */
385 mutex_lock(&rdev->pm.mutex);
386 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
387 rdev->pm.current_clock_mode_index = 0;
388 rdev->pm.current_sclk = rdev->clock.default_sclk;
389 rdev->pm.current_mclk = rdev->clock.default_mclk;
390 mutex_unlock(&rdev->pm.mutex);
391 radeon_pm_compute_clocks(rdev);
394 int radeon_pm_init(struct radeon_device *rdev)
397 /* default to profile method */
398 rdev->pm.pm_method = PM_METHOD_PROFILE;
399 rdev->pm.profile = PM_PROFILE_DEFAULT;
400 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
401 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
402 rdev->pm.dynpm_can_upclock = true;
403 rdev->pm.dynpm_can_downclock = true;
404 rdev->pm.current_sclk = rdev->clock.default_sclk;
405 rdev->pm.current_mclk = rdev->clock.default_mclk;
408 if (rdev->is_atom_bios)
409 radeon_atombios_get_power_modes(rdev);
411 radeon_combios_get_power_modes(rdev);
412 radeon_pm_init_profile(rdev);
415 if (rdev->pm.num_power_states > 1) {
416 /* where's the best place to put these? */
417 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
419 DRM_ERROR("failed to create device file for power profile\n");
420 ret = device_create_file(rdev->dev, &dev_attr_power_method);
422 DRM_ERROR("failed to create device file for power method\n");
425 rdev->acpi_nb.notifier_call = radeon_acpi_event;
426 register_acpi_notifier(&rdev->acpi_nb);
428 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
430 if (radeon_debugfs_pm_init(rdev)) {
431 DRM_ERROR("Failed to register debugfs file for PM!\n");
434 DRM_INFO("radeon: power management initialized\n");
440 void radeon_pm_fini(struct radeon_device *rdev)
442 if (rdev->pm.num_power_states > 1) {
443 mutex_lock(&rdev->pm.mutex);
444 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
445 rdev->pm.profile = PM_PROFILE_DEFAULT;
446 radeon_pm_update_profile(rdev);
447 radeon_pm_set_clocks(rdev);
448 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
450 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
451 /* reset default clocks */
452 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
453 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
454 radeon_pm_set_clocks(rdev);
456 mutex_unlock(&rdev->pm.mutex);
458 device_remove_file(rdev->dev, &dev_attr_power_profile);
459 device_remove_file(rdev->dev, &dev_attr_power_method);
461 unregister_acpi_notifier(&rdev->acpi_nb);
465 if (rdev->pm.i2c_bus)
466 radeon_i2c_destroy(rdev->pm.i2c_bus);
469 void radeon_pm_compute_clocks(struct radeon_device *rdev)
471 struct drm_device *ddev = rdev->ddev;
472 struct drm_crtc *crtc;
473 struct radeon_crtc *radeon_crtc;
475 if (rdev->pm.num_power_states < 2)
478 mutex_lock(&rdev->pm.mutex);
480 rdev->pm.active_crtcs = 0;
481 rdev->pm.active_crtc_count = 0;
482 list_for_each_entry(crtc,
483 &ddev->mode_config.crtc_list, head) {
484 radeon_crtc = to_radeon_crtc(crtc);
485 if (radeon_crtc->enabled) {
486 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
487 rdev->pm.active_crtc_count++;
491 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
492 radeon_pm_update_profile(rdev);
493 radeon_pm_set_clocks(rdev);
494 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
495 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
496 if (rdev->pm.active_crtc_count > 1) {
497 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
498 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
500 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
501 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
502 radeon_pm_get_dynpm_state(rdev);
503 radeon_pm_set_clocks(rdev);
505 DRM_DEBUG("radeon: dynamic power management deactivated\n");
507 } else if (rdev->pm.active_crtc_count == 1) {
508 /* TODO: Increase clocks if needed for current mode */
510 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
511 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
512 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
513 radeon_pm_get_dynpm_state(rdev);
514 radeon_pm_set_clocks(rdev);
516 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
517 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
518 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
519 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
520 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
521 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
522 DRM_DEBUG("radeon: dynamic power management activated\n");
524 } else { /* count == 0 */
525 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
526 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
528 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
529 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
530 radeon_pm_get_dynpm_state(rdev);
531 radeon_pm_set_clocks(rdev);
537 mutex_unlock(&rdev->pm.mutex);
540 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
542 u32 stat_crtc = 0, vbl = 0, position = 0;
545 if (ASIC_IS_DCE4(rdev)) {
546 if (rdev->pm.active_crtcs & (1 << 0)) {
547 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
548 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
549 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
550 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
552 if (rdev->pm.active_crtcs & (1 << 1)) {
553 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
554 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
555 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
556 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
558 if (rdev->pm.active_crtcs & (1 << 2)) {
559 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
560 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
561 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
562 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
564 if (rdev->pm.active_crtcs & (1 << 3)) {
565 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
566 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
567 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
568 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
570 if (rdev->pm.active_crtcs & (1 << 4)) {
571 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
572 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
573 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
574 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
576 if (rdev->pm.active_crtcs & (1 << 5)) {
577 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
578 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
579 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
580 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
582 } else if (ASIC_IS_AVIVO(rdev)) {
583 if (rdev->pm.active_crtcs & (1 << 0)) {
584 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
585 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
587 if (rdev->pm.active_crtcs & (1 << 1)) {
588 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
589 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
591 if (position < vbl && position > 1)
594 if (rdev->pm.active_crtcs & (1 << 0)) {
595 stat_crtc = RREG32(RADEON_CRTC_STATUS);
596 if (!(stat_crtc & 1))
599 if (rdev->pm.active_crtcs & (1 << 1)) {
600 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
601 if (!(stat_crtc & 1))
606 if (position < vbl && position > 1)
612 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
615 bool in_vbl = radeon_pm_in_vbl(rdev);
618 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
619 finish ? "exit" : "entry");
623 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
625 struct radeon_device *rdev;
627 rdev = container_of(work, struct radeon_device,
628 pm.dynpm_idle_work.work);
630 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
631 mutex_lock(&rdev->pm.mutex);
632 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
633 unsigned long irq_flags;
634 int not_processed = 0;
636 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
637 if (!list_empty(&rdev->fence_drv.emited)) {
638 struct list_head *ptr;
639 list_for_each(ptr, &rdev->fence_drv.emited) {
640 /* count up to 3, that's enought info */
641 if (++not_processed >= 3)
645 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
647 if (not_processed >= 3) { /* should upclock */
648 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
649 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
650 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
651 rdev->pm.dynpm_can_upclock) {
652 rdev->pm.dynpm_planned_action =
653 DYNPM_ACTION_UPCLOCK;
654 rdev->pm.dynpm_action_timeout = jiffies +
655 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
657 } else if (not_processed == 0) { /* should downclock */
658 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
659 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
660 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
661 rdev->pm.dynpm_can_downclock) {
662 rdev->pm.dynpm_planned_action =
663 DYNPM_ACTION_DOWNCLOCK;
664 rdev->pm.dynpm_action_timeout = jiffies +
665 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
669 /* Note, radeon_pm_set_clocks is called with static_switch set
670 * to false since we want to wait for vbl to avoid flicker.
672 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
673 jiffies > rdev->pm.dynpm_action_timeout) {
674 radeon_pm_get_dynpm_state(rdev);
675 radeon_pm_set_clocks(rdev);
678 mutex_unlock(&rdev->pm.mutex);
679 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
681 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
682 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
688 #if defined(CONFIG_DEBUG_FS)
690 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
692 struct drm_info_node *node = (struct drm_info_node *) m->private;
693 struct drm_device *dev = node->minor->dev;
694 struct radeon_device *rdev = dev->dev_private;
696 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
697 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
698 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
699 if (rdev->asic->get_memory_clock)
700 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
701 if (rdev->asic->get_pcie_lanes)
702 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
707 static struct drm_info_list radeon_pm_info_list[] = {
708 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
712 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
714 #if defined(CONFIG_DEBUG_FS)
715 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));