2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
26 #define RADEON_IDLE_LOOP_MS 100
27 #define RADEON_RECLOCK_DELAY_MS 200
29 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
30 static void radeon_pm_set_clocks(struct radeon_device *rdev);
31 static void radeon_pm_reclock_work_handler(struct work_struct *work);
32 static void radeon_pm_idle_work_handler(struct work_struct *work);
33 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
35 static const char *pm_state_names[4] = {
42 static const char *pm_state_types[5] = {
50 static void radeon_print_power_mode_info(struct radeon_device *rdev)
55 DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
56 for (i = 0; i < rdev->pm.num_power_states; i++) {
57 if (rdev->pm.default_power_state == &rdev->pm.power_state[i])
61 DRM_INFO("State %d %s %s\n", i,
62 pm_state_types[rdev->pm.power_state[i].type],
63 is_default ? "(default)" : "");
64 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
65 DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
66 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
67 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
68 if (rdev->flags & RADEON_IS_IGP)
69 DRM_INFO("\t\t%d engine: %d\n",
71 rdev->pm.power_state[i].clock_info[j].sclk * 10);
73 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
75 rdev->pm.power_state[i].clock_info[j].sclk * 10,
76 rdev->pm.power_state[i].clock_info[j].mclk * 10);
81 static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev,
82 enum radeon_pm_state_type type)
85 struct radeon_power_state *power_state = NULL;
88 case POWER_STATE_TYPE_DEFAULT:
90 return rdev->pm.default_power_state;
91 case POWER_STATE_TYPE_POWERSAVE:
92 for (i = 0; i < rdev->pm.num_power_states; i++) {
93 if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_POWERSAVE) {
94 power_state = &rdev->pm.power_state[i];
98 if (power_state == NULL) {
99 for (i = 0; i < rdev->pm.num_power_states; i++) {
100 if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY) {
101 power_state = &rdev->pm.power_state[i];
107 case POWER_STATE_TYPE_BATTERY:
108 for (i = 0; i < rdev->pm.num_power_states; i++) {
109 if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY) {
110 power_state = &rdev->pm.power_state[i];
114 if (power_state == NULL) {
115 for (i = 0; i < rdev->pm.num_power_states; i++) {
116 if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_POWERSAVE) {
117 power_state = &rdev->pm.power_state[i];
123 case POWER_STATE_TYPE_BALANCED:
124 case POWER_STATE_TYPE_PERFORMANCE:
125 for (i = 0; i < rdev->pm.num_power_states; i++) {
126 if (rdev->pm.power_state[i].type == type) {
127 power_state = &rdev->pm.power_state[i];
134 if (power_state == NULL)
135 return rdev->pm.default_power_state;
140 static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev,
141 struct radeon_power_state *power_state,
142 enum radeon_pm_clock_mode_type type)
145 case POWER_MODE_TYPE_DEFAULT:
147 return power_state->default_clock_mode;
148 case POWER_MODE_TYPE_LOW:
149 return &power_state->clock_info[0];
150 case POWER_MODE_TYPE_MID:
151 if (power_state->num_clock_modes > 2)
152 return &power_state->clock_info[1];
154 return &power_state->clock_info[0];
156 case POWER_MODE_TYPE_HIGH:
157 return &power_state->clock_info[power_state->num_clock_modes - 1];
162 static void radeon_get_power_state(struct radeon_device *rdev,
163 enum radeon_pm_action action)
168 rdev->pm.requested_power_state = rdev->pm.current_power_state;
169 rdev->pm.requested_power_state->requested_clock_mode =
170 rdev->pm.requested_power_state->current_clock_mode;
172 case PM_ACTION_MINIMUM:
173 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY);
174 rdev->pm.requested_power_state->requested_clock_mode =
175 radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW);
177 case PM_ACTION_DOWNCLOCK:
178 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE);
179 rdev->pm.requested_power_state->requested_clock_mode =
180 radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID);
182 case PM_ACTION_UPCLOCK:
183 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT);
184 rdev->pm.requested_power_state->requested_clock_mode =
185 radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH);
188 DRM_INFO("Requested: e: %d m: %d p: %d\n",
189 rdev->pm.requested_power_state->requested_clock_mode->sclk,
190 rdev->pm.requested_power_state->requested_clock_mode->mclk,
191 rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
194 static void radeon_set_power_state(struct radeon_device *rdev)
196 if (rdev->pm.requested_power_state == rdev->pm.current_power_state)
199 DRM_INFO("Setting: e: %d m: %d p: %d\n",
200 rdev->pm.requested_power_state->requested_clock_mode->sclk,
201 rdev->pm.requested_power_state->requested_clock_mode->mclk,
202 rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
205 /* set engine clock */
206 radeon_set_engine_clock(rdev, rdev->pm.requested_power_state->requested_clock_mode->sclk);
207 /* set memory clock */
209 rdev->pm.current_power_state = rdev->pm.requested_power_state;
212 int radeon_pm_init(struct radeon_device *rdev)
214 rdev->pm.state = PM_STATE_DISABLED;
215 rdev->pm.planned_action = PM_ACTION_NONE;
216 rdev->pm.downclocked = false;
217 rdev->pm.vblank_callback = false;
220 if (rdev->is_atom_bios)
221 radeon_atombios_get_power_modes(rdev);
223 radeon_combios_get_power_modes(rdev);
224 radeon_print_power_mode_info(rdev);
227 if (radeon_debugfs_pm_init(rdev)) {
228 DRM_ERROR("Failed to register debugfs file for PM!\n");
231 INIT_WORK(&rdev->pm.reclock_work, radeon_pm_reclock_work_handler);
232 INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
234 if (radeon_dynpm != -1 && radeon_dynpm) {
235 rdev->pm.state = PM_STATE_PAUSED;
236 DRM_INFO("radeon: dynamic power management enabled\n");
239 DRM_INFO("radeon: power management initialized\n");
244 void radeon_pm_compute_clocks(struct radeon_device *rdev)
246 struct drm_device *ddev = rdev->ddev;
247 struct drm_connector *connector;
248 struct radeon_crtc *radeon_crtc;
251 if (rdev->pm.state == PM_STATE_DISABLED)
254 mutex_lock(&rdev->pm.mutex);
256 rdev->pm.active_crtcs = 0;
257 list_for_each_entry(connector,
258 &ddev->mode_config.connector_list, head) {
259 if (connector->encoder &&
260 connector->dpms != DRM_MODE_DPMS_OFF) {
261 radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
262 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
268 if (rdev->pm.state == PM_STATE_ACTIVE) {
269 wait_queue_head_t wait;
270 init_waitqueue_head(&wait);
272 cancel_delayed_work(&rdev->pm.idle_work);
274 rdev->pm.state = PM_STATE_PAUSED;
275 rdev->pm.planned_action = PM_ACTION_UPCLOCK;
276 rdev->pm.vblank_callback = true;
278 mutex_unlock(&rdev->pm.mutex);
280 wait_event_timeout(wait, !rdev->pm.downclocked,
281 msecs_to_jiffies(300));
282 if (!rdev->pm.downclocked)
283 radeon_pm_set_clocks(rdev);
285 DRM_DEBUG("radeon: dynamic power management deactivated\n");
287 mutex_unlock(&rdev->pm.mutex);
289 } else if (count == 1) {
290 /* TODO: Increase clocks if needed for current mode */
292 if (rdev->pm.state == PM_STATE_MINIMUM) {
293 rdev->pm.state = PM_STATE_ACTIVE;
294 rdev->pm.planned_action = PM_ACTION_UPCLOCK;
295 radeon_pm_set_clocks_locked(rdev);
297 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
298 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
300 else if (rdev->pm.state == PM_STATE_PAUSED) {
301 rdev->pm.state = PM_STATE_ACTIVE;
302 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
303 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
304 DRM_DEBUG("radeon: dynamic power management activated\n");
307 mutex_unlock(&rdev->pm.mutex);
309 else { /* count == 0 */
310 if (rdev->pm.state != PM_STATE_MINIMUM) {
311 cancel_delayed_work(&rdev->pm.idle_work);
313 rdev->pm.state = PM_STATE_MINIMUM;
314 rdev->pm.planned_action = PM_ACTION_MINIMUM;
315 radeon_pm_set_clocks_locked(rdev);
318 mutex_unlock(&rdev->pm.mutex);
322 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
324 /*radeon_fence_wait_last(rdev);*/
325 switch (rdev->pm.planned_action) {
326 case PM_ACTION_UPCLOCK:
327 radeon_get_power_state(rdev, PM_ACTION_UPCLOCK);
328 rdev->pm.downclocked = false;
330 case PM_ACTION_DOWNCLOCK:
331 radeon_get_power_state(rdev, PM_ACTION_DOWNCLOCK);
332 rdev->pm.downclocked = true;
334 case PM_ACTION_MINIMUM:
335 radeon_get_power_state(rdev, PM_ACTION_MINIMUM);
338 radeon_get_power_state(rdev, PM_ACTION_NONE);
339 DRM_ERROR("%s: PM_ACTION_NONE\n", __func__);
342 radeon_set_power_state(rdev);
343 rdev->pm.planned_action = PM_ACTION_NONE;
346 static void radeon_pm_set_clocks(struct radeon_device *rdev)
348 mutex_lock(&rdev->pm.mutex);
349 /* new VBLANK irq may come before handling previous one */
350 if (rdev->pm.vblank_callback) {
351 mutex_lock(&rdev->cp.mutex);
352 if (rdev->pm.req_vblank & (1 << 0)) {
353 rdev->pm.req_vblank &= ~(1 << 0);
354 drm_vblank_put(rdev->ddev, 0);
356 if (rdev->pm.req_vblank & (1 << 1)) {
357 rdev->pm.req_vblank &= ~(1 << 1);
358 drm_vblank_put(rdev->ddev, 1);
360 rdev->pm.vblank_callback = false;
361 radeon_pm_set_clocks_locked(rdev);
362 mutex_unlock(&rdev->cp.mutex);
364 mutex_unlock(&rdev->pm.mutex);
367 static void radeon_pm_reclock_work_handler(struct work_struct *work)
369 struct radeon_device *rdev;
370 rdev = container_of(work, struct radeon_device,
372 radeon_pm_set_clocks(rdev);
375 static void radeon_pm_idle_work_handler(struct work_struct *work)
377 struct radeon_device *rdev;
378 rdev = container_of(work, struct radeon_device,
381 mutex_lock(&rdev->pm.mutex);
382 if (rdev->pm.state == PM_STATE_ACTIVE &&
383 !rdev->pm.vblank_callback) {
384 unsigned long irq_flags;
385 int not_processed = 0;
387 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
388 if (!list_empty(&rdev->fence_drv.emited)) {
389 struct list_head *ptr;
390 list_for_each(ptr, &rdev->fence_drv.emited) {
391 /* count up to 3, that's enought info */
392 if (++not_processed >= 3)
396 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
398 if (not_processed >= 3) { /* should upclock */
399 if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
400 rdev->pm.planned_action = PM_ACTION_NONE;
401 } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
402 rdev->pm.downclocked) {
403 rdev->pm.planned_action =
405 rdev->pm.action_timeout = jiffies +
406 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
408 } else if (not_processed == 0) { /* should downclock */
409 if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
410 rdev->pm.planned_action = PM_ACTION_NONE;
411 } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
412 !rdev->pm.downclocked) {
413 rdev->pm.planned_action =
415 rdev->pm.action_timeout = jiffies +
416 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
420 if (rdev->pm.planned_action != PM_ACTION_NONE &&
421 jiffies > rdev->pm.action_timeout) {
422 if (rdev->pm.active_crtcs & (1 << 0)) {
423 rdev->pm.req_vblank |= (1 << 0);
424 drm_vblank_get(rdev->ddev, 0);
426 if (rdev->pm.active_crtcs & (1 << 1)) {
427 rdev->pm.req_vblank |= (1 << 1);
428 drm_vblank_get(rdev->ddev, 1);
430 rdev->pm.vblank_callback = true;
433 mutex_unlock(&rdev->pm.mutex);
435 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
436 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
442 #if defined(CONFIG_DEBUG_FS)
444 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
446 struct drm_info_node *node = (struct drm_info_node *) m->private;
447 struct drm_device *dev = node->minor->dev;
448 struct radeon_device *rdev = dev->dev_private;
450 seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
451 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
452 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
453 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
454 if (rdev->asic->get_memory_clock)
455 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
460 static struct drm_info_list radeon_pm_info_list[] = {
461 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
465 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
467 #if defined(CONFIG_DEBUG_FS)
468 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));