SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25
  26 #define RADEON_IDLE_LOOP_MS 100
  27 #define RADEON_RECLOCK_DELAY_MS 200
  28 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  29
  30 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
  31 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  32 static void radeon_pm_idle_work_handler(struct work_struct *work);
  33 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  34
  35 static const char *pm_state_names[4] = {
  36         "PM_STATE_DISABLED",
  37         "PM_STATE_MINIMUM",
  38         "PM_STATE_PAUSED",
  39         "PM_STATE_ACTIVE"
  40 };
  41
  42 static const char *pm_state_types[5] = {
  43         "Default",
  44         "Powersave",
  45         "Battery",
  46         "Balanced",
  47         "Performance",
  48 };
  49
  50 static void radeon_print_power_mode_info(struct radeon_device *rdev)
  51 {
  52         int i, j;
  53         bool is_default;
  54
  55         DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
  56         for (i = 0; i < rdev->pm.num_power_states; i++) {
  57                 if (rdev->pm.default_power_state == &rdev->pm.power_state[i])
  58                         is_default = true;
  59                 else
  60                         is_default = false;
  61                 DRM_INFO("State %d %s %s\n", i,
  62                          pm_state_types[rdev->pm.power_state[i].type],
  63                          is_default ? "(default)" : "");
  64                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
  65                         DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
  66                 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
  67                 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
  68                         if (rdev->flags & RADEON_IS_IGP)
  69                                 DRM_INFO("\t\t%d engine: %d\n",
  70                                          j,
  71                                          rdev->pm.power_state[i].clock_info[j].sclk * 10);
  72                         else
  73                                 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
  74                                          j,
  75                                          rdev->pm.power_state[i].clock_info[j].sclk * 10,
  76                                          rdev->pm.power_state[i].clock_info[j].mclk * 10);
  77                 }
  78         }
  79 }
  80
  81 static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev,
  82                                                            enum radeon_pm_state_type type)
  83 {
  84         int i, j;
  85         enum radeon_pm_state_type wanted_types[2];
  86         int wanted_count;
  87
  88         switch (type) {
  89         case POWER_STATE_TYPE_DEFAULT:
  90         default:
  91                 return rdev->pm.default_power_state;
  92         case POWER_STATE_TYPE_POWERSAVE:
  93                 wanted_types[0] = POWER_STATE_TYPE_POWERSAVE;
  94                 wanted_types[1] = POWER_STATE_TYPE_BATTERY;
  95                 wanted_count = 2;
  96                 break;
  97         case POWER_STATE_TYPE_BATTERY:
  98                 wanted_types[0] = POWER_STATE_TYPE_BATTERY;
  99                 wanted_types[1] = POWER_STATE_TYPE_POWERSAVE;
 100                 wanted_count = 2;
 101                 break;
 102         case POWER_STATE_TYPE_BALANCED:
 103         case POWER_STATE_TYPE_PERFORMANCE:
 104                 wanted_types[0] = type;
 105                 wanted_count = 1;
 106                 break;
 107         }
 108
 109         for (i = 0; i < wanted_count; i++) {
 110                 for (j = 0; j < rdev->pm.num_power_states; j++) {
 111                         if (rdev->pm.power_state[j].type == wanted_types[i])
 112                                 return &rdev->pm.power_state[j];
 113                 }
 114         }
 115
 116         return rdev->pm.default_power_state;
 117 }
 118
 119 static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev,
 120                                                             struct radeon_power_state *power_state,
 121                                                             enum radeon_pm_clock_mode_type type)
 122 {
 123         switch (type) {
 124         case POWER_MODE_TYPE_DEFAULT:
 125         default:
 126                 return power_state->default_clock_mode;
 127         case POWER_MODE_TYPE_LOW:
 128                 return &power_state->clock_info[0];
 129         case POWER_MODE_TYPE_MID:
 130                 if (power_state->num_clock_modes > 2)
 131                         return &power_state->clock_info[1];
 132                 else
 133                         return &power_state->clock_info[0];
 134                 break;
 135         case POWER_MODE_TYPE_HIGH:
 136                 return &power_state->clock_info[power_state->num_clock_modes - 1];
 137         }
 138
 139 }
 140
 141 static void radeon_get_power_state(struct radeon_device *rdev,
 142                                    enum radeon_pm_action action)
 143 {
 144         switch (action) {
 145         case PM_ACTION_NONE:
 146         default:
 147                 rdev->pm.requested_power_state = rdev->pm.current_power_state;
 148                 rdev->pm.requested_power_state->requested_clock_mode =
 149                         rdev->pm.requested_power_state->current_clock_mode;
 150                 break;
 151         case PM_ACTION_MINIMUM:
 152                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY);
 153                 rdev->pm.requested_power_state->requested_clock_mode =
 154                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW);
 155                 break;
 156         case PM_ACTION_DOWNCLOCK:
 157                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE);
 158                 rdev->pm.requested_power_state->requested_clock_mode =
 159                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID);
 160                 break;
 161         case PM_ACTION_UPCLOCK:
 162                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT);
 163                 rdev->pm.requested_power_state->requested_clock_mode =
 164                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH);
 165                 break;
 166         }
 167         DRM_INFO("Requested: e: %d m: %d p: %d\n",
 168                  rdev->pm.requested_power_state->requested_clock_mode->sclk,
 169                  rdev->pm.requested_power_state->requested_clock_mode->mclk,
 170                  rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
 171 }
 172
 173 static void radeon_set_power_state(struct radeon_device *rdev)
 174 {
 175         if (rdev->pm.requested_power_state == rdev->pm.current_power_state)
 176                 return;
 177
 178         DRM_INFO("Setting: e: %d m: %d p: %d\n",
 179                  rdev->pm.requested_power_state->requested_clock_mode->sclk,
 180                  rdev->pm.requested_power_state->requested_clock_mode->mclk,
 181                  rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
 182         /* set pcie lanes */
 183         /* set voltage */
 184         /* set engine clock */
 185         radeon_set_engine_clock(rdev, rdev->pm.requested_power_state->requested_clock_mode->sclk);
 186         /* set memory clock */
 187
 188         rdev->pm.current_power_state = rdev->pm.requested_power_state;
 189 }
 190
 191 int radeon_pm_init(struct radeon_device *rdev)
 192 {
 193         rdev->pm.state = PM_STATE_DISABLED;
 194         rdev->pm.planned_action = PM_ACTION_NONE;
 195         rdev->pm.downclocked = false;
 196
 197         if (rdev->bios) {
 198                 if (rdev->is_atom_bios)
 199                         radeon_atombios_get_power_modes(rdev);
 200                 else
 201                         radeon_combios_get_power_modes(rdev);
 202                 radeon_print_power_mode_info(rdev);
 203         }
 204
 205         if (radeon_debugfs_pm_init(rdev)) {
 206                 DRM_ERROR("Failed to register debugfs file for PM!\n");
 207         }
 208
 209         INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
 210
 211         if (radeon_dynpm != -1 && radeon_dynpm) {
 212                 rdev->pm.state = PM_STATE_PAUSED;
 213                 DRM_INFO("radeon: dynamic power management enabled\n");
 214         }
 215
 216         DRM_INFO("radeon: power management initialized\n");
 217
 218         return 0;
 219 }
 220
 221 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 222 {
 223         struct drm_device *ddev = rdev->ddev;
 224         struct drm_connector *connector;
 225         struct radeon_crtc *radeon_crtc;
 226         int count = 0;
 227
 228         if (rdev->pm.state == PM_STATE_DISABLED)
 229                 return;
 230
 231         mutex_lock(&rdev->pm.mutex);
 232
 233         rdev->pm.active_crtcs = 0;
 234         list_for_each_entry(connector,
 235                 &ddev->mode_config.connector_list, head) {
 236                 if (connector->encoder &&
 237                         connector->dpms != DRM_MODE_DPMS_OFF) {
 238                         radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
 239                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 240                         ++count;
 241                 }
 242         }
 243
 244         if (count > 1) {
 245                 if (rdev->pm.state == PM_STATE_ACTIVE) {
 246                         cancel_delayed_work(&rdev->pm.idle_work);
 247
 248                         rdev->pm.state = PM_STATE_PAUSED;
 249                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 250                         if (rdev->pm.downclocked)
 251                                 radeon_pm_set_clocks(rdev);
 252
 253                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 254                 }
 255         } else if (count == 1) {
 256                 /* TODO: Increase clocks if needed for current mode */
 257
 258                 if (rdev->pm.state == PM_STATE_MINIMUM) {
 259                         rdev->pm.state = PM_STATE_ACTIVE;
 260                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 261                         radeon_pm_set_clocks(rdev);
 262
 263                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 264                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 265                 }
 266                 else if (rdev->pm.state == PM_STATE_PAUSED) {
 267                         rdev->pm.state = PM_STATE_ACTIVE;
 268                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 269                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 270                         DRM_DEBUG("radeon: dynamic power management activated\n");
 271                 }
 272         }
 273         else { /* count == 0 */
 274                 if (rdev->pm.state != PM_STATE_MINIMUM) {
 275                         cancel_delayed_work(&rdev->pm.idle_work);
 276
 277                         rdev->pm.state = PM_STATE_MINIMUM;
 278                         rdev->pm.planned_action = PM_ACTION_MINIMUM;
 279                         radeon_pm_set_clocks(rdev);
 280                 }
 281         }
 282
 283         mutex_unlock(&rdev->pm.mutex);
 284 }
 285
 286 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
 287 {
 288         /*radeon_fence_wait_last(rdev);*/
 289         switch (rdev->pm.planned_action) {
 290         case PM_ACTION_UPCLOCK:
 291                 rdev->pm.downclocked = false;
 292                 break;
 293         case PM_ACTION_DOWNCLOCK:
 294                 rdev->pm.downclocked = true;
 295                 break;
 296         case PM_ACTION_MINIMUM:
 297                 break;
 298         case PM_ACTION_NONE:
 299                 DRM_ERROR("%s: PM_ACTION_NONE\n", __func__);
 300                 break;
 301         }
 302         radeon_set_power_state(rdev);
 303         rdev->pm.planned_action = PM_ACTION_NONE;
 304 }
 305
 306 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 307 {
 308         radeon_get_power_state(rdev, rdev->pm.planned_action);
 309         mutex_lock(&rdev->cp.mutex);
 310
 311         if (rdev->pm.active_crtcs & (1 << 0)) {
 312                 rdev->pm.req_vblank |= (1 << 0);
 313                 drm_vblank_get(rdev->ddev, 0);
 314         }
 315         if (rdev->pm.active_crtcs & (1 << 1)) {
 316                 rdev->pm.req_vblank |= (1 << 1);
 317                 drm_vblank_get(rdev->ddev, 1);
 318         }
 319         if (rdev->pm.active_crtcs)
 320                 wait_event_interruptible_timeout(
 321                         rdev->irq.vblank_queue, 0,
 322                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 323         if (rdev->pm.req_vblank & (1 << 0)) {
 324                 rdev->pm.req_vblank &= ~(1 << 0);
 325                 drm_vblank_put(rdev->ddev, 0);
 326         }
 327         if (rdev->pm.req_vblank & (1 << 1)) {
 328                 rdev->pm.req_vblank &= ~(1 << 1);
 329                 drm_vblank_put(rdev->ddev, 1);
 330         }
 331
 332         radeon_pm_set_clocks_locked(rdev);
 333         mutex_unlock(&rdev->cp.mutex);
 334 }
 335
 336 static void radeon_pm_idle_work_handler(struct work_struct *work)
 337 {
 338         struct radeon_device *rdev;
 339         rdev = container_of(work, struct radeon_device,
 340                                 pm.idle_work.work);
 341
 342         mutex_lock(&rdev->pm.mutex);
 343         if (rdev->pm.state == PM_STATE_ACTIVE) {
 344                 unsigned long irq_flags;
 345                 int not_processed = 0;
 346
 347                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 348                 if (!list_empty(&rdev->fence_drv.emited)) {
 349                         struct list_head *ptr;
 350                         list_for_each(ptr, &rdev->fence_drv.emited) {
 351                                 /* count up to 3, that's enought info */
 352                                 if (++not_processed >= 3)
 353                                         break;
 354                         }
 355                 }
 356                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 357
 358                 if (not_processed >= 3) { /* should upclock */
 359                         if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
 360                                 rdev->pm.planned_action = PM_ACTION_NONE;
 361                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 362                                 rdev->pm.downclocked) {
 363                                 rdev->pm.planned_action =
 364                                         PM_ACTION_UPCLOCK;
 365                                 rdev->pm.action_timeout = jiffies +
 366                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 367                         }
 368                 } else if (not_processed == 0) { /* should downclock */
 369                         if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
 370                                 rdev->pm.planned_action = PM_ACTION_NONE;
 371                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 372                                 !rdev->pm.downclocked) {
 373                                 rdev->pm.planned_action =
 374                                         PM_ACTION_DOWNCLOCK;
 375                                 rdev->pm.action_timeout = jiffies +
 376                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 377                         }
 378                 }
 379
 380                 if (rdev->pm.planned_action != PM_ACTION_NONE &&
 381                     jiffies > rdev->pm.action_timeout) {
 382                         radeon_pm_set_clocks(rdev);
 383                 }
 384         }
 385         mutex_unlock(&rdev->pm.mutex);
 386
 387         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 388                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 389 }
 390
 391 /*
 392  * Debugfs info
 393  */
 394 #if defined(CONFIG_DEBUG_FS)
 395
 396 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 397 {
 398         struct drm_info_node *node = (struct drm_info_node *) m->private;
 399         struct drm_device *dev = node->minor->dev;
 400         struct radeon_device *rdev = dev->dev_private;
 401
 402         seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
 403         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 404         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 405         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 406         if (rdev->asic->get_memory_clock)
 407                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 408
 409         return 0;
 410 }
 411
 412 static struct drm_info_list radeon_pm_info_list[] = {
 413         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 414 };
 415 #endif
 416
 417 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 418 {
 419 #if defined(CONFIG_DEBUG_FS)
 420         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 421 #else
 422         return 0;
 423 #endif
 424 }