SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25
  26 #define RADEON_IDLE_LOOP_MS 100
  27 #define RADEON_RECLOCK_DELAY_MS 200
  28 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  29
  30 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
  31 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  32 static void radeon_pm_idle_work_handler(struct work_struct *work);
  33 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  34
  35 static const char *pm_state_names[4] = {
  36         "PM_STATE_DISABLED",
  37         "PM_STATE_MINIMUM",
  38         "PM_STATE_PAUSED",
  39         "PM_STATE_ACTIVE"
  40 };
  41
  42 static const char *pm_state_types[5] = {
  43         "Default",
  44         "Powersave",
  45         "Battery",
  46         "Balanced",
  47         "Performance",
  48 };
  49
  50 static void radeon_print_power_mode_info(struct radeon_device *rdev)
  51 {
  52         int i, j;
  53         bool is_default;
  54
  55         DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
  56         for (i = 0; i < rdev->pm.num_power_states; i++) {
  57                 if (rdev->pm.default_power_state == &rdev->pm.power_state[i])
  58                         is_default = true;
  59                 else
  60                         is_default = false;
  61                 DRM_INFO("State %d %s %s\n", i,
  62                          pm_state_types[rdev->pm.power_state[i].type],
  63                          is_default ? "(default)" : "");
  64                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
  65                         DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
  66                 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
  67                 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
  68                         if (rdev->flags & RADEON_IS_IGP)
  69                                 DRM_INFO("\t\t%d engine: %d\n",
  70                                          j,
  71                                          rdev->pm.power_state[i].clock_info[j].sclk * 10);
  72                         else
  73                                 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
  74                                          j,
  75                                          rdev->pm.power_state[i].clock_info[j].sclk * 10,
  76                                          rdev->pm.power_state[i].clock_info[j].mclk * 10);
  77                 }
  78         }
  79 }
  80
  81 static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev,
  82                                                            enum radeon_pm_state_type type)
  83 {
  84         int i;
  85         struct radeon_power_state *power_state = NULL;
  86
  87         switch (type) {
  88         case POWER_STATE_TYPE_DEFAULT:
  89         default:
  90                 return rdev->pm.default_power_state;
  91         case POWER_STATE_TYPE_POWERSAVE:
  92                 for (i = 0; i < rdev->pm.num_power_states; i++) {
  93                         if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_POWERSAVE) {
  94                                 power_state = &rdev->pm.power_state[i];
  95                                 break;
  96                         }
  97                 }
  98                 if (power_state == NULL) {
  99                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 100                                 if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY) {
 101                                         power_state = &rdev->pm.power_state[i];
 102                                         break;
 103                                 }
 104                         }
 105                 }
 106                 break;
 107         case POWER_STATE_TYPE_BATTERY:
 108                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 109                         if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY) {
 110                                 power_state = &rdev->pm.power_state[i];
 111                                 break;
 112                         }
 113                 }
 114                 if (power_state == NULL) {
 115                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 116                                 if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_POWERSAVE) {
 117                                         power_state = &rdev->pm.power_state[i];
 118                                         break;
 119                                 }
 120                         }
 121                 }
 122                 break;
 123         case POWER_STATE_TYPE_BALANCED:
 124         case POWER_STATE_TYPE_PERFORMANCE:
 125                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 126                         if (rdev->pm.power_state[i].type == type) {
 127                                 power_state = &rdev->pm.power_state[i];
 128                                 break;
 129                         }
 130                 }
 131                 break;
 132         }
 133
 134         if (power_state == NULL)
 135                 return rdev->pm.default_power_state;
 136
 137         return power_state;
 138 }
 139
 140 static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev,
 141                                                             struct radeon_power_state *power_state,
 142                                                             enum radeon_pm_clock_mode_type type)
 143 {
 144         switch (type) {
 145         case POWER_MODE_TYPE_DEFAULT:
 146         default:
 147                 return power_state->default_clock_mode;
 148         case POWER_MODE_TYPE_LOW:
 149                 return &power_state->clock_info[0];
 150         case POWER_MODE_TYPE_MID:
 151                 if (power_state->num_clock_modes > 2)
 152                         return &power_state->clock_info[1];
 153                 else
 154                         return &power_state->clock_info[0];
 155                 break;
 156         case POWER_MODE_TYPE_HIGH:
 157                 return &power_state->clock_info[power_state->num_clock_modes - 1];
 158         }
 159
 160 }
 161
 162 static void radeon_get_power_state(struct radeon_device *rdev,
 163                                    enum radeon_pm_action action)
 164 {
 165         switch (action) {
 166         case PM_ACTION_NONE:
 167         default:
 168                 rdev->pm.requested_power_state = rdev->pm.current_power_state;
 169                 rdev->pm.requested_power_state->requested_clock_mode =
 170                         rdev->pm.requested_power_state->current_clock_mode;
 171                 break;
 172         case PM_ACTION_MINIMUM:
 173                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY);
 174                 rdev->pm.requested_power_state->requested_clock_mode =
 175                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW);
 176                 break;
 177         case PM_ACTION_DOWNCLOCK:
 178                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE);
 179                 rdev->pm.requested_power_state->requested_clock_mode =
 180                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID);
 181                 break;
 182         case PM_ACTION_UPCLOCK:
 183                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT);
 184                 rdev->pm.requested_power_state->requested_clock_mode =
 185                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH);
 186                 break;
 187         }
 188         DRM_INFO("Requested: e: %d m: %d p: %d\n",
 189                  rdev->pm.requested_power_state->requested_clock_mode->sclk,
 190                  rdev->pm.requested_power_state->requested_clock_mode->mclk,
 191                  rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
 192 }
 193
 194 static void radeon_set_power_state(struct radeon_device *rdev)
 195 {
 196         if (rdev->pm.requested_power_state == rdev->pm.current_power_state)
 197                 return;
 198
 199         DRM_INFO("Setting: e: %d m: %d p: %d\n",
 200                  rdev->pm.requested_power_state->requested_clock_mode->sclk,
 201                  rdev->pm.requested_power_state->requested_clock_mode->mclk,
 202                  rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
 203         /* set pcie lanes */
 204         /* set voltage */
 205         /* set engine clock */
 206         radeon_set_engine_clock(rdev, rdev->pm.requested_power_state->requested_clock_mode->sclk);
 207         /* set memory clock */
 208
 209         rdev->pm.current_power_state = rdev->pm.requested_power_state;
 210 }
 211
 212 int radeon_pm_init(struct radeon_device *rdev)
 213 {
 214         rdev->pm.state = PM_STATE_DISABLED;
 215         rdev->pm.planned_action = PM_ACTION_NONE;
 216         rdev->pm.downclocked = false;
 217
 218         if (rdev->bios) {
 219                 if (rdev->is_atom_bios)
 220                         radeon_atombios_get_power_modes(rdev);
 221                 else
 222                         radeon_combios_get_power_modes(rdev);
 223                 radeon_print_power_mode_info(rdev);
 224         }
 225
 226         if (radeon_debugfs_pm_init(rdev)) {
 227                 DRM_ERROR("Failed to register debugfs file for PM!\n");
 228         }
 229
 230         INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
 231
 232         if (radeon_dynpm != -1 && radeon_dynpm) {
 233                 rdev->pm.state = PM_STATE_PAUSED;
 234                 DRM_INFO("radeon: dynamic power management enabled\n");
 235         }
 236
 237         DRM_INFO("radeon: power management initialized\n");
 238
 239         return 0;
 240 }
 241
 242 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 243 {
 244         struct drm_device *ddev = rdev->ddev;
 245         struct drm_connector *connector;
 246         struct radeon_crtc *radeon_crtc;
 247         int count = 0;
 248
 249         if (rdev->pm.state == PM_STATE_DISABLED)
 250                 return;
 251
 252         mutex_lock(&rdev->pm.mutex);
 253
 254         rdev->pm.active_crtcs = 0;
 255         list_for_each_entry(connector,
 256                 &ddev->mode_config.connector_list, head) {
 257                 if (connector->encoder &&
 258                         connector->dpms != DRM_MODE_DPMS_OFF) {
 259                         radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
 260                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 261                         ++count;
 262                 }
 263         }
 264
 265         if (count > 1) {
 266                 if (rdev->pm.state == PM_STATE_ACTIVE) {
 267                         cancel_delayed_work(&rdev->pm.idle_work);
 268
 269                         rdev->pm.state = PM_STATE_PAUSED;
 270                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 271                         if (rdev->pm.downclocked)
 272                                 radeon_pm_set_clocks(rdev);
 273
 274                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 275                 }
 276         } else if (count == 1) {
 277                 /* TODO: Increase clocks if needed for current mode */
 278
 279                 if (rdev->pm.state == PM_STATE_MINIMUM) {
 280                         rdev->pm.state = PM_STATE_ACTIVE;
 281                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 282                         radeon_pm_set_clocks(rdev);
 283
 284                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 285                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 286                 }
 287                 else if (rdev->pm.state == PM_STATE_PAUSED) {
 288                         rdev->pm.state = PM_STATE_ACTIVE;
 289                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 290                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 291                         DRM_DEBUG("radeon: dynamic power management activated\n");
 292                 }
 293         }
 294         else { /* count == 0 */
 295                 if (rdev->pm.state != PM_STATE_MINIMUM) {
 296                         cancel_delayed_work(&rdev->pm.idle_work);
 297
 298                         rdev->pm.state = PM_STATE_MINIMUM;
 299                         rdev->pm.planned_action = PM_ACTION_MINIMUM;
 300                         radeon_pm_set_clocks(rdev);
 301                 }
 302         }
 303
 304         mutex_unlock(&rdev->pm.mutex);
 305 }
 306
 307 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
 308 {
 309         /*radeon_fence_wait_last(rdev);*/
 310         switch (rdev->pm.planned_action) {
 311         case PM_ACTION_UPCLOCK:
 312                 rdev->pm.downclocked = false;
 313                 break;
 314         case PM_ACTION_DOWNCLOCK:
 315                 rdev->pm.downclocked = true;
 316                 break;
 317         case PM_ACTION_MINIMUM:
 318                 break;
 319         case PM_ACTION_NONE:
 320                 DRM_ERROR("%s: PM_ACTION_NONE\n", __func__);
 321                 break;
 322         }
 323         radeon_set_power_state(rdev);
 324         rdev->pm.planned_action = PM_ACTION_NONE;
 325 }
 326
 327 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 328 {
 329         radeon_get_power_state(rdev, rdev->pm.planned_action);
 330         mutex_lock(&rdev->cp.mutex);
 331
 332         if (rdev->pm.active_crtcs & (1 << 0)) {
 333                 rdev->pm.req_vblank |= (1 << 0);
 334                 drm_vblank_get(rdev->ddev, 0);
 335         }
 336         if (rdev->pm.active_crtcs & (1 << 1)) {
 337                 rdev->pm.req_vblank |= (1 << 1);
 338                 drm_vblank_get(rdev->ddev, 1);
 339         }
 340         if (rdev->pm.active_crtcs)
 341                 wait_event_interruptible_timeout(
 342                         rdev->irq.vblank_queue, 0,
 343                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 344         if (rdev->pm.req_vblank & (1 << 0)) {
 345                 rdev->pm.req_vblank &= ~(1 << 0);
 346                 drm_vblank_put(rdev->ddev, 0);
 347         }
 348         if (rdev->pm.req_vblank & (1 << 1)) {
 349                 rdev->pm.req_vblank &= ~(1 << 1);
 350                 drm_vblank_put(rdev->ddev, 1);
 351         }
 352
 353         radeon_pm_set_clocks_locked(rdev);
 354         mutex_unlock(&rdev->cp.mutex);
 355 }
 356
 357 static void radeon_pm_idle_work_handler(struct work_struct *work)
 358 {
 359         struct radeon_device *rdev;
 360         rdev = container_of(work, struct radeon_device,
 361                                 pm.idle_work.work);
 362
 363         mutex_lock(&rdev->pm.mutex);
 364         if (rdev->pm.state == PM_STATE_ACTIVE) {
 365                 unsigned long irq_flags;
 366                 int not_processed = 0;
 367
 368                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 369                 if (!list_empty(&rdev->fence_drv.emited)) {
 370                         struct list_head *ptr;
 371                         list_for_each(ptr, &rdev->fence_drv.emited) {
 372                                 /* count up to 3, that's enought info */
 373                                 if (++not_processed >= 3)
 374                                         break;
 375                         }
 376                 }
 377                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 378
 379                 if (not_processed >= 3) { /* should upclock */
 380                         if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
 381                                 rdev->pm.planned_action = PM_ACTION_NONE;
 382                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 383                                 rdev->pm.downclocked) {
 384                                 rdev->pm.planned_action =
 385                                         PM_ACTION_UPCLOCK;
 386                                 rdev->pm.action_timeout = jiffies +
 387                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 388                         }
 389                 } else if (not_processed == 0) { /* should downclock */
 390                         if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
 391                                 rdev->pm.planned_action = PM_ACTION_NONE;
 392                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 393                                 !rdev->pm.downclocked) {
 394                                 rdev->pm.planned_action =
 395                                         PM_ACTION_DOWNCLOCK;
 396                                 rdev->pm.action_timeout = jiffies +
 397                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 398                         }
 399                 }
 400
 401                 if (rdev->pm.planned_action != PM_ACTION_NONE &&
 402                     jiffies > rdev->pm.action_timeout) {
 403                         radeon_pm_set_clocks(rdev);
 404                 }
 405         }
 406         mutex_unlock(&rdev->pm.mutex);
 407
 408         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 409                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 410 }
 411
 412 /*
 413  * Debugfs info
 414  */
 415 #if defined(CONFIG_DEBUG_FS)
 416
 417 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 418 {
 419         struct drm_info_node *node = (struct drm_info_node *) m->private;
 420         struct drm_device *dev = node->minor->dev;
 421         struct radeon_device *rdev = dev->dev_private;
 422
 423         seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
 424         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 425         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 426         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 427         if (rdev->asic->get_memory_clock)
 428                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 429
 430         return 0;
 431 }
 432
 433 static struct drm_info_list radeon_pm_info_list[] = {
 434         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 435 };
 436 #endif
 437
 438 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 439 {
 440 #if defined(CONFIG_DEBUG_FS)
 441         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 442 #else
 443         return 0;
 444 #endif
 445 }