SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26
  27 #define RADEON_IDLE_LOOP_MS 100
  28 #define RADEON_RECLOCK_DELAY_MS 200
  29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  30 #define RADEON_WAIT_IDLE_TIMEOUT 200
  31
  32 static void radeon_pm_idle_work_handler(struct work_struct *work);
  33 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  34
  35 static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
  36 {
  37         int i;
  38
  39         mutex_lock(&rdev->cp.mutex);
  40
  41         /* wait for GPU idle */
  42         rdev->pm.gui_idle = false;
  43         rdev->irq.gui_idle = true;
  44         radeon_irq_set(rdev);
  45         wait_event_interruptible_timeout(
  46                 rdev->irq.idle_queue, rdev->pm.gui_idle,
  47                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
  48         rdev->irq.gui_idle = false;
  49         radeon_irq_set(rdev);
  50
  51         if (!static_switch) {
  52                 for (i = 0; i < rdev->num_crtc; i++) {
  53                         if (rdev->pm.active_crtcs & (1 << i)) {
  54                                 rdev->pm.req_vblank |= (1 << i);
  55                                 drm_vblank_get(rdev->ddev, i);
  56                         }
  57                 }
  58         }
  59
  60         radeon_set_power_state(rdev, static_switch);
  61
  62         if (!static_switch) {
  63                 for (i = 0; i < rdev->num_crtc; i++) {
  64                         if (rdev->pm.req_vblank & (1 << i)) {
  65                                 rdev->pm.req_vblank &= ~(1 << i);
  66                                 drm_vblank_put(rdev->ddev, i);
  67                         }
  68                 }
  69         }
  70
  71         /* update display watermarks based on new power state */
  72         radeon_update_bandwidth_info(rdev);
  73         if (rdev->pm.active_crtc_count)
  74                 radeon_bandwidth_update(rdev);
  75
  76         rdev->pm.planned_action = PM_ACTION_NONE;
  77
  78         mutex_unlock(&rdev->cp.mutex);
  79 }
  80
  81 static ssize_t radeon_get_power_state_static(struct device *dev,
  82                                              struct device_attribute *attr,
  83                                              char *buf)
  84 {
  85         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  86         struct radeon_device *rdev = ddev->dev_private;
  87
  88         return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
  89                         rdev->pm.current_clock_mode_index);
  90 }
  91
  92 static ssize_t radeon_set_power_state_static(struct device *dev,
  93                                              struct device_attribute *attr,
  94                                              const char *buf,
  95                                              size_t count)
  96 {
  97         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  98         struct radeon_device *rdev = ddev->dev_private;
  99         int ps, cm;
 100
 101         if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
 102                 DRM_ERROR("Invalid power state!\n");
 103                 return count;
 104         }
 105
 106         mutex_lock(&rdev->pm.mutex);
 107         if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
 108             (cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
 109                 if ((rdev->pm.active_crtc_count > 1) &&
 110                     (rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) {
 111                         DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
 112                 } else {
 113                         /* disable dynpm */
 114                         rdev->pm.state = PM_STATE_DISABLED;
 115                         rdev->pm.planned_action = PM_ACTION_NONE;
 116                         rdev->pm.requested_power_state_index = ps;
 117                         rdev->pm.requested_clock_mode_index = cm;
 118                         radeon_pm_set_clocks(rdev, true);
 119                 }
 120         } else
 121                 DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
 122         mutex_unlock(&rdev->pm.mutex);
 123
 124         return count;
 125 }
 126
 127 static ssize_t radeon_get_dynpm(struct device *dev,
 128                                 struct device_attribute *attr,
 129                                 char *buf)
 130 {
 131         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 132         struct radeon_device *rdev = ddev->dev_private;
 133
 134         return snprintf(buf, PAGE_SIZE, "%s\n",
 135                         (rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
 136 }
 137
 138 static ssize_t radeon_set_dynpm(struct device *dev,
 139                                 struct device_attribute *attr,
 140                                 const char *buf,
 141                                 size_t count)
 142 {
 143         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 144         struct radeon_device *rdev = ddev->dev_private;
 145         int tmp = simple_strtoul(buf, NULL, 10);
 146
 147         if (tmp == 0) {
 148                 /* update power mode info */
 149                 radeon_pm_compute_clocks(rdev);
 150                 /* disable dynpm */
 151                 mutex_lock(&rdev->pm.mutex);
 152                 rdev->pm.state = PM_STATE_DISABLED;
 153                 rdev->pm.planned_action = PM_ACTION_NONE;
 154                 mutex_unlock(&rdev->pm.mutex);
 155                 DRM_INFO("radeon: dynamic power management disabled\n");
 156         } else if (tmp == 1) {
 157                 if (rdev->pm.num_power_states > 1) {
 158                         /* enable dynpm */
 159                         mutex_lock(&rdev->pm.mutex);
 160                         rdev->pm.state = PM_STATE_PAUSED;
 161                         rdev->pm.planned_action = PM_ACTION_DEFAULT;
 162                         radeon_get_power_state(rdev, rdev->pm.planned_action);
 163                         mutex_unlock(&rdev->pm.mutex);
 164                         /* update power mode info */
 165                         radeon_pm_compute_clocks(rdev);
 166                         DRM_INFO("radeon: dynamic power management enabled\n");
 167                 } else
 168                         DRM_ERROR("dynpm not valid on this system\n");
 169         } else
 170                 DRM_ERROR("Invalid setting: %d\n", tmp);
 171
 172         return count;
 173 }
 174
 175 static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
 176 static DEVICE_ATTR(dynpm, S_IRUGO | S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);
 177
 178
 179 static const char *pm_state_names[4] = {
 180         "PM_STATE_DISABLED",
 181         "PM_STATE_MINIMUM",
 182         "PM_STATE_PAUSED",
 183         "PM_STATE_ACTIVE"
 184 };
 185
 186 static const char *pm_state_types[5] = {
 187         "",
 188         "Powersave",
 189         "Battery",
 190         "Balanced",
 191         "Performance",
 192 };
 193
 194 static void radeon_print_power_mode_info(struct radeon_device *rdev)
 195 {
 196         int i, j;
 197         bool is_default;
 198
 199         DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
 200         for (i = 0; i < rdev->pm.num_power_states; i++) {
 201                 if (rdev->pm.default_power_state_index == i)
 202                         is_default = true;
 203                 else
 204                         is_default = false;
 205                 DRM_INFO("State %d %s %s\n", i,
 206                          pm_state_types[rdev->pm.power_state[i].type],
 207                          is_default ? "(default)" : "");
 208                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 209                         DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
 210                 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 211                         DRM_INFO("\tSingle display only\n");
 212                 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
 213                 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
 214                         if (rdev->flags & RADEON_IS_IGP)
 215                                 DRM_INFO("\t\t%d engine: %d\n",
 216                                          j,
 217                                          rdev->pm.power_state[i].clock_info[j].sclk * 10);
 218                         else
 219                                 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
 220                                          j,
 221                                          rdev->pm.power_state[i].clock_info[j].sclk * 10,
 222                                          rdev->pm.power_state[i].clock_info[j].mclk * 10);
 223                 }
 224         }
 225 }
 226
 227 void radeon_sync_with_vblank(struct radeon_device *rdev)
 228 {
 229         if (rdev->pm.active_crtcs) {
 230                 rdev->pm.vblank_sync = false;
 231                 wait_event_timeout(
 232                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 233                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 234         }
 235 }
 236
 237 int radeon_pm_init(struct radeon_device *rdev)
 238 {
 239         rdev->pm.state = PM_STATE_DISABLED;
 240         rdev->pm.planned_action = PM_ACTION_NONE;
 241         rdev->pm.can_upclock = true;
 242         rdev->pm.can_downclock = true;
 243
 244         if (rdev->bios) {
 245                 if (rdev->is_atom_bios)
 246                         radeon_atombios_get_power_modes(rdev);
 247                 else
 248                         radeon_combios_get_power_modes(rdev);
 249                 radeon_print_power_mode_info(rdev);
 250         }
 251
 252         if (radeon_debugfs_pm_init(rdev)) {
 253                 DRM_ERROR("Failed to register debugfs file for PM!\n");
 254         }
 255
 256         /* where's the best place to put this? */
 257         device_create_file(rdev->dev, &dev_attr_power_state);
 258         device_create_file(rdev->dev, &dev_attr_dynpm);
 259
 260         INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
 261
 262         if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
 263                 rdev->pm.state = PM_STATE_PAUSED;
 264                 DRM_INFO("radeon: dynamic power management enabled\n");
 265         }
 266
 267         DRM_INFO("radeon: power management initialized\n");
 268
 269         return 0;
 270 }
 271
 272 void radeon_pm_fini(struct radeon_device *rdev)
 273 {
 274         if (rdev->pm.state != PM_STATE_DISABLED) {
 275                 /* cancel work */
 276                 cancel_delayed_work_sync(&rdev->pm.idle_work);
 277                 /* reset default clocks */
 278                 rdev->pm.state = PM_STATE_DISABLED;
 279                 rdev->pm.planned_action = PM_ACTION_DEFAULT;
 280                 radeon_pm_set_clocks(rdev, false);
 281         } else if ((rdev->pm.current_power_state_index !=
 282                     rdev->pm.default_power_state_index) ||
 283                    (rdev->pm.current_clock_mode_index != 0)) {
 284                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 285                 rdev->pm.requested_clock_mode_index = 0;
 286                 mutex_lock(&rdev->pm.mutex);
 287                 radeon_pm_set_clocks(rdev, true);
 288                 mutex_unlock(&rdev->pm.mutex);
 289         }
 290
 291         device_remove_file(rdev->dev, &dev_attr_power_state);
 292         device_remove_file(rdev->dev, &dev_attr_dynpm);
 293
 294         if (rdev->pm.i2c_bus)
 295                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 296 }
 297
 298 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 299 {
 300         struct drm_device *ddev = rdev->ddev;
 301         struct drm_crtc *crtc;
 302         struct radeon_crtc *radeon_crtc;
 303
 304         if (rdev->pm.state == PM_STATE_DISABLED)
 305                 return;
 306
 307         mutex_lock(&rdev->pm.mutex);
 308
 309         rdev->pm.active_crtcs = 0;
 310         rdev->pm.active_crtc_count = 0;
 311         list_for_each_entry(crtc,
 312                 &ddev->mode_config.crtc_list, head) {
 313                 radeon_crtc = to_radeon_crtc(crtc);
 314                 if (radeon_crtc->enabled) {
 315                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 316                         rdev->pm.active_crtc_count++;
 317                 }
 318         }
 319
 320         if (rdev->pm.active_crtc_count > 1) {
 321                 if (rdev->pm.state == PM_STATE_ACTIVE) {
 322                         cancel_delayed_work(&rdev->pm.idle_work);
 323
 324                         rdev->pm.state = PM_STATE_PAUSED;
 325                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 326                         radeon_pm_set_clocks(rdev, false);
 327
 328                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 329                 }
 330         } else if (rdev->pm.active_crtc_count == 1) {
 331                 /* TODO: Increase clocks if needed for current mode */
 332
 333                 if (rdev->pm.state == PM_STATE_MINIMUM) {
 334                         rdev->pm.state = PM_STATE_ACTIVE;
 335                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 336                         radeon_pm_set_clocks(rdev, false);
 337
 338                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 339                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 340                 } else if (rdev->pm.state == PM_STATE_PAUSED) {
 341                         rdev->pm.state = PM_STATE_ACTIVE;
 342                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 343                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 344                         DRM_DEBUG("radeon: dynamic power management activated\n");
 345                 }
 346         } else { /* count == 0 */
 347                 if (rdev->pm.state != PM_STATE_MINIMUM) {
 348                         cancel_delayed_work(&rdev->pm.idle_work);
 349
 350                         rdev->pm.state = PM_STATE_MINIMUM;
 351                         rdev->pm.planned_action = PM_ACTION_MINIMUM;
 352                         radeon_pm_set_clocks(rdev, false);
 353                 }
 354         }
 355
 356         mutex_unlock(&rdev->pm.mutex);
 357 }
 358
 359 bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 360 {
 361         u32 stat_crtc = 0;
 362         bool in_vbl = true;
 363
 364         if (ASIC_IS_DCE4(rdev)) {
 365                 if (rdev->pm.active_crtcs & (1 << 0)) {
 366                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
 367                         if (!(stat_crtc & 1))
 368                                 in_vbl = false;
 369                 }
 370                 if (rdev->pm.active_crtcs & (1 << 1)) {
 371                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
 372                         if (!(stat_crtc & 1))
 373                                 in_vbl = false;
 374                 }
 375                 if (rdev->pm.active_crtcs & (1 << 2)) {
 376                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
 377                         if (!(stat_crtc & 1))
 378                                 in_vbl = false;
 379                 }
 380                 if (rdev->pm.active_crtcs & (1 << 3)) {
 381                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
 382                         if (!(stat_crtc & 1))
 383                                 in_vbl = false;
 384                 }
 385                 if (rdev->pm.active_crtcs & (1 << 4)) {
 386                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
 387                         if (!(stat_crtc & 1))
 388                                 in_vbl = false;
 389                 }
 390                 if (rdev->pm.active_crtcs & (1 << 5)) {
 391                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
 392                         if (!(stat_crtc & 1))
 393                                 in_vbl = false;
 394                 }
 395         } else if (ASIC_IS_AVIVO(rdev)) {
 396                 if (rdev->pm.active_crtcs & (1 << 0)) {
 397                         stat_crtc = RREG32(D1CRTC_STATUS);
 398                         if (!(stat_crtc & 1))
 399                                 in_vbl = false;
 400                 }
 401                 if (rdev->pm.active_crtcs & (1 << 1)) {
 402                         stat_crtc = RREG32(D2CRTC_STATUS);
 403                         if (!(stat_crtc & 1))
 404                                 in_vbl = false;
 405                 }
 406         } else {
 407                 if (rdev->pm.active_crtcs & (1 << 0)) {
 408                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 409                         if (!(stat_crtc & 1))
 410                                 in_vbl = false;
 411                 }
 412                 if (rdev->pm.active_crtcs & (1 << 1)) {
 413                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 414                         if (!(stat_crtc & 1))
 415                                 in_vbl = false;
 416                 }
 417         }
 418         if (in_vbl == false)
 419                 DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
 420                          finish ? "exit" : "entry");
 421         return in_vbl;
 422 }
 423
 424 static void radeon_pm_idle_work_handler(struct work_struct *work)
 425 {
 426         struct radeon_device *rdev;
 427         rdev = container_of(work, struct radeon_device,
 428                                 pm.idle_work.work);
 429
 430         mutex_lock(&rdev->pm.mutex);
 431         if (rdev->pm.state == PM_STATE_ACTIVE) {
 432                 unsigned long irq_flags;
 433                 int not_processed = 0;
 434
 435                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 436                 if (!list_empty(&rdev->fence_drv.emited)) {
 437                         struct list_head *ptr;
 438                         list_for_each(ptr, &rdev->fence_drv.emited) {
 439                                 /* count up to 3, that's enought info */
 440                                 if (++not_processed >= 3)
 441                                         break;
 442                         }
 443                 }
 444                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 445
 446                 if (not_processed >= 3) { /* should upclock */
 447                         if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
 448                                 rdev->pm.planned_action = PM_ACTION_NONE;
 449                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 450                                    rdev->pm.can_upclock) {
 451                                 rdev->pm.planned_action =
 452                                         PM_ACTION_UPCLOCK;
 453                                 rdev->pm.action_timeout = jiffies +
 454                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 455                         }
 456                 } else if (not_processed == 0) { /* should downclock */
 457                         if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
 458                                 rdev->pm.planned_action = PM_ACTION_NONE;
 459                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 460                                    rdev->pm.can_downclock) {
 461                                 rdev->pm.planned_action =
 462                                         PM_ACTION_DOWNCLOCK;
 463                                 rdev->pm.action_timeout = jiffies +
 464                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 465                         }
 466                 }
 467
 468                 if (rdev->pm.planned_action != PM_ACTION_NONE &&
 469                     jiffies > rdev->pm.action_timeout) {
 470                         radeon_pm_set_clocks(rdev, false);
 471                 }
 472         }
 473         mutex_unlock(&rdev->pm.mutex);
 474
 475         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 476                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 477 }
 478
 479 /*
 480  * Debugfs info
 481  */
 482 #if defined(CONFIG_DEBUG_FS)
 483
 484 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 485 {
 486         struct drm_info_node *node = (struct drm_info_node *) m->private;
 487         struct drm_device *dev = node->minor->dev;
 488         struct radeon_device *rdev = dev->dev_private;
 489
 490         seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
 491         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 492         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 493         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 494         if (rdev->asic->get_memory_clock)
 495                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 496         if (rdev->asic->get_pcie_lanes)
 497                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 498
 499         return 0;
 500 }
 501
 502 static struct drm_info_list radeon_pm_info_list[] = {
 503         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 504 };
 505 #endif
 506
 507 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 508 {
 509 #if defined(CONFIG_DEBUG_FS)
 510         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 511 #else
 512         return 0;
 513 #endif
 514 }