SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #ifdef CONFIG_ACPI
  27 #include <linux/acpi.h>
  28 #endif
  29 #include <linux/power_supply.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34 #define RADEON_WAIT_IDLE_TIMEOUT 200
  35
  36 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  37 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  38 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  39 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  40 static void radeon_pm_update_profile(struct radeon_device *rdev);
  41 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  42
  43 #define ACPI_AC_CLASS           "ac_adapter"
  44
  45 #ifdef CONFIG_ACPI
  46 static int radeon_acpi_event(struct notifier_block *nb,
  47                              unsigned long val,
  48                              void *data)
  49 {
  50         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  51         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  52
  53         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  54                 if (power_supply_is_system_supplied() > 0)
  55                         DRM_DEBUG("pm: AC\n");
  56                 else
  57                         DRM_DEBUG("pm: DC\n");
  58
  59                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  60                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
  61                                 mutex_lock(&rdev->pm.mutex);
  62                                 radeon_pm_update_profile(rdev);
  63                                 radeon_pm_set_clocks(rdev);
  64                                 mutex_unlock(&rdev->pm.mutex);
  65                         }
  66                 }
  67         }
  68
  69         return NOTIFY_OK;
  70 }
  71 #endif
  72
  73 static void radeon_pm_update_profile(struct radeon_device *rdev)
  74 {
  75         switch (rdev->pm.profile) {
  76         case PM_PROFILE_DEFAULT:
  77                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  78                 break;
  79         case PM_PROFILE_AUTO:
  80                 if (power_supply_is_system_supplied() > 0) {
  81                         if (rdev->pm.active_crtc_count > 1)
  82                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  83                         else
  84                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  85                 } else {
  86                         if (rdev->pm.active_crtc_count > 1)
  87                                 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  88                         else
  89                                 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  90                 }
  91                 break;
  92         case PM_PROFILE_LOW:
  93                 if (rdev->pm.active_crtc_count > 1)
  94                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  95                 else
  96                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  97                 break;
  98         case PM_PROFILE_HIGH:
  99                 if (rdev->pm.active_crtc_count > 1)
 100                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 101                 else
 102                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 103                 break;
 104         }
 105
 106         if (rdev->pm.active_crtc_count == 0) {
 107                 rdev->pm.requested_power_state_index =
 108                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 109                 rdev->pm.requested_clock_mode_index =
 110                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 111         } else {
 112                 rdev->pm.requested_power_state_index =
 113                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 114                 rdev->pm.requested_clock_mode_index =
 115                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 116         }
 117 }
 118
 119 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 120 {
 121         struct radeon_bo *bo, *n;
 122
 123         if (list_empty(&rdev->gem.objects))
 124                 return;
 125
 126         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 127                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 128                         ttm_bo_unmap_virtual(&bo->tbo);
 129         }
 130 }
 131
 132 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 133 {
 134         if (rdev->pm.active_crtcs) {
 135                 rdev->pm.vblank_sync = false;
 136                 wait_event_timeout(
 137                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 138                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 139         }
 140 }
 141
 142 static void radeon_set_power_state(struct radeon_device *rdev)
 143 {
 144         u32 sclk, mclk;
 145         bool misc_after = false;
 146
 147         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 148             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 149                 return;
 150
 151         if (radeon_gui_idle(rdev)) {
 152                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 153                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 154                 if (sclk > rdev->clock.default_sclk)
 155                         sclk = rdev->clock.default_sclk;
 156
 157                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 158                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 159                 if (mclk > rdev->clock.default_mclk)
 160                         mclk = rdev->clock.default_mclk;
 161
 162                 /* upvolt before raising clocks, downvolt after lowering clocks */
 163                 if (sclk < rdev->pm.current_sclk)
 164                         misc_after = true;
 165
 166                 radeon_sync_with_vblank(rdev);
 167
 168                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 169                         if (!radeon_pm_in_vbl(rdev))
 170                                 return;
 171                 }
 172
 173                 radeon_pm_prepare(rdev);
 174
 175                 if (!misc_after)
 176                         /* voltage, pcie lanes, etc.*/
 177                         radeon_pm_misc(rdev);
 178
 179                 /* set engine clock */
 180                 if (sclk != rdev->pm.current_sclk) {
 181                         radeon_pm_debug_check_in_vbl(rdev, false);
 182                         radeon_set_engine_clock(rdev, sclk);
 183                         radeon_pm_debug_check_in_vbl(rdev, true);
 184                         rdev->pm.current_sclk = sclk;
 185                         DRM_DEBUG("Setting: e: %d\n", sclk);
 186                 }
 187
 188                 /* set memory clock */
 189                 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 190                         radeon_pm_debug_check_in_vbl(rdev, false);
 191                         radeon_set_memory_clock(rdev, mclk);
 192                         radeon_pm_debug_check_in_vbl(rdev, true);
 193                         rdev->pm.current_mclk = mclk;
 194                         DRM_DEBUG("Setting: m: %d\n", mclk);
 195                 }
 196
 197                 if (misc_after)
 198                         /* voltage, pcie lanes, etc.*/
 199                         radeon_pm_misc(rdev);
 200
 201                 radeon_pm_finish(rdev);
 202
 203                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 204                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 205         } else
 206                 DRM_DEBUG("pm: GUI not idle!!!\n");
 207 }
 208
 209 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 210 {
 211         int i;
 212
 213         mutex_lock(&rdev->ddev->struct_mutex);
 214         mutex_lock(&rdev->vram_mutex);
 215         mutex_lock(&rdev->cp.mutex);
 216
 217         /* gui idle int has issues on older chips it seems */
 218         if (rdev->family >= CHIP_R600) {
 219                 if (rdev->irq.installed) {
 220                         /* wait for GPU idle */
 221                         rdev->pm.gui_idle = false;
 222                         rdev->irq.gui_idle = true;
 223                         radeon_irq_set(rdev);
 224                         wait_event_interruptible_timeout(
 225                                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 226                                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 227                         rdev->irq.gui_idle = false;
 228                         radeon_irq_set(rdev);
 229                 }
 230         } else {
 231                 if (rdev->cp.ready) {
 232                         struct radeon_fence *fence;
 233                         radeon_ring_alloc(rdev, 64);
 234                         radeon_fence_create(rdev, &fence);
 235                         radeon_fence_emit(rdev, fence);
 236                         radeon_ring_commit(rdev);
 237                         radeon_fence_wait(fence, false);
 238                         radeon_fence_unref(&fence);
 239                 }
 240         }
 241         radeon_unmap_vram_bos(rdev);
 242
 243         if (rdev->irq.installed) {
 244                 for (i = 0; i < rdev->num_crtc; i++) {
 245                         if (rdev->pm.active_crtcs & (1 << i)) {
 246                                 rdev->pm.req_vblank |= (1 << i);
 247                                 drm_vblank_get(rdev->ddev, i);
 248                         }
 249                 }
 250         }
 251
 252         radeon_set_power_state(rdev);
 253
 254         if (rdev->irq.installed) {
 255                 for (i = 0; i < rdev->num_crtc; i++) {
 256                         if (rdev->pm.req_vblank & (1 << i)) {
 257                                 rdev->pm.req_vblank &= ~(1 << i);
 258                                 drm_vblank_put(rdev->ddev, i);
 259                         }
 260                 }
 261         }
 262
 263         /* update display watermarks based on new power state */
 264         radeon_update_bandwidth_info(rdev);
 265         if (rdev->pm.active_crtc_count)
 266                 radeon_bandwidth_update(rdev);
 267
 268         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 269
 270         mutex_unlock(&rdev->cp.mutex);
 271         mutex_unlock(&rdev->vram_mutex);
 272         mutex_unlock(&rdev->ddev->struct_mutex);
 273 }
 274
 275 static ssize_t radeon_get_pm_profile(struct device *dev,
 276                                      struct device_attribute *attr,
 277                                      char *buf)
 278 {
 279         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 280         struct radeon_device *rdev = ddev->dev_private;
 281         int cp = rdev->pm.profile;
 282
 283         return snprintf(buf, PAGE_SIZE, "%s\n",
 284                         (cp == PM_PROFILE_AUTO) ? "auto" :
 285                         (cp == PM_PROFILE_LOW) ? "low" :
 286                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 287 }
 288
 289 static ssize_t radeon_set_pm_profile(struct device *dev,
 290                                      struct device_attribute *attr,
 291                                      const char *buf,
 292                                      size_t count)
 293 {
 294         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 295         struct radeon_device *rdev = ddev->dev_private;
 296
 297         mutex_lock(&rdev->pm.mutex);
 298         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 299                 if (strncmp("default", buf, strlen("default")) == 0)
 300                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 301                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 302                         rdev->pm.profile = PM_PROFILE_AUTO;
 303                 else if (strncmp("low", buf, strlen("low")) == 0)
 304                         rdev->pm.profile = PM_PROFILE_LOW;
 305                 else if (strncmp("high", buf, strlen("high")) == 0)
 306                         rdev->pm.profile = PM_PROFILE_HIGH;
 307                 else {
 308                         DRM_ERROR("invalid power profile!\n");
 309                         goto fail;
 310                 }
 311                 radeon_pm_update_profile(rdev);
 312                 radeon_pm_set_clocks(rdev);
 313         }
 314 fail:
 315         mutex_unlock(&rdev->pm.mutex);
 316
 317         return count;
 318 }
 319
 320 static ssize_t radeon_get_pm_method(struct device *dev,
 321                                     struct device_attribute *attr,
 322                                     char *buf)
 323 {
 324         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 325         struct radeon_device *rdev = ddev->dev_private;
 326         int pm = rdev->pm.pm_method;
 327
 328         return snprintf(buf, PAGE_SIZE, "%s\n",
 329                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 330 }
 331
 332 static ssize_t radeon_set_pm_method(struct device *dev,
 333                                     struct device_attribute *attr,
 334                                     const char *buf,
 335                                     size_t count)
 336 {
 337         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 338         struct radeon_device *rdev = ddev->dev_private;
 339
 340
 341         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 342                 mutex_lock(&rdev->pm.mutex);
 343                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 344                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 345                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 346                 mutex_unlock(&rdev->pm.mutex);
 347         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 348                 mutex_lock(&rdev->pm.mutex);
 349                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 350                 /* disable dynpm */
 351                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 352                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 353                 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 354                 mutex_unlock(&rdev->pm.mutex);
 355         } else {
 356                 DRM_ERROR("invalid power method!\n");
 357                 goto fail;
 358         }
 359         radeon_pm_compute_clocks(rdev);
 360 fail:
 361         return count;
 362 }
 363
 364 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 365 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 366
 367 void radeon_pm_suspend(struct radeon_device *rdev)
 368 {
 369         mutex_lock(&rdev->pm.mutex);
 370         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 371         rdev->pm.current_power_state_index = -1;
 372         rdev->pm.current_clock_mode_index = -1;
 373         rdev->pm.current_sclk = 0;
 374         rdev->pm.current_mclk = 0;
 375         mutex_unlock(&rdev->pm.mutex);
 376 }
 377
 378 void radeon_pm_resume(struct radeon_device *rdev)
 379 {
 380         radeon_pm_compute_clocks(rdev);
 381 }
 382
 383 int radeon_pm_init(struct radeon_device *rdev)
 384 {
 385         int ret;
 386         /* default to profile method */
 387         rdev->pm.pm_method = PM_METHOD_PROFILE;
 388         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 389         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 390         rdev->pm.dynpm_can_upclock = true;
 391         rdev->pm.dynpm_can_downclock = true;
 392         rdev->pm.current_sclk = 0;
 393         rdev->pm.current_mclk = 0;
 394
 395         if (rdev->bios) {
 396                 if (rdev->is_atom_bios)
 397                         radeon_atombios_get_power_modes(rdev);
 398                 else
 399                         radeon_combios_get_power_modes(rdev);
 400                 radeon_pm_init_profile(rdev);
 401                 rdev->pm.current_power_state_index = -1;
 402                 rdev->pm.current_clock_mode_index = -1;
 403         }
 404
 405         if (rdev->pm.num_power_states > 1) {
 406                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 407                         mutex_lock(&rdev->pm.mutex);
 408                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 409                         radeon_pm_update_profile(rdev);
 410                         radeon_pm_set_clocks(rdev);
 411                         mutex_unlock(&rdev->pm.mutex);
 412                 }
 413
 414                 /* where's the best place to put these? */
 415                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 416                 if (ret)
 417                         DRM_ERROR("failed to create device file for power profile\n");
 418                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 419                 if (ret)
 420                         DRM_ERROR("failed to create device file for power method\n");
 421
 422 #ifdef CONFIG_ACPI
 423                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
 424                 register_acpi_notifier(&rdev->acpi_nb);
 425 #endif
 426                 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 427
 428                 if (radeon_debugfs_pm_init(rdev)) {
 429                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 430                 }
 431
 432                 DRM_INFO("radeon: power management initialized\n");
 433         }
 434
 435         return 0;
 436 }
 437
 438 void radeon_pm_fini(struct radeon_device *rdev)
 439 {
 440         if (rdev->pm.num_power_states > 1) {
 441                 mutex_lock(&rdev->pm.mutex);
 442                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 443                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 444                         radeon_pm_update_profile(rdev);
 445                         radeon_pm_set_clocks(rdev);
 446                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 447                         /* cancel work */
 448                         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 449                         /* reset default clocks */
 450                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 451                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 452                         radeon_pm_set_clocks(rdev);
 453                 }
 454                 mutex_unlock(&rdev->pm.mutex);
 455
 456                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 457                 device_remove_file(rdev->dev, &dev_attr_power_method);
 458 #ifdef CONFIG_ACPI
 459                 unregister_acpi_notifier(&rdev->acpi_nb);
 460 #endif
 461         }
 462
 463         if (rdev->pm.i2c_bus)
 464                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 465 }
 466
 467 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 468 {
 469         struct drm_device *ddev = rdev->ddev;
 470         struct drm_crtc *crtc;
 471         struct radeon_crtc *radeon_crtc;
 472
 473         if (rdev->pm.num_power_states < 2)
 474                 return;
 475
 476         mutex_lock(&rdev->pm.mutex);
 477
 478         rdev->pm.active_crtcs = 0;
 479         rdev->pm.active_crtc_count = 0;
 480         list_for_each_entry(crtc,
 481                 &ddev->mode_config.crtc_list, head) {
 482                 radeon_crtc = to_radeon_crtc(crtc);
 483                 if (radeon_crtc->enabled) {
 484                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 485                         rdev->pm.active_crtc_count++;
 486                 }
 487         }
 488
 489         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 490                 radeon_pm_update_profile(rdev);
 491                 radeon_pm_set_clocks(rdev);
 492         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 493                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 494                         if (rdev->pm.active_crtc_count > 1) {
 495                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 496                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 497
 498                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 499                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 500                                         radeon_pm_get_dynpm_state(rdev);
 501                                         radeon_pm_set_clocks(rdev);
 502
 503                                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 504                                 }
 505                         } else if (rdev->pm.active_crtc_count == 1) {
 506                                 /* TODO: Increase clocks if needed for current mode */
 507
 508                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 509                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 510                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 511                                         radeon_pm_get_dynpm_state(rdev);
 512                                         radeon_pm_set_clocks(rdev);
 513
 514                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 515                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 516                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 517                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 518                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 519                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 520                                         DRM_DEBUG("radeon: dynamic power management activated\n");
 521                                 }
 522                         } else { /* count == 0 */
 523                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 524                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 525
 526                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 527                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 528                                         radeon_pm_get_dynpm_state(rdev);
 529                                         radeon_pm_set_clocks(rdev);
 530                                 }
 531                         }
 532                 }
 533         }
 534
 535         mutex_unlock(&rdev->pm.mutex);
 536 }
 537
 538 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 539 {
 540         u32 stat_crtc = 0, vbl = 0, position = 0;
 541         bool in_vbl = true;
 542
 543         if (ASIC_IS_DCE4(rdev)) {
 544                 if (rdev->pm.active_crtcs & (1 << 0)) {
 545                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 546                                      EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 547                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 548                                           EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 549                 }
 550                 if (rdev->pm.active_crtcs & (1 << 1)) {
 551                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 552                                      EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 553                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 554                                           EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 555                 }
 556                 if (rdev->pm.active_crtcs & (1 << 2)) {
 557                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 558                                      EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 559                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 560                                           EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 561                 }
 562                 if (rdev->pm.active_crtcs & (1 << 3)) {
 563                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 564                                      EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 565                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 566                                           EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 567                 }
 568                 if (rdev->pm.active_crtcs & (1 << 4)) {
 569                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 570                                      EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 571                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 572                                           EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 573                 }
 574                 if (rdev->pm.active_crtcs & (1 << 5)) {
 575                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 576                                      EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 577                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 578                                           EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 579                 }
 580         } else if (ASIC_IS_AVIVO(rdev)) {
 581                 if (rdev->pm.active_crtcs & (1 << 0)) {
 582                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
 583                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
 584                 }
 585                 if (rdev->pm.active_crtcs & (1 << 1)) {
 586                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
 587                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
 588                 }
 589                 if (position < vbl && position > 1)
 590                         in_vbl = false;
 591         } else {
 592                 if (rdev->pm.active_crtcs & (1 << 0)) {
 593                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 594                         if (!(stat_crtc & 1))
 595                                 in_vbl = false;
 596                 }
 597                 if (rdev->pm.active_crtcs & (1 << 1)) {
 598                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 599                         if (!(stat_crtc & 1))
 600                                 in_vbl = false;
 601                 }
 602         }
 603
 604         if (position < vbl && position > 1)
 605                 in_vbl = false;
 606
 607         return in_vbl;
 608 }
 609
 610 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 611 {
 612         u32 stat_crtc = 0;
 613         bool in_vbl = radeon_pm_in_vbl(rdev);
 614
 615         if (in_vbl == false)
 616                 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
 617                          finish ? "exit" : "entry");
 618         return in_vbl;
 619 }
 620
 621 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 622 {
 623         struct radeon_device *rdev;
 624         int resched;
 625         rdev = container_of(work, struct radeon_device,
 626                                 pm.dynpm_idle_work.work);
 627
 628         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 629         mutex_lock(&rdev->pm.mutex);
 630         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 631                 unsigned long irq_flags;
 632                 int not_processed = 0;
 633
 634                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 635                 if (!list_empty(&rdev->fence_drv.emited)) {
 636                         struct list_head *ptr;
 637                         list_for_each(ptr, &rdev->fence_drv.emited) {
 638                                 /* count up to 3, that's enought info */
 639                                 if (++not_processed >= 3)
 640                                         break;
 641                         }
 642                 }
 643                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 644
 645                 if (not_processed >= 3) { /* should upclock */
 646                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 647                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 648                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 649                                    rdev->pm.dynpm_can_upclock) {
 650                                 rdev->pm.dynpm_planned_action =
 651                                         DYNPM_ACTION_UPCLOCK;
 652                                 rdev->pm.dynpm_action_timeout = jiffies +
 653                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 654                         }
 655                 } else if (not_processed == 0) { /* should downclock */
 656                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 657                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 658                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 659                                    rdev->pm.dynpm_can_downclock) {
 660                                 rdev->pm.dynpm_planned_action =
 661                                         DYNPM_ACTION_DOWNCLOCK;
 662                                 rdev->pm.dynpm_action_timeout = jiffies +
 663                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 664                         }
 665                 }
 666
 667                 /* Note, radeon_pm_set_clocks is called with static_switch set
 668                  * to false since we want to wait for vbl to avoid flicker.
 669                  */
 670                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 671                     jiffies > rdev->pm.dynpm_action_timeout) {
 672                         radeon_pm_get_dynpm_state(rdev);
 673                         radeon_pm_set_clocks(rdev);
 674                 }
 675         }
 676         mutex_unlock(&rdev->pm.mutex);
 677         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 678
 679         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 680                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 681 }
 682
 683 /*
 684  * Debugfs info
 685  */
 686 #if defined(CONFIG_DEBUG_FS)
 687
 688 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 689 {
 690         struct drm_info_node *node = (struct drm_info_node *) m->private;
 691         struct drm_device *dev = node->minor->dev;
 692         struct radeon_device *rdev = dev->dev_private;
 693
 694         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 695         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 696         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 697         if (rdev->asic->get_memory_clock)
 698                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 699         if (rdev->asic->get_pcie_lanes)
 700                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 701
 702         return 0;
 703 }
 704
 705 static struct drm_info_list radeon_pm_info_list[] = {
 706         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 707 };
 708 #endif
 709
 710 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 711 {
 712 #if defined(CONFIG_DEBUG_FS)
 713         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 714 #else
 715         return 0;
 716 #endif
 717 }