SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26
  27 #define RADEON_IDLE_LOOP_MS 100
  28 #define RADEON_RECLOCK_DELAY_MS 200
  29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  30 #define RADEON_WAIT_IDLE_TIMEOUT 200
  31
  32 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  33 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
  34 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  35 static void radeon_pm_idle_work_handler(struct work_struct *work);
  36 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  37
  38 static const char *pm_state_names[4] = {
  39         "PM_STATE_DISABLED",
  40         "PM_STATE_MINIMUM",
  41         "PM_STATE_PAUSED",
  42         "PM_STATE_ACTIVE"
  43 };
  44
  45 static const char *pm_state_types[5] = {
  46         "Default",
  47         "Powersave",
  48         "Battery",
  49         "Balanced",
  50         "Performance",
  51 };
  52
  53 static void radeon_print_power_mode_info(struct radeon_device *rdev)
  54 {
  55         int i, j;
  56         bool is_default;
  57
  58         DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
  59         for (i = 0; i < rdev->pm.num_power_states; i++) {
  60                 if (rdev->pm.default_power_state == &rdev->pm.power_state[i])
  61                         is_default = true;
  62                 else
  63                         is_default = false;
  64                 DRM_INFO("State %d %s %s\n", i,
  65                          pm_state_types[rdev->pm.power_state[i].type],
  66                          is_default ? "(default)" : "");
  67                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
  68                         DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
  69                 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
  70                 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
  71                         if (rdev->flags & RADEON_IS_IGP)
  72                                 DRM_INFO("\t\t%d engine: %d\n",
  73                                          j,
  74                                          rdev->pm.power_state[i].clock_info[j].sclk * 10);
  75                         else
  76                                 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
  77                                          j,
  78                                          rdev->pm.power_state[i].clock_info[j].sclk * 10,
  79                                          rdev->pm.power_state[i].clock_info[j].mclk * 10);
  80                 }
  81         }
  82 }
  83
  84 static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev,
  85                                                            enum radeon_pm_state_type type)
  86 {
  87         int i, j;
  88         enum radeon_pm_state_type wanted_types[2];
  89         int wanted_count;
  90
  91         switch (type) {
  92         case POWER_STATE_TYPE_DEFAULT:
  93         default:
  94                 return rdev->pm.default_power_state;
  95         case POWER_STATE_TYPE_POWERSAVE:
  96                 if (rdev->flags & RADEON_IS_MOBILITY) {
  97                         wanted_types[0] = POWER_STATE_TYPE_POWERSAVE;
  98                         wanted_types[1] = POWER_STATE_TYPE_BATTERY;
  99                         wanted_count = 2;
 100                 } else {
 101                         wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
 102                         wanted_count = 1;
 103                 }
 104                 break;
 105         case POWER_STATE_TYPE_BATTERY:
 106                 if (rdev->flags & RADEON_IS_MOBILITY) {
 107                         wanted_types[0] = POWER_STATE_TYPE_BATTERY;
 108                         wanted_types[1] = POWER_STATE_TYPE_POWERSAVE;
 109                         wanted_count = 2;
 110                 } else {
 111                         wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
 112                         wanted_count = 1;
 113                 }
 114                 break;
 115         case POWER_STATE_TYPE_BALANCED:
 116         case POWER_STATE_TYPE_PERFORMANCE:
 117                 wanted_types[0] = type;
 118                 wanted_count = 1;
 119                 break;
 120         }
 121
 122         for (i = 0; i < wanted_count; i++) {
 123                 for (j = 0; j < rdev->pm.num_power_states; j++) {
 124                         if (rdev->pm.power_state[j].type == wanted_types[i])
 125                                 return &rdev->pm.power_state[j];
 126                 }
 127         }
 128
 129         return rdev->pm.default_power_state;
 130 }
 131
 132 static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev,
 133                                                             struct radeon_power_state *power_state,
 134                                                             enum radeon_pm_clock_mode_type type)
 135 {
 136         switch (type) {
 137         case POWER_MODE_TYPE_DEFAULT:
 138         default:
 139                 return power_state->default_clock_mode;
 140         case POWER_MODE_TYPE_LOW:
 141                 return &power_state->clock_info[0];
 142         case POWER_MODE_TYPE_MID:
 143                 if (power_state->num_clock_modes > 2)
 144                         return &power_state->clock_info[1];
 145                 else
 146                         return &power_state->clock_info[0];
 147                 break;
 148         case POWER_MODE_TYPE_HIGH:
 149                 return &power_state->clock_info[power_state->num_clock_modes - 1];
 150         }
 151
 152 }
 153
 154 static void radeon_get_power_state(struct radeon_device *rdev,
 155                                    enum radeon_pm_action action)
 156 {
 157         switch (action) {
 158         case PM_ACTION_MINIMUM:
 159                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY);
 160                 rdev->pm.requested_clock_mode =
 161                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW);
 162                 break;
 163         case PM_ACTION_DOWNCLOCK:
 164                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE);
 165                 rdev->pm.requested_clock_mode =
 166                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID);
 167                 break;
 168         case PM_ACTION_UPCLOCK:
 169                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT);
 170                 rdev->pm.requested_clock_mode =
 171                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH);
 172                 break;
 173         case PM_ACTION_NONE:
 174         default:
 175                 DRM_ERROR("Requested mode for not defined action\n");
 176                 return;
 177         }
 178         DRM_INFO("Requested: e: %d m: %d p: %d\n",
 179                  rdev->pm.requested_clock_mode->sclk,
 180                  rdev->pm.requested_clock_mode->mclk,
 181                  rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
 182 }
 183
 184 static inline void radeon_sync_with_vblank(struct radeon_device *rdev)
 185 {
 186         if (rdev->pm.active_crtcs) {
 187                 rdev->pm.vblank_sync = false;
 188                 wait_event_timeout(
 189                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 190                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 191         }
 192 }
 193
 194 static void radeon_set_power_state(struct radeon_device *rdev)
 195 {
 196         /* if *_clock_mode are the same, *_power_state are as well */
 197         if (rdev->pm.requested_clock_mode == rdev->pm.current_clock_mode)
 198                 return;
 199
 200         DRM_INFO("Setting: e: %d m: %d p: %d\n",
 201                  rdev->pm.requested_clock_mode->sclk,
 202                  rdev->pm.requested_clock_mode->mclk,
 203                  rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
 204
 205         /* set pcie lanes */
 206         /* TODO */
 207
 208         /* set voltage */
 209         /* TODO */
 210
 211         /* set engine clock */
 212         radeon_sync_with_vblank(rdev);
 213         radeon_pm_debug_check_in_vbl(rdev, false);
 214         radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk);
 215         radeon_pm_debug_check_in_vbl(rdev, true);
 216
 217 #if 0
 218         /* set memory clock */
 219         if (rdev->asic->set_memory_clock) {
 220                 radeon_sync_with_vblank(rdev);
 221                 radeon_pm_debug_check_in_vbl(rdev, false);
 222                 radeon_set_memory_clock(rdev, rdev->pm.requested_clock_mode->mclk);
 223                 radeon_pm_debug_check_in_vbl(rdev, true);
 224         }
 225 #endif
 226
 227         rdev->pm.current_power_state = rdev->pm.requested_power_state;
 228         rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode;
 229 }
 230
 231 int radeon_pm_init(struct radeon_device *rdev)
 232 {
 233         rdev->pm.state = PM_STATE_DISABLED;
 234         rdev->pm.planned_action = PM_ACTION_NONE;
 235         rdev->pm.downclocked = false;
 236
 237         if (rdev->bios) {
 238                 if (rdev->is_atom_bios)
 239                         radeon_atombios_get_power_modes(rdev);
 240                 else
 241                         radeon_combios_get_power_modes(rdev);
 242                 radeon_print_power_mode_info(rdev);
 243         }
 244
 245         if (radeon_debugfs_pm_init(rdev)) {
 246                 DRM_ERROR("Failed to register debugfs file for PM!\n");
 247         }
 248
 249         INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
 250
 251         if (radeon_dynpm != -1 && radeon_dynpm) {
 252                 rdev->pm.state = PM_STATE_PAUSED;
 253                 DRM_INFO("radeon: dynamic power management enabled\n");
 254         }
 255
 256         DRM_INFO("radeon: power management initialized\n");
 257
 258         return 0;
 259 }
 260
 261 void radeon_pm_fini(struct radeon_device *rdev)
 262 {
 263         if (rdev->pm.i2c_bus)
 264                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 265 }
 266
 267 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 268 {
 269         struct drm_device *ddev = rdev->ddev;
 270         struct drm_connector *connector;
 271         struct radeon_crtc *radeon_crtc;
 272         int count = 0;
 273
 274         if (rdev->pm.state == PM_STATE_DISABLED)
 275                 return;
 276
 277         mutex_lock(&rdev->pm.mutex);
 278
 279         rdev->pm.active_crtcs = 0;
 280         list_for_each_entry(connector,
 281                 &ddev->mode_config.connector_list, head) {
 282                 if (connector->encoder &&
 283                     connector->encoder->crtc &&
 284                     connector->dpms != DRM_MODE_DPMS_OFF) {
 285                         radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
 286                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 287                         ++count;
 288                 }
 289         }
 290
 291         if (count > 1) {
 292                 if (rdev->pm.state == PM_STATE_ACTIVE) {
 293                         cancel_delayed_work(&rdev->pm.idle_work);
 294
 295                         rdev->pm.state = PM_STATE_PAUSED;
 296                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 297                         if (rdev->pm.downclocked)
 298                                 radeon_pm_set_clocks(rdev);
 299
 300                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 301                 }
 302         } else if (count == 1) {
 303                 /* TODO: Increase clocks if needed for current mode */
 304
 305                 if (rdev->pm.state == PM_STATE_MINIMUM) {
 306                         rdev->pm.state = PM_STATE_ACTIVE;
 307                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 308                         radeon_pm_set_clocks(rdev);
 309
 310                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 311                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 312                 }
 313                 else if (rdev->pm.state == PM_STATE_PAUSED) {
 314                         rdev->pm.state = PM_STATE_ACTIVE;
 315                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 316                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 317                         DRM_DEBUG("radeon: dynamic power management activated\n");
 318                 }
 319         }
 320         else { /* count == 0 */
 321                 if (rdev->pm.state != PM_STATE_MINIMUM) {
 322                         cancel_delayed_work(&rdev->pm.idle_work);
 323
 324                         rdev->pm.state = PM_STATE_MINIMUM;
 325                         rdev->pm.planned_action = PM_ACTION_MINIMUM;
 326                         radeon_pm_set_clocks(rdev);
 327                 }
 328         }
 329
 330         mutex_unlock(&rdev->pm.mutex);
 331 }
 332
 333 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 334 {
 335         u32 stat_crtc1 = 0, stat_crtc2 = 0;
 336         bool in_vbl = true;
 337
 338         if (ASIC_IS_AVIVO(rdev)) {
 339                 if (rdev->pm.active_crtcs & (1 << 0)) {
 340                         stat_crtc1 = RREG32(D1CRTC_STATUS);
 341                         if (!(stat_crtc1 & 1))
 342                                 in_vbl = false;
 343                 }
 344                 if (rdev->pm.active_crtcs & (1 << 1)) {
 345                         stat_crtc2 = RREG32(D2CRTC_STATUS);
 346                         if (!(stat_crtc2 & 1))
 347                                 in_vbl = false;
 348                 }
 349         }
 350         if (in_vbl == false)
 351                 DRM_INFO("not in vbl for pm change %08x %08x at %s\n", stat_crtc1,
 352                          stat_crtc2, finish ? "exit" : "entry");
 353         return in_vbl;
 354 }
 355 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
 356 {
 357         /*radeon_fence_wait_last(rdev);*/
 358         switch (rdev->pm.planned_action) {
 359         case PM_ACTION_UPCLOCK:
 360                 rdev->pm.downclocked = false;
 361                 break;
 362         case PM_ACTION_DOWNCLOCK:
 363                 rdev->pm.downclocked = true;
 364                 break;
 365         case PM_ACTION_MINIMUM:
 366                 break;
 367         case PM_ACTION_NONE:
 368                 DRM_ERROR("%s: PM_ACTION_NONE\n", __func__);
 369                 break;
 370         }
 371
 372         radeon_set_power_state(rdev);
 373         rdev->pm.planned_action = PM_ACTION_NONE;
 374 }
 375
 376 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 377 {
 378         radeon_get_power_state(rdev, rdev->pm.planned_action);
 379         mutex_lock(&rdev->cp.mutex);
 380
 381         /* wait for GPU idle */
 382         rdev->pm.gui_idle = false;
 383         rdev->irq.gui_idle = true;
 384         radeon_irq_set(rdev);
 385         wait_event_interruptible_timeout(
 386                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 387                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 388         rdev->irq.gui_idle = false;
 389         radeon_irq_set(rdev);
 390
 391         if (rdev->pm.active_crtcs & (1 << 0)) {
 392                 rdev->pm.req_vblank |= (1 << 0);
 393                 drm_vblank_get(rdev->ddev, 0);
 394         }
 395         if (rdev->pm.active_crtcs & (1 << 1)) {
 396                 rdev->pm.req_vblank |= (1 << 1);
 397                 drm_vblank_get(rdev->ddev, 1);
 398         }
 399         radeon_pm_set_clocks_locked(rdev);
 400         if (rdev->pm.req_vblank & (1 << 0)) {
 401                 rdev->pm.req_vblank &= ~(1 << 0);
 402                 drm_vblank_put(rdev->ddev, 0);
 403         }
 404         if (rdev->pm.req_vblank & (1 << 1)) {
 405                 rdev->pm.req_vblank &= ~(1 << 1);
 406                 drm_vblank_put(rdev->ddev, 1);
 407         }
 408
 409         mutex_unlock(&rdev->cp.mutex);
 410 }
 411
 412 static void radeon_pm_idle_work_handler(struct work_struct *work)
 413 {
 414         struct radeon_device *rdev;
 415         rdev = container_of(work, struct radeon_device,
 416                                 pm.idle_work.work);
 417
 418         mutex_lock(&rdev->pm.mutex);
 419         if (rdev->pm.state == PM_STATE_ACTIVE) {
 420                 unsigned long irq_flags;
 421                 int not_processed = 0;
 422
 423                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 424                 if (!list_empty(&rdev->fence_drv.emited)) {
 425                         struct list_head *ptr;
 426                         list_for_each(ptr, &rdev->fence_drv.emited) {
 427                                 /* count up to 3, that's enought info */
 428                                 if (++not_processed >= 3)
 429                                         break;
 430                         }
 431                 }
 432                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 433
 434                 if (not_processed >= 3) { /* should upclock */
 435                         if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
 436                                 rdev->pm.planned_action = PM_ACTION_NONE;
 437                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 438                                 rdev->pm.downclocked) {
 439                                 rdev->pm.planned_action =
 440                                         PM_ACTION_UPCLOCK;
 441                                 rdev->pm.action_timeout = jiffies +
 442                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 443                         }
 444                 } else if (not_processed == 0) { /* should downclock */
 445                         if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
 446                                 rdev->pm.planned_action = PM_ACTION_NONE;
 447                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 448                                 !rdev->pm.downclocked) {
 449                                 rdev->pm.planned_action =
 450                                         PM_ACTION_DOWNCLOCK;
 451                                 rdev->pm.action_timeout = jiffies +
 452                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 453                         }
 454                 }
 455
 456                 if (rdev->pm.planned_action != PM_ACTION_NONE &&
 457                     jiffies > rdev->pm.action_timeout) {
 458                         radeon_pm_set_clocks(rdev);
 459                 }
 460         }
 461         mutex_unlock(&rdev->pm.mutex);
 462
 463         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 464                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 465 }
 466
 467 /*
 468  * Debugfs info
 469  */
 470 #if defined(CONFIG_DEBUG_FS)
 471
 472 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 473 {
 474         struct drm_info_node *node = (struct drm_info_node *) m->private;
 475         struct drm_device *dev = node->minor->dev;
 476         struct radeon_device *rdev = dev->dev_private;
 477
 478         seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
 479         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 480         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 481         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 482         if (rdev->asic->get_memory_clock)
 483                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 484         if (rdev->asic->get_pcie_lanes)
 485                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 486
 487         return 0;
 488 }
 489
 490 static struct drm_info_list radeon_pm_info_list[] = {
 491         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 492 };
 493 #endif
 494
 495 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 496 {
 497 #if defined(CONFIG_DEBUG_FS)
 498         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 499 #else
 500         return 0;
 501 #endif
 502 }