SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26
  27 #define RADEON_IDLE_LOOP_MS 100
  28 #define RADEON_RECLOCK_DELAY_MS 200
  29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  30 #define RADEON_WAIT_IDLE_TIMEOUT 200
  31
  32 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
  33 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  34 static void radeon_pm_idle_work_handler(struct work_struct *work);
  35 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  36
  37 static const char *pm_state_names[4] = {
  38         "PM_STATE_DISABLED",
  39         "PM_STATE_MINIMUM",
  40         "PM_STATE_PAUSED",
  41         "PM_STATE_ACTIVE"
  42 };
  43
  44 static const char *pm_state_types[5] = {
  45         "",
  46         "Powersave",
  47         "Battery",
  48         "Balanced",
  49         "Performance",
  50 };
  51
  52 static void radeon_print_power_mode_info(struct radeon_device *rdev)
  53 {
  54         int i, j;
  55         bool is_default;
  56
  57         DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
  58         for (i = 0; i < rdev->pm.num_power_states; i++) {
  59                 if (rdev->pm.default_power_state_index == i)
  60                         is_default = true;
  61                 else
  62                         is_default = false;
  63                 DRM_INFO("State %d %s %s\n", i,
  64                          pm_state_types[rdev->pm.power_state[i].type],
  65                          is_default ? "(default)" : "");
  66                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
  67                         DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
  68                 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
  69                         DRM_INFO("\tSingle display only\n");
  70                 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
  71                 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
  72                         if (rdev->flags & RADEON_IS_IGP)
  73                                 DRM_INFO("\t\t%d engine: %d\n",
  74                                          j,
  75                                          rdev->pm.power_state[i].clock_info[j].sclk * 10);
  76                         else
  77                                 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
  78                                          j,
  79                                          rdev->pm.power_state[i].clock_info[j].sclk * 10,
  80                                          rdev->pm.power_state[i].clock_info[j].mclk * 10);
  81                 }
  82         }
  83 }
  84
  85 void radeon_sync_with_vblank(struct radeon_device *rdev)
  86 {
  87         if (rdev->pm.active_crtcs) {
  88                 rdev->pm.vblank_sync = false;
  89                 wait_event_timeout(
  90                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
  91                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
  92         }
  93 }
  94
  95 int radeon_pm_init(struct radeon_device *rdev)
  96 {
  97         rdev->pm.state = PM_STATE_DISABLED;
  98         rdev->pm.planned_action = PM_ACTION_NONE;
  99         rdev->pm.can_upclock = true;
 100         rdev->pm.can_downclock = true;
 101
 102         if (rdev->bios) {
 103                 if (rdev->is_atom_bios)
 104                         radeon_atombios_get_power_modes(rdev);
 105                 else
 106                         radeon_combios_get_power_modes(rdev);
 107                 radeon_print_power_mode_info(rdev);
 108         }
 109
 110         if (radeon_debugfs_pm_init(rdev)) {
 111                 DRM_ERROR("Failed to register debugfs file for PM!\n");
 112         }
 113
 114         INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
 115
 116         if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
 117                 rdev->pm.state = PM_STATE_PAUSED;
 118                 DRM_INFO("radeon: dynamic power management enabled\n");
 119         }
 120
 121         DRM_INFO("radeon: power management initialized\n");
 122
 123         return 0;
 124 }
 125
 126 void radeon_pm_fini(struct radeon_device *rdev)
 127 {
 128         if (rdev->pm.state != PM_STATE_DISABLED) {
 129                 /* cancel work */
 130                 cancel_delayed_work_sync(&rdev->pm.idle_work);
 131                 /* reset default clocks */
 132                 rdev->pm.state = PM_STATE_DISABLED;
 133                 rdev->pm.planned_action = PM_ACTION_DEFAULT;
 134                 radeon_pm_set_clocks(rdev);
 135         }
 136
 137         if (rdev->pm.i2c_bus)
 138                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 139 }
 140
 141 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 142 {
 143         struct drm_device *ddev = rdev->ddev;
 144         struct drm_crtc *crtc;
 145         struct radeon_crtc *radeon_crtc;
 146
 147         if (rdev->pm.state == PM_STATE_DISABLED)
 148                 return;
 149
 150         mutex_lock(&rdev->pm.mutex);
 151
 152         rdev->pm.active_crtcs = 0;
 153         rdev->pm.active_crtc_count = 0;
 154         list_for_each_entry(crtc,
 155                 &ddev->mode_config.crtc_list, head) {
 156                 radeon_crtc = to_radeon_crtc(crtc);
 157                 if (radeon_crtc->enabled) {
 158                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 159                         rdev->pm.active_crtc_count++;
 160                 }
 161         }
 162
 163         if (rdev->pm.active_crtc_count > 1) {
 164                 if (rdev->pm.state == PM_STATE_ACTIVE) {
 165                         cancel_delayed_work(&rdev->pm.idle_work);
 166
 167                         rdev->pm.state = PM_STATE_PAUSED;
 168                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 169                         radeon_pm_set_clocks(rdev);
 170
 171                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 172                 }
 173         } else if (rdev->pm.active_crtc_count == 1) {
 174                 /* TODO: Increase clocks if needed for current mode */
 175
 176                 if (rdev->pm.state == PM_STATE_MINIMUM) {
 177                         rdev->pm.state = PM_STATE_ACTIVE;
 178                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 179                         radeon_pm_set_clocks(rdev);
 180
 181                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 182                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 183                 } else if (rdev->pm.state == PM_STATE_PAUSED) {
 184                         rdev->pm.state = PM_STATE_ACTIVE;
 185                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 186                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 187                         DRM_DEBUG("radeon: dynamic power management activated\n");
 188                 }
 189         } else { /* count == 0 */
 190                 if (rdev->pm.state != PM_STATE_MINIMUM) {
 191                         cancel_delayed_work(&rdev->pm.idle_work);
 192
 193                         rdev->pm.state = PM_STATE_MINIMUM;
 194                         rdev->pm.planned_action = PM_ACTION_MINIMUM;
 195                         radeon_pm_set_clocks(rdev);
 196                 }
 197         }
 198
 199         mutex_unlock(&rdev->pm.mutex);
 200 }
 201
 202 bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 203 {
 204         u32 stat_crtc = 0;
 205         bool in_vbl = true;
 206
 207         if (ASIC_IS_DCE4(rdev)) {
 208                 if (rdev->pm.active_crtcs & (1 << 0)) {
 209                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
 210                         if (!(stat_crtc & 1))
 211                                 in_vbl = false;
 212                 }
 213                 if (rdev->pm.active_crtcs & (1 << 1)) {
 214                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
 215                         if (!(stat_crtc & 1))
 216                                 in_vbl = false;
 217                 }
 218                 if (rdev->pm.active_crtcs & (1 << 2)) {
 219                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
 220                         if (!(stat_crtc & 1))
 221                                 in_vbl = false;
 222                 }
 223                 if (rdev->pm.active_crtcs & (1 << 3)) {
 224                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
 225                         if (!(stat_crtc & 1))
 226                                 in_vbl = false;
 227                 }
 228                 if (rdev->pm.active_crtcs & (1 << 4)) {
 229                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
 230                         if (!(stat_crtc & 1))
 231                                 in_vbl = false;
 232                 }
 233                 if (rdev->pm.active_crtcs & (1 << 5)) {
 234                         stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
 235                         if (!(stat_crtc & 1))
 236                                 in_vbl = false;
 237                 }
 238         } else if (ASIC_IS_AVIVO(rdev)) {
 239                 if (rdev->pm.active_crtcs & (1 << 0)) {
 240                         stat_crtc = RREG32(D1CRTC_STATUS);
 241                         if (!(stat_crtc & 1))
 242                                 in_vbl = false;
 243                 }
 244                 if (rdev->pm.active_crtcs & (1 << 1)) {
 245                         stat_crtc = RREG32(D2CRTC_STATUS);
 246                         if (!(stat_crtc & 1))
 247                                 in_vbl = false;
 248                 }
 249         } else {
 250                 if (rdev->pm.active_crtcs & (1 << 0)) {
 251                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 252                         if (!(stat_crtc & 1))
 253                                 in_vbl = false;
 254                 }
 255                 if (rdev->pm.active_crtcs & (1 << 1)) {
 256                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 257                         if (!(stat_crtc & 1))
 258                                 in_vbl = false;
 259                 }
 260         }
 261         if (in_vbl == false)
 262                 DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
 263                          finish ? "exit" : "entry");
 264         return in_vbl;
 265 }
 266 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
 267 {
 268         /*radeon_fence_wait_last(rdev);*/
 269
 270         radeon_set_power_state(rdev);
 271         rdev->pm.planned_action = PM_ACTION_NONE;
 272 }
 273
 274 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 275 {
 276         int i;
 277
 278         radeon_get_power_state(rdev, rdev->pm.planned_action);
 279         mutex_lock(&rdev->cp.mutex);
 280
 281         /* wait for GPU idle */
 282         rdev->pm.gui_idle = false;
 283         rdev->irq.gui_idle = true;
 284         radeon_irq_set(rdev);
 285         wait_event_interruptible_timeout(
 286                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 287                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 288         rdev->irq.gui_idle = false;
 289         radeon_irq_set(rdev);
 290
 291         for (i = 0; i < rdev->num_crtc; i++) {
 292                 if (rdev->pm.active_crtcs & (1 << i)) {
 293                         rdev->pm.req_vblank |= (1 << i);
 294                         drm_vblank_get(rdev->ddev, i);
 295                 }
 296         }
 297         radeon_pm_set_clocks_locked(rdev);
 298         for (i = 0; i < rdev->num_crtc; i++) {
 299                 if (rdev->pm.req_vblank & (1 << i)) {
 300                         rdev->pm.req_vblank &= ~(1 << i);
 301                         drm_vblank_put(rdev->ddev, i);
 302                 }
 303         }
 304
 305         /* update display watermarks based on new power state */
 306         radeon_update_bandwidth_info(rdev);
 307         if (rdev->pm.active_crtc_count)
 308                 radeon_bandwidth_update(rdev);
 309
 310         mutex_unlock(&rdev->cp.mutex);
 311 }
 312
 313 static void radeon_pm_idle_work_handler(struct work_struct *work)
 314 {
 315         struct radeon_device *rdev;
 316         rdev = container_of(work, struct radeon_device,
 317                                 pm.idle_work.work);
 318
 319         mutex_lock(&rdev->pm.mutex);
 320         if (rdev->pm.state == PM_STATE_ACTIVE) {
 321                 unsigned long irq_flags;
 322                 int not_processed = 0;
 323
 324                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 325                 if (!list_empty(&rdev->fence_drv.emited)) {
 326                         struct list_head *ptr;
 327                         list_for_each(ptr, &rdev->fence_drv.emited) {
 328                                 /* count up to 3, that's enought info */
 329                                 if (++not_processed >= 3)
 330                                         break;
 331                         }
 332                 }
 333                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 334
 335                 if (not_processed >= 3) { /* should upclock */
 336                         if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
 337                                 rdev->pm.planned_action = PM_ACTION_NONE;
 338                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 339                                    rdev->pm.can_upclock) {
 340                                 rdev->pm.planned_action =
 341                                         PM_ACTION_UPCLOCK;
 342                                 rdev->pm.action_timeout = jiffies +
 343                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 344                         }
 345                 } else if (not_processed == 0) { /* should downclock */
 346                         if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
 347                                 rdev->pm.planned_action = PM_ACTION_NONE;
 348                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 349                                    rdev->pm.can_downclock) {
 350                                 rdev->pm.planned_action =
 351                                         PM_ACTION_DOWNCLOCK;
 352                                 rdev->pm.action_timeout = jiffies +
 353                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 354                         }
 355                 }
 356
 357                 if (rdev->pm.planned_action != PM_ACTION_NONE &&
 358                     jiffies > rdev->pm.action_timeout) {
 359                         radeon_pm_set_clocks(rdev);
 360                 }
 361         }
 362         mutex_unlock(&rdev->pm.mutex);
 363
 364         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 365                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 366 }
 367
 368 /*
 369  * Debugfs info
 370  */
 371 #if defined(CONFIG_DEBUG_FS)
 372
 373 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 374 {
 375         struct drm_info_node *node = (struct drm_info_node *) m->private;
 376         struct drm_device *dev = node->minor->dev;
 377         struct radeon_device *rdev = dev->dev_private;
 378
 379         seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
 380         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 381         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 382         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 383         if (rdev->asic->get_memory_clock)
 384                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 385         if (rdev->asic->get_pcie_lanes)
 386                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 387
 388         return 0;
 389 }
 390
 391 static struct drm_info_list radeon_pm_info_list[] = {
 392         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 393 };
 394 #endif
 395
 396 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 397 {
 398 #if defined(CONFIG_DEBUG_FS)
 399         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 400 #else
 401         return 0;
 402 #endif
 403 }