2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
34 #include "radeon_drm.h"
38 int radeon_ttm_init(struct radeon_device *rdev);
39 void radeon_ttm_fini(struct radeon_device *rdev);
40 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
43 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
44 * function are calling it.
47 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
51 bo = container_of(tbo, struct radeon_bo, tbo);
52 mutex_lock(&bo->rdev->gem.mutex);
53 list_del_init(&bo->list);
54 mutex_unlock(&bo->rdev->gem.mutex);
55 radeon_bo_clear_surface_reg(bo);
59 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
63 rbo->placement.fpfn = 0;
64 rbo->placement.lpfn = 0;
65 rbo->placement.placement = rbo->placements;
66 rbo->placement.busy_placement = rbo->placements;
67 if (domain & RADEON_GEM_DOMAIN_VRAM)
68 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
70 if (domain & RADEON_GEM_DOMAIN_GTT)
71 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
72 if (domain & RADEON_GEM_DOMAIN_CPU)
73 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
74 rbo->placement.num_placement = c;
75 rbo->placement.num_busy_placement = c;
78 int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
79 unsigned long size, bool kernel, u32 domain,
80 struct radeon_bo **bo_ptr)
83 enum ttm_bo_type type;
86 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
87 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
90 type = ttm_bo_type_kernel;
92 type = ttm_bo_type_device;
95 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
100 bo->surface_reg = -1;
101 INIT_LIST_HEAD(&bo->list);
103 radeon_ttm_placement_from_domain(bo, domain);
104 /* Kernel allocation are uninterruptible */
105 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
106 &bo->placement, 0, 0, !kernel, NULL, size,
107 &radeon_ttm_bo_destroy);
108 if (unlikely(r != 0)) {
109 if (r != -ERESTARTSYS)
111 "object_init failed for (%lu, 0x%08X)\n",
117 mutex_lock(&bo->rdev->gem.mutex);
118 list_add_tail(&bo->list, &rdev->gem.objects);
119 mutex_unlock(&bo->rdev->gem.mutex);
124 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
135 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
139 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
143 radeon_bo_check_tiling(bo, 0, 0);
147 void radeon_bo_kunmap(struct radeon_bo *bo)
149 if (bo->kptr == NULL)
152 radeon_bo_check_tiling(bo, 0, 0);
153 ttm_bo_kunmap(&bo->kmap);
156 void radeon_bo_unref(struct radeon_bo **bo)
158 struct ttm_buffer_object *tbo;
168 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
172 radeon_ttm_placement_from_domain(bo, domain);
176 *gpu_addr = radeon_bo_gpu_offset(bo);
179 radeon_ttm_placement_from_domain(bo, domain);
180 for (i = 0; i < bo->placement.num_placement; i++)
181 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
182 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
183 if (likely(r == 0)) {
185 if (gpu_addr != NULL)
186 *gpu_addr = radeon_bo_gpu_offset(bo);
188 if (unlikely(r != 0))
189 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
193 int radeon_bo_unpin(struct radeon_bo *bo)
197 if (!bo->pin_count) {
198 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
204 for (i = 0; i < bo->placement.num_placement; i++)
205 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
206 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
207 if (unlikely(r != 0))
208 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
212 int radeon_bo_evict_vram(struct radeon_device *rdev)
214 if (rdev->flags & RADEON_IS_IGP) {
215 /* Useless to evict on IGP chips */
218 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
221 void radeon_bo_force_delete(struct radeon_device *rdev)
223 struct radeon_bo *bo, *n;
224 struct drm_gem_object *gobj;
226 if (list_empty(&rdev->gem.objects)) {
229 dev_err(rdev->dev, "Userspace still has active objects !\n");
230 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
231 mutex_lock(&rdev->ddev->struct_mutex);
233 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
234 gobj, bo, (unsigned long)gobj->size,
235 *((unsigned long *)&gobj->refcount));
236 mutex_lock(&bo->rdev->gem.mutex);
237 list_del_init(&bo->list);
238 mutex_unlock(&bo->rdev->gem.mutex);
239 radeon_bo_unref(&bo);
240 gobj->driver_private = NULL;
241 drm_gem_object_unreference(gobj);
242 mutex_unlock(&rdev->ddev->struct_mutex);
246 int radeon_bo_init(struct radeon_device *rdev)
248 /* Add an MTRR for the VRAM */
249 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
250 MTRR_TYPE_WRCOMB, 1);
251 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
252 rdev->mc.mc_vram_size >> 20,
253 (unsigned long long)rdev->mc.aper_size >> 20);
254 DRM_INFO("RAM width %dbits %cDR\n",
255 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
256 return radeon_ttm_init(rdev);
259 void radeon_bo_fini(struct radeon_device *rdev)
261 radeon_ttm_fini(rdev);
264 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
265 struct list_head *head)
268 list_add(&lobj->list, head);
270 list_add_tail(&lobj->list, head);
274 int radeon_bo_list_reserve(struct list_head *head)
276 struct radeon_bo_list *lobj;
279 list_for_each_entry(lobj, head, list){
280 r = radeon_bo_reserve(lobj->bo, false);
281 if (unlikely(r != 0))
287 void radeon_bo_list_unreserve(struct list_head *head)
289 struct radeon_bo_list *lobj;
291 list_for_each_entry(lobj, head, list) {
292 /* only unreserve object we successfully reserved */
293 if (radeon_bo_is_reserved(lobj->bo))
294 radeon_bo_unreserve(lobj->bo);
298 int radeon_bo_list_validate(struct list_head *head, void *fence)
300 struct radeon_bo_list *lobj;
301 struct radeon_bo *bo;
302 struct radeon_fence *old_fence = NULL;
305 r = radeon_bo_list_reserve(head);
306 if (unlikely(r != 0)) {
309 list_for_each_entry(lobj, head, list) {
311 if (!bo->pin_count) {
313 radeon_ttm_placement_from_domain(bo,
316 radeon_ttm_placement_from_domain(bo,
319 r = ttm_bo_validate(&bo->tbo, &bo->placement,
324 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
325 lobj->tiling_flags = bo->tiling_flags;
327 old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
328 bo->tbo.sync_obj = radeon_fence_ref(fence);
329 bo->tbo.sync_obj_arg = NULL;
332 radeon_fence_unref(&old_fence);
338 void radeon_bo_list_unvalidate(struct list_head *head, void *fence)
340 struct radeon_bo_list *lobj;
341 struct radeon_fence *old_fence;
344 list_for_each_entry(lobj, head, list) {
345 old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
346 if (old_fence == fence) {
347 lobj->bo->tbo.sync_obj = NULL;
348 radeon_fence_unref(&old_fence);
351 radeon_bo_list_unreserve(head);
354 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
355 struct vm_area_struct *vma)
357 return ttm_fbdev_mmap(vma, &bo->tbo);
360 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
362 struct radeon_device *rdev = bo->rdev;
363 struct radeon_surface_reg *reg;
364 struct radeon_bo *old_object;
368 BUG_ON(!atomic_read(&bo->tbo.reserved));
370 if (!bo->tiling_flags)
373 if (bo->surface_reg >= 0) {
374 reg = &rdev->surface_regs[bo->surface_reg];
380 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
382 reg = &rdev->surface_regs[i];
386 old_object = reg->bo;
387 if (old_object->pin_count == 0)
391 /* if we are all out */
392 if (i == RADEON_GEM_MAX_SURFACES) {
395 /* find someone with a surface reg and nuke their BO */
396 reg = &rdev->surface_regs[steal];
397 old_object = reg->bo;
398 /* blow away the mapping */
399 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
400 ttm_bo_unmap_virtual(&old_object->tbo);
401 old_object->surface_reg = -1;
409 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
410 bo->tbo.mem.mm_node->start << PAGE_SHIFT,
411 bo->tbo.num_pages << PAGE_SHIFT);
415 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
417 struct radeon_device *rdev = bo->rdev;
418 struct radeon_surface_reg *reg;
420 if (bo->surface_reg == -1)
423 reg = &rdev->surface_regs[bo->surface_reg];
424 radeon_clear_surface_reg(rdev, bo->surface_reg);
427 bo->surface_reg = -1;
430 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
431 uint32_t tiling_flags, uint32_t pitch)
435 r = radeon_bo_reserve(bo, false);
436 if (unlikely(r != 0))
438 bo->tiling_flags = tiling_flags;
440 radeon_bo_unreserve(bo);
444 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
445 uint32_t *tiling_flags,
448 BUG_ON(!atomic_read(&bo->tbo.reserved));
450 *tiling_flags = bo->tiling_flags;
455 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
458 BUG_ON(!atomic_read(&bo->tbo.reserved));
460 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
464 radeon_bo_clear_surface_reg(bo);
468 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
472 if (bo->surface_reg >= 0)
473 radeon_bo_clear_surface_reg(bo);
477 if ((bo->surface_reg >= 0) && !has_moved)
480 return radeon_bo_get_surface_reg(bo);
483 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
484 struct ttm_mem_reg *mem)
486 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
487 radeon_bo_check_tiling(rbo, 0, 1);
490 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
492 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
493 radeon_bo_check_tiling(rbo, 0, 0);