SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon_fixed.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  34                                        struct drm_display_mode *mode,
  35                                        struct drm_display_mode *adjusted_mode)
  36 {
  37         struct drm_device *dev = crtc->dev;
  38         struct radeon_device *rdev = dev->dev_private;
  39         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  40         int xres = mode->hdisplay;
  41         int yres = mode->vdisplay;
  42         bool hscale = true, vscale = true;
  43         int hsync_wid;
  44         int vsync_wid;
  45         int hsync_start;
  46         int blank_width;
  47         u32 scale, inc, crtc_more_cntl;
  48         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  49         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  50         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  51         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  52
  53         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  54                 (RADEON_VERT_STRETCH_RESERVED |
  55                  RADEON_VERT_AUTO_RATIO_INC);
  56         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  57                 (RADEON_HORZ_FP_LOOP_STRETCH |
  58                  RADEON_HORZ_AUTO_RATIO_INC);
  59
  60         crtc_more_cntl = 0;
  61         if ((rdev->family == CHIP_RS100) ||
  62             (rdev->family == CHIP_RS200)) {
  63                 /* This is to workaround the asic bug for RMX, some versions
  64                    of BIOS dosen't have this register initialized correctly. */
  65                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  66         }
  67
  68
  69         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  70                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  71
  72         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  73         if (!hsync_wid)
  74                 hsync_wid = 1;
  75         hsync_start = mode->crtc_hsync_start - 8;
  76
  77         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  78                               | ((hsync_wid & 0x3f) << 16)
  79                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  80                                  ? RADEON_CRTC_H_SYNC_POL
  81                                  : 0));
  82
  83         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  84                                 | ((mode->crtc_vdisplay - 1) << 16));
  85
  86         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  87         if (!vsync_wid)
  88                 vsync_wid = 1;
  89
  90         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
  91                               | ((vsync_wid & 0x1f) << 16)
  92                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
  93                                  ? RADEON_CRTC_V_SYNC_POL
  94                                  : 0));
  95
  96         fp_horz_vert_active = 0;
  97
  98         if (native_mode->hdisplay == 0 ||
  99             native_mode->vdisplay == 0) {
 100                 hscale = false;
 101                 vscale = false;
 102         } else {
 103                 if (xres > native_mode->hdisplay)
 104                         xres = native_mode->hdisplay;
 105                 if (yres > native_mode->vdisplay)
 106                         yres = native_mode->vdisplay;
 107
 108                 if (xres == native_mode->hdisplay)
 109                         hscale = false;
 110                 if (yres == native_mode->vdisplay)
 111                         vscale = false;
 112         }
 113
 114         switch (radeon_crtc->rmx_type) {
 115         case RMX_FULL:
 116         case RMX_ASPECT:
 117                 if (!hscale)
 118                         fp_horz_stretch |= ((xres/8-1) << 16);
 119                 else {
 120                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 121                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 122                                 / native_mode->hdisplay + 1;
 123                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 124                                         RADEON_HORZ_STRETCH_BLEND |
 125                                         RADEON_HORZ_STRETCH_ENABLE |
 126                                         ((native_mode->hdisplay/8-1) << 16));
 127                 }
 128
 129                 if (!vscale)
 130                         fp_vert_stretch |= ((yres-1) << 12);
 131                 else {
 132                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 133                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 134                                 / native_mode->vdisplay + 1;
 135                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 136                                         RADEON_VERT_STRETCH_ENABLE |
 137                                         RADEON_VERT_STRETCH_BLEND |
 138                                         ((native_mode->vdisplay-1) << 12));
 139                 }
 140                 break;
 141         case RMX_CENTER:
 142                 fp_horz_stretch |= ((xres/8-1) << 16);
 143                 fp_vert_stretch |= ((yres-1) << 12);
 144
 145                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 146                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 147
 148                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 149                 if (blank_width > 110)
 150                         blank_width = 110;
 151
 152                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 153                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 154
 155                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 156                 if (!hsync_wid)
 157                         hsync_wid = 1;
 158
 159                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 160                                 | ((hsync_wid & 0x3f) << 16)
 161                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 162                                         ? RADEON_CRTC_H_SYNC_POL
 163                                         : 0));
 164
 165                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 166                                 | ((mode->crtc_vdisplay - 1) << 16));
 167
 168                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 169                 if (!vsync_wid)
 170                         vsync_wid = 1;
 171
 172                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 173                                         | ((vsync_wid & 0x1f) << 16)
 174                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 175                                                 ? RADEON_CRTC_V_SYNC_POL
 176                                                 : 0)));
 177
 178                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 179                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 180                 break;
 181         case RMX_OFF:
 182         default:
 183                 fp_horz_stretch |= ((xres/8-1) << 16);
 184                 fp_vert_stretch |= ((yres-1) << 12);
 185                 break;
 186         }
 187
 188         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 189         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 190         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 191         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 192         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 193         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 194         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 195         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 196 }
 197
 198 void radeon_restore_common_regs(struct drm_device *dev)
 199 {
 200         /* don't need this yet */
 201 }
 202
 203 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 204 {
 205         struct radeon_device *rdev = dev->dev_private;
 206         int i = 0;
 207
 208         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 209            the cause yet, but this workaround will mask the problem for now.
 210            Other chips usually will pass at the very first test, so the
 211            workaround shouldn't have any effect on them. */
 212         for (i = 0;
 213              (i < 10000 &&
 214               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 215              i++);
 216 }
 217
 218 static void radeon_pll_write_update(struct drm_device *dev)
 219 {
 220         struct radeon_device *rdev = dev->dev_private;
 221
 222         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 223
 224         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 225                            RADEON_PPLL_ATOMIC_UPDATE_W,
 226                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 227 }
 228
 229 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 230 {
 231         struct radeon_device *rdev = dev->dev_private;
 232         int i = 0;
 233
 234
 235         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 236            the cause yet, but this workaround will mask the problem for now.
 237            Other chips usually will pass at the very first test, so the
 238            workaround shouldn't have any effect on them. */
 239         for (i = 0;
 240              (i < 10000 &&
 241               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 242              i++);
 243 }
 244
 245 static void radeon_pll2_write_update(struct drm_device *dev)
 246 {
 247         struct radeon_device *rdev = dev->dev_private;
 248
 249         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 250
 251         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 252                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 253                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 254 }
 255
 256 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 257                                        uint16_t fb_div)
 258 {
 259         unsigned int vcoFreq;
 260
 261         if (!ref_div)
 262                 return 1;
 263
 264         vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
 265
 266         /*
 267          * This is horribly crude: the VCO frequency range is divided into
 268          * 3 parts, each part having a fixed PLL gain value.
 269          */
 270         if (vcoFreq >= 30000)
 271                 /*
 272                  * [300..max] MHz : 7
 273                  */
 274                 return 7;
 275         else if (vcoFreq >= 18000)
 276                 /*
 277                  * [180..300) MHz : 4
 278                  */
 279                 return 4;
 280         else
 281                 /*
 282                  * [0..180) MHz : 1
 283                  */
 284                 return 1;
 285 }
 286
 287 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 288 {
 289         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 290         struct drm_device *dev = crtc->dev;
 291         struct radeon_device *rdev = dev->dev_private;
 292         uint32_t mask;
 293
 294         if (radeon_crtc->crtc_id)
 295                 mask = (RADEON_CRTC2_EN |
 296                         RADEON_CRTC2_DISP_DIS |
 297                         RADEON_CRTC2_VSYNC_DIS |
 298                         RADEON_CRTC2_HSYNC_DIS |
 299                         RADEON_CRTC2_DISP_REQ_EN_B);
 300         else
 301                 mask = (RADEON_CRTC_DISPLAY_DIS |
 302                         RADEON_CRTC_VSYNC_DIS |
 303                         RADEON_CRTC_HSYNC_DIS);
 304
 305         switch (mode) {
 306         case DRM_MODE_DPMS_ON:
 307                 if (radeon_crtc->crtc_id)
 308                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
 309                 else {
 310                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 311                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 312                         WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 313                 }
 314                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 315                 radeon_crtc_load_lut(crtc);
 316                 break;
 317         case DRM_MODE_DPMS_STANDBY:
 318         case DRM_MODE_DPMS_SUSPEND:
 319         case DRM_MODE_DPMS_OFF:
 320                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 321                 if (radeon_crtc->crtc_id)
 322                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
 323                 else {
 324                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 325                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 326                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 327                 }
 328                 break;
 329         }
 330 }
 331
 332 /* properly set crtc bpp when using atombios */
 333 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
 334 {
 335         struct drm_device *dev = crtc->dev;
 336         struct radeon_device *rdev = dev->dev_private;
 337         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 338         int format;
 339         uint32_t crtc_gen_cntl;
 340         uint32_t disp_merge_cntl;
 341         uint32_t crtc_pitch;
 342
 343         switch (crtc->fb->bits_per_pixel) {
 344         case 8:
 345                 format = 2;
 346                 break;
 347         case 15:      /*  555 */
 348                 format = 3;
 349                 break;
 350         case 16:      /*  565 */
 351                 format = 4;
 352                 break;
 353         case 24:      /*  RGB */
 354                 format = 5;
 355                 break;
 356         case 32:      /* xRGB */
 357                 format = 6;
 358                 break;
 359         default:
 360                 return;
 361         }
 362
 363         crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
 364                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 365                        (crtc->fb->bits_per_pixel * 8));
 366         crtc_pitch |= crtc_pitch << 16;
 367
 368         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 369
 370         switch (radeon_crtc->crtc_id) {
 371         case 0:
 372                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 373                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 374                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 375
 376                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
 377                 crtc_gen_cntl |= (format << 8);
 378                 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
 379                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 380                 break;
 381         case 1:
 382                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 383                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 384                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
 385
 386                 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
 387                 crtc_gen_cntl |= (format << 8);
 388                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
 389                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
 390                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
 391                 break;
 392         }
 393 }
 394
 395 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 396                          struct drm_framebuffer *old_fb)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         struct radeon_device *rdev = dev->dev_private;
 400         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 401         struct radeon_framebuffer *radeon_fb;
 402         struct drm_gem_object *obj;
 403         uint64_t base;
 404         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 405         uint32_t crtc_pitch, pitch_pixels;
 406         uint32_t tiling_flags;
 407         int format;
 408         uint32_t gen_cntl_reg, gen_cntl_val;
 409
 410         DRM_DEBUG("\n");
 411         /* no fb bound */
 412         if (!crtc->fb) {
 413                 DRM_DEBUG("No FB bound\n");
 414                 return 0;
 415         }
 416
 417         radeon_fb = to_radeon_framebuffer(crtc->fb);
 418
 419         switch (crtc->fb->bits_per_pixel) {
 420         case 8:
 421                 format = 2;
 422                 break;
 423         case 15:      /*  555 */
 424                 format = 3;
 425                 break;
 426         case 16:      /*  565 */
 427                 format = 4;
 428                 break;
 429         case 24:      /*  RGB */
 430                 format = 5;
 431                 break;
 432         case 32:      /* xRGB */
 433                 format = 6;
 434                 break;
 435         default:
 436                 return false;
 437         }
 438
 439         obj = radeon_fb->obj;
 440         if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
 441                 return -EINVAL;
 442         }
 443         /* if scanout was in GTT this really wouldn't work */
 444         /* crtc offset is from display base addr not FB location */
 445         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
 446
 447         base -= radeon_crtc->legacy_display_base_addr;
 448
 449         crtc_offset_cntl = 0;
 450
 451         pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 452         crtc_pitch  = (((pitch_pixels * crtc->fb->bits_per_pixel) +
 453                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 454                        (crtc->fb->bits_per_pixel * 8));
 455         crtc_pitch |= crtc_pitch << 16;
 456
 457         radeon_object_get_tiling_flags(obj->driver_private,
 458                                        &tiling_flags, NULL);
 459         if (tiling_flags & RADEON_TILING_MICRO)
 460                 DRM_ERROR("trying to scanout microtiled buffer\n");
 461
 462         if (tiling_flags & RADEON_TILING_MACRO) {
 463                 if (ASIC_IS_R300(rdev))
 464                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 465                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 466                                              R300_CRTC_MACRO_TILE_EN);
 467                 else
 468                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 469         } else {
 470                 if (ASIC_IS_R300(rdev))
 471                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 472                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 473                                               R300_CRTC_MACRO_TILE_EN);
 474                 else
 475                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 476         }
 477
 478         if (tiling_flags & RADEON_TILING_MACRO) {
 479                 if (ASIC_IS_R300(rdev)) {
 480                         crtc_tile_x0_y0 = x | (y << 16);
 481                         base &= ~0x7ff;
 482                 } else {
 483                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 484                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 485                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 486                         crtc_offset_cntl |= (y % 16);
 487                 }
 488         } else {
 489                 int offset = y * pitch_pixels + x;
 490                 switch (crtc->fb->bits_per_pixel) {
 491                 case 8:
 492                         offset *= 1;
 493                         break;
 494                 case 15:
 495                 case 16:
 496                         offset *= 2;
 497                         break;
 498                 case 24:
 499                         offset *= 3;
 500                         break;
 501                 case 32:
 502                         offset *= 4;
 503                         break;
 504                 default:
 505                         return false;
 506                 }
 507                 base += offset;
 508         }
 509
 510         base &= ~7;
 511
 512         if (radeon_crtc->crtc_id == 1)
 513                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 514         else
 515                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 516
 517         gen_cntl_val = RREG32(gen_cntl_reg);
 518         gen_cntl_val &= ~(0xf << 8);
 519         gen_cntl_val |= (format << 8);
 520         WREG32(gen_cntl_reg, gen_cntl_val);
 521
 522         crtc_offset = (u32)base;
 523
 524         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 525
 526         if (ASIC_IS_R300(rdev)) {
 527                 if (radeon_crtc->crtc_id)
 528                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 529                 else
 530                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 531         }
 532         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 533         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 534         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 535
 536         if (old_fb && old_fb != crtc->fb) {
 537                 radeon_fb = to_radeon_framebuffer(old_fb);
 538                 radeon_gem_object_unpin(radeon_fb->obj);
 539         }
 540
 541         /* Bytes per pixel may have changed */
 542         radeon_bandwidth_update(rdev);
 543
 544         return 0;
 545 }
 546
 547 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 548 {
 549         struct drm_device *dev = crtc->dev;
 550         struct radeon_device *rdev = dev->dev_private;
 551         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 552         struct drm_encoder *encoder;
 553         int format;
 554         int hsync_start;
 555         int hsync_wid;
 556         int vsync_wid;
 557         uint32_t crtc_h_total_disp;
 558         uint32_t crtc_h_sync_strt_wid;
 559         uint32_t crtc_v_total_disp;
 560         uint32_t crtc_v_sync_strt_wid;
 561         bool is_tv = false;
 562
 563         DRM_DEBUG("\n");
 564         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 565                 if (encoder->crtc == crtc) {
 566                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 567                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 568                                 is_tv = true;
 569                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 570                                 break;
 571                         }
 572                 }
 573         }
 574
 575         switch (crtc->fb->bits_per_pixel) {
 576         case 8:
 577                 format = 2;
 578                 break;
 579         case 15:      /*  555 */
 580                 format = 3;
 581                 break;
 582         case 16:      /*  565 */
 583                 format = 4;
 584                 break;
 585         case 24:      /*  RGB */
 586                 format = 5;
 587                 break;
 588         case 32:      /* xRGB */
 589                 format = 6;
 590                 break;
 591         default:
 592                 return false;
 593         }
 594
 595         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 596                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 597
 598         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 599         if (!hsync_wid)
 600                 hsync_wid = 1;
 601         hsync_start = mode->crtc_hsync_start - 8;
 602
 603         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 604                                 | ((hsync_wid & 0x3f) << 16)
 605                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 606                                    ? RADEON_CRTC_H_SYNC_POL
 607                                    : 0));
 608
 609         /* This works for double scan mode. */
 610         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 611                              | ((mode->crtc_vdisplay - 1) << 16));
 612
 613         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 614         if (!vsync_wid)
 615                 vsync_wid = 1;
 616
 617         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 618                                 | ((vsync_wid & 0x1f) << 16)
 619                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 620                                    ? RADEON_CRTC_V_SYNC_POL
 621                                    : 0));
 622
 623         /* TODO -> Dell Server */
 624         if (0) {
 625                 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 626                 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 627                 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 628                 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 629
 630                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
 631                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 632
 633                 /* For CRT on DAC2, don't turn it on if BIOS didn't
 634                    enable it, even it's detected.
 635                 */
 636                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 637                 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
 638                 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 639
 640                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 641                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 642                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 643                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 644         }
 645
 646         if (radeon_crtc->crtc_id) {
 647                 uint32_t crtc2_gen_cntl;
 648                 uint32_t disp2_merge_cntl;
 649
 650                 /* if TV DAC is enabled for another crtc and keep it enabled */
 651                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 652                 crtc2_gen_cntl |= ((format << 8)
 653                                    | RADEON_CRTC2_VSYNC_DIS
 654                                    | RADEON_CRTC2_HSYNC_DIS
 655                                    | RADEON_CRTC2_DISP_DIS
 656                                    | RADEON_CRTC2_DISP_REQ_EN_B
 657                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 658                                       ? RADEON_CRTC2_DBL_SCAN_EN
 659                                       : 0)
 660                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 661                                       ? RADEON_CRTC2_CSYNC_EN
 662                                       : 0)
 663                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 664                                       ? RADEON_CRTC2_INTERLACE_EN
 665                                       : 0));
 666
 667                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 668                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 669
 670                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 671                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 672
 673                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 674                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 675         } else {
 676                 uint32_t crtc_gen_cntl;
 677                 uint32_t crtc_ext_cntl;
 678                 uint32_t disp_merge_cntl;
 679
 680                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 681                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 682                                  | (format << 8)
 683                                  | RADEON_CRTC_DISP_REQ_EN_B
 684                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 685                                     ? RADEON_CRTC_DBL_SCAN_EN
 686                                     : 0)
 687                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 688                                     ? RADEON_CRTC_CSYNC_EN
 689                                     : 0)
 690                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 691                                     ? RADEON_CRTC_INTERLACE_EN
 692                                     : 0));
 693
 694                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 695                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 696                                   RADEON_CRTC_VSYNC_DIS |
 697                                   RADEON_CRTC_HSYNC_DIS |
 698                                   RADEON_CRTC_DISPLAY_DIS);
 699
 700                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 701                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 702
 703                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 704                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 705                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 706         }
 707
 708         if (is_tv)
 709                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 710                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 711                                                  &crtc_v_sync_strt_wid);
 712
 713         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 714         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 715         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 716         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 717
 718         return true;
 719 }
 720
 721 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 722 {
 723         struct drm_device *dev = crtc->dev;
 724         struct radeon_device *rdev = dev->dev_private;
 725         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 726         struct drm_encoder *encoder;
 727         uint32_t feedback_div = 0;
 728         uint32_t frac_fb_div = 0;
 729         uint32_t reference_div = 0;
 730         uint32_t post_divider = 0;
 731         uint32_t freq = 0;
 732         uint8_t pll_gain;
 733         int pll_flags = RADEON_PLL_LEGACY;
 734         bool use_bios_divs = false;
 735         /* PLL registers */
 736         uint32_t pll_ref_div = 0;
 737         uint32_t pll_fb_post_div = 0;
 738         uint32_t htotal_cntl = 0;
 739         bool is_tv = false;
 740         struct radeon_pll *pll;
 741
 742         struct {
 743                 int divider;
 744                 int bitvalue;
 745         } *post_div, post_divs[]   = {
 746                 /* From RAGE 128 VR/RAGE 128 GL Register
 747                  * Reference Manual (Technical Reference
 748                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 749                  * 3-17 (PLL_DIV_[3:0]).
 750                  */
 751                 {  1, 0 },              /* VCLK_SRC                 */
 752                 {  2, 1 },              /* VCLK_SRC/2               */
 753                 {  4, 2 },              /* VCLK_SRC/4               */
 754                 {  8, 3 },              /* VCLK_SRC/8               */
 755                 {  3, 4 },              /* VCLK_SRC/3               */
 756                 { 16, 5 },              /* VCLK_SRC/16              */
 757                 {  6, 6 },              /* VCLK_SRC/6               */
 758                 { 12, 7 },              /* VCLK_SRC/12              */
 759                 {  0, 0 }
 760         };
 761
 762         if (radeon_crtc->crtc_id)
 763                 pll = &rdev->clock.p2pll;
 764         else
 765                 pll = &rdev->clock.p1pll;
 766
 767         if (mode->clock > 200000) /* range limits??? */
 768                 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 769         else
 770                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 771
 772         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 773                 if (encoder->crtc == crtc) {
 774                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 775
 776                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 777                                 is_tv = true;
 778                                 break;
 779                         }
 780
 781                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 782                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 783                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 784                                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 785                                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 786                                 if (lvds) {
 787                                         if (lvds->use_bios_dividers) {
 788                                                 pll_ref_div = lvds->panel_ref_divider;
 789                                                 pll_fb_post_div   = (lvds->panel_fb_divider |
 790                                                                      (lvds->panel_post_divider << 16));
 791                                                 htotal_cntl  = 0;
 792                                                 use_bios_divs = true;
 793                                         }
 794                                 }
 795                                 pll_flags |= RADEON_PLL_USE_REF_DIV;
 796                         }
 797                 }
 798         }
 799
 800         DRM_DEBUG("\n");
 801
 802         if (!use_bios_divs) {
 803                 radeon_compute_pll(pll, mode->clock,
 804                                    &freq, &feedback_div, &frac_fb_div,
 805                                    &reference_div, &post_divider,
 806                                    pll_flags);
 807
 808                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 809                         if (post_div->divider == post_divider)
 810                                 break;
 811                 }
 812
 813                 if (!post_div->divider)
 814                         post_div = &post_divs[0];
 815
 816                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 817                           (unsigned)freq,
 818                           feedback_div,
 819                           reference_div,
 820                           post_divider);
 821
 822                 pll_ref_div   = reference_div;
 823 #if defined(__powerpc__) && (0) /* TODO */
 824                 /* apparently programming this otherwise causes a hang??? */
 825                 if (info->MacModel == RADEON_MAC_IBOOK)
 826                         pll_fb_post_div = 0x000600ad;
 827                 else
 828 #endif
 829                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 830
 831                 htotal_cntl    = mode->htotal & 0x7;
 832
 833         }
 834
 835         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 836                                            pll_ref_div & 0x3ff,
 837                                            pll_fb_post_div & 0x7ff);
 838
 839         if (radeon_crtc->crtc_id) {
 840                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 841                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 842                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 843
 844                 if (is_tv) {
 845                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 846                                                      &pll_ref_div, &pll_fb_post_div,
 847                                                      &pixclks_cntl);
 848                 }
 849
 850                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 851                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 852                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 853
 854                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 855                              RADEON_P2PLL_RESET
 856                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 857                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 858                              ~(RADEON_P2PLL_RESET
 859                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 860                                | RADEON_P2PLL_PVG_MASK));
 861
 862                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 863                              pll_ref_div,
 864                              ~RADEON_P2PLL_REF_DIV_MASK);
 865
 866                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 867                              pll_fb_post_div,
 868                              ~RADEON_P2PLL_FB0_DIV_MASK);
 869
 870                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 871                              pll_fb_post_div,
 872                              ~RADEON_P2PLL_POST0_DIV_MASK);
 873
 874                 radeon_pll2_write_update(dev);
 875                 radeon_pll2_wait_for_read_update_complete(dev);
 876
 877                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 878
 879                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 880                              0,
 881                              ~(RADEON_P2PLL_RESET
 882                                | RADEON_P2PLL_SLEEP
 883                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 884
 885                 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 886                           (unsigned)pll_ref_div,
 887                           (unsigned)pll_fb_post_div,
 888                           (unsigned)htotal_cntl,
 889                           RREG32_PLL(RADEON_P2PLL_CNTL));
 890                 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
 891                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 892                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 893                           (unsigned)((pll_fb_post_div &
 894                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 895
 896                 mdelay(50); /* Let the clock to lock */
 897
 898                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 899                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 900                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 901
 902                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 903         } else {
 904                 uint32_t pixclks_cntl;
 905
 906
 907                 if (is_tv) {
 908                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 909                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 910                                                      &pll_fb_post_div, &pixclks_cntl);
 911                 }
 912
 913                 if (rdev->flags & RADEON_IS_MOBILITY) {
 914                         /* A temporal workaround for the occational blanking on certain laptop panels.
 915                            This appears to related to the PLL divider registers (fail to lock?).
 916                            It occurs even when all dividers are the same with their old settings.
 917                            In this case we really don't need to fiddle with PLL registers.
 918                            By doing this we can avoid the blanking problem with some panels.
 919                         */
 920                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 921                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 922                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 923                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 924                                          RADEON_PLL_DIV_SEL,
 925                                          ~(RADEON_PLL_DIV_SEL));
 926                                 r100_pll_errata_after_index(rdev);
 927                                 return;
 928                         }
 929                 }
 930
 931                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 932                              RADEON_VCLK_SRC_SEL_CPUCLK,
 933                              ~(RADEON_VCLK_SRC_SEL_MASK));
 934                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 935                              RADEON_PPLL_RESET
 936                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 937                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 938                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 939                              ~(RADEON_PPLL_RESET
 940                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 941                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 942                                | RADEON_PPLL_PVG_MASK));
 943
 944                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 945                          RADEON_PLL_DIV_SEL,
 946                          ~(RADEON_PLL_DIV_SEL));
 947                 r100_pll_errata_after_index(rdev);
 948
 949                 if (ASIC_IS_R300(rdev) ||
 950                     (rdev->family == CHIP_RS300) ||
 951                     (rdev->family == CHIP_RS400) ||
 952                     (rdev->family == CHIP_RS480)) {
 953                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 954                                 /* When restoring console mode, use saved PPLL_REF_DIV
 955                                  * setting.
 956                                  */
 957                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 958                                              pll_ref_div,
 959                                              0);
 960                         } else {
 961                                 /* R300 uses ref_div_acc field as real ref divider */
 962                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 963                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 964                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 965                         }
 966                 } else
 967                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 968                                      pll_ref_div,
 969                                      ~RADEON_PPLL_REF_DIV_MASK);
 970
 971                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 972                              pll_fb_post_div,
 973                              ~RADEON_PPLL_FB3_DIV_MASK);
 974
 975                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 976                              pll_fb_post_div,
 977                              ~RADEON_PPLL_POST3_DIV_MASK);
 978
 979                 radeon_pll_write_update(dev);
 980                 radeon_pll_wait_for_read_update_complete(dev);
 981
 982                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 983
 984                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 985                              0,
 986                              ~(RADEON_PPLL_RESET
 987                                | RADEON_PPLL_SLEEP
 988                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 989                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 990
 991                 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 992                           pll_ref_div,
 993                           pll_fb_post_div,
 994                           (unsigned)htotal_cntl,
 995                           RREG32_PLL(RADEON_PPLL_CNTL));
 996                 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
 997                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 998                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
 999                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1000
1001                 mdelay(50); /* Let the clock to lock */
1002
1003                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1004                              RADEON_VCLK_SRC_SEL_PPLLCLK,
1005                              ~(RADEON_VCLK_SRC_SEL_MASK));
1006
1007                 if (is_tv)
1008                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1009         }
1010 }
1011
1012 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1013                                    struct drm_display_mode *mode,
1014                                    struct drm_display_mode *adjusted_mode)
1015 {
1016         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1017                 return false;
1018         return true;
1019 }
1020
1021 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1022                                  struct drm_display_mode *mode,
1023                                  struct drm_display_mode *adjusted_mode,
1024                                  int x, int y, struct drm_framebuffer *old_fb)
1025 {
1026         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1027
1028         /* TODO TV */
1029         radeon_crtc_set_base(crtc, x, y, old_fb);
1030         radeon_set_crtc_timing(crtc, adjusted_mode);
1031         radeon_set_pll(crtc, adjusted_mode);
1032         if (radeon_crtc->crtc_id == 0) {
1033                 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
1034         } else {
1035                 if (radeon_crtc->rmx_type != RMX_OFF) {
1036                         /* FIXME: only first crtc has rmx what should we
1037                          * do ?
1038                          */
1039                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1040                 }
1041         }
1042         return 0;
1043 }
1044
1045 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1046 {
1047         struct drm_device *dev = crtc->dev;
1048         struct drm_crtc *crtci;
1049
1050         /*
1051         * The hardware wedges sometimes if you reconfigure one CRTC
1052         * whilst another is running (see fdo bug #24611).
1053         */
1054         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1055                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1056 }
1057
1058 static void radeon_crtc_commit(struct drm_crtc *crtc)
1059 {
1060         struct drm_device *dev = crtc->dev;
1061         struct drm_crtc *crtci;
1062
1063         /*
1064         * Reenable the CRTCs that should be running.
1065         */
1066         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1067                 if (crtci->enabled)
1068                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1069         }
1070 }
1071
1072 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1073         .dpms = radeon_crtc_dpms,
1074         .mode_fixup = radeon_crtc_mode_fixup,
1075         .mode_set = radeon_crtc_mode_set,
1076         .mode_set_base = radeon_crtc_set_base,
1077         .prepare = radeon_crtc_prepare,
1078         .commit = radeon_crtc_commit,
1079         .load_lut = radeon_crtc_load_lut,
1080 };
1081
1082
1083 void radeon_legacy_init_crtc(struct drm_device *dev,
1084                                struct radeon_crtc *radeon_crtc)
1085 {
1086         if (radeon_crtc->crtc_id == 1)
1087                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1088         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1089 }