SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon_fixed.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  34                                        struct drm_display_mode *mode,
  35                                        struct drm_display_mode *adjusted_mode)
  36 {
  37         struct drm_device *dev = crtc->dev;
  38         struct radeon_device *rdev = dev->dev_private;
  39         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  40         int xres = mode->hdisplay;
  41         int yres = mode->vdisplay;
  42         bool hscale = true, vscale = true;
  43         int hsync_wid;
  44         int vsync_wid;
  45         int hsync_start;
  46         int blank_width;
  47         u32 scale, inc, crtc_more_cntl;
  48         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  49         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  50         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  51         struct radeon_native_mode *native_mode = &radeon_crtc->native_mode;
  52
  53         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  54                 (RADEON_VERT_STRETCH_RESERVED |
  55                  RADEON_VERT_AUTO_RATIO_INC);
  56         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  57                 (RADEON_HORZ_FP_LOOP_STRETCH |
  58                  RADEON_HORZ_AUTO_RATIO_INC);
  59
  60         crtc_more_cntl = 0;
  61         if ((rdev->family == CHIP_RS100) ||
  62             (rdev->family == CHIP_RS200)) {
  63                 /* This is to workaround the asic bug for RMX, some versions
  64                    of BIOS dosen't have this register initialized correctly. */
  65                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  66         }
  67
  68
  69         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  70                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  71
  72         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  73         if (!hsync_wid)
  74                 hsync_wid = 1;
  75         hsync_start = mode->crtc_hsync_start - 8;
  76
  77         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  78                               | ((hsync_wid & 0x3f) << 16)
  79                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  80                                  ? RADEON_CRTC_H_SYNC_POL
  81                                  : 0));
  82
  83         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  84                                 | ((mode->crtc_vdisplay - 1) << 16));
  85
  86         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  87         if (!vsync_wid)
  88                 vsync_wid = 1;
  89
  90         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
  91                               | ((vsync_wid & 0x1f) << 16)
  92                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
  93                                  ? RADEON_CRTC_V_SYNC_POL
  94                                  : 0));
  95
  96         fp_horz_vert_active = 0;
  97
  98         if (native_mode->panel_xres == 0 ||
  99             native_mode->panel_yres == 0) {
 100                 hscale = false;
 101                 vscale = false;
 102         } else {
 103                 if (xres > native_mode->panel_xres)
 104                         xres = native_mode->panel_xres;
 105                 if (yres > native_mode->panel_yres)
 106                         yres = native_mode->panel_yres;
 107
 108                 if (xres == native_mode->panel_xres)
 109                         hscale = false;
 110                 if (yres == native_mode->panel_yres)
 111                         vscale = false;
 112         }
 113
 114         switch (radeon_crtc->rmx_type) {
 115         case RMX_FULL:
 116         case RMX_ASPECT:
 117                 if (!hscale)
 118                         fp_horz_stretch |= ((xres/8-1) << 16);
 119                 else {
 120                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 121                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 122                                 / native_mode->panel_xres + 1;
 123                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 124                                         RADEON_HORZ_STRETCH_BLEND |
 125                                         RADEON_HORZ_STRETCH_ENABLE |
 126                                         ((native_mode->panel_xres/8-1) << 16));
 127                 }
 128
 129                 if (!vscale)
 130                         fp_vert_stretch |= ((yres-1) << 12);
 131                 else {
 132                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 133                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 134                                 / native_mode->panel_yres + 1;
 135                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 136                                         RADEON_VERT_STRETCH_ENABLE |
 137                                         RADEON_VERT_STRETCH_BLEND |
 138                                         ((native_mode->panel_yres-1) << 12));
 139                 }
 140                 break;
 141         case RMX_CENTER:
 142                 fp_horz_stretch |= ((xres/8-1) << 16);
 143                 fp_vert_stretch |= ((yres-1) << 12);
 144
 145                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 146                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 147
 148                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 149                 if (blank_width > 110)
 150                         blank_width = 110;
 151
 152                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 153                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 154
 155                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 156                 if (!hsync_wid)
 157                         hsync_wid = 1;
 158
 159                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 160                                 | ((hsync_wid & 0x3f) << 16)
 161                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 162                                         ? RADEON_CRTC_H_SYNC_POL
 163                                         : 0));
 164
 165                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 166                                 | ((mode->crtc_vdisplay - 1) << 16));
 167
 168                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 169                 if (!vsync_wid)
 170                         vsync_wid = 1;
 171
 172                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 173                                         | ((vsync_wid & 0x1f) << 16)
 174                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 175                                                 ? RADEON_CRTC_V_SYNC_POL
 176                                                 : 0)));
 177
 178                 fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) |
 179                                 (((native_mode->panel_xres / 8) & 0x1ff) << 16));
 180                 break;
 181         case RMX_OFF:
 182         default:
 183                 fp_horz_stretch |= ((xres/8-1) << 16);
 184                 fp_vert_stretch |= ((yres-1) << 12);
 185                 break;
 186         }
 187
 188         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 189         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 190         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 191         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 192         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 193         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 194         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 195         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 196 }
 197
 198 void radeon_restore_common_regs(struct drm_device *dev)
 199 {
 200         /* don't need this yet */
 201 }
 202
 203 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 204 {
 205         struct radeon_device *rdev = dev->dev_private;
 206         int i = 0;
 207
 208         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 209            the cause yet, but this workaround will mask the problem for now.
 210            Other chips usually will pass at the very first test, so the
 211            workaround shouldn't have any effect on them. */
 212         for (i = 0;
 213              (i < 10000 &&
 214               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 215              i++);
 216 }
 217
 218 static void radeon_pll_write_update(struct drm_device *dev)
 219 {
 220         struct radeon_device *rdev = dev->dev_private;
 221
 222         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 223
 224         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 225                            RADEON_PPLL_ATOMIC_UPDATE_W,
 226                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 227 }
 228
 229 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 230 {
 231         struct radeon_device *rdev = dev->dev_private;
 232         int i = 0;
 233
 234
 235         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 236            the cause yet, but this workaround will mask the problem for now.
 237            Other chips usually will pass at the very first test, so the
 238            workaround shouldn't have any effect on them. */
 239         for (i = 0;
 240              (i < 10000 &&
 241               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 242              i++);
 243 }
 244
 245 static void radeon_pll2_write_update(struct drm_device *dev)
 246 {
 247         struct radeon_device *rdev = dev->dev_private;
 248
 249         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 250
 251         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 252                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 253                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 254 }
 255
 256 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 257                                        uint16_t fb_div)
 258 {
 259         unsigned int vcoFreq;
 260
 261         if (!ref_div)
 262                 return 1;
 263
 264         vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
 265
 266         /*
 267          * This is horribly crude: the VCO frequency range is divided into
 268          * 3 parts, each part having a fixed PLL gain value.
 269          */
 270         if (vcoFreq >= 30000)
 271                 /*
 272                  * [300..max] MHz : 7
 273                  */
 274                 return 7;
 275         else if (vcoFreq >= 18000)
 276                 /*
 277                  * [180..300) MHz : 4
 278                  */
 279                 return 4;
 280         else
 281                 /*
 282                  * [0..180) MHz : 1
 283                  */
 284                 return 1;
 285 }
 286
 287 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 288 {
 289         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 290         struct drm_device *dev = crtc->dev;
 291         struct radeon_device *rdev = dev->dev_private;
 292         uint32_t mask;
 293
 294         if (radeon_crtc->crtc_id)
 295                 mask = (RADEON_CRTC2_EN |
 296                         RADEON_CRTC2_DISP_DIS |
 297                         RADEON_CRTC2_VSYNC_DIS |
 298                         RADEON_CRTC2_HSYNC_DIS |
 299                         RADEON_CRTC2_DISP_REQ_EN_B);
 300         else
 301                 mask = (RADEON_CRTC_DISPLAY_DIS |
 302                         RADEON_CRTC_VSYNC_DIS |
 303                         RADEON_CRTC_HSYNC_DIS);
 304
 305         switch (mode) {
 306         case DRM_MODE_DPMS_ON:
 307                 if (radeon_crtc->crtc_id)
 308                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
 309                 else {
 310                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 311                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 312                         WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 313                 }
 314                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 315                 radeon_crtc_load_lut(crtc);
 316                 break;
 317         case DRM_MODE_DPMS_STANDBY:
 318         case DRM_MODE_DPMS_SUSPEND:
 319         case DRM_MODE_DPMS_OFF:
 320                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 321                 if (radeon_crtc->crtc_id)
 322                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
 323                 else {
 324                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 325                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 326                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 327                 }
 328                 break;
 329         }
 330 }
 331
 332 /* properly set crtc bpp when using atombios */
 333 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
 334 {
 335         struct drm_device *dev = crtc->dev;
 336         struct radeon_device *rdev = dev->dev_private;
 337         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 338         int format;
 339         uint32_t crtc_gen_cntl;
 340         uint32_t disp_merge_cntl;
 341         uint32_t crtc_pitch;
 342
 343         switch (crtc->fb->bits_per_pixel) {
 344         case 8:
 345                 format = 2;
 346                 break;
 347         case 15:      /*  555 */
 348                 format = 3;
 349                 break;
 350         case 16:      /*  565 */
 351                 format = 4;
 352                 break;
 353         case 24:      /*  RGB */
 354                 format = 5;
 355                 break;
 356         case 32:      /* xRGB */
 357                 format = 6;
 358                 break;
 359         default:
 360                 return;
 361         }
 362
 363         crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
 364                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 365                        (crtc->fb->bits_per_pixel * 8));
 366         crtc_pitch |= crtc_pitch << 16;
 367
 368         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 369
 370         switch (radeon_crtc->crtc_id) {
 371         case 0:
 372                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 373                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 374                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 375
 376                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
 377                 crtc_gen_cntl |= (format << 8);
 378                 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
 379                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 380                 break;
 381         case 1:
 382                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 383                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 384                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
 385
 386                 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
 387                 crtc_gen_cntl |= (format << 8);
 388                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
 389                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
 390                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
 391                 break;
 392         }
 393 }
 394
 395 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 396                          struct drm_framebuffer *old_fb)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         struct radeon_device *rdev = dev->dev_private;
 400         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 401         struct radeon_framebuffer *radeon_fb;
 402         struct drm_gem_object *obj;
 403         uint64_t base;
 404         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 405         uint32_t crtc_pitch, pitch_pixels;
 406         uint32_t tiling_flags;
 407         int format;
 408         uint32_t gen_cntl_reg, gen_cntl_val;
 409
 410         DRM_DEBUG("\n");
 411
 412         radeon_fb = to_radeon_framebuffer(crtc->fb);
 413
 414         switch (crtc->fb->bits_per_pixel) {
 415         case 8:
 416                 format = 2;
 417                 break;
 418         case 15:      /*  555 */
 419                 format = 3;
 420                 break;
 421         case 16:      /*  565 */
 422                 format = 4;
 423                 break;
 424         case 24:      /*  RGB */
 425                 format = 5;
 426                 break;
 427         case 32:      /* xRGB */
 428                 format = 6;
 429                 break;
 430         default:
 431                 return false;
 432         }
 433
 434         obj = radeon_fb->obj;
 435         if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
 436                 return -EINVAL;
 437         }
 438         /* if scanout was in GTT this really wouldn't work */
 439         /* crtc offset is from display base addr not FB location */
 440         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
 441
 442         base -= radeon_crtc->legacy_display_base_addr;
 443
 444         crtc_offset_cntl = 0;
 445
 446         pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 447         crtc_pitch  = (((pitch_pixels * crtc->fb->bits_per_pixel) +
 448                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 449                        (crtc->fb->bits_per_pixel * 8));
 450         crtc_pitch |= crtc_pitch << 16;
 451
 452         radeon_object_get_tiling_flags(obj->driver_private,
 453                                        &tiling_flags, NULL);
 454         if (tiling_flags & RADEON_TILING_MICRO)
 455                 DRM_ERROR("trying to scanout microtiled buffer\n");
 456
 457         if (tiling_flags & RADEON_TILING_MACRO) {
 458                 if (ASIC_IS_R300(rdev))
 459                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 460                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 461                                              R300_CRTC_MACRO_TILE_EN);
 462                 else
 463                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 464         } else {
 465                 if (ASIC_IS_R300(rdev))
 466                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 467                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 468                                               R300_CRTC_MACRO_TILE_EN);
 469                 else
 470                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 471         }
 472
 473         if (tiling_flags & RADEON_TILING_MACRO) {
 474                 if (ASIC_IS_R300(rdev)) {
 475                         crtc_tile_x0_y0 = x | (y << 16);
 476                         base &= ~0x7ff;
 477                 } else {
 478                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 479                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 480                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 481                         crtc_offset_cntl |= (y % 16);
 482                 }
 483         } else {
 484                 int offset = y * pitch_pixels + x;
 485                 switch (crtc->fb->bits_per_pixel) {
 486                 case 8:
 487                         offset *= 1;
 488                         break;
 489                 case 15:
 490                 case 16:
 491                         offset *= 2;
 492                         break;
 493                 case 24:
 494                         offset *= 3;
 495                         break;
 496                 case 32:
 497                         offset *= 4;
 498                         break;
 499                 default:
 500                         return false;
 501                 }
 502                 base += offset;
 503         }
 504
 505         base &= ~7;
 506
 507         if (radeon_crtc->crtc_id == 1)
 508                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 509         else
 510                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 511
 512         gen_cntl_val = RREG32(gen_cntl_reg);
 513         gen_cntl_val &= ~(0xf << 8);
 514         gen_cntl_val |= (format << 8);
 515         WREG32(gen_cntl_reg, gen_cntl_val);
 516
 517         crtc_offset = (u32)base;
 518
 519         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 520
 521         if (ASIC_IS_R300(rdev)) {
 522                 if (radeon_crtc->crtc_id)
 523                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 524                 else
 525                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 526         }
 527         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 528         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 529         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 530
 531         if (old_fb && old_fb != crtc->fb) {
 532                 radeon_fb = to_radeon_framebuffer(old_fb);
 533                 radeon_gem_object_unpin(radeon_fb->obj);
 534         }
 535         return 0;
 536 }
 537
 538 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 539 {
 540         struct drm_device *dev = crtc->dev;
 541         struct radeon_device *rdev = dev->dev_private;
 542         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 543         struct drm_encoder *encoder;
 544         int format;
 545         int hsync_start;
 546         int hsync_wid;
 547         int vsync_wid;
 548         uint32_t crtc_h_total_disp;
 549         uint32_t crtc_h_sync_strt_wid;
 550         uint32_t crtc_v_total_disp;
 551         uint32_t crtc_v_sync_strt_wid;
 552         bool is_tv = false;
 553
 554         DRM_DEBUG("\n");
 555         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 556                 if (encoder->crtc == crtc) {
 557                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 558                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 559                                 is_tv = true;
 560                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 561                                 break;
 562                         }
 563                 }
 564         }
 565
 566         switch (crtc->fb->bits_per_pixel) {
 567         case 8:
 568                 format = 2;
 569                 break;
 570         case 15:      /*  555 */
 571                 format = 3;
 572                 break;
 573         case 16:      /*  565 */
 574                 format = 4;
 575                 break;
 576         case 24:      /*  RGB */
 577                 format = 5;
 578                 break;
 579         case 32:      /* xRGB */
 580                 format = 6;
 581                 break;
 582         default:
 583                 return false;
 584         }
 585
 586         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 587                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 588
 589         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 590         if (!hsync_wid)
 591                 hsync_wid = 1;
 592         hsync_start = mode->crtc_hsync_start - 8;
 593
 594         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 595                                 | ((hsync_wid & 0x3f) << 16)
 596                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 597                                    ? RADEON_CRTC_H_SYNC_POL
 598                                    : 0));
 599
 600         /* This works for double scan mode. */
 601         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 602                              | ((mode->crtc_vdisplay - 1) << 16));
 603
 604         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 605         if (!vsync_wid)
 606                 vsync_wid = 1;
 607
 608         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 609                                 | ((vsync_wid & 0x1f) << 16)
 610                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 611                                    ? RADEON_CRTC_V_SYNC_POL
 612                                    : 0));
 613
 614         /* TODO -> Dell Server */
 615         if (0) {
 616                 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 617                 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 618                 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 619                 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 620
 621                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
 622                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 623
 624                 /* For CRT on DAC2, don't turn it on if BIOS didn't
 625                    enable it, even it's detected.
 626                 */
 627                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 628                 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
 629                 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 630
 631                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 632                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 633                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 634                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 635         }
 636
 637         if (radeon_crtc->crtc_id) {
 638                 uint32_t crtc2_gen_cntl;
 639                 uint32_t disp2_merge_cntl;
 640
 641                 /* check to see if TV DAC is enabled for another crtc and keep it enabled */
 642                 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
 643                         crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
 644                 else
 645                         crtc2_gen_cntl = 0;
 646
 647                 crtc2_gen_cntl |= ((format << 8)
 648                                    | RADEON_CRTC2_VSYNC_DIS
 649                                    | RADEON_CRTC2_HSYNC_DIS
 650                                    | RADEON_CRTC2_DISP_DIS
 651                                    | RADEON_CRTC2_DISP_REQ_EN_B
 652                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 653                                       ? RADEON_CRTC2_DBL_SCAN_EN
 654                                       : 0)
 655                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 656                                       ? RADEON_CRTC2_CSYNC_EN
 657                                       : 0)
 658                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 659                                       ? RADEON_CRTC2_INTERLACE_EN
 660                                       : 0));
 661
 662                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 663                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 664
 665                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 666                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 667         } else {
 668                 uint32_t crtc_gen_cntl;
 669                 uint32_t crtc_ext_cntl;
 670                 uint32_t disp_merge_cntl;
 671
 672                 crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
 673                                  | (format << 8)
 674                                  | RADEON_CRTC_DISP_REQ_EN_B
 675                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 676                                     ? RADEON_CRTC_DBL_SCAN_EN
 677                                     : 0)
 678                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 679                                     ? RADEON_CRTC_CSYNC_EN
 680                                     : 0)
 681                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 682                                     ? RADEON_CRTC_INTERLACE_EN
 683                                     : 0));
 684
 685                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 686                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 687                                   RADEON_CRTC_VSYNC_DIS |
 688                                   RADEON_CRTC_HSYNC_DIS |
 689                                   RADEON_CRTC_DISPLAY_DIS);
 690
 691                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 692                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 693
 694                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 695                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 696                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 697         }
 698
 699         if (is_tv)
 700                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 701                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 702                                                  &crtc_v_sync_strt_wid);
 703
 704         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 705         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 706         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 707         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 708
 709         return true;
 710 }
 711
 712 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 713 {
 714         struct drm_device *dev = crtc->dev;
 715         struct radeon_device *rdev = dev->dev_private;
 716         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 717         struct drm_encoder *encoder;
 718         uint32_t feedback_div = 0;
 719         uint32_t frac_fb_div = 0;
 720         uint32_t reference_div = 0;
 721         uint32_t post_divider = 0;
 722         uint32_t freq = 0;
 723         uint8_t pll_gain;
 724         int pll_flags = RADEON_PLL_LEGACY;
 725         bool use_bios_divs = false;
 726         /* PLL registers */
 727         uint32_t pll_ref_div = 0;
 728         uint32_t pll_fb_post_div = 0;
 729         uint32_t htotal_cntl = 0;
 730         bool is_tv = false;
 731         struct radeon_pll *pll;
 732
 733         struct {
 734                 int divider;
 735                 int bitvalue;
 736         } *post_div, post_divs[]   = {
 737                 /* From RAGE 128 VR/RAGE 128 GL Register
 738                  * Reference Manual (Technical Reference
 739                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 740                  * 3-17 (PLL_DIV_[3:0]).
 741                  */
 742                 {  1, 0 },              /* VCLK_SRC                 */
 743                 {  2, 1 },              /* VCLK_SRC/2               */
 744                 {  4, 2 },              /* VCLK_SRC/4               */
 745                 {  8, 3 },              /* VCLK_SRC/8               */
 746                 {  3, 4 },              /* VCLK_SRC/3               */
 747                 { 16, 5 },              /* VCLK_SRC/16              */
 748                 {  6, 6 },              /* VCLK_SRC/6               */
 749                 { 12, 7 },              /* VCLK_SRC/12              */
 750                 {  0, 0 }
 751         };
 752
 753         if (radeon_crtc->crtc_id)
 754                 pll = &rdev->clock.p2pll;
 755         else
 756                 pll = &rdev->clock.p1pll;
 757
 758         if (mode->clock > 200000) /* range limits??? */
 759                 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 760         else
 761                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 762
 763         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 764                 if (encoder->crtc == crtc) {
 765                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 766
 767                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 768                                 is_tv = true;
 769                                 break;
 770                         }
 771
 772                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 773                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 774                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 775                                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 776                                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 777                                 if (lvds) {
 778                                         if (lvds->use_bios_dividers) {
 779                                                 pll_ref_div = lvds->panel_ref_divider;
 780                                                 pll_fb_post_div   = (lvds->panel_fb_divider |
 781                                                                      (lvds->panel_post_divider << 16));
 782                                                 htotal_cntl  = 0;
 783                                                 use_bios_divs = true;
 784                                         }
 785                                 }
 786                                 pll_flags |= RADEON_PLL_USE_REF_DIV;
 787                         }
 788                 }
 789         }
 790
 791         DRM_DEBUG("\n");
 792
 793         if (!use_bios_divs) {
 794                 radeon_compute_pll(pll, mode->clock,
 795                                    &freq, &feedback_div, &frac_fb_div,
 796                                    &reference_div, &post_divider,
 797                                    pll_flags);
 798
 799                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 800                         if (post_div->divider == post_divider)
 801                                 break;
 802                 }
 803
 804                 if (!post_div->divider)
 805                         post_div = &post_divs[0];
 806
 807                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 808                           (unsigned)freq,
 809                           feedback_div,
 810                           reference_div,
 811                           post_divider);
 812
 813                 pll_ref_div   = reference_div;
 814 #if defined(__powerpc__) && (0) /* TODO */
 815                 /* apparently programming this otherwise causes a hang??? */
 816                 if (info->MacModel == RADEON_MAC_IBOOK)
 817                         pll_fb_post_div = 0x000600ad;
 818                 else
 819 #endif
 820                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 821
 822                 htotal_cntl    = mode->htotal & 0x7;
 823
 824         }
 825
 826         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 827                                            pll_ref_div & 0x3ff,
 828                                            pll_fb_post_div & 0x7ff);
 829
 830         if (radeon_crtc->crtc_id) {
 831                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 832                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 833                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 834
 835                 if (is_tv) {
 836                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 837                                                      &pll_ref_div, &pll_fb_post_div,
 838                                                      &pixclks_cntl);
 839                 }
 840
 841                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 842                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 843                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 844
 845                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 846                              RADEON_P2PLL_RESET
 847                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 848                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 849                              ~(RADEON_P2PLL_RESET
 850                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 851                                | RADEON_P2PLL_PVG_MASK));
 852
 853                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 854                              pll_ref_div,
 855                              ~RADEON_P2PLL_REF_DIV_MASK);
 856
 857                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 858                              pll_fb_post_div,
 859                              ~RADEON_P2PLL_FB0_DIV_MASK);
 860
 861                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 862                              pll_fb_post_div,
 863                              ~RADEON_P2PLL_POST0_DIV_MASK);
 864
 865                 radeon_pll2_write_update(dev);
 866                 radeon_pll2_wait_for_read_update_complete(dev);
 867
 868                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 869
 870                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 871                              0,
 872                              ~(RADEON_P2PLL_RESET
 873                                | RADEON_P2PLL_SLEEP
 874                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 875
 876                 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 877                           (unsigned)pll_ref_div,
 878                           (unsigned)pll_fb_post_div,
 879                           (unsigned)htotal_cntl,
 880                           RREG32_PLL(RADEON_P2PLL_CNTL));
 881                 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
 882                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 883                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 884                           (unsigned)((pll_fb_post_div &
 885                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 886
 887                 mdelay(50); /* Let the clock to lock */
 888
 889                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 890                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 891                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 892
 893                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 894         } else {
 895                 uint32_t pixclks_cntl;
 896
 897
 898                 if (is_tv) {
 899                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 900                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 901                                                      &pll_fb_post_div, &pixclks_cntl);
 902                 }
 903
 904                 if (rdev->flags & RADEON_IS_MOBILITY) {
 905                         /* A temporal workaround for the occational blanking on certain laptop panels.
 906                            This appears to related to the PLL divider registers (fail to lock?).
 907                            It occurs even when all dividers are the same with their old settings.
 908                            In this case we really don't need to fiddle with PLL registers.
 909                            By doing this we can avoid the blanking problem with some panels.
 910                         */
 911                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 912                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 913                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 914                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 915                                          RADEON_PLL_DIV_SEL,
 916                                          ~(RADEON_PLL_DIV_SEL));
 917                                 r100_pll_errata_after_index(rdev);
 918                                 return;
 919                         }
 920                 }
 921
 922                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 923                              RADEON_VCLK_SRC_SEL_CPUCLK,
 924                              ~(RADEON_VCLK_SRC_SEL_MASK));
 925                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 926                              RADEON_PPLL_RESET
 927                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 928                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 929                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 930                              ~(RADEON_PPLL_RESET
 931                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 932                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 933                                | RADEON_PPLL_PVG_MASK));
 934
 935                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 936                          RADEON_PLL_DIV_SEL,
 937                          ~(RADEON_PLL_DIV_SEL));
 938                 r100_pll_errata_after_index(rdev);
 939
 940                 if (ASIC_IS_R300(rdev) ||
 941                     (rdev->family == CHIP_RS300) ||
 942                     (rdev->family == CHIP_RS400) ||
 943                     (rdev->family == CHIP_RS480)) {
 944                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 945                                 /* When restoring console mode, use saved PPLL_REF_DIV
 946                                  * setting.
 947                                  */
 948                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 949                                              pll_ref_div,
 950                                              0);
 951                         } else {
 952                                 /* R300 uses ref_div_acc field as real ref divider */
 953                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 954                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 955                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 956                         }
 957                 } else
 958                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 959                                      pll_ref_div,
 960                                      ~RADEON_PPLL_REF_DIV_MASK);
 961
 962                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 963                              pll_fb_post_div,
 964                              ~RADEON_PPLL_FB3_DIV_MASK);
 965
 966                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 967                              pll_fb_post_div,
 968                              ~RADEON_PPLL_POST3_DIV_MASK);
 969
 970                 radeon_pll_write_update(dev);
 971                 radeon_pll_wait_for_read_update_complete(dev);
 972
 973                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 974
 975                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 976                              0,
 977                              ~(RADEON_PPLL_RESET
 978                                | RADEON_PPLL_SLEEP
 979                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 980                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 981
 982                 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 983                           pll_ref_div,
 984                           pll_fb_post_div,
 985                           (unsigned)htotal_cntl,
 986                           RREG32_PLL(RADEON_PPLL_CNTL));
 987                 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
 988                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 989                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
 990                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 991
 992                 mdelay(50); /* Let the clock to lock */
 993
 994                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 995                              RADEON_VCLK_SRC_SEL_PPLLCLK,
 996                              ~(RADEON_VCLK_SRC_SEL_MASK));
 997
 998                 if (is_tv)
 999                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1000         }
1001 }
1002
1003 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1004                                    struct drm_display_mode *mode,
1005                                    struct drm_display_mode *adjusted_mode)
1006 {
1007         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1008                 return false;
1009         return true;
1010 }
1011
1012 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1013                                  struct drm_display_mode *mode,
1014                                  struct drm_display_mode *adjusted_mode,
1015                                  int x, int y, struct drm_framebuffer *old_fb)
1016 {
1017         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1018         struct drm_device *dev = crtc->dev;
1019         struct radeon_device *rdev = dev->dev_private;
1020
1021         /* TODO TV */
1022         radeon_crtc_set_base(crtc, x, y, old_fb);
1023         radeon_set_crtc_timing(crtc, adjusted_mode);
1024         radeon_set_pll(crtc, adjusted_mode);
1025         radeon_bandwidth_update(rdev);
1026         if (radeon_crtc->crtc_id == 0) {
1027                 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
1028         } else {
1029                 if (radeon_crtc->rmx_type != RMX_OFF) {
1030                         /* FIXME: only first crtc has rmx what should we
1031                          * do ?
1032                          */
1033                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1034                 }
1035         }
1036         return 0;
1037 }
1038
1039 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1040 {
1041         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1042 }
1043
1044 static void radeon_crtc_commit(struct drm_crtc *crtc)
1045 {
1046         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1047 }
1048
1049 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1050         .dpms = radeon_crtc_dpms,
1051         .mode_fixup = radeon_crtc_mode_fixup,
1052         .mode_set = radeon_crtc_mode_set,
1053         .mode_set_base = radeon_crtc_set_base,
1054         .prepare = radeon_crtc_prepare,
1055         .commit = radeon_crtc_commit,
1056         .load_lut = radeon_crtc_load_lut,
1057 };
1058
1059
1060 void radeon_legacy_init_crtc(struct drm_device *dev,
1061                                struct radeon_crtc *radeon_crtc)
1062 {
1063         if (radeon_crtc->crtc_id == 1)
1064                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1065         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1066 }